STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6 8-bit ultra-low-power MCU, up to 32 KB Flash, 1 KB Data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators Datasheet - production data Features • Operating conditions – Operating power supply range 1.8 V to LQFP48 UFQFPN4 8 UFQFPN32 (5x5mm) 3.6 V (down to 1.65 V at power down) 7x7mm 7x7mm LQFP32 7x7mm (cid:35)(cid:51)(cid:48) – Temp. range: - 40 °C to 85, 105 or 125 °C • Low power features UFQFPN28 (4x4mm) WLCSP28 – 5 low power modes: Wait, Low power run • 12-bit DAC with output buffer (5.1 µA), Low power wait (3 µA), Active-halt • 12-bit ADC up to 1 Msps/25 channels with full RTC (1.3 µA), Halt (350 nA) – T. sensor and internal reference voltage – Consumption: 195 µA/MHz + 440 µA – Ultra-low leakage per I/0: 50 nA • 2 ultra-low-power comparators – Fast wakeup from Halt: 4.7 µs – 1 with fixed threshold and 1 rail to rail • Advanced STM8 core – Wakeup capability – Harvard architecture and 3-stage pipeline • Timers – Max freq. 16 MHz, 16 CISC MIPS peak – Two 16-bit timers with 2 channels (used as – Up to 40 external interrupt sources IC, OC, PWM), quadrature encoder • Reset and supply management – One 16-bit advanced control timer with 3 channels, supporting motor control – Low power, ultra-safe BOR reset with 5 – One 8-bit timer with 7-bit prescaler selectable thresholds – 2 watchdogs: 1 Window, 1 Independent – Ultra-low-power POR/PDR – Beeper timer with 1, 2 or 4 kHz frequencies – Programmable voltage detector (PVD) • Clock management • Communication interfaces – Synchronous serial interface (SPI) – 1 to 16 MHz crystal oscillator – Fast I2C 400 kHz SMBus and PMBus – 32 kHz crystal oscillator – USART (ISO 7816 interface and IrDA) – Internal 16 MHz factory-trimmed RC – Internal 38 kHz low consumption RC • Up to 41 I/Os, all mappable on interrupt vectors – Clock security system • Up to 16 capacitive sensing channels • Low power RTC supporting touchkey, proximity, linear touch – BCD calendar with alarm interrupt and rotary touch sensors – Auto-wakeup from Halt w/ periodic interrupt • Development support • LCD: up to 4x28 segments w/ step-up – Fast on-chip programming and non converter intrusive debugging with SWIM • Memories – Bootloader using USART – Up to 32 KB of Flash program memory and • 96-bit unique ID 1 Kbyte of data EEPROM with ECC, RWW – Flexible write and read protection modes Table 1. Device summary – Up to 2 Kbyte of RAM Reference Part number • DMA STM8L151xx STM8L151C4, STM8L151C6, STM8L151K4, – 4 channels; supported peripherals: ADC, (without LCD) STM8L151K6, STM8L151G4, STM8L151G6 DAC, SPI, I2C, USART, timers STM8L152xx STM8L152C4, STM8L152C6, STM8L152K4, – 1 channel for memory-to-memory (with LCD) STM8L152K6 April 2017 DocID15962 Rev 15 1/142 This is information on a product in full production. www.st.com

Contents STM8L151x4/6, STM8L152x4/6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 21 3.13 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Contents 3.16 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 67 9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DocID15962 Rev 15 3/142 4

Contents STM8L151x4/6, STM8L152x4/6 9.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.9 LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.3.12 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.3.13 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.14 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 10.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 10.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.6 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.7 WLCSP28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Medium-density STM8L151x4/6 and STM8L152x4/6 low-power device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4. Legend/abbreviation for table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description. . . . . . . . . . . . . . . . . . . . 29 Table 6. Flash and RAM boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7. Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 8. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 12. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 13. Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 14. Unique ID registers (96 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 20. Total current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 21. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 22. Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 23. Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 76 Table 24. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V. . . . . 78 Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 80 Table 26. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 80 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 28. Current consumption under external reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 29. HSE external clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 30. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 31. HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 32. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 34. LSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 36. Flash program and data EEPROM memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 37. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 38. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 39. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 40. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 41. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 93 Table 42. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 43. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 44. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 45. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 46. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DocID15962 Rev 15 5/142 6

List of tables STM8L151x4/6, STM8L152x4/6 Table 47. TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 48. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 49. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 50. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 51. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 52. DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 53. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 54. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 55. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 56. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 57. R max for f = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AIN ADC Table 58. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 59. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 60. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 61. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 63. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 64. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 65. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 66. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 67. WLCSP28 - 28-pin, 1.703 x 2.841 mm, 0.4 mm pitch wafer level chip scale package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 68. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 69. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 List of figures List of figures Figure 1. Medium-density STM8L151x4/6 and STM8L152x4/6 device block diagram . . . . . . . . . . . 14 Figure 2. Medium-density STM8L151x4/6 and STM8L152x4/6 clock tree diagram . . . . . . . . . . . . . 19 Figure 3. STM8L151C4, STM8L151C6 48-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 4. STM8L151K4, STM8L151K6 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . 26 Figure 5. STM8L151Gx UFQFPN28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. STM8L151G4, STM8L151G6 WLCSP28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7. STM8L152C4, STM8L152C6 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. STM8L152K4, STM8L152K6 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . 28 Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 11. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 12. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 13. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 14. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 15. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 16. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 18. LSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 19. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DD Figure 20. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 21. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 22. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 23. Typical pull-up resistance R vs V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PU DD Figure 24. Typical pull-up current I vs V with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 pu DD Figure 25. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 26. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 27. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 28. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 29. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 30. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 31. Typical NRST pull-up resistance R vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PU DD Figure 32. Typical NRST pull-up current I vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 pu DD Figure 33. Recommended NRST pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 34. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 35. SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 36. SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 37. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 38. ADC1 accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 39. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 40. Maximum dynamic current consumption on V supply pin during ADC REF+ conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 41. Power supply and reference decoupling (V not connected to V ). . . . . . . . . . . . . 113 REF+ DDA Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . 113 Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 116 Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 45. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 46. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat DocID15962 Rev 15 7/142 8

List of figures STM8L151x4/6, STM8L152x4/6 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 47. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 48. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 49. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 123 Figure 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 51. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 52. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 53. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 54. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 55. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 56. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 57. UFQFPN28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 58. WLCSP28 - 28-pin, 1.703 x 2.841 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 59. WLCSP28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 60. Medium-density STM8L15x ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . 136 8/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Introduction 1 Introduction This document describes the features, pinout, mechanical data and ordering information of the medium-density STM8L151x4/6 and STM8L152x4/6 devices (STM8L151Cx/Kx/Gx, STM8L152Cx/Kx microcontrollers with a 16-Kbyte or 32-Kbyte Flash memory density). These devices are referred to as medium-density devices in the STM8L15x and STM8L16x reference manual (RM0031) and in the STM8L Flash programming manual (PM0054). For more details on the whole STMicroelectronics ultra-low-power family please refer to Section 2.2: Ultra-low-power continuum on page 13. For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). The medium-density devices provide the following benefits: • Integrated system – Up to 32 Kbyte of medium-density embedded Flash program memory – 1 Kbyte of data EEPROM – Internal high speed and low-power low speed RC – Embedded reset • Ultra-low power consumption – 195 µA/MHz + 440 µA (consumption) – 0.9 µA with LSI in Active-halt mode – Clock gated system and optimized power management – Capability to execute from RAM for Low power wait mode and Low power run mode • Advanced features – Up to 16 MIPS at 16 MHz CPU clock frequency – Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access • Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals – Wide choice of development tools All devices offer 12-bit ADC, DAC, two comparators, Real-time clock three 16-bit timers, one 8-bit timer as well as standard communication interface such as SPI, I2C and USART. A 4x28-segment LCD is available on the medium-density STM8L152xx line. Table 2: Medium- density STM8L151x4/6 and STM8L152x4/6 low-power device features and peripheral counts and Section 3: Functional overview give an overview of the complete range of peripherals proposed in this family. Figure 1 on page 14 shows the general block diagram of the device family. DocID15962 Rev 15 9/142 58

Introduction STM8L151x4/6, STM8L152x4/6 The medium-density STM8L15x microcontroller family is suitable for a wide range of applications: • Medical and hand-held equipment • Application control and user interface • PC peripherals, gaming, GPS and sport equipment • Alarm systems, wired and wireless sensors 10/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Description 2 Description The medium-density STM8L151x4/6 and STM8L152x4/6 devices are members of the STM8L ultra-low-power 8-bit family. The medium-density STM8L15x family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85 °C and -40 to +125 °C temperature ranges. The medium-density STM8L15x ultra-low-power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming. All medium-density STM8L15x microcontrollers feature embedded data EEPROM and low- power, low-voltage, single-supply program Flash memory. They incorporate an extensive range of enhanced I/Os and peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. Six different packages are proposed from 28 to 48 pins. Depending on the device chosen, different sets of peripherals are included. All STM8L ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout. DocID15962 Rev 15 11/142 58

Description STM8L151x4/6, STM8L152x4/6 2.1 Device overview Table 2. M edium-density STM8L151x4/6 and STM8L152x4/6 low-power device features and peripheral counts Features STM8L151Gx STM8L15xKx STM8L15xCx Flash (Kbyte) 16 32 16 32 16 32 Data EEPROM (Kbyte) 1 RAM (Kbyte) 2 LCD No 4x17 (1) 4x28 (1) 1 Basic (8-bit) 2 Timers General purpose (16-bit) 1 Advanced control (16-bit) SPI 1 Communication I2C 1 interfaces USART 1 GPIOs 26(3) 30 (2)(3) or 29 (1)(3) 41(3) 12-bit synchronized ADC 1 1 1 (number of channels) (18) (22 (2) or 21 (1)) (25) 12-Bit DAC 1 (number of channels) (1) Comparators COMP1/COMP2 2 RTC, window watchdog, independent watchdog, Others 16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator CPU frequency 16 MHz Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power down) Operating temperature -40 to +85 °C/ -40 to +105 °C / -40 to +125 °C UFQFPN28 (4x4; LQFP32(7x7) LQFP48 Packages 0.6 mm thickness) UFQFPN32 (5x5; UFQFPN48 (4x4; WLCSP28 0.6 mm thickness) 0.6 mm thickness) 1. STM8L152xx versions only 2. STM8L151xx versions only 3. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1). 12/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Description 2.2 Ultra-low-power continuum The ultra-low-power medium-densitySTM8L151x4/6 and STM8L152x4/6 devices are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM8L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 µm ultra-low leakage process. Note: 1 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices. 2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family. Please refer to STM32L15x documentation for more information on these devices. Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM® Cortex®-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. Shared peripherals STM8L151xx/152xx and STM8L15xxx share identical peripherals which ensure a very easy migration from one family to another: • Analog peripherals: ADC1, DAC, and comparators COMP1/COMP2 • Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L151xx/152xx and STM8L15xxx devices use a common architecture: • Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down • Architecture optimized to reach ultra-low consumption both in low power modes and Run mode • Fast startup strategy from low power modes • Flexible system clock • Ultra-safe reset: same reset strategy for both STM8L15x and STM32L15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST ultra-low-power continuum also lies in feature compatibility: • More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm • Memory density ranging from 4 to 128 Kbyte DocID15962 Rev 15 13/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 3 Functional overview Figure 1. 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Legend: ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access DAC: Digital-to-analog converter I²C: Inter-integrated circuit multi master interface 14/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview IWDG: Independent watchdog LCD: Liquid crystal display POR/PDR: Power on reset / power down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog 3.1 Low-power modes The medium-density STM8L151x4/6 and STM8L152x4/6 devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt, event or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 21. • Low power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power run mode consumption: refer to Table 22. • Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode consumption: refer to Table 23. • Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Active-halt consumption: refer to Table 24 and Table 25. • Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs. Halt consumption: refer to Table 26. DocID15962 Rev 15 15/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 3.2 Central processing unit STM8 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. Architecture and registers • Harvard architecture • 3-stage pipeline • 32-bit wide program memory bus - single cycle fetching most instructions • X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations • 8-bit accumulator • 24-bit program counter - 16 Mbyte linear memory space • 16-bit stack pointer - access to a 64 Kbyte level stack • 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing • 20 addressing modes • Indexed indirect addressing mode for lookup tables located anywhere in the address space • Stack pointer relative addressing mode for local variables and parameter passing Instruction set • 80 instructions with 2-byte average instruction size • Standard data movement and logic/arithmetic functions • 8-bit by 8-bit multiplication • 16-bit by 8-bit and 16-bit by 16-bit division • Bit manipulation • Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers 3.2.2 Interrupt controller The medium-density STM8L151x4/6 and STM8L152x4/6 feature a nested vectored interrupt controller: • Nested interrupts with 3 software priority levels • 32 interrupt vectors with hardware priority • Up to 40 external interrupt sources on 11 vectors • Trap and reset interrupts 16/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.65 V to 3.6 V operating supply voltage (V ). The external power DD supply pins must be connected as follows: • V ; V = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for SS1 DD1 I/Os and for the internal regulator. Provided externally through V pins, the DD1 corresponding ground pin is V . SS1 • V V = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for SSA; DDA analog peripherals (minimum voltage to be applied to V is 1.8 V when the ADC1 is DDA used). V and V must be connected to V and V , respectively. DDA SSA DD1 SS1 • V ; V = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for SS2 DD2 I/Os. V and V must be connected to V and V , respectively. DD2 SS2 DD1 SS1 • V ; V (for ADC1): external reference voltage for ADC1. Must be provided REF+ REF- externally through V and V pin. REF+ REF- • V (for DAC): external voltage reference for DAC must be provided externally REF+ through V . REF+ 3.3.2 Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the V min value at power down is 1.65 V). DD Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains under reset when V is below a specified threshold, V or V , without the need DD POR/PDR BOR for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the V /V power supply and compares it to the V threshold. This PVD offers 7 different DD DDA PVD levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V /V drops below the V threshold and/or when DD DDA PVD V /V is higher than the V threshold. The interrupt service routine can then generate DD DDA PVD a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The medium-density STM8L151x4/6 and STM8L152x4/6 embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: • Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes. • Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes. When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. DocID15962 Rev 15 17/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 3.4 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features • Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock sources: 4 different clock sources can be used to drive the system clock: – 1-16 MHz High speed external crystal (HSE) – 16 MHz High speed internal RC oscillator (HSI) – 32.768 kHz Low speed external crystal (LSE) – 38 kHz Low speed internal RC (LSI) • RTC and LCD clock sources: the above four sources can be chosen to clock the RTC and the LCD, whatever the system clock. • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI. • Configurable main clock output (CCO): This outputs an external clock for use by the application. 18/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview Figure 2. Medium-density STM8L151x4/6 and STM8L152x4/6 clock tree diagram (cid:38)(cid:54)(cid:54) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:43)(cid:54)(cid:40)(cid:3)(cid:3)(cid:50)(cid:54)(cid:38) (cid:43)(cid:54)(cid:40)(cid:3)(cid:11)(cid:20)(cid:12) (cid:3) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:20)(cid:3)(cid:16)(cid:3)(cid:20)(cid:25)(cid:3)(cid:48)(cid:43)(cid:93) (cid:43)(cid:54)(cid:44) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46)(cid:3)(cid:3) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46)(cid:3)(cid:87)(cid:82)(cid:3)(cid:70)(cid:82)(cid:85)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:20)(cid:43)(cid:25)(cid:54)(cid:3)(cid:48)(cid:44)(cid:3)(cid:3)(cid:53)(cid:43)(cid:38)(cid:93) (cid:47)(cid:47)(cid:54)(cid:54)(cid:40)(cid:44)(cid:3)(cid:11)(cid:21)(cid:12) (cid:18)(cid:20)(cid:30)(cid:21)(cid:30)(cid:23)(cid:30)(cid:83)(cid:27)(cid:85)(cid:30)(cid:72)(cid:20)(cid:86)(cid:25)(cid:70)(cid:30)(cid:22)(cid:68)(cid:21)(cid:79)(cid:72)(cid:30)(cid:25)(cid:85)(cid:23)(cid:30)(cid:20)(cid:21)(cid:27) (cid:51)(cid:38)(cid:47)(cid:46) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79) (cid:87)(cid:82)(cid:3)(cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:20)(cid:24)(cid:3)(cid:69)(cid:76)(cid:87)(cid:12) (cid:47)(cid:54)(cid:40)(cid:11)(cid:3)(cid:21)(cid:12) (cid:37)(cid:40)(cid:40)(cid:51)(cid:38)(cid:47)(cid:46) (cid:3) (cid:87)(cid:82)(cid:3)(cid:37)(cid:40)(cid:40)(cid:51) (cid:47)(cid:54)(cid:44)(cid:3)(cid:53)(cid:38) (cid:47)(cid:54)(cid:44) (cid:38)(cid:47)(cid:46)(cid:37)(cid:40)(cid:40)(cid:51)(cid:54)(cid:40)(cid:47)(cid:62)(cid:20)(cid:29)(cid:19)(cid:64) (cid:44)(cid:58)(cid:39)(cid:42)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:44)(cid:58)(cid:39)(cid:42) (cid:22)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93) (cid:53)(cid:55)(cid:38)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:3)(cid:53)(cid:55)(cid:38) (cid:53)(cid:55)(cid:38)(cid:54)(cid:40)(cid:47)(cid:62)(cid:22)(cid:29)(cid:19)(cid:64) (cid:47)(cid:38)(cid:39)(cid:3)(cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:20)(cid:3)(cid:69)(cid:76)(cid:87)(cid:12) (cid:53)(cid:55)(cid:38)(cid:3)(cid:3) (cid:53)(cid:55)(cid:38)(cid:38)(cid:47)(cid:46) (cid:53)(cid:55)(cid:38)(cid:38)(cid:47)(cid:46)(cid:18)(cid:21) (cid:83)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85) (cid:18)(cid:3)(cid:21) (cid:87)(cid:82)(cid:3)(cid:47)(cid:38)(cid:39) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:47)(cid:54)(cid:40)(cid:3)(cid:3)(cid:50)(cid:54)(cid:38) (cid:18)(cid:20)(cid:30)(cid:21)(cid:30)(cid:23)(cid:30)(cid:27)(cid:30)(cid:20)(cid:25)(cid:30)(cid:22)(cid:21)(cid:30)(cid:25)(cid:23) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93) (cid:43)(cid:68)(cid:79)(cid:87) (cid:47)(cid:38)(cid:39)(cid:38)(cid:47)(cid:46) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:47)(cid:38)(cid:39) (cid:38)(cid:38)(cid:50) (cid:70)(cid:70)(cid:82)(cid:79)(cid:82)(cid:81)(cid:70)(cid:73)(cid:78)(cid:76)(cid:74)(cid:3)(cid:82)(cid:88)(cid:88)(cid:85)(cid:68)(cid:87)(cid:83)(cid:69)(cid:88)(cid:79)(cid:72)(cid:87) (cid:83)(cid:85)(cid:72)(cid:38)(cid:86)(cid:38)(cid:70)(cid:50)(cid:68)(cid:79)(cid:3)(cid:72)(cid:85) (cid:43)(cid:47)(cid:54)(cid:54)(cid:44)(cid:44) (cid:47)(cid:38)(cid:39)(cid:3)(cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79) (cid:18)(cid:20)(cid:30)(cid:21)(cid:30)(cid:23)(cid:30)(cid:27)(cid:30)(cid:20)(cid:25)(cid:30)(cid:22)(cid:21)(cid:30)(cid:25)(cid:23) (cid:43)(cid:47)(cid:54)(cid:54)(cid:40)(cid:40)(cid:11)(cid:11)(cid:21)(cid:20)(cid:12)(cid:12) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:20)(cid:3)(cid:69)(cid:76)(cid:87)(cid:12) (cid:68)(cid:76)(cid:20)(cid:24)(cid:22)(cid:25)(cid:25)(cid:74) 1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 3.5 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. • Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours • Periodic alarms based on the calendar can also be generated from every second to every year DocID15962 Rev 15 19/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 3.6 LCD (Liquid crystal display) The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels. • Internal step-up converter to guarantee contrast control whatever V . DD • Static 1/2, 1/3, 1/4 duty supported. • Static 1/2, 1/3 bias supported. • Phase inversion to reduce power consumption and EMI. • Up to 4 pixels which can programmed to blink. • The LCD controller can operate in Halt mode. Note: Unnecessary segments and common pins can be used as general I/O pins. 3.7 Memories The medium-density STM8L151x4/6 and STM8L152x4/6 devices have the following main features: • Up to 2 Kbyte of RAM • The non-volatile memory is divided into three arrays: – Up to 32 Kbyte of medium-density embedded Flash program memory – 1 Kbyte of data EEPROM – Option bytes. The EEPROM embeds the error correction code (ECC) feature. It supports the read-while- write (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix. The option byte protects part of the Flash program memory from write and readout piracy. 3.8 DMA A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, DAC, I2C1, SPI1, USART1, the four Timers. 3.9 Analog-to-digital converter • 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage • Conversion time down to 1 µs with f = 16 MHz SYSCLK • Programmable resolution • Programmable sampling time • Single and continuous mode of conversion • Scan capability: automatic conversion performed on a selected group of analog inputs • Analog watchdog • Triggered by timer 20/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview Note: ADC1 can be served by DMA1. 3.10 Digital-to-analog converter (DAC) • 12-bit DAC with output buffer • Synchronized update capability using TIM4 • DMA capability • External triggers for conversion • Input reference voltage V for better resolution REF+ Note: DAC can be served by DMA1. 3.11 Ultra-low-power comparators The medium-density STM8L151x4/6 and STM8L152x4/6 embed two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external (coming from an I/O). • One comparator with fixed threshold (COMP1). • One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one of the following: – DAC output – External I/O – Internal reference voltage or internal reference voltage sub multiple (1/4, 1/2, 3/4) The two comparators can be used together to offer a window function. They can wake up from Halt mode. 3.12 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1, COMP2, DAC and the internal reference voltage V . It also REFINT provides a set of registers for efficiently managing the charge transfer acquisition sequence (Section 3.13: Touch sensing). 3.13 Touch sensing Medium-density STM8L151x4/6 and STM8L152x4/6 devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (example, glass, plastic). The capacitive variation introduced by a finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. In medium-density STM8L151x4/6 DocID15962 Rev 15 21/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 and STM8L152x4/6 devices, the acquisition sequence is managed by software and it involves analog I/O groups and the routing interface. Reliable touch sensing solutions can be quickly and easily implemented using the free STM8 Touch Sensing Library. 3.14 Timers Medium-density STM8L151x4/6 and STM8L152x4/6devices contain one advanced control timer (TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 3 compares the features of the advanced control, general-purpose and basic timers. Table 3. Timer feature comparison DMA1 Counter Counter Capture/compare Complementary Timer Prescaler factor request resolution type channels outputs generation Any integer TIM1 3 + 1 3 from 1 to 65536 16-bit up/down TIM2 Any power of 2 Yes 2 TIM3 from 1 to 128 None Any power of 2 TIM4 8-bit up 0 from 1 to 32768 3.14.1 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. • 16-bit up, down and up/down autoreload counter with 16-bit prescaler • 3 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output • 1 additional capture/compare channel which is not connected to an external I/O • Synchronization module to control the timer with external signals • Break input to force timer outputs into a defined state • 3 complementary outputs with adjustable dead time • Encoder mode • Interrupt capability on various events (capture, compare, overflow, break, trigger) 22/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview 3.14.2 16-bit general purpose timers • 16-bit autoreload (AR) up/down-counter • 7-bit prescaler adjustable to fixed power of 2 ratios (1…128) • 2 individually configurable capture/compare channels • PWM mode • Interrupt capability on various events (capture, compare, overflow, break, trigger) • Synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.14.3 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow or for DAC trigger generation. 3.15 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 3.15.1 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.15.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 3.16 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. DocID15962 Rev 15 23/142 58

Functional overview STM8L151x4/6, STM8L152x4/6 3.17 Communication interfaces 3.17.1 SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices. • Maximum speed: 8 Mbit/s (f /2) both for master and slave SYSCLK • Full duplex synchronous transfers • Simplex synchronous transfers on 2 lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • Hardware CRC calculation • Slave/master selection input pin Note: SPI1 can be served by the DMA1 Controller. 3.17.2 I²C The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus- specific sequencing, protocol, arbitration and timing. • Master, slave and multi-master capability • Standard mode up to 100 kHz and fast speed modes up to 400 kHz. • 7-bit and 10-bit addressing modes. • SMBus 2.0 and PMBus support • Hardware CRC calculation Note: I2C1 can be served by the DMA1 Controller. 3.17.3 USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. • 1 Mbit/s full duplex SCI • SPI1 emulation • High precision baud rate generator • SmartCard emulation • IrDA SIR encoder decoder • Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.18 Infrared (IR) interface The medium-density STM8L151x4/6 and STM8L152x4/6 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 24/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Functional overview 3.19 Development support Development tools Development tools for the STM8 microcontrollers include: • The STice emulation system offering tracing and code profiling • The STVD high-level language debugger including C compiler, assembler and integrated development environment • The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The single-wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in real- time by means of shadow registers. Bootloader A bootloader is available to reprogram the Flash memory using the USART1 interface. The reference document for the bootloader is UM0560: STM8 bootloader user manual. DocID15962 Rev 15 25/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 4 Pinout and pin description Figure 3. STM8L151C4, STM8L151C6 48-pin pinout (without LCD) (cid:51)(cid:40)(cid:26)(cid:51)(cid:40)(cid:25)(cid:51)(cid:38)(cid:26)(cid:51)(cid:38)(cid:25)(cid:51)(cid:38)(cid:24)(cid:51)(cid:38)(cid:23)(cid:51)(cid:38)(cid:22)(cid:51)(cid:38)(cid:21)(cid:57)(cid:54)(cid:54)(cid:21)(cid:57)(cid:39)(cid:39)(cid:21)(cid:51)(cid:38)(cid:20)(cid:51)(cid:38)(cid:19) (cid:23)(cid:27)(cid:23)(cid:26)(cid:23)(cid:25)(cid:23)(cid:24)(cid:23)(cid:23)(cid:23)(cid:22)(cid:23)(cid:21)(cid:23)(cid:20)(cid:23)(cid:19)(cid:22)(cid:28)(cid:22)(cid:27)(cid:22)(cid:26) (cid:51)(cid:36)(cid:19) (cid:20) (cid:22)(cid:25) (cid:51)(cid:39)(cid:26) (cid:49)(cid:53)(cid:54)(cid:55)(cid:18)(cid:51)(cid:36)(cid:20) (cid:21) (cid:22)(cid:24) (cid:51)(cid:39)(cid:25) (cid:51)(cid:36)(cid:21) (cid:22) (cid:22)(cid:23) (cid:51)(cid:39)(cid:24) (cid:51)(cid:36)(cid:22) (cid:23) (cid:22)(cid:22) (cid:51)(cid:39)(cid:23) (cid:51)(cid:36)(cid:23) (cid:24) (cid:22)(cid:21) (cid:51)(cid:41)(cid:19) (cid:51)(cid:36)(cid:24) (cid:25)(cid:3) (cid:22)(cid:20) (cid:51)(cid:37)(cid:26) (cid:51)(cid:36)(cid:25) (cid:26)(cid:3) (cid:22)(cid:19) (cid:51)(cid:37)(cid:25) (cid:51)(cid:36)(cid:26) (cid:27)(cid:3) (cid:21)(cid:28) (cid:51)(cid:37)(cid:24) (cid:57)(cid:54)(cid:54)(cid:20)(cid:18)(cid:57)(cid:54)(cid:54)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:28)(cid:3) (cid:21)(cid:27) (cid:51)(cid:37)(cid:23) (cid:57)(cid:57)(cid:39)(cid:39)(cid:39)(cid:39)(cid:36)(cid:20) (cid:20)(cid:20)(cid:19)(cid:20) (cid:21)(cid:21)(cid:26)(cid:25) (cid:51)(cid:51)(cid:37)(cid:37)(cid:21)(cid:22) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:20)(cid:21) (cid:21)(cid:24) (cid:51)(cid:37)(cid:20) (cid:20)(cid:22)(cid:20)(cid:23)(cid:20)(cid:24)(cid:20)(cid:25)(cid:20)(cid:26)(cid:20)(cid:27)(cid:20)(cid:28)(cid:21)(cid:19)(cid:21)(cid:20)(cid:21)(cid:21)(cid:21)(cid:22)(cid:21)(cid:23) (cid:11)(cid:20)(cid:12)(cid:86)(cid:17)(cid:3)(cid:51)(cid:40)(cid:19)(cid:51)(cid:40)(cid:20)(cid:51)(cid:40)(cid:21)(cid:51)(cid:40)(cid:22)(cid:51)(cid:40)(cid:23)(cid:51)(cid:40)(cid:24)(cid:51)(cid:39)(cid:19)(cid:51)(cid:39)(cid:20)(cid:51)(cid:39)(cid:21)(cid:51)(cid:39)(cid:22)(cid:51)(cid:37)(cid:19) (cid:72) (cid:53) (cid:48)(cid:54)(cid:22)(cid:21)(cid:25)(cid:21)(cid:27)(cid:57)(cid:20) 1. Reserved. Must be tied to V . DD Figure 4. STM8L151K4, STM8L151K6 32-pin package pinout (without LCD) (cid:36)(cid:19)(cid:3)(cid:38)(cid:25)(cid:38)(cid:24)(cid:38)(cid:23)(cid:38)(cid:22)(cid:38)(cid:21)(cid:38)(cid:20)(cid:38)(cid:19) (cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:22)(cid:21) (cid:22)(cid:20) (cid:22)(cid:19) (cid:21)(cid:28) (cid:21)(cid:27) (cid:21)(cid:26) (cid:21)(cid:25) (cid:21)(cid:24) (cid:49)(cid:53)(cid:54)(cid:55)(cid:18)(cid:51)(cid:36)(cid:20) (cid:20) (cid:21)(cid:23) (cid:51)(cid:39)(cid:26) (cid:51)(cid:36)(cid:21) (cid:21) (cid:21)(cid:22) (cid:51)(cid:39)(cid:25) (cid:51)(cid:36)(cid:22) (cid:22) (cid:21)(cid:21) (cid:51)(cid:39)(cid:24) (cid:51)(cid:36)(cid:23) (cid:23) (cid:21)(cid:20) (cid:51)(cid:39)(cid:23) (cid:51)(cid:36)(cid:24) (cid:24) (cid:21)(cid:19) (cid:51)(cid:37)(cid:26) (cid:51)(cid:36)(cid:25) (cid:25) (cid:20)(cid:28) (cid:51)(cid:37)(cid:25) (cid:57)(cid:54)(cid:54)(cid:20) (cid:26) (cid:20)(cid:27) (cid:51)(cid:37)(cid:24) (cid:57)(cid:39)(cid:39)(cid:20) (cid:27) (cid:28) (cid:20)(cid:19) (cid:20)(cid:20) (cid:20)(cid:21) (cid:20)(cid:22) (cid:20)(cid:23) (cid:20)(cid:24) (cid:20)(cid:25)(cid:20)(cid:26) (cid:51)(cid:37)(cid:23) (cid:19)(cid:20)(cid:21)(cid:22)(cid:19)(cid:20)(cid:21)(cid:22) (cid:39)(cid:39)(cid:39)(cid:39)(cid:37)(cid:37)(cid:37)(cid:37) (cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:24)(cid:20)(cid:69) 1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package. Figure 5. STM8L151Gx UFQFPN28 package pinout (cid:36)(cid:19) (cid:38)(cid:25) (cid:38)(cid:24) (cid:38)(cid:23) (cid:38)(cid:22) (cid:38)(cid:21) (cid:38)(cid:20) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:21)(cid:27) (cid:21)(cid:26) (cid:21)(cid:25) (cid:21)(cid:24) (cid:21)(cid:23) (cid:21)(cid:22) (cid:21)(cid:21) (cid:49)(cid:53)(cid:54)(cid:55)(cid:18)(cid:51)(cid:36)(cid:20) (cid:20) (cid:21)(cid:20) (cid:51)(cid:38)(cid:19) (cid:51)(cid:36)(cid:21) (cid:21) (cid:21)(cid:19) (cid:51)(cid:39)(cid:23) (cid:51)(cid:36)(cid:22) (cid:22) (cid:20)(cid:28) (cid:51)(cid:37)(cid:26) (cid:51)(cid:36)(cid:23) (cid:23) (cid:20)(cid:27) (cid:51)(cid:37)(cid:25) (cid:51)(cid:36)(cid:24) (cid:24) (cid:20)(cid:26) (cid:51)(cid:37)(cid:24) (cid:57)(cid:54)(cid:54)(cid:20)(cid:18)(cid:57)(cid:54)(cid:54)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:25) (cid:20)(cid:25) (cid:51)(cid:37)(cid:23) (cid:57)(cid:39)(cid:39)(cid:20)(cid:18)(cid:57)(cid:39)(cid:39)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:26) (cid:20)(cid:24) (cid:51)(cid:37)(cid:22) (cid:27) (cid:28) (cid:20)(cid:19) (cid:20)(cid:20) (cid:20)(cid:21) (cid:20)(cid:22) (cid:20)(cid:23) (cid:19) (cid:20) (cid:21) (cid:22) (cid:19) (cid:20) (cid:21) (cid:39) (cid:39) (cid:39) (cid:39) (cid:37) (cid:37) (cid:37) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:24)(cid:19)(cid:69) 26/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description Figure 6. STM8L151G4, STM8L151G6 WLCSP28 package pinout (cid:23) (cid:22) (cid:21) (cid:20) (cid:36) (cid:51)(cid:36)(cid:19) (cid:51)(cid:38)(cid:24) (cid:51)(cid:38)(cid:22) (cid:51)(cid:38)(cid:20) (cid:37) (cid:51)(cid:36)(cid:21) (cid:51)(cid:38)(cid:25) (cid:51)(cid:38)(cid:21) (cid:51)(cid:38)(cid:19) (cid:38) (cid:51)(cid:36)(cid:22) (cid:51)(cid:36)(cid:20) (cid:51)(cid:38)(cid:23) (cid:51)(cid:39)(cid:23) (cid:39) (cid:51)(cid:36)(cid:24) (cid:51)(cid:36)(cid:23) (cid:51)(cid:37)(cid:23) (cid:51)(cid:37)(cid:24) (cid:40) (cid:51)(cid:39)(cid:21) (cid:51)(cid:37)(cid:19) (cid:51)(cid:37)(cid:22) (cid:51)(cid:37)(cid:26) (cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:51)(cid:39)(cid:22) (cid:51)(cid:37)(cid:21) (cid:51)(cid:37)(cid:25) (cid:42) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:51)(cid:39)(cid:19) (cid:51)(cid:39)(cid:20) (cid:51)(cid:37)(cid:20) (cid:68)(cid:76)(cid:20)(cid:26)(cid:19)(cid:27)(cid:23)(cid:69) Figure 7. STM8L152C4, STM8L152C6 48-pin pinout (with LCD) (cid:48)(cid:37)(cid:23)(cid:48)(cid:37)(cid:22)(cid:48)(cid:35)(cid:23)(cid:48)(cid:35)(cid:22)(cid:48)(cid:35)(cid:21)(cid:48)(cid:35)(cid:20)(cid:48)(cid:35)(cid:19)(cid:48)(cid:35)(cid:18)(cid:54)(cid:51)(cid:51)(cid:18)(cid:54)(cid:36)(cid:36)(cid:18)(cid:48)(cid:35)(cid:17)(cid:48)(cid:35)(cid:16) (cid:20)(cid:24)(cid:20)(cid:23)(cid:20)(cid:22)(cid:20)(cid:21)(cid:20)(cid:20)(cid:20)(cid:19)(cid:20)(cid:18)(cid:20)(cid:17)(cid:20)(cid:16)(cid:19)(cid:25)(cid:19)(cid:24)(cid:19)(cid:23) (cid:48)(cid:33)(cid:16) (cid:17) (cid:19)(cid:22) (cid:48)(cid:36)(cid:23) (cid:46)(cid:50)(cid:51)(cid:52)(cid:15)(cid:48)(cid:33)(cid:17) (cid:18) (cid:19)(cid:21) (cid:48)(cid:36)(cid:22) (cid:48)(cid:33)(cid:18) (cid:19) (cid:19)(cid:20) (cid:48)(cid:36)(cid:21) (cid:48)(cid:33)(cid:19) (cid:20) (cid:19)(cid:19) (cid:48)(cid:36)(cid:20) (cid:48)(cid:33)(cid:20) (cid:21) (cid:19)(cid:18) (cid:48)(cid:38)(cid:16) (cid:48)(cid:33)(cid:21) (cid:22)(cid:0) (cid:19)(cid:17) (cid:48)(cid:34)(cid:23) (cid:48)(cid:33)(cid:22) (cid:23)(cid:0) (cid:19)(cid:16) (cid:48)(cid:34)(cid:22) (cid:48)(cid:33)(cid:23) (cid:24)(cid:0) (cid:18)(cid:25) (cid:48)(cid:34)(cid:21) (cid:54)(cid:51)(cid:51)(cid:17)(cid:15)(cid:54)(cid:51)(cid:51)(cid:33)(cid:15)(cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:25)(cid:0) (cid:18)(cid:24) (cid:48)(cid:34)(cid:20) (cid:54)(cid:54)(cid:36)(cid:36)(cid:36)(cid:36)(cid:33)(cid:17) (cid:17)(cid:17)(cid:16)(cid:17) (cid:18)(cid:18)(cid:23)(cid:22) (cid:48)(cid:48)(cid:34)(cid:34)(cid:18)(cid:19) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:17)(cid:18) (cid:18)(cid:21) (cid:48)(cid:34)(cid:17) (cid:17)(cid:19)(cid:17)(cid:20)(cid:17)(cid:21)(cid:17)(cid:22)(cid:17)(cid:23)(cid:17)(cid:24)(cid:17)(cid:25)(cid:18)(cid:16)(cid:18)(cid:17)(cid:18)(cid:18)(cid:18)(cid:19)(cid:18)(cid:20) (cid:36)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:16)(cid:17)(cid:18)(cid:19)(cid:16) (cid:35)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:36)(cid:36)(cid:36)(cid:36)(cid:34) (cid:44)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48) (cid:54) (cid:46)(cid:52)(cid:20)(cid:19)(cid:23)(cid:19)(cid:26)(cid:55)(cid:18) DocID15962 Rev 15 27/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 Figure 8. STM8L152K4, STM8L152K6 32-pin package pinout (with LCD) (cid:19)(cid:3)(cid:25)(cid:24)(cid:23) (cid:22)(cid:21)(cid:20)(cid:19) (cid:36)(cid:38)(cid:38)(cid:38) (cid:38)(cid:38)(cid:38)(cid:38) (cid:51)(cid:51)(cid:51)(cid:51) (cid:51)(cid:51)(cid:51)(cid:51) (cid:22)(cid:21) (cid:22)(cid:20) (cid:22)(cid:19) (cid:21)(cid:28) (cid:21)(cid:27) (cid:21)(cid:26) (cid:21)(cid:25) (cid:21)(cid:24) (cid:49)(cid:53)(cid:54)(cid:55)(cid:18)(cid:51)(cid:36)(cid:20) (cid:20) (cid:21)(cid:23) (cid:51)(cid:39)(cid:26) (cid:51)(cid:36)(cid:21) (cid:21) (cid:21)(cid:22) (cid:51)(cid:39)(cid:25) (cid:51)(cid:36)(cid:22) (cid:22) (cid:21)(cid:21) (cid:51)(cid:39)(cid:24) (cid:51)(cid:36)(cid:23) (cid:23) (cid:21)(cid:20) (cid:51)(cid:39)(cid:23) (cid:51)(cid:36)(cid:24) (cid:24) (cid:21)(cid:19) (cid:51)(cid:37)(cid:26) (cid:51)(cid:36)(cid:25) (cid:25) (cid:20)(cid:28) (cid:51)(cid:37)(cid:25) (cid:57)(cid:54)(cid:54)(cid:20) (cid:26) (cid:20)(cid:27) (cid:51)(cid:37)(cid:24) (cid:57)(cid:39)(cid:39)(cid:20) (cid:27) (cid:28) (cid:20)(cid:19) (cid:20)(cid:20) (cid:20)(cid:21) (cid:20)(cid:22) (cid:20)(cid:23) (cid:20)(cid:24) (cid:20)(cid:25)(cid:20)(cid:26) (cid:51)(cid:37)(cid:23) (cid:39)(cid:20)(cid:21)(cid:22)(cid:19)(cid:20)(cid:21)(cid:22) (cid:38)(cid:39)(cid:39)(cid:39)(cid:37)(cid:37)(cid:37)(cid:37) (cid:47)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:57) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:24)(cid:21)(cid:69) 1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package. 28/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description Table 4. Legend/abbreviation for table 5 Type I= input, O = output, S = power supply FT Five-volt tolerant Level TT 3.6 V tolerant Output HS = high sink/source (20 mA) Port and control Input float = floating, wpu = weak pull-up configuration Output T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Reset state Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L 2 1 1 C3 NRST/PA1(1) I/O X HS X Reset PA1 HSE oscillator input / PA2/OSC_IN/ [USART1 transmit] / 3 2 2 B4 [USART1_TX](4)/ I/O X X X HS X X Port A2 [SPI1 master in- slave [SPI1_MISO] (4) out] / HSE oscillator output / PA3/OSC_OUT/[USART1 4 3 3 C4 I/O X X X HS X X Port A3 [USART1 receive]/ [SPI1 _RX](4)/[SPI1_MOSI](4) master out/slave in]/ Timer 2 - break input / PA4/TIM2_BKIN/ TT LCD COM 0 / ADC1 5 - - - LCD_COM0(2)/ADC1_IN2/ I/O X X X HS X X Port A4 (3) input 2 / Comparator 1 COMP1_INP positive input Timer 2 - break input / PA4/TIM2_BKIN/ [Timer 2 - external [TIM2_ETR](4)/ TT trigger] / LCD_COM 0 / - 4 4 D3 I/O X X X HS X X Port A4 LCD_COM0(2)/ (3) ADC1 input 2 / ADC1_IN2/COMP1_INP Comparator 1 positive input Timer 3 - break input / PA5/TIM3_BKIN/ LCD_COM 1 / ADC1 TT 6 - - - LCD_COM1(2)/ADC1_IN1/ I/O X X X HS X X Port A5 input 1/ (3) COMP1_INP Comparator 1 positive input DocID15962 Rev 15 29/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L Timer 3 - break input / PA5/TIM3_BKIN/ [Timer 3 - external [TIM3_ETR](4)/ TT trigger] / LCD_COM 1 / - 5 5 D4 I/O X X X HS X X Port A5 LCD_COM1(2)/ADC1_IN1/ (3) ADC1 input 1 / COMP1_INP Comparator 1 positive input [ADC1 - trigger] / PA6/[ADC1_TRIG](4)/ LCD_COM2 / TT 7 6 - - LCD_COM2(2)/ADC1_IN0/ I/O X X X HS X X Port A6 ADC1 input 0 / (3) COMP1_INP Comparator 1 positive input 8 - - - PA7/LCD_SEG0(2)(5) I/O FT X X X HS X X Port A7 LCD segment 0 Timer 2 - channel 1 / PB0(6)/TIM2_CH1/ LCD segment 10 / TT 24 13 12 E3 LCD_SEG10(2)/ I/O X(6) X(6) X HS X X Port B0 ADC1_IN18 / (3) ADC1_IN18/COMP1_INP Comparator 1 positive input Timer 3 - channel 1 / PB1/TIM3_CH1/ LCD segment 11 / TT 25 14 13 G1 LCD_SEG11(2)/ I/O X X X HS X X Port B1 ADC1_IN17 / (3) ADC1_IN17/COMP1_INP Comparator 1 positive input Timer 2 - channel 2 / PB2/ TIM2_CH2/ LCD segment 12 / TT 26 15 14 F2 LCD_SEG12(2)/ I/O X X X HS X X Port B2 ADC1_IN16/ (3) ADC1_IN16/COMP1_INP Comparator 1 positive input Timer 2 - external trigger PB3/TIM2_ETR/ / LCD segment 13 TT 27 - - - LCD_SEG13(2)/ I/O X X X HS X X Port B3 /ADC1_IN15 / (3) ADC1_IN15/COMP1_INP Comparator 1 positive input 30/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L [Timer 2 - external trigger] / Timer 1 inverted PB3/[TIM2_ETR](4)/ channel 2 / LCD TIM1_CH2N/LCD_SEG13 TT - 16 - - I/O X X X HS X X Port B3 segment 13 / (2)/ADC1_IN15/ (3) ADC1_IN15 / COMP1_INP Comparator 1 positive input [Timer 2 - external PB3/[TIM2_ETR](4)/ trigger] / Timer 1 inverted TIM1_CH1N/ TT channel 1/ LCD segment - - 15 E2 LCD_SEG13(2)/ I/O X X X HS X X Port B3 (3) 13 / ADC1_IN15 / ADC1_IN15/RTC_ALARM RTC alarm/ Comparator /COMP1_INP 1 positive input [SPI1 master/slave PB4(6)/[SPI1_NSS](4)/ select] / LCD segment TT 28 - - - LCD_SEG14(2)/ I/O X(6) X(6) X HS X X Port B4 14 / ADC1_IN14 / (3) ADC1_IN14/COMP1_INP Comparator 1 positive input [SPI1 master/slave PB4(6)/[SPI1_NSS](4)/ select] / LCD segment LCD_SEG14(2)/ TT 14 / ADC1_IN14 / - 17 16 D2 I/O X(6) X(6) X HS X X Port B4 ADC1_IN14/ (3) DAC output / COMP1_INP/DAC_OUT Comparator 1 positive input [SPI1 clock] / LCD PB5/[SPI1_SCK](4)/ segment 15 / TT 29 - - - LCD_SEG15(2)/ I/O X X X HS X X Port B5 ADC1_IN13 / (3) ADC1_IN13/COMP1_INP Comparator 1 positive input [SPI1 clock] / LCD PB5/[SPI1_SCK](4)/ segment 15 / LCD_SEG15(2)/ TT ADC1_IN13 / DAC - 18 17 D1 I/O X X X HS X X Port B5 ADC1_IN13/DAC_OUT/ (3) output/ COMP1_INP Comparator 1 positive input DocID15962 Rev 15 31/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L [SPI1 master out/slave in]/ PB6/[SPI1_MOSI](4)/ TT LCD segment 16 / 30 - - - LCD_SEG16(2)/ I/O X X X HS X X Port B6 (3) ADC1_IN12 / ADC1_IN12/COMP1_INP Comparator 1 positive input [SPI1 master out]/ PB6/[SPI1_MOSI](4)/ slave in / LCD segment LCD_SEG16(2)/ TT - 19 18 F1 I/O X X X HS X X Port B6 16 / ADC1_IN12 / DAC ADC1_IN12/COMP1_INP/ (3) output / Comparator 1 DAC_OUT positive input [SPI1 master in- slave out] / PB7/[SPI1_MISO](4)/ TT LCD segment 17 / 31 20 19 E1 LCD_SEG17(2)/ I/O X X X HS X X Port B7 (3) ADC1_IN11 / ADC1_IN11/COMP1_INP Comparator 1 positive input 37 25 21 B1 PC0(5)/I2C1_SDA I/O FT X X T(7) Port C0 I2C1 data 38 26 22 A1 PC1(5)/I2C1_SCL I/O FT X X T(7) Port C1 I2C1 clock USART1 receive / PC2/USART1_RX/ LCD segment 22 / TT 41 27 23 B2 LCD_SEG22/ADC1_IN6/ I/O X X X HS X X Port C2 ADC1_IN6 / Comparator (3) COMP1_INP/VREFINT 1 positive input / Internal voltage reference output USART1 transmit / PC3/USART1_TX/ LCD segment 23 / LCD_SEG23(2)/ TT ADC1_IN5 / Comparator 42 28 24 A2 I/O X X X HS X X Port C3 ADC1_IN5/COMP1_INP/ (3) 1 positive input / COMP2_INM Comparator 2 negative input USART1 synchronous clock / I2C1_SMB / PC4/USART1_CK/ Configurable clock I2C1_SMB/CCO/ TT output / LCD segment 24 43 29 25 C2 LCD_SEG24(2)/ I/O X X X HS X X Port C4 (3) / ADC1_IN4 / ADC1_IN4/COMP2_INM/ Comparator 2 negative COMP1_INP input / Comparator 1 positive input 32/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L LSE oscillator input / PC5/OSC32_IN [SPI1 master/slave 44 30 26 A3 /[SPI1_NSS](4)/ I/O X X X HS X X Port C5 select] / [USART1 [USART1_TX](4) transmit] PC6/OSC32_OUT/ LSE oscillator output / 45 31 27 B3 [SPI1_SCK](4)/ I/O X X X HS X X Port C6 [SPI1 clock] / [USART1 [USART1_RX](4) receive] LCD segment 25 PC7/LCD_SEG25(2)/ /ADC1_IN3/ Comparator TT 46 - - - ADC1_IN3/COMP2_INM/ I/O X X X HS X X Port C7 negative input / (3) COMP1_INP Comparator 1 positive input Timer 3 - channel 2 / PD0/TIM3_CH2/ [ADC1_Trigger] / LCD [ADC1_TRIG](4)/ TT segment 7 / ADC1_IN22 20 - 8 G3 LCD_SEG7(2)/ADC1_IN2 I/O X X X HS X X Port D0 (3) / Comparator 2 positive 2/COMP2_INP/ input / Comparator 1 COMP1_INP positive input Timer 3 - channel 2 / PD0/TIM3_CH2/ [ADC1_Trigger] / [ADC1_TRIG](4)/ TT Port ADC1_IN22 / - 9 - - I/O X X X HS X X ADC1_IN22/COMP2_INP/ (3) D0(8) Comparator 2 positive COMP1_INP input / Comparator 1 positive input Timer 3 - external trigger PD1/TIM3_ETR/ / LCD_COM3 / LCD_COM3(2)/ TT ADC1_IN21 / 21 - - - I/O X X X HS X X Port D1 ADC1_IN21/COMP2_INP/ (3) comparator 2 positive COMP1_INP input / Comparator 1 positive input [Timer 3 - external trigger]/ TIM1 inverted PD1/TIM1_CH3N/[TIM3_ channel 3 / LCD_COM3/ ETR](4)/ LCD_COM3(2)/ TT - 10 - - I/O X X X HS X X Port D1 ADC1_IN21 / ADC1_IN21/COMP2_INP/ (3) Comparator 2 positive COMP1_INP input / Comparator 1 positive input DocID15962 Rev 15 33/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L Timer 1 channel 3 / [Timer 3 - external PD1/TIM1_CH3/[TIM3_ET trigger] / LCD_COM3/ R](4)/LCD_COM3(2)/ TT - - 9 G2 I/O X X X HS X X Port D1 ADC1_IN21 / ADC1_IN21/COMP2_INP/ (3) Comparator 2 positive COMP1_INP input / Comparator 1 positive input Timer 1 - channel 1 / PD2/TIM1_CH1 LCD segment 8 / TT 22 11 10 E4 /LCD_SEG8(2)/ I/O X X X HS X X Port D2 ADC1_IN20 / (3) ADC1_IN20/COMP1_INP Comparator 1 positive input Timer 1 - external trigger PD3/ TIM1_ETR/ / LCD segment 9 / TT 23 12 - - LCD_SEG9(2)/ADC1_IN1 I/O X X X HS X X Port D3 ADC1_IN19 / (3) 9/COMP1_INP Comparator 1 positive input Timer 1 - external trigger PD3/ TIM1_ETR/ / LCD segment 9 / LCD_SEG9(2)/ TT ADC1_IN19 / Timer 1 - - 11 F3 ADC1_IN19/TIM1_BKIN/ I/O X X X HS X X Port D3 (3) break input / RTC COMP1_INP/ calibration / Comparator RTC_CALIB 1 positive input Timer 1 - channel 2 / PD4/TIM1_CH2 LCD segment 18 / TT 33 21 20 C1 /LCD_SEG18(2)/ I/O X X X HS X X Port D4 ADC1_IN10/ (3) ADC1_IN10/COMP1_INP Comparator 1 positive input Timer 1 - channel 3 / PD5/TIM1_CH3 TT LCD segment 19 / 34 22 - - /LCD_SEG19(2)/ I/O X X X HS X X Port D5 (3) ADC1_IN9/ Comparator ADC1_IN9/COMP1_INP 1 positive input Timer 1 - break input / PD6/TIM1_BKIN LCD segment 20 / /LCD_SEG20(2)/ ADC1_IN8 / RTC TT 35 23 - - ADC1_IN8/RTC_CALIB/ I/O X X X HS X X Port D6 calibration / Internal (3) /VREFINT/ voltage reference output COMP1_INP / Comparator 1 positive input 34/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L Timer 1 - inverted PD7/TIM1_CH1N channel 1/ LCD segment /LCD_SEG21(2)/ 21 / ADC1_IN7 / RTC TT 36 24 - - ADC1_IN7/RTC_ALARM/ I/O X X X HS X X Port D7 alarm / Internal voltage (3) VREFINT/ reference output COMP1_INP /Comparator 1 positive input 14 - - - PE0(5)/LCD_SEG1(2) I/O FT X X X HS X X Port E0 LCD segment 1 Timer 1 - inverted PE1/TIM1_CH2N TT 15 - - - I/O X X X HS X X Port E1 channel 2 / LCD /LCD_SEG2(2) (3) segment 2 Timer 1 - inverted PE2/TIM1_CH3N TT 16 - - - I/O X X X HS X X Port E2 channel 3 / LCD /LCD_SEG3(2) (3) segment 3 TT 17 - - - PE3/LCD_SEG4(2) I/O X X X HS X X Port E3 LCD segment 4 (3) TT 18 - - - PE4/LCD_SEG5(2) I/O X X X HS X X Port E4 LCD segment 5 (3) LCD segment 6 / PE5/LCD_SEG6(2)/ ADC1_IN23 TT 19 - - - ADC1_IN23/COMP2_INP/ I/O X X X HS X X Port E5 / Comparator 2 positive (3) COMP1_INP input / Comparator 1 positive input PE6/LCD_SEG26(2)/ TT LCD segment 47 - - - I/O X X X HS X X Port E6 PVD_IN (3) 26/PVD_IN TT 48 - - - PE7/LCD_SEG27(2) I/O X X X HS X X Port E7 LCD segment 27 (3) PF0/ADC1_IN24/ TT 32 - - - I/O X X X HS X X Port F0 ADC1_IN24 / DAC_OUT DAC_OUT (3) 13 9 - - VLCD(2) S - - - - - - - LCD booster external capacitor 13 - - - Reserved(8) - - - - - - - - Reserved. Must be tied to V DD 10 - - - V S - - - - - - - Digital power supply DD 11 - - - V S - - - - - - - Analog supply voltage DDA ADC1 and DAC positive voltage 12 - - - V S - - - - - - - REF+ reference DocID15962 Rev 15 35/142 58

Pinout and pin description STM8L151x4/6, STM8L152x4/6 Table 5. Medium-density STM8L151x4/6, STM8L152x4/6 pin description (continued) Pin Input Output number P48/UFQFPN48 P32/UFQFPN32 UFQFPN28 WLCSP28 Pin name Type I/O level floating wpu xt. interrupt h sink/source OD PP Main function(after reset) Defafuulnt catlitoenrnate F F E g Q Q Hi L L Digital power supply / Analog - 8 7 G4 V /V /V S - - - - - - - supply voltage / ADC1 positive DD1 DDA REF+ voltage reference I/O ground / Analog ground voltage 9 7 6 F4 V /V V S - - - - - - - / SS1 SSA/ REF- ADC1 negative voltage reference 39 - - - V S - - - - - - - IOs supply voltage DD2 40 - - - V S - - - - - - - IOs ground voltage SS2 [USART1 synchronous PA0(9)/[USART1_CK](4)/ HS clock](4) / SWIM input 1 32 28 A4 I/O X X(9) X X X Port A0 and output / SWIM/BEEP/IR_TIM (10) (10) Beep output / Infrared Timer output 1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031). 2. Available on STM8L152xx devices only. 3. In the 3.6 V tolerant I/Os, protection diode to V is not implemented. DD 4. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 5. In the 5 V tolerant I/Os, protection diode to V is not implemented. DD 6. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release. 7. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V are DD not implemented). 8. Available on STM8L151xx devices only. 9. The PA0 pin is in input pull-up during the reset phase and after reset release. 10. High Sink LED driver capability available on PA0. Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By default, the slope control is limited to 2 MHz. 36/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Pinout and pin description 4.1 System configuration options As shown in Table 5: Medium-density STM8L151x4/6, STM8L152x4/6 pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “Routing interface (RI) and system configuration controller” section in the STM8L15xxx and STM8L16xxx reference manual (RM0031). DocID15962 Rev 15 37/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:36)(cid:48)(cid:3)(cid:11)(cid:21)(cid:3)(cid:46)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86)(cid:12)(cid:3)(cid:11)(cid:20)(cid:12) (cid:76)(cid:81)(cid:70)(cid:79)(cid:88)(cid:71)(cid:76)(cid:81)(cid:74) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:19)(cid:26)(cid:41)(cid:41) (cid:54)(cid:87)(cid:68)(cid:70)(cid:78)(cid:3)(cid:11)(cid:24)(cid:20)(cid:22)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86)(cid:12)(cid:3)(cid:11)(cid:20)(cid:12) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:19)(cid:27)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:19)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:20)(cid:19)(cid:19)(cid:19) (cid:39)(cid:68)(cid:87)(cid:68)(cid:3)(cid:40)(cid:40)(cid:51)(cid:53)(cid:50)(cid:48) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:20)(cid:22)(cid:41)(cid:41) (cid:11)(cid:20)(cid:3)(cid:46)(cid:69)(cid:92)(cid:87)(cid:72)(cid:12) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:20)(cid:23)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:19)(cid:19) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:82)(cid:85)(cid:87)(cid:86) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:24)(cid:19) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:26)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:26)(cid:19) (cid:39)(cid:48)(cid:36)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:27)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:28)(cid:40) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86) (cid:54)(cid:60)(cid:54)(cid:38)(cid:41)(cid:42) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:27)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:36)(cid:19) (cid:44)(cid:55)(cid:38)(cid:16)(cid:40)(cid:59)(cid:55)(cid:44) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:36)(cid:25) (cid:58)(cid:41)(cid:40) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:37)(cid:19) (cid:53)(cid:54)(cid:55) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:19)(cid:28) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:37)(cid:21) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:20)(cid:19) (cid:57)(cid:53)(cid:40)(cid:41)(cid:44)(cid:49)(cid:55)(cid:66)(cid:41)(cid:68)(cid:70)(cid:87)(cid:82)(cid:85)(cid:92)(cid:66)(cid:38)(cid:50)(cid:49)(cid:57)(cid:11)(cid:21)(cid:12) (cid:51)(cid:58)(cid:53) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:20)(cid:20) (cid:55)(cid:54)(cid:66)(cid:41)(cid:68)(cid:70)(cid:87)(cid:82)(cid:85)(cid:92)(cid:66)(cid:38)(cid:3)(cid:50)(cid:49)(cid:57)(cid:66)(cid:57)(cid:28)(cid:19)(cid:11)(cid:22)(cid:12) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:38)(cid:19) (cid:38)(cid:47)(cid:46) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:20)(cid:21) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:39)(cid:22) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:58)(cid:58)(cid:39)(cid:42) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:21)(cid:24) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:40)(cid:19) (cid:44)(cid:58)(cid:39)(cid:42) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:21)(cid:25) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:22)(cid:20) (cid:56)(cid:81)(cid:76)(cid:84)(cid:88)(cid:72)(cid:3)(cid:44)(cid:39) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:41)(cid:22) (cid:37)(cid:40)(cid:40)(cid:51) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:28)(cid:22)(cid:21) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:20)(cid:23)(cid:19) (cid:53)(cid:55)(cid:38) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:23)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:19)(cid:19) (cid:54)(cid:51)(cid:44)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:20)(cid:19) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:86) (cid:44)(cid:21)(cid:38)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:22)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:26)(cid:41)(cid:41) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:27)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:24)(cid:19) (cid:55)(cid:44)(cid:48)(cid:21) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:27)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:55)(cid:44)(cid:48)(cid:22) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:37)(cid:19) (cid:55)(cid:44)(cid:48)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:25)(cid:19)(cid:19)(cid:19) (cid:37)(cid:82)(cid:82)(cid:87)(cid:3)(cid:53)(cid:50)(cid:48)(cid:3) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:40)(cid:19) (cid:55)(cid:44)(cid:48)(cid:23) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:25)(cid:26)(cid:41)(cid:41) (cid:11)(cid:21)(cid:3)(cid:46)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86)(cid:12) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:21)(cid:41)(cid:41) (cid:44)(cid:53)(cid:55)(cid:44)(cid:48) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:25)(cid:27)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:22)(cid:23)(cid:19) (cid:36)(cid:39)(cid:38)(cid:20) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:22)(cid:27)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:39)(cid:36)(cid:38) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:23)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:26)(cid:40)(cid:41)(cid:41) (cid:47)(cid:38)(cid:39) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:26)(cid:41)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:23)(cid:22)(cid:19) (cid:53)(cid:44) (cid:38)(cid:51)(cid:56)(cid:18)(cid:54)(cid:58)(cid:44)(cid:48)(cid:18)(cid:39)(cid:72)(cid:69)(cid:88)(cid:74)(cid:18)(cid:44)(cid:55)(cid:38) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:24)(cid:23)(cid:23)(cid:19) (cid:38)(cid:50)(cid:48)(cid:51) (cid:53)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:86) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:26)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:27)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:85)(cid:88)(cid:83)(cid:87)(cid:3)(cid:89)(cid:72)(cid:70)(cid:87)(cid:82)(cid:85)(cid:86) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:27)(cid:19)(cid:26)(cid:41) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:27)(cid:19)(cid:27)(cid:19) (cid:48)(cid:72)(cid:71)(cid:76)(cid:88)(cid:80)(cid:16)(cid:71)(cid:72)(cid:81)(cid:86)(cid:76)(cid:87)(cid:92) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:83)(cid:85)(cid:82)(cid:74)(cid:85)(cid:3)(cid:68)(cid:80)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:11)(cid:88)(cid:83)(cid:3)(cid:87)(cid:82)(cid:3)(cid:22)(cid:21)(cid:3)(cid:46)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86)(cid:12)(cid:3) (cid:19)(cid:91)(cid:19)(cid:19)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:48)(cid:54)(cid:22)(cid:21)(cid:25)(cid:22)(cid:21)(cid:57)(cid:20) 1. Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. The VREFINT_Factory_CONV byte represents the LSB of the V 12-bit ADC conversion result. The REFINT MSB have a fixed value: 0x6. 3. The TS_Factory_CONV_V90 byte represents the LSB of the V 12-bit ADC conversion result. The MSB 90 38/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map have a fixed value: 0x3. 4. Refer to Table 9 for an overview of hardware register mapping, to Table 8 for details on I/O port hardware registers, and to Table 10 for information on CPU/SWIM/debug module controller registers. Table 6. Flash and RAM boundary addresses Memory area Size Start address End address RAM 2 Kbyte 0x00 0000 0x00 07FF 16 Kbyte 0x00 8000 0x00 BFFF Flash program memory 32 Kbyte 0x00 8000 0x00 FFFF 5.2 Register map Table 7. Factory conversion registers Reset Address Block Register label Register name status VREFINT_Factory_ Internal reference voltage factory 0x00 4910 - 0xXX CONV(1) conversion TS_Factory_CONV_ 0x00 4911 - Temperature sensor output voltage 0xXX V90(2) 1. The VREFINT_Factory_CONV byte represents the 8 LSB of the result of the VREFINT 12-bit ADC conversion performed in factory. The MSB have a fixed value: 0x6. 2. The TS_Factory_CONV_V90 byte represents the 8 LSB of the result of the V90 12-bit ADC conversion performed in factory. The 2 MSB have a fixed value: 0x3. Table 8. I/O port hardware register map Reset Address Block Register label Register name status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x01 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 DocID15962 Rev 15 39/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 8. I/O port hardware register map (continued) Reset Address Block Register label Register name status 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX 0x00 5016 Port E PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 Table 9. General hardware register map Reset Address Block Register label Register name status 0x00 501E to Reserved area (28 bytes) 0x00 5049 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 Flash program memory unprotection key 0x00 5052 FLASH _PUKR 0x00 Flash register 0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00 Flash in-application programming status 0x00 5054 FLASH _IAPSR 0x00 register 40/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5055 to Reserved area (27 bytes) 0x00 506F DMA1 global configuration & status 0x00 5070 DMA1_GCSR 0xFC register 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 0x00 5072 to Reserved area (3 bytes) 0x00 5074 0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00 DMA1 number of data to transfer register 0x00 5077 DMA1_C0NDTR 0x00 (channel 0) DMA1 peripheral address high register 0x00 5078 DMA1_C0PARH 0x52 (channel 0) DMA1 peripheral address low register 0x00 5079 DMA1_C0PARL 0x00 (channel 0) 0x00 507A Reserved area (1 byte) DMA1 DMA1 memory 0 address high register 0x00 507B DMA1_C0M0ARH 0x00 (channel 0) DMA1 memory 0 address low register 0x00 507C DMA1_C0M0ARL 0x00 (channel 0) 0x00 507D to Reserved area (2 bytes) 0x00 507E 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00 DMA1 number of data to transfer register 0x00 5081 DMA1_C1NDTR 0x00 (channel 1) DMA1 peripheral address high register 0x00 5082 DMA1_C1PARH 0x52 (channel 1) DMA1 peripheral address low register 0x00 5083 DMA1_C1PARL 0x00 (channel 1) DocID15962 Rev 15 41/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5084 Reserved area (1 byte) DMA1 memory 0 address high register 0x00 5085 DMA1_C1M0ARH 0x00 (channel 1) DMA1 memory 0 address low register 0x00 5086 DMA1_C1M0ARL 0x00 (channel 1) 0x00 5087 Reserved area (2 bytes) 0x00 5088 0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00 DMA1 number of data to transfer register 0x00 508B DMA1_C2NDTR 0x00 (channel 2) DMA1 peripheral address high register 0x00 508C DMA1_C2PARH 0x52 (channel 2) DMA1 peripheral address low register 0x00 508D DMA1_C2PARL 0x00 (channel 2) 0x00 508E Reserved area (1 byte) DMA1 memory 0 address high register 0x00 508F DMA1_C2M0ARH 0x00 (channel 2) DMA1 DMA1 memory 0 address low register 0x00 5090 DMA1_C2M0ARL 0x00 (channel 2) 0x00 5091 Reserved area (2 bytes) 0x00 5092 0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00 DMA1 number of data to transfer register 0x00 5095 DMA1_C3NDTR 0x00 (channel 3) DMA1_C3PARH_ DMA1 peripheral address high register 0x00 5096 0x40 C3M1ARH (channel 3) DMA1_C3PARL_ DMA1 peripheral address low register 0x00 5097 0x00 C3M1ARL (channel 3) 0x00 5098 Reserved area (1 byte) DMA1 memory 0 address high register 0x00 5099 DMA1_C3M0ARH 0x00 (channel 3) DMA1 memory 0 address low register 0x00 509A DMA1_C3M0ARL 0x00 (channel 3) 0x00 509B to Reserved area (3 bytes) 0x00 509D 0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00 SYSCFG 0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00 42/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00 ITC - EXTI 0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE_CR1 WFE control register 1 0x00 0x00 50A7 WFE WFE_CR2 WFE control register 2 0x00 0x00 50A8 WFE_CR3 WFE control register 3 0x00 0x00 50A9 to Reserved area (7 bytes) 0x00 50AF 0x00 50B0 RST_CR Reset control register 0x00 RST 0x00 50B1 RST_SR Reset status register 0x01 0x00 50B2 PWR_CSR1 Power control and status register 1 0x00 PWR 0x00 50B3 PWR_CSR2 Power control and status register 2 0x00 0x00 50B4 to Reserved area (12 bytes) 0x00 50BF 0x00 50C0 CLK_DIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 0x00 50C7 CLK_SCSR System clock status register 0x01 CLK 0x00 50C8 CLK_SWR System clock switch register 0x01 0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000 0x00 50CA CLK_CSSR Clock security system register 0x00 0x00 50CB CLK_CBEEPR Clock BEEP register 0x00 0x00 50CC CLK_HSICALR HSI calibration register 0xxx 0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x DocID15962 Rev 15 43/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 50D0 to Reserved area (3 bytes) 0x00 50D2 0x00 50D3 WWDG_CR WWDG control register 0x7F WWDG 0x00 50D4 WWDG_WR WWDR window register 0x7F 0x00 50D5 to Reserved area (11 bytes) 00 50DF 0x00 50E0 IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to Reserved area (13 bytes) 0x00 50EF 0x00 50F0 BEEP_CSR1 BEEP control/status register 1 0x00 0x00 50F1 BEEP Reserved area (2 bytes) 0x00 50F2 0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F 0x00 50F4 to Reserved area (76 bytes) 0x00 513F 44/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5140 RTC_TR1 Time register 1 0x00 0x00 5141 RTC_TR2 Time register 2 0x00 0x00 5142 RTC_TR3 Time register 3 0x00 0x00 5143 Reserved area (1 byte) 0x00 5144 RTC_DR1 Date register 1 0x01 0x00 5145 RTC_DR2 Date register 2 0x21 0x00 5146 RTC_DR3 Date register 3 0x00 0x00 5147 Reserved area (1 byte) 0x00 5148 RTC_CR1 Control register 1 0x00 0x00 5149 RTC_CR2 Control register 2 0x00 0x00 514A RTC_CR3 Control register 3 0x00 0x00 514B Reserved area (1 byte) 0x00 514C RTC_ISR1 Initialization and status register 1 0x00 0x00 514D RTC_ISR2 Initialization and Status register 2 0x00 0x00 514E RTC Reserved area (2 bytes) 0x00 514F 0x00 5150 RTC_SPRERH(1) Synchronous prescaler register high 0x00(1) 0x00 5151 RTC_SPRERL(1) Synchronous prescaler register low 0xFF(1) 0x00 5152 RTC_APRER(1) Asynchronous prescaler register 0x7F(1) 0x00 5153 Reserved area (1 byte) 0x00 5154 RTC_WUTRH(1) Wakeup timer register high 0xFF(1) 0x00 5155 RTC_WUTRL(1) Wakeup timer register low 0xFF(1) 0x00 5156 to Reserved area (3 bytes) 0x00 5158 0x00 5159 RTC_WPR Write protection register 0x00 0x00 515A Reserved area (2 bytes) 0x00 515B 0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00 0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00 0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00 0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00 0x00 5160 to Reserved area (160 bytes) 0x00 51FF DocID15962 Rev 15 45/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5200 SPI1_CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00 0x00 5203 SPI1_SR SPI1 status register 0x02 SPI1 0x00 5204 SPI1_DR SPI1 data register 0x00 0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00 0x00 5208 to Reserved area (8 bytes) 0x00 520F 0x00 5210 I2C1_CR1 I2C1 control register 1 0x00 0x00 5211 I2C1_CR2 I2C1 control register 2 0x00 0x00 5212 I2C1_FREQR I2C1 frequency register 0x00 0x00 5213 I2C1_OARL I2C1 own address register low 0x00 0x00 5214 I2C1_OARH I2C1 own address register high 0x00 0x00 5215 Reserved (1 byte) 0x00 5216 I2C1_DR I2C1 data register 0x00 0x00 5217 I2C1 I2C1_SR1 I2C1 status register 1 0x00 0x00 5218 I2C1_SR2 I2C1 status register 2 0x00 0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x 0x00 521A I2C1_ITR I2C1 interrupt control register 0x00 0x00 521B I2C1_CCRL I2C1 clock control register low 0x00 0x00 521C I2C1_CCRH I2C1 clock control register high 0x00 0x00 521D I2C1_TRISER I2C1 TRISE register 0x02 0x00 521E I2C1_PECR I2C1 packet error checking register 0x00 0x00 521F to Reserved area (17 bytes) 0x00 522F 46/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5230 USART1_SR USART1 status register 0xC0 0x00 5231 USART1_DR USART1 data register undefined 0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1_CR1 USART1 control register 1 0x00 0x00 5235 USART1 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 0x00 523B to Reserved area (21 bytes) 0x00 524F DocID15962 Rev 15 47/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2_SR1 TIM2 status register 1 0x00 0x00 5257 TIM2_SR2 TIM2 status register 2 0x00 0x00 5258 TIM2_EGR TIM2 event generation register 0x00 0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 525B TIM2 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 525C TIM2_CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5265 TIM2_BKR TIM2 break register 0x00 0x00 5266 TIM2_OISR TIM2 output idle state register 0x00 0x00 5267 to Reserved area (25 bytes) 0x00 527F 48/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3_SR1 TIM3 status register 1 0x00 0x00 5287 TIM3_SR2 TIM3 status register 2 0x00 0x00 5288 TIM3_EGR TIM3 event generation register 0x00 0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00 0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00 0x00 528B TIM3 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00 0x00 528C TIM3_CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF 0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF 0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00 0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00 0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 0x00 5297 to Reserved area (25 bytes) 0x00 52AF DocID15962 Rev 15 49/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00 0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00 0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00 0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00 0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00 0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00 0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00 0x00 52B8 TIM1_EGR TIM1 event generation register 0x00 0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00 0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00 0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00 0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00 0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00 0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00 0x00 52BF TIM1_CNTRH TIM1 counter high 0x00 0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00 TIM1 0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF 0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF 0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00 0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00 0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00 0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00 0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00 0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00 0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00 0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00 0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00 0x00 52CE TIM1_BKR TIM1 break register 0x00 0x00 52CF TIM1_DTR TIM1 dead-time register 0x00 0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00 0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00 50/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 52D2 TIM1_DCR2 TIM1 DMA1 control register 2 0x00 TIM1 0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00 0x00 52D4 to Reserved area (12 bytes) 0x00 52DF 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00 0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00 TIM4 0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00 0x00 52EA to Reserved area (21 bytes) 0x00 52FE 0x00 52FF IRTIM IR_CR Infrared control register 0x00 0x00 5300 to Reserved area (64 bytes) 0x00 533F 0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F 0x00 5343 ADC1_SR ADC1 status register 0x00 0x00 5344 ADC1_DRH ADC1 data register high 0x00 0x00 5345 ADC1_DRL ADC1 data register low 0x00 0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F ADC1 0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF 0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00 0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 DocID15962 Rev 15 51/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00 ADC1 0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 0x00 5352 to Reserved area (46 bytes) 0x00 537F 0x00 5380 DAC_CR1 DAC control register 1 0x00 0x00 5381 DAC_CR2 DAC control register 2 0x00 0x00 5382 Reserved area (2 bytes) to 0x00 5383 0x00 5384 DAC_SWTRIGR DAC software trigger register 0x00 0x00 5385 DAC_SR DAC status register 0x00 0x00 5386 to Reserved area (2 bytes) 0x00 5387 DAC right aligned data holding register 0x00 5388 DAC_RDHRH 0x00 high 0x00 5389 DAC_RDHRL DAC right aligned data holding register low 0x00 DAC 0x00 538A to Reserved area (2 bytes) 0x00 538B 0x00 538C DAC_LDHRH DAC left aligned data holding register high 0x00 0x00 538D DAC_LDHRL DAC left aligned data holding register low 0x00 0x00 538E Reserved area (2 bytes) to 0x00 538F 0x00 5390 DAC_DHR8 DAC 8-bit data holding register 0x00 0x00 5391 to Reserved area (27 bytes) 0x00 53AB 0x00 53AC DAC_DORH DAC data output register high 0x00 0x00 53AD DAC_DORL DAC data output register low 0x00 0x00 53AE to Reserved area (82 bytes) 0x00 53FF 52/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5400 LCD_CR1 LCD control register 1 0x00 0x00 5401 LCD_CR2 LCD control register 2 0x00 0x00 5402 LCD_CR3 LCD control register 3 0x00 0x00 5403 LCD_FRQ LCD frequency selection register 0x00 LCD 0x00 5404 LCD_PM0 LCD Port mask register 0 0x00 0x00 5405 LCD_PM1 LCD Port mask register 1 0x00 0x00 5406 LCD_PM2 LCD Port mask register 2 0x00 0x00 5407 LCD_PM3 LCD Port mask register 3 0x00 0x00 5408 to Reserved area (4 bytes) 0x00 540B 0x00 540C LCD_RAM0 LCD display memory 0 0x00 0x00 540D LCD_RAM1 LCD display memory 1 0x00 0x00 540E LCD_RAM2 LCD display memory 2 0x00 0x00 540F LCD_RAM3 LCD display memory 3 0x00 0x00 5410 LCD_RAM4 LCD display memory 4 0x00 0x00 5411 LCD_RAM5 LCD display memory 5 0x00 LCD 0x00 5412 LCD_RAM6 LCD display memory 6 0x00 0x00 5413 LCD_RAM7 LCD display memory 7 0x00 0x00 5414 LCD_RAM8 LCD display memory 8 0x00 0x00 5415 LCD_RAM9 LCD display memory 9 0x00 0x00 5416 LCD_RAM10 LCD display memory 10 0x00 0x00 5417 LCD_RAM11 LCD display memory 11 0x00 0x00 5418 LCD_RAM12 LCD display memory 12 0x00 0x00 5419 LCD_RAM13 LCD display memory 13 0x00 0x00 541A to Reserved area (22 bytes) 0x00 542F DocID15962 Rev 15 53/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5430 Reserved area (1 byte) 0x00 0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00 0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00 0x00 5433 RI_IOIR1 I/O input register 1 undefined 0x00 5434 RI_IOIR2 I/O input register 2 undefined 0x00 5435 RI_IOIR3 I/O input register 3 undefined 0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00 0x00 5437 RI_IOCMR2 I/O control mode register 2 0x00 RI 0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00 0x00 5439 RI_IOSR1 I/O switch register 1 0x00 0x00 543A RI_IOSR2 I/O switch register 2 0x00 0x00 543B RI_IOSR3 I/O switch register 3 0x00 0x00 543C RI_IOGCR I/O group control register 0x3F 0x00 543D RI_ASCR1 Analog switch register 1 0x00 0x00 543E RI_ASCR2 Analog switch register 2 0x00 0x00 543F RI_RCR Resistor control register 1 0x00 0x00 5440 COMP_CSR1 Comparator control and status register 1 0x00 0x00 5441 COMP_CSR2 Comparator control and status register 2 0x00 0x00 5442 COMP COMP_CSR3 Comparator control and status register 3 0x00 0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00 0x00 5444 COMP_CSR5 Comparator control and status register 5 0x00 1. These registers are not impacted by a system reset. They are reset at power-on. 54/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Memory and register map Table 10. CPU/SWIM/debug module/interrupt controller registers Reset Address Block Register Label Register Name Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU(1) XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 0x00 7F0B to Reserved area (85 byte) 0x00 7F5F CPU 0x00 7F60 CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF ITC-SPR 0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F78 to Reserved area (2 byte) 0x00 7F79 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 0x00 7F81 to Reserved area (15 byte) 0x00 7F8F DocID15962 Rev 15 55/142 58

Memory and register map STM8L151x4/6, STM8L152x4/6 Table 10. CPU/SWIM/debug module/interrupt controller registers (continued) Reset Address Block Register Label Register Name Status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM Debug module control register 1 0x00 0x00 7F97 DM_CR2 DM Debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F9B to Reserved area (5 byte) 0x00 7F9F 1. Accessible by debug module only 56/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Interrupt vector mapping 6 Interrupt vector mapping Table 11. Interrupt mapping Wakeup Wakeup Wakeup Wakeup IRQ Source from from Wait from Wait Vector Description from Halt No. block Active-halt (WFI (WFE address mode mode mode) mode)(1) - RESET Reset Yes Yes Yes Yes 0x00 8000 - TRAP Software interrupt - - - - 0x00 8004 0 Reserved 0x00 8008 FLASH end of programing/ 1 FLASH write attempted to - - Yes Yes 0x00 800C protected page interrupt DMA1 channels 0/1 half 2 DMA1 0/1 transaction/transaction - - Yes Yes 0x00 8010 complete interrupt DMA1 channels 2/3 half 3 DMA1 2/3 transaction/transaction - - Yes Yes 0x00 8014 complete interrupt RTC alarm A/ 4 RTC Yes Yes Yes Yes 0x00 8018 wakeup EXTI E/F/ External interrupt port E/F 5 Yes Yes Yes Yes 0x00 801C PVD(2) PVD interrupt 6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes 0x00 8020 7 EXTID/H External interrupt port D/H Yes Yes Yes Yes 0x00 8024 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 LCD LCD interrupt - - Yes Yes 0x00 8048 CLK system clock switch/ CLK/TIM1/ 17 CSS interrupt/ - - Yes Yes 0x00 804C DAC TIM 1 break/DAC COMP1 interrupt COMP1/ COMP2 interrupt 18 COMP2/ ACD1 end of conversion/ Yes Yes Yes Yes 0x00 8050 ADC1 analog watchdog/ overrun interrupt DocID15962 Rev 15 57/142 58

Interrupt vector mapping STM8L151x4/6, STM8L152x4/6 Table 11. Interrupt mapping (continued) Wakeup Wakeup Wakeup Wakeup IRQ Source from from Wait from Wait Vector Description from Halt No. block Active-halt (WFI (WFE address mode mode mode) mode)(1) TIM2 update/overflow/ 19 TIM2 - - Yes Yes 0x00 8054 trigger/break interrupt TIM2 capture/ 20 TIM2 - - Yes Yes 0x00 8058 compare interrupt TIM3 update/overflow/ 21 TIM3 - - Yes Yes 0x00 805C trigger/break interrupt TIM3 capture/ 22 TIM3 - - Yes Yes 0x00 8060 compare interrupt Update /overflow/trigger/ 23 TIM1 - - - Yes 0x00 8064 COM 24 TIM1 Capture/compare - - - Yes 0x00 8068 TIM4 update/overflow/ 25 TIM4 - - Yes Yes 0x00 806C trigger interrupt SPI1 TX buffer empty/ 26 SPI1 RX buffer not empty/ Yes Yes Yes Yes 0x00 8070 error/wakeup interrupt USART1 transmit data register empty/ 27 USART1 - - Yes Yes 0x00 8074 transmission complete interrupt USART1 received data ready/overrun error/ 28 USART1 - - Yes Yes 0x00 8078 idle line detected/parity error/global error interrupt 29 I2C1 I2C1 interrupt(3) Yes Yes Yes Yes 0x00 807C 1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. 2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031). 3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. 58/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Option bytes 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 12 for details on option byte addresses. The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for the ROP and UBC values which can only be taken into account when they are modified in ICP mode (with the SWIM). Refer to the STM8L15x Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0470) for information on SWIM programming procedures. Table 12. Option byte addresses Option Option bits Factory Addr. Option name byte default No. 7 6 5 4 3 2 1 0 setting Read-out 0x00 4800 protection OPT0 ROP[7:0] 0xAA (ROP) UBC (User 0x00 4802 OPT1 UBC[7:0] 0x00 Boot code size) 0x00 4807 Reserved 0x00 Independent OPT3 WWDG WWDG IWDG IWDG 0x00 4808 watchdog Reserved 0x00 [3:0] _HALT _HW _HALT _HW option Number of stabilization 0x00 4809 clock cycles for OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00 HSE and LSE oscillators Brownout reset OPT5 BOR_ 0x00 480A Reserved BOR_TH 0x00 (BOR) [3:0] ON 0x00 480B Bootloader 0x00 OPTBL option bytes OPTBL[15:0] 0x00 480C (OPTBL) [15:0] 0x00 DocID15962 Rev 15 59/142 61

Option bytes STM8L151x4/6, STM8L152x4/6 Table 13. Option byte description Option byte Option description No. ROP[7:0] Memory readout protection (ROP) OPT0 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031). UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01: the UBC contains only the interrupt vectors. 0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt OPT1 vectors. 0x03 - Page 0 to 2 reserved for UBC, memory write-protected 0xFF - Page 0 to 254 reserved for UBC, memory write-protected Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031). OPT2 Reserved IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent window watchdog off on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode OPT3 WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles Refer to Table 32: LSE oscillator characteristics on page 84. 60/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Option bytes Table 13. Option byte description (continued) Option byte Option description No. BOR_ON: 0: Brownout reset off OPT5 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 23 for details on the thresholds according to the value of BOR_TH bits. OPTBL[15:0]: This option is checked by the boot ROM code after reset. Depending on OPTBL content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 bootloader user manual for more details. DocID15962 Rev 15 61/142 61

Unique ID STM8L151x4/6, STM8L152x4/6 8 Unique ID STM8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: • For use as serial numbers • For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory. • To activate secure boot processes Table 14. Unique ID registers (96 bits) Unique ID bits Content Address description 7 6 5 4 3 2 1 0 0x4926 X co-ordinate on U_ID[7:0] 0x4927 the wafer U_ID[15:8] 0x4928 Y co-ordinate on U_ID[23:16] the wafer 0x4929 U_ID[31:24] 0x492A Wafer number U_ID[39:32] 0x492B U_ID[47:40] 0x492C U_ID[55:48] 0x492D U_ID[63:56] 0x492E Lot number U_ID[71:64] 0x492F U_ID[79:72] 0x4930 U_ID[87:80] 0x4931 U_ID[95:88] 62/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to V . SS 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 9.1.2 Typical values Unless otherwise specified, typical data is based on T = 25 °C, V = 3 V. It is given only as A DD design guidelines and is not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions (cid:54)(cid:55)(cid:48)(cid:27)(cid:36)(cid:47)(cid:3)(cid:51)(cid:44)(cid:49) (cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:26)(cid:26)(cid:23)(cid:57)(cid:20) DocID15962 Rev 15 63/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage (cid:54)(cid:55)(cid:48)(cid:27)(cid:54)(cid:3)(cid:51)(cid:44)(cid:49) (cid:57) (cid:44)(cid:49) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:26)(cid:26)(cid:24)(cid:57)(cid:20) 9.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics, Table 16: Current characteristics, and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 15. Voltage characteristics Symbol Ratings Min Max Unit External supply voltage (including V V - V DDA - 0.3 4.0 V DD SS and V )(1) DD2 Input voltage on true open-drain pins V - 0.3 V + 4.0 (PC0 and PC1) SS DD Input voltage on five-volt tolerant (FT) VIN(2) pins (PA7 and PE0) VSS - 0.3 VDD + 4.0 V Input voltage on 3.6 V tolerant (TT) pins V - 0.3 4.0 SS Input voltage on any other pin V - 0.3 4.0 SS see Absolute maximum V Electrostatic discharge voltage ratings (electrical sensitivity) ESD on page 115 1. All power (V , V , V ) and ground (V , V , V ) pins must always be connected to the DD1 DD2 DDA SS1 SS2 SSA external power supply. 2. V maximum must always be respected. Refer to Table 16. for maximum allowed injected current values. IN 64/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Table 16. Current characteristics Symbol Ratings Max. Unit I Total current into V power line (source) 80 VDD DD I Total current out of V ground line (sink) 80 VSS SS Output current sunk by IR_TIM pin (with high sink LED driver 80 mA capability) I IO Output current sunk by any other I/O and control pin 25 Output current sourced by any I/Os and control pin - 25 Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0 Injected current on five-volt tolerant (FT) pins (PA7 and PE0) (1) - 5 / +0 I mA INJ(PIN) Injected current on 3.6 V tolerant (TT) pins (1) - 5 / +0 Injected current on any other pin (2) - 5 / +5 ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) (3) ± 25 1. Positive injection is not possible on these I/Os. A negative injection is induced by V <V . I must IN SS INJ(PIN) never be exceeded. Refer to Table 15. for maximum allowed input voltage values. 2. A positive injection is induced by V >V while a negative injection is induced by V <V . I must IN DD IN SS INJ(PIN) never be exceeded. Refer to Table 15. for maximum allowed input voltage values. 3. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the INJ(PIN) positive and negative injected currents (instantaneous values). Table 17. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range -65 to +150 STG ° C T Maximum junction temperature 150 J DocID15962 Rev 15 65/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3 Operating conditions Subject to general operating conditions for V and T . DD A 9.3.1 General operating conditions Table 18. General operating conditions Symbol Parameter Conditions Min. Max. Unit System clock f (1) 1.65 V ≤ V < 3.6 V 0 16 MHz SYSCLK frequency DD Standard operating V - 1.65(2) 3.6 V DD voltage ADC and DAC 1.65(2) 3.6 V Analog operating not used Must be at the same V DDA voltage ADC or DAC potential as VDD 1.8 3.6 V used LQFP48 - 288 UFQFPN48 - 169 Power dissipation at LQFP32 - 288 T = 85 °C for suffix 6 A devices UFQFPN32 - 169 UFQFPN28 - 169 WLCSP28 - 286 P (3) mW D LQFP48 - 77 Power dissipation at UFQFPN48 - 156 TA= 125 °C for suffix 3 LQFP32 - 85 devices and at T = 105 °C for suffix 7 UFQFPN32 - 131 A devices UFQFPN28 - 42 WLCSP28 - 71 1.65 V ≤ V < 3.6 V (6 suffix version) -40 85 DD T Temperature range 1.65 V ≤ V < 3.6 V (7 suffix version) -40 105 °C A DD 1.65 V ≤ V < 3.6 V (3 suffix version) -40 125 DD -40 °C ≤ T < 85 °C A -40 105(4) (6 suffix version) Junction temperature -40 °C ≤ T < 105 °C T A -40 110(4) °C J range (7 suffix version) -40 °C ≤ T < 125 °C A -40 130 (3 suffix version) 1. f = f SYSCLK CPU 2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled Θ Θ 3. To calculate P (T ), use the formula P =(T -T )/ with T in this table and in “Thermal characteristics” Dmax A Dmax Jmax A JA Jmax JA table. 4. T is given by the test limit. Above this value the product behavior is not guaranteed. Jmax 66/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 9.3.2 Embedded reset and power control block characteristics Table 19. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit BOR detector VDD rise time rate enabled 0(1) - ∞ (1) t µs/V VDD BOR detector VDD fall time rate enabled 20(1) - ∞ (1) V rising DD BOR detector - 3 - enabled t Reset release delay ms TEMP V rising DD BOR detector - 1 - disabled V Power-down reset threshold Falling edge 1.30(2) 1.50 1.65 V PDR Brown-out reset threshold 0 Falling edge 1.67 1.70 1.74 V BOR0 (BOR_TH[2:0]=000) Rising edge 1.69 1.75 1.80 Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97 V BOR1 (BOR_TH[2:0]=001) Rising edge 1.96 2.04 2.07 Brown-out reset threshold 2 Falling edge 2.22 2.3 2.35 V V BOR2 (BOR_TH[2:0]=010) Rising edge 2.31 2.41 2.44 Brown-out reset threshold 3 Falling edge 2.45 2.55 2.60 V BOR3 (BOR_TH[2:0]=011) Rising edge 2.54 2.66 2.7 Brown-out reset threshold 4 Falling edge 2.68 2.80 2.85 V BOR4 (BOR_TH[2:0]=100) Rising edge 2.78 2.90 2.95 Falling edge 1.80 1.84 1.88 V PVD threshold 0 PVD0 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 V PVD threshold 1 PVD1 Rising edge 2.08 2.14 2.18 Falling edge 2.2 2.24 2.28 V PVD threshold 2 PVD2 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 V PVD threshold 3 V PVD3 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 V PVD threshold 4 PVD4 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 V PVD threshold 5 PVD5 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 V PVD threshold 6 PVD6 Rising edge 3.08 3.15 3.20 DocID15962 Rev 15 67/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 1. Data guaranteed by design. 2. Data based on characterization results. Figure 12. POR/BOR thresholds (cid:57)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39) (cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:50)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:86)(cid:88)(cid:83)(cid:83)(cid:79)(cid:3)(cid:92) (cid:57)(cid:39)(cid:39) (cid:37)(cid:50)(cid:53)(cid:3)(cid:87)(cid:75)(cid:85)(cid:72)(cid:86)(cid:75)(cid:82)(cid:79)(cid:71)(cid:66)(cid:19) (cid:37)(cid:50)(cid:53)(cid:3)(cid:3)(cid:87)(cid:75)(cid:85)(cid:72)(cid:86)(cid:75)(cid:82)(cid:79)(cid:71) (cid:20)(cid:17)(cid:27)(cid:3)(cid:57) (cid:57)(cid:37)(cid:50)(cid:53)(cid:19) (cid:90)(cid:76)(cid:87)(cid:75)(cid:82)(cid:88)(cid:87)(cid:3)(cid:37)(cid:50)(cid:53)(cid:3)(cid:32)(cid:3)(cid:3)(cid:69)(cid:68)(cid:87)(cid:87)(cid:72)(cid:85)(cid:92)(cid:3)(cid:3)(cid:79)(cid:76)(cid:73)(cid:72)(cid:3)(cid:3)(cid:72)(cid:91)(cid:87)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81) (cid:72) (cid:86) (cid:68) (cid:3)(cid:68)(cid:73)(cid:72)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:85)(cid:72)(cid:79)(cid:72) (cid:54)(cid:68)(cid:73)(cid:72)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3) (cid:53)(cid:72)(cid:86)(cid:72)(cid:87) (cid:51)(cid:39)(cid:53)(cid:3)(cid:87)(cid:3)(cid:75)(cid:85)(cid:72)(cid:86)(cid:75)(cid:82)(cid:79)(cid:71) (cid:57)(cid:51)(cid:39)(cid:53) (cid:54) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:49)(cid:53)(cid:54)(cid:55) (cid:90)(cid:76)(cid:87)(cid:75) (cid:90)(cid:76)(cid:87)(cid:75) (cid:90)(cid:76)(cid:87)(cid:75)(cid:82)(cid:88)(cid:87) (cid:37)(cid:50)(cid:53) (cid:37)(cid:50)(cid:53)(cid:3) (cid:37)(cid:50)(cid:53) (cid:55)(cid:76)(cid:80)(cid:72) (cid:37)(cid:50)(cid:53)(cid:3)(cid:68)(cid:79)(cid:90)(cid:68)(cid:92)(cid:86)(cid:3)(cid:68)(cid:70)(cid:87)(cid:76)(cid:89)(cid:72)(cid:3)(cid:3) (cid:37)(cid:50)(cid:53)(cid:3)(cid:68)(cid:70)(cid:87)(cid:76)(cid:89)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:69)(cid:92)(cid:3)(cid:88)(cid:86)(cid:72)(cid:85)(cid:3) (cid:68)(cid:87)(cid:3)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:88)(cid:83) (cid:73)(cid:82)(cid:85)(cid:3)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:16)(cid:71)(cid:82)(cid:90)(cid:81)(cid:3)(cid:71)(cid:72)(cid:87)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81) (cid:68)(cid:76)(cid:20)(cid:26)(cid:19)(cid:22)(cid:22)(cid:69) 9.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: l All I/O pins in input mode with a static value at V or V (no load) DD SS l All peripherals are disabled except if explicitly mentioned. In the following table, data is based on characterization results, unless otherwise specified. Subject to general operating conditions for V and T . DD A 68/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Table 20. Total current consumption in Run mode Max Para Symbol Conditions(1) Typ Unit meter 55 °C 85 °C(2) 105°C(3) 125 °C(4) fCPU = 125 kHz 0.39 0.47 0.49 0.52 0.55 fCPU = 1 MHz 0.48 0.56 0.58 0.61 0.65 HSI RC osc. (16 MHz)(6) fCPU = 4 MHz 0.75 0.84 0.86 0.91 0.99 fCPU = 8 MHz 1.10 1.20 1.25 1.31 1.40 All fCPU = 16 MHz 1.85 1.93 2.12(8) 2.29(8) 2.36(8) peripherals OFF, fCPU = 125 kHz 0.05 0.06 0.09 0.11 0.12 Supply code IDD(RUN) cinu rrurenn t executed HSE external fCPU = 1 MHz 0.18 0.19 0.20 0.22 0.23 mA mode(5) from RAM, clock fCPU = 4 MHz 0.55 0.62 0.64 0.71 0.77 VDD from (f =f )(7) 1.65 V to CPU HSE fCPU = 8 MHz 0.99 1.20 1.21 1.22 1.24 3.6 V fCPU = 16 MHz 1.90 2.22 2.23(8) 2.24(8) 2.28(8) LSI RC osc. (typ. 38 kHz) fCPU = fLSI 0.040 0.045 0.046 0.048 0.050 LSE external clock fCPU = fLSE 0.035 0.040 0.048(8) 0.050 0.062 (32.768 kHz) fCPU = 125 kHz 0.43 0.55 0.56 0.58 0.62 fCPU = 1 MHz 0.60 0.77 0.80 0.82 0.87 HSI RC osc.(9) fCPU = 4 MHz 1.11 1.34 1.37 1.39 1.43 fCPU = 8 MHz 1.90 2.20 2.23 2.31 2.40 All fCPU = 16 MHz 3.8 4.60 4.75 4.87 4.88 peripherals fCPU = 125 kHz 0.30 0.36 0.39 0.44 0.47 Supply OFF, code current executed HSE external fCPU = 1 MHz 0.40 0.50 0.52 0.55 0.56 IDD(RUN) in Run from Flash, clock mA mode VDD from (fCPU=fHSE) fCPU = 4 MHz 1.15 1.31 1.40 1.45 1.48 1.65 V to (7) fCPU = 8 MHz 2.17 2.33 2.44 2.56 2.77 3.6 V fCPU = 16 MHz 4.0 4.46 4.52 4.59 4.77 LSI RC osc. fCPU = fLSI 0.110 0.123 0.130 0.140 0.150 LSE ext. clock (32.768 fCPU = fLSE 0.100 0.101 0.104 0.119 0.122 kHz)(10) 1. All peripherals OFF, V from 1.65 V to 3.6 V, HSI internal RC osc., f =f DD CPU SYSCLK 2. For devices with suffix 6 3. For devices with suffix 7 4. For devices with suffix 3 DocID15962 Rev 15 69/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 5. CPU executing typical data processing 6. The run from RAM consumption can be approximated with the linear formula: I (run_from_RAM) = Freq * 90 µA/MHz + 380 µA DD 7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (I ) must be added. Refer to Table 31. DD HSE 8. Tested in production. 9. The run from Flash consumption can be approximated with the linear formula: I (run_from_Flash) = Freq * 195 µA/MHz + 440 µA DD 10. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (I ) must be added. Refer to Table 32. DD LSE Figure 13. Typ. I vs. V , f = 16 MHz DD(RUN) DD CPU (cid:22)(cid:17)(cid:19)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:21)(cid:17)(cid:26)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:80)(cid:36)(cid:64) (cid:21)(cid:17)(cid:24)(cid:19) (cid:54)(cid:44)(cid:3)(cid:62) (cid:43) (cid:49)(cid:12) (cid:21)(cid:17)(cid:21)(cid:24) (cid:56) (cid:53) (cid:39)(cid:11) (cid:39) (cid:21)(cid:17)(cid:19)(cid:19) (cid:44) (cid:20)(cid:17)(cid:26)(cid:24) (cid:20)(cid:17)(cid:24)(cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57) (cid:62)(cid:57)(cid:64) (cid:39)(cid:39)(cid:3) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:22)(cid:69) 1. Typical current consumption measured with code executed from RAM 70/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 21. Total current consumption in Wait mode Max Symbol Parameter Conditions(1) Typ 85 105 °C 125 °C Unit 55°C °C(2) (3) (4) fCPU = 125 kHz 0.33 0.39 0.41 0.43 0.45 fCPU = 1 MHz 0.35 0.41 0.44 0.45 0.48 HSI fCPU = 4 MHz 0.42 0.51 0.52 0.54 0.58 fCPU = 8 MHz 0.52 0.57 0.58 0.59 0.62 0.82 0.85 CPU not fCPU = 16 MHz 0.68 0.76 0.79 (7) (7) clocked, all peripherals fCPU = 125 kHz 0.032 0.056 0.068 0.072 0.093 OFF, Supply code executed HSE external fCPU = 1 MHz 0.078 0.121 0.144 0.163 0.197 IDD(Wait) cWuarrite mnto idne fwroitmh FRlaAsMh i n c(flock =f ) fCPU = 4 MHz 0.218 0.26 0.30 0.36 0.40 mA CPU HSE I mode(5), (6) fCPU = 8 MHz 0.40 0.52 0.57 0.62 0.66 DDQ VDD from 1.09 1.16 1.65 V to 3.6 V fCPU = 16 MHz 0.760 1.01 1.05 (7) (7) LSI fCPU = fLSI 0.035 0.044 0.046 0.049 0.054 LSE(8) external clock fCPU = fLSE 0.032 0.036 0.038 0.044 0.051 (32.768 kHz) DocID15962 Rev 15 71/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Table 21. Total current consumption in Wait mode (continued) Max Symbol Parameter Conditions(1) Typ 85 105 °C 125 °C Unit 55°C °C(2) (3) (4) fCPU = 125 kHz 0.38 0.48 0.49 0.50 0.56 fCPU = 1 MHz 0.41 0.49 0.51 0.53 0.59 HSI fCPU = 4 MHz 0.50 0.57 0.58 0.62 0.66 fCPU = 8 MHz 0.60 0.66 0.68 0.72 0.74 CPU not fCPU = 16 MHz 0.79 0.84 0.86 0.87 0.90 Supply callol pckeeridp,h erals HSE(6) fCPU = 125 kHz 0.06 0.08 0.09 0.10 0.12 current in OFF, fCPU = 1 MHz 0.10 0.17 0.18 0.19 0.22 I external mA DD(Wait) Wmoadite cfroodme Felxaeschu, ted c(flock =HSE) fCPU = 4 MHz 0.24 0.36 0.39 0.41 0.44 VDD from CPU fCPU = 8 MHz 0.50 0.58 0.61 0.62 0.64 1.65 V to 3.6 V fCPU = 16 MHz 1.00 1.08 1.14 1.16 1.18 LSI fCPU = fLSI 0.055 0.058 0.065 0.073 0.080 LSE(8) external clock fCPU = fLSE 0.051 0.056 0.060 0.065 0.073 (32.768 kHz) 1. All peripherals OFF, V from 1.65 V to 3.6 V, HSI internal RC osc., f = f DD CPU SYSCLK 2. For temperature range 6. 3. For temperature range 7. 4. For temperature range 3. 5. Flash is configured in I mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register. DDQ 6. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (I ) must be added. Refer to Table 31. DD HSE 7. Tested in production. 8. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (I ) must be added. Refer to Table 32. DD HSE 72/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 14. Typ. I vs. V , f = 16 MHz 1) DD(Wait) DD CPU (cid:20)(cid:19)(cid:19)(cid:19) (cid:28)(cid:24)(cid:19) (cid:28)(cid:19)(cid:19) (cid:36)(cid:64) (cid:27)(cid:24)(cid:19) (cid:151) (cid:62) (cid:3) (cid:54)(cid:44) (cid:27)(cid:19)(cid:19) (cid:43) (cid:55)(cid:12) (cid:36)(cid:44) (cid:26)(cid:24)(cid:19) (cid:58) (cid:39)(cid:11) (cid:26)(cid:19)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:39) (cid:44) (cid:25)(cid:24)(cid:19) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:25)(cid:19)(cid:19) (cid:24)(cid:24)(cid:19) (cid:24)(cid:19)(cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57) (cid:62)(cid:57)(cid:64) (cid:39)(cid:39)(cid:3) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:23)(cid:69) 1. Typical current consumption measured with code executed from Flash memory. DocID15962 Rev 15 73/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 In the following table, data is based on characterization results, unless otherwise specified. Table 22. Total current consumption and timing in Low power run mode at V = 1.65 V to 3.6 V DD Symbol Parameter Conditions(1) Typ Max Unit T = -40 °C A 5.1 5.4 to 25 °C T = 55 °C 5.7 6 A all peripherals OFF T = 85 °C 6.8 7.5 A T = 105 °C 9.2 10.4 A LSI RC osc. TA = 125 °C 13.4 16.6 (at 38 kHz) T = -40 °C A 5.4 5.7 to 25 °C T = 55 °C 6.0 6.3 A with TIM2 active(2) T = 85 °C 7.2 7.8 A T = 105 °C 9.4 10.7 A IDD(LPR) Spouwppelry r ucunr mreondt ein Low TTA == -14205 °°CC 13.8 17 μA A 5.25 5.6 to 25 °C T = 55 °C 5.67 6.1 A all peripherals OFF T = 85 °C 5.85 6.3 A T = 105 °C 7.11 7.6 A LSE (3) external T = 125 °C 9.84 12 A clock T = -40 °C (32.768 kHz) A 5.59 6 to 25 °C T = 55 °C 6.10 6.4 A with TIM2 active (2) T = 85 °C 6.30 7 A T = 105 °C 7.55 8.4 A T = 125 °C 10.1 15 A 1. No floating I/Os 2. Timer 2 clock enabled and counter running 3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (I ) must be added. Refer to Table 32 DD LSE 74/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 15. Typ. I vs. V (LSI clock source) DD(LPR) DD (cid:20)(cid:27) (cid:20)(cid:25) (cid:20)(cid:23) (cid:16)(cid:23)(cid:19)(cid:131)(cid:3)(cid:38) (cid:21)(cid:24)(cid:131)(cid:3)(cid:38) (cid:20)(cid:21) (cid:36)(cid:64) (cid:27)(cid:24)(cid:131)(cid:3)(cid:38) (cid:151) (cid:3)(cid:3)(cid:62)(cid:54)(cid:44) (cid:20)(cid:19) (cid:47) (cid:53)(cid:12) (cid:51) (cid:27) (cid:47) (cid:39)(cid:11) (cid:39) (cid:44) (cid:25) (cid:23) (cid:21) (cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:25)(cid:69) DocID15962 Rev 15 75/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 In the following table, data is based on characterization results, unless otherwise specified. T a ble 23. Total current consumption in Low power wait mode at V = 1.65 V to 3.6 V DD Symbol Parameter Conditions(1) Typ Max Unit TA = -40 °C to 25 °C 3 3.3 T = 55 °C 3.3 3.6 A all peripherals OFF T = 85 °C 4.4 5 A T = 105 °C 6.7 8 A LSI RC osc. TA = 125 °C 11 14 (at 38 kHz) TA = -40 °C to 25 °C 3.4 3.7 T = 55 °C 3.7 4 A with TIM2 active(2) T = 85 °C 4.8 5.4 A T = 105 °C 7 8.3 A Supply current in T = 125 °C 11.3 14.5 IDD(LPW) Low power wait A μA mode TA = -40 °C to 25 °C 2.35 2.7 T = 55 °C 2.42 2.82 A all peripherals OFF T = 85 °C 3.10 3.71 A T = 105 °C 4.36 5.7 A LSE external T = 125 °C 7.20 11 clock(3) A (32.768 kHz) TA = -40 °C to 25 °C 2.46 2.75 T = 55 °C 2.50 2.81 A with TIM2 active (2) T = 85 °C 3.16 3.82 A T = 105 °C 4.51 5.9 A T = 125 °C 7.28 11 A 1. No floating I/Os. 2. Timer 2 clock enabled and counter is running. 3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (I ) must be added. Refer to Table 32. DD LSE 76/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 16. Typ. I vs. V (LSI clock source) DD(LPW) DD (cid:20)(cid:25)(cid:17)(cid:19)(cid:19) (cid:20)(cid:23)(cid:17)(cid:19)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:20)(cid:21)(cid:17)(cid:19)(cid:19) (cid:21)(cid:24)(cid:131)(cid:38) (cid:36)(cid:64) (cid:20)(cid:19)(cid:17)(cid:19)(cid:19) (cid:27)(cid:24)(cid:131)(cid:38) (cid:151) (cid:3)(cid:62)(cid:54)(cid:44) (cid:58)(cid:3)(cid:12)(cid:47) (cid:27)(cid:17)(cid:19)(cid:19) (cid:51) (cid:47) (cid:39)(cid:39)(cid:11) (cid:25)(cid:17)(cid:19)(cid:19) (cid:44) (cid:23)(cid:17)(cid:19)(cid:19) (cid:21)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:19)(cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:26)(cid:69) DocID15962 Rev 15 77/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 In the following table, data is based on characterization results, unless otherwise specified. Table 24. T otal current consumption and timing in Active-halt mode at V = 1.65 V to 3.6 V DD Symbol Parameter Conditions (1) Typ Max Unit TA = -40 °C to 25 °C 0.9 2.1 T = 55 °C 1.2 3 A LCD OFF(2) T = 85 °C 1.5 3.4 A T = 105 °C 2.6 6.6 A T = 125 °C 5.1 12 A TA = -40 °C to 25 °C 1.4 3.1 LCD ON T = 55 °C 1.5 3.3 (static duty/ A external TA = 85 °C 1.9 4.3 VLCD) (3) TA = 105 °C 2.9 6.8 IDD(AH) SAuctpivpely-h caultr rmenotd ien L(aSt I3 R8C k Hz) TTAA == 1-4205 °°CC to 25 °C 15..95 41.33 μA LCD ON T = 55 °C 1.95 4.4 (1/4 duty/ A external TA = 85 °C 2.4 5.4 VLCD) (4) TA = 105 °C 3.4 7.6 T = 125 °C 6.0 15 A TA = -40 °C to 25 °C 3.9 8.75 LCD ON T = 55 °C 4.15 9.3 (1/4 duty/ A internal TA = 85 °C 4.5 10.2 VLCD) (5) TA = 105 °C 5.6 13.5 T = 125 °C 6.8 16.3 A 78/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Table 24. Total current consumption and timing in Active-halt mode at V = 1.65 V to 3.6 V DD Symbol Parameter Conditions (1) Typ Max Unit TA = -40 °C to 25 °C 0.5 1.2 T = 55 °C 0.62 1.4 A LCD OFF(7) T = 85 °C 0.88 2.1 A T = 105 °C 2.1 4.85 A T = 125 °C 4.8 11 A TA = -40 °C to 25 °C 0.85 1.9 LCD ON T = 55 °C 0.95 2.2 (static duty/ A external TA = 85 °C 1.3 3.2 LSE external VLCD) (3) TA = 105 °C 2.3 5.3 IDD(AH) SAuctpivpely-h caultr rmenotd ien c(3lo2c.7k6 8 kHz) TTAA == 1-4205 °°CC to 25 °C 15..50 21.25 μA (6) LCD ON T = 55 °C 1.6 3.8 (1/4 duty/ A external TA = 85 °C 1.8 4.2 VLCD) (4) TA = 105 °C 2.9 7.0 T = 125 °C 5.7 14 A TA = -40 °C to 25 °C 3.4 7.6 LCD ON T = 55 °C 3.7 8.3 (1/4 duty/ A internal TA = 85 °C 3.9 9.2 VLCD) (5) TA = 105 °C 5.0 14.5 T = 125 °C 6.3 15.2 A Supply current during wakeup time from IDD(WUFAH) Active-halt mode - - 2.4 - mA (using HSI) Wakeup time from t (8)(9) Active-halt mode to - - 4.7 7 μs WU_HSI(AH) Run mode (using HSI) Wakeup time from tWU_LSI(AH)(8) Active-halt mode to - - 150 - μs (9) Run mode (using LSI) 1. No floating I/O, unless otherwise specified. 2. RTC enabled. Clock source = LSI 3. RTC enabled, LCD enabled with external V = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected. LCD 4. RTC enabled, LCD enabled with external V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. LCD 5. LCD enabled with internal LCD booster V = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD LCD connected. 6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (I ) must be added. Refer to Table 32. DD LSE 7. RTC enabled. Clock source = LSE. 8. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after t . WU 9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register. DocID15962 Rev 15 79/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal Symbol Parameter Condition(1) Typ Unit LSE 1.15 V = 1.8 V DD LSE/32(3) 1.05 LSE 1.30 Supply current in Active-halt I (2) V = 3 V µA DD(AH) mode DD LSE/32(3) 1.20 LSE 1.45 V = 3.6 V DD LSE/32(3) 1.35 1. No floating I/O, unless otherwise specified. 2. Based on measurements on bench with 32.768 kHz external crystal oscillator. 3. RTC clock is LSE divided by 32. In the following table, data is based on characterization results, unless otherwise specified. Table 26. Total current consumption and timing in Halt mode at V = 1.65 to 3.6 V DD Symbol Parameter Condition(1) Typ Max Unit TA = -40 °C to 25 °C 350 1400(2) T = 55 °C 580 2000 A Supply current in Halt mode nA IDD(Halt) (Ultra-low-power ULP bit =1 in TA = 85 °C 1160 2800(2) the PWR_CSR2 register) TA = 105 °C 2560 6700(2) TA = 125 °C 4.4 13(2) µA Supply current during wakeup IDD(WUHalt) time from Halt mode (using - 2.4 - mA HSI) Wakeup time from Halt to Run t (3)(4) - 4.7 7 µs WU_HSI(Halt) mode (using HSI) Wakeup time from Halt mode t (3)(4) - 150 - µs WU_LSI(Halt) to Run mode (using LSI) 1. T = -40 to 125 °C, no floating I/O, unless otherwise specified. A 2. Tested in production. 3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register. 4. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after t . WU 80/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Current consumption of on-chip peripherals Table 27. Peripheral current consumption Typ. Symbol Parameter Unit V = 3.0 V DD IDD(TIM1) TIM1 supply current(1) 13 IDD(TIM2) TIM2 supply current (1) 8 IDD(TIM3) TIM3 supply current (1) 8 IDD(TIM4) TIM4 timer supply current (1) 3 IDD(USART1) USART1 supply current (2) 6 µA/MHz IDD(SPI1) SPI1 supply current (2) 3 IDD(I2C1) I2C1 supply current (2) 5 IDD(DMA1) DMA1 supply current(2) 3 IDD(WWDG) WWDG supply current(2) 2 IDD(ALL) Peripherals ON(3) 44 µA/MHz IDD(ADC1) ADC1 supply current(4) 1500 µA IDD(DAC) DAC supply current(5) 370 µA IDD(COMP1) Comparator 1 supply current(6) 0.160 Slow mode 2 IDD(COMP2) Comparator 2 supply current(6) Fast mode 5 Power voltage detector and brownout Reset unit supply IDD(PVD/BOR) current (7) 2.6 µA IDD(BOR) Brownout Reset unit supply current (7) 2.4 including LSI supply 0.45 current IDD(IDWDG) Independent watchdog supply current excluding LSI 0.05 supply current 1. Data based on a differential I measurement between all peripherals OFF and a timer counter running at 16 MHz. The DD CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production. 2. Data based on a differential I measurement between the on-chip peripheral in reset configuration and not clocked and DD the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling. Not tested in production. 3. Peripherals listed above the I parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG. DD(ALL) 4. Data based on a differential I measurement between ADC in reset configuration and continuous ADC conversion. DD 5. Data based on a differential I measurement between DAC in reset configuration and continuous DAC conversion of DD V /2. Floating DAC output. DD 6. Data based on a differential I measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 DD enabled with static inputs. Supply current of internal reference voltage excluded. 7. Including supply current of internal reference voltage. DocID15962 Rev 15 81/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Table 28. Current consumption under external reset Symbol Parameter Conditions Typ Unit V = 1.8 V 48 DD Supply current under All pins are externally IDD(RST) external reset (1) tied to VDD VDD = 3 V 76 µA V = 3.6 V 91 DD 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 9.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for V and T . DD A Table 29. HSE external clock characteristics Symbol Parameter Conditions Min Typ Max Unit External clock source fHSE_ext frequency(1) 1 - 16 MHz OSC_IN input pin high level VHSEH voltage - 0.7 x VDD - VDD V OSC_IN input pin low level VHSEL voltage VSS - 0.3 x VDD OSC_IN input Cin(HSE) capacitance(1) - - 2.6 - pF OSC_IN input leakage ILEAK_HSE current VSS < VIN < VDD - - ±1 µA 1. Data guaranteed by design. LSE external clock (LSEBYP=1 in CLK_ECKCR) Subject to general operating conditions for V and T . DD A Table 30. LSE external clock characteristics Symbol Parameter Min Typ Max Unit fLSE_ext External clock source frequency(1) - 32.768 - kHz V (2) OSC32_IN input pin high level voltage 0.7 x V - V LSEH DD DD V V (2) OSC32_IN input pin low level voltage V - 0.3 x V LSEL SS DD Cin(LSE) OSC32_IN input capacitance(1) - 0.6 - pF ILEAK_LSE OSC32_IN input leakage current - - ±1 µA 1. Data guaranteed by design. 2. Data based on characterization results. 82/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 31. HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit High speed external oscillator f - 1 - 16 MHz HSE frequency R Feedback resistor - - 200 - kΩ F C(1) Recommended load capacitance (2) - - 20 - pF C = 20 pF, 2.5 (startup) - - f = 16 MHz 0.7 (stabilized)(3) OSC I HSE oscillator power consumption mA DD(HSE) C = 10 pF, 2.5 (startup) - - f =16 MHz 0.46 (stabilized)(3) OSC g Oscillator transconductance - 3.5(3) - - mA/V m t (4) Startup time V is stabilized - 1 - ms SU(HSE) DD 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value. m Refer to crystal manufacturer for more details 3. Data guaranteed by design. 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This SU(HSE) value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 17. HSE oscillator circuit diagram (cid:53)(cid:80) (cid:73)(cid:43)(cid:54)(cid:40)(cid:3)(cid:87)(cid:82)(cid:3)(cid:3)(cid:70)(cid:82)(cid:85)(cid:72) (cid:38) (cid:47)(cid:80) (cid:50) (cid:53)(cid:41) (cid:38)(cid:80) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:44)(cid:49) (cid:74)(cid:80) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:38)(cid:82)(cid:81)(cid:86)(cid:88)(cid:80)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:50)(cid:54)(cid:38)(cid:50)(cid:56)(cid:55) (cid:38)(cid:47)(cid:21) (cid:54)(cid:55)(cid:48)(cid:27) (cid:48)(cid:54)(cid:22)(cid:25)(cid:23)(cid:28)(cid:19)(cid:57)(cid:21) DocID15962 Rev 15 83/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 HSE oscillator critical g formula m g = (2× Π× f )2× R (2Co+C)2 mcrit HSE m Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification), Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification), CL1=CL2=C: Grounded external capacitance gm >> gmcrit LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 32. LSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Low speed external oscillator f - - 32.768 - kHz LSE frequency R Feedback resistor ΔV = 200 mV - 1.2 - MΩ F C(1) Recommended load capacitance (2) - - 8 - pF - - - 1.4(3) µA V = 1.8 V - 450 - DD I LSE oscillator power consumption DD(LSE) V = 3 V - 600 - nA DD V = 3.6 V - 750 - DD g Oscillator transconductance - 3(3) - - µA/V m t (4) Startup time V is stabilized - 1 - s SU(LSE) DD 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R value. Refer to crystal manufacturer for more details. m 3. Data guaranteed by design. 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized SU(LSE) 32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 84/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 18. LSE oscillator circuit diagram (cid:53)(cid:80) (cid:73)(cid:47)(cid:54)(cid:40) (cid:38) (cid:47)(cid:80) (cid:50) (cid:53)(cid:41) (cid:38)(cid:80) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:44)(cid:49) (cid:74)(cid:80) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:38)(cid:82)(cid:81)(cid:86)(cid:88)(cid:80)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:50)(cid:54)(cid:38)(cid:50)(cid:56)(cid:55) (cid:38)(cid:47)(cid:21) (cid:54)(cid:55)(cid:48)(cid:27) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:26)(cid:26)(cid:25)(cid:57)(cid:20) Internal clock sources Subject to general operating conditions for V , and T . DD A High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 33. HSI oscillator characteristics Symbol Parameter Conditions(1) Min Typ Max Unit f Frequency V = 3.0 V - 16 - MHz HSI DD V = 3.0 V, T = 25 °C -1 (2) - 1(2) % DD A V = 3.0 V, 0 °C ≤ T ≤ 55 °C -1.5 - 1.5 % DD A Accuracy of HSI VDD = 3.0 V, -10 °C ≤ TA ≤ 70 °C -2 - 2 % ACCHSI oscillator (factory VDD = 3.0 V, -10 °C ≤ TA ≤ 85 °C -2.5 - 2 % calibrated) V = 3.0 V, -10 °C ≤ T ≤ 125 °C -4.5 - 2 % DD A 1.65 V ≤ V ≤ 3.6 V, DD -4.5 - 3 % -40 °C ≤ T ≤ 125 °C A HSI user trimming Trimming code ≠ multiple of 16 - 0.4 0.7 % TRIM step(3) Trimming code = multiple of 16 - ± 1.5 % HSI oscillator setup t - - 3.7 6(4) µs su(HSI) time (wakeup time) HSI oscillator power I - - 100 140(4) µA DD(HSI) consumption 1. V = 3.0 V, T = -40 to 125 °C unless otherwise specified. DD A 2. Tested in production. 3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for more details. 4. Guaranteed by design. DocID15962 Rev 15 85/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 19. Typical HSI frequency vs V DD (cid:20)(cid:27)(cid:17)(cid:19) (cid:20)(cid:26)(cid:17)(cid:24) (cid:20)(cid:26)(cid:17)(cid:19) (cid:93)(cid:64) (cid:20)(cid:25)(cid:17)(cid:24) (cid:43) (cid:48) (cid:92)(cid:3)(cid:62) (cid:20)(cid:25)(cid:17)(cid:19) (cid:70) (cid:81) (cid:72) (cid:20)(cid:24)(cid:17)(cid:24) (cid:88) (cid:84) (cid:54)(cid:44)(cid:3)(cid:73)(cid:85)(cid:72) (cid:20)(cid:24)(cid:17)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:43) (cid:20)(cid:23)(cid:17)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:20)(cid:23)(cid:17)(cid:19) (cid:27)(cid:24)(cid:131)(cid:38) (cid:20)(cid:22)(cid:17)(cid:24) (cid:20)(cid:22)(cid:17)(cid:19) (cid:20)(cid:17)(cid:27) (cid:20)(cid:17)(cid:28)(cid:24) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:21)(cid:24) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:24)(cid:24) (cid:21)(cid:17)(cid:26) (cid:21)(cid:17)(cid:27)(cid:24) (cid:22) (cid:22)(cid:17)(cid:20)(cid:24) (cid:22)(cid:17)(cid:22) (cid:22)(cid:17)(cid:23)(cid:24) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:27)(cid:70) Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 34. LSI oscillator characteristics Symbol Parameter (1) Conditions(1) Min Typ Max Unit f Frequency - 26 38 56 kHz LSI t LSI oscillator wakeup time - - - 200(2) µs su(LSI) LSI oscillator frequency I 0 °C ≤ T ≤ 85 °C -12 - 11 % DD(LSI) drift(3) A 1. V = 1.65 V to 3.6 V, T = -40 to 125 °C unless otherwise specified. DD A 2. Guaranteed by design. 3. This is a deviation for an individual part, once the initial frequency has been measured. 86/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 20. Typical LSI frequency vs. V DD (cid:23)(cid:24) (cid:23)(cid:22) (cid:23)(cid:20) (cid:93)(cid:64) (cid:43) (cid:22)(cid:28) (cid:78) (cid:92)(cid:3)(cid:62) (cid:70) (cid:22)(cid:26) (cid:81) (cid:72) (cid:88) (cid:84) (cid:22)(cid:24) (cid:72) (cid:54)(cid:44)(cid:3)(cid:73)(cid:85) (cid:22)(cid:22) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:47) (cid:22)(cid:20) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:21)(cid:28) (cid:21)(cid:26) (cid:21)(cid:24) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:20)(cid:28)(cid:69) DocID15962 Rev 15 87/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.5 Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 35. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit V Data retention mode (1) Halt mode (or Reset) 1.65 - - V RM 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 36. Flash program and data EEPROM memory Max Symbol Parameter Conditions Min Typ Unit (1) Operating voltage V f = 16 MHz 1.65 - 3.6 V DD (all modes, read/write/erase) SYSCLK Programming time for 1 or 64 bytes (block) - - 6 - ms erase/write cycles (on programmed byte) t prog Programming time for 1 to 64 bytes (block) - - 3 - ms write cycles (on erased byte) T =+25 °C, V = 3.0 V - 0.7 - A DD I Programming/ erasing consumption mA prog T =+25 °C, V = 1.8 V - 0.7 - A DD Data retention (program memory) after 10000 erase/write cycles at T = –40 to +85 °C T = +85 °C 30(1) - - A RET (6 suffix) Data retention (program memory) after 10000 erase/write cycles at T = –40 to +125 °C T = +125 °C 5(1) - - A RET (3 suffix) t (2) years RET Data retention (data memory) after 300000 erase/write cycles at T = –40 to +85 °C T = +85 °C 30(1) - - A RET (6 suffix) Data retention (data memory) after 300000 erase/write cycles at T = –40 to +125 °C T = +125 °C 5(1) - - A RET (3 suffix) Erase/write cycles (program memory) T = –40 to +85 °C 10(1) - - A (6 suffix), NRW (3) Erase/write cycles (data memory) TA = –40 to +125 °C 30(40)(1) - - kcycles (3 suffix) 1. Data based on characterization results. 2. Conforming to JEDEC JESD22a117 3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. Data based on characterization performed on the whole data memory. 88/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 9.3.6 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard pins) should be avoided during normal product operation. DD However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 37. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on true open-drain pins (PC0 and -5 +0 PC1) I Injected current on all five-volt tolerant (FT) pins -5 +0 mA INJ Injected current on all 3.6 V tolerant (TT) pins -5 +0 Injected current on any other pin -5 +5 9.3.7 I/O port pin characteristics General characteristics Subject to general operating conditions for V and T unless otherwise specified. All DD A unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. DocID15962 Rev 15 89/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Table 38. I/O static characteristics Symbol Parameter Conditions(1) Min Typ Max Unit Input voltage on true open-drain pins (PC0 and PC1) VSS-0.3 - 0.3 x VDD Input voltage on five-volt tolerant (FT) pins (PA7 and VSS-0.3 - 0.3 x VDD VIL Input low level voltage(2) PE0) V Input voltage on 3.6 V tolerant (TT) pins VSS-0.3 - 0.3 x VDD Input voltage on any other pin VSS-0.3 - 0.3 x VDD Input voltage on true open-drain pins (PC0 and PC1) - 5.2 with V < 2 V DD 0.70 x V DD Input voltage on true open-drain pins (PC0 and PC1) - 5.5 with V ≥ 2 V DD Input voltage on five-volt tolerant (FT) pins (PA7 and VIH Input high level voltage (2) PE0) - 5.2 V with V < 2 V DD Input voltage on five-volt 0.70 x V tolerant (FT) pins (PA7 and DD PE0) - 5.5 with V ≥ 2 V DD Input voltage on 3.6 V tolerant - 3.6 (TT) pins Input voltage on any other pin 0.70 x VDD - VDD+0.3 Schmitt trigger voltage I/Os - 200 - Vhys hysteresis (3) True open drain I/Os - 200 - mV VSS≤ VIN≤ VDD - - 50 (5) High sink I/Os VSS≤ VIN≤ VDD - - 200(5) I Input leakage current (4) True open drain I/Os nA lkg VSS≤ VIN≤ VDD PA0 with high sink LED driver - - 200(5) capability Weak pull-up equivalent RPU resistor(2)(6) VIN=VSS 30 45 60 kΩ CIO I/O pin capacitance - - 5 - pF 1. V = 3.0 V, T = -40 to 125 °C unless otherwise specified. DD A 2. Data based on characterization results. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 90/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 6. R pull-up equivalent resistor based on a resistive transistor (corresponding I current characteristics described in PU PU Figure 24). Figure 21. Typical V and V vs V (high sink I/Os) IL IH DD (cid:22) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:21)(cid:17)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:57)(cid:64) (cid:21) (cid:3)(cid:62)(cid:43) (cid:57)(cid:44) (cid:71)(cid:3) (cid:20)(cid:17)(cid:24) (cid:81) (cid:68) (cid:3)(cid:47) (cid:57)(cid:44) (cid:20) (cid:19)(cid:17)(cid:24) (cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:19)(cid:70) Figure 22. Typical V and V vs V (true open drain I/Os) IL IH DD (cid:22) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:21)(cid:17)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:21) (cid:57)(cid:64) (cid:3)(cid:62)(cid:43) (cid:57)(cid:44) (cid:71)(cid:3) (cid:20)(cid:17)(cid:24) (cid:81) (cid:68) (cid:3)(cid:47) (cid:57)(cid:44) (cid:20) (cid:19)(cid:17)(cid:24) (cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:20)(cid:69) DocID15962 Rev 15 91/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 23. Typical pull-up resistance R vs V with V =V PU DD IN SS (cid:25)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:24)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:159)(cid:64) (cid:24)(cid:19) (cid:78) (cid:72)(cid:3)(cid:62) (cid:70) (cid:81) (cid:86)(cid:87)(cid:68) (cid:23)(cid:24) (cid:86)(cid:76) (cid:3)(cid:72) (cid:83)(cid:3)(cid:85) (cid:88) (cid:23)(cid:19) (cid:88)(cid:79)(cid:79)(cid:16) (cid:51) (cid:22)(cid:24) (cid:22)(cid:19) (cid:20)(cid:17)(cid:27) (cid:21) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:21)(cid:69) Figure 24. Typical pull-up current I vs V with V =V pu DD IN SS (cid:20)(cid:21)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:21)(cid:24)(cid:131)(cid:38) (cid:20)(cid:19)(cid:19) (cid:27)(cid:24)(cid:131)(cid:38) (cid:36)(cid:64) (cid:27)(cid:19) (cid:151) (cid:81)(cid:87)(cid:3)(cid:62) (cid:72) (cid:88)(cid:85)(cid:85) (cid:25)(cid:19) (cid:70) (cid:83)(cid:3) (cid:88) (cid:88)(cid:79)(cid:79)(cid:16) (cid:23)(cid:19) (cid:51) (cid:21)(cid:19) (cid:19) (cid:20)(cid:17)(cid:27) (cid:20)(cid:17)(cid:28)(cid:24) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:21)(cid:24) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:24)(cid:24) (cid:21)(cid:17)(cid:26) (cid:21)(cid:17)(cid:27)(cid:24) (cid:22) (cid:22)(cid:17)(cid:20)(cid:24) (cid:22)(cid:17)(cid:22) (cid:22)(cid:17)(cid:23)(cid:24) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:22)(cid:69) 92/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Output driving current Subject to general operating conditions for V and T unless otherwise specified. DD A Table 39. Output driving current (high sink ports) I/O Symbol Parameter Conditions Min Max Unit Type I = +2 mA, IO - 0.45 V V = 3.0 V DD I = +2 mA, V (1) Output low level voltage for an I/O pin IO - 0.45 V OL V = 1.8 V DD I = +10 mA, IO k - 0.7 V sin VDD = 3.0 V High IVIO = =-2 3 m.0A V, VDD-0.45 - V DD I = -1 mA, VOH (2) Output high level voltage for an I/O pin VIO = 1.8 V VDD-0.45 - V DD I = -10 mA, IO V -0.7 - V V = 3.0 V DD DD 1. The I current sunk must always respect the absolute maximum rating specified in Table 16 and the sum IO of I (I/O ports and control pins) must not exceed I . IO VSS 2. The I current sourced must always respect the absolute maximum rating specified in Table 16 and the IO sum of I (I/O ports and control pins) must not exceed I . IO VDD Table 40. Output driving current (true open drain ports) I/O Symbol Parameter Conditions Min Max Unit Type I = +3 mA, ain VIO = 3.0 V - 0.45 pen dr VOL (1) Output low level voltage for an I/O pin IIOD D= +1 mA, - 0.45 V O V = 1.8 V DD 1. The I current sunk must always respect the absolute maximum rating specified in Table 16 and the sum IO of I (I/O ports and control pins) must not exceed I . IO VSS Table 41. Output driving current (PA0 with high sink LED driver capability) I/O Symbol Parameter Conditions Min Max Unit Type I = +20 mA, R V (1) Output low level voltage for an I/O pin IO - 0.45 V I OL VDD = 2.0 V 1. The I current sunk must always respect the absolute maximum rating specified in Table 16 and the sum IO of I (I/O ports and control pins) must not exceed I . IO VSS DocID15962 Rev 15 93/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 25. Typ. V @ V = 3.0 V (high sink Figure 26. Typ. V @ V = 1.8 V (high sink OL DD OL DD ports) ports) (cid:17) (cid:16)(cid:14)(cid:23) (cid:16)(cid:14)(cid:23)(cid:21) (cid:13)(cid:18)(cid:20)(cid:21)(cid:16)(cid:160)(cid:160)(cid:35)(cid:35) (cid:16)(cid:14)(cid:22) (cid:13)(cid:20)(cid:16)(cid:160)(cid:35) (cid:18)(cid:21)(cid:160)(cid:35) (cid:25)(cid:16)(cid:160)(cid:35) (cid:16)(cid:14)(cid:21) (cid:25)(cid:16)(cid:160)(cid:35) (cid:54)(cid:59)(cid:54)(cid:61)(cid:47)(cid:44)(cid:0) (cid:16)(cid:14)(cid:21) (cid:17)(cid:19)(cid:16)(cid:160)(cid:35) (cid:54)(cid:59)(cid:54)(cid:61)(cid:47)(cid:44)(cid:0)(cid:16)(cid:16)(cid:14)(cid:14)(cid:19)(cid:20) (cid:17)(cid:19)(cid:16)(cid:160)(cid:35) (cid:16)(cid:14)(cid:18)(cid:21) (cid:16)(cid:14)(cid:18) (cid:16)(cid:14)(cid:17) (cid:16) (cid:16) (cid:18) (cid:20) (cid:22) (cid:24) (cid:17)(cid:16) (cid:17)(cid:18) (cid:17)(cid:20) (cid:17)(cid:22) (cid:17)(cid:24) (cid:18)(cid:16) (cid:16) (cid:41)(cid:47)(cid:44)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:16) (cid:17) (cid:18) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:41)(cid:47)(cid:44)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:65)(cid:73)(cid:17)(cid:24)(cid:18)(cid:18)(cid:22) (cid:65)(cid:73)(cid:17)(cid:24)(cid:18)(cid:18)(cid:23) Figure 27. Typ. V @ V = 3.0 V (true open Figure 28. Typ. V @ V = 1.8 V (true open OL DD OL DD drain ports) drain ports) (cid:16)(cid:14)(cid:21) (cid:16)(cid:14)(cid:21) (cid:13)(cid:20)(cid:16)(cid:160)(cid:35) (cid:16)(cid:14)(cid:20) (cid:18)(cid:21)(cid:160)(cid:35) (cid:16)(cid:14)(cid:20) (cid:13)(cid:20)(cid:16)(cid:160)(cid:35) (cid:25)(cid:16)(cid:160)(cid:35) (cid:18)(cid:21)(cid:160)(cid:35) (cid:54)(cid:59)(cid:54)(cid:61)(cid:47)(cid:44)(cid:0)(cid:16)(cid:14)(cid:19) (cid:17)(cid:19)(cid:16)(cid:160)(cid:35) (cid:54)(cid:59)(cid:54)(cid:61)(cid:47)(cid:44)(cid:0)(cid:16)(cid:14)(cid:19) (cid:25)(cid:17)(cid:16)(cid:19)(cid:160)(cid:16)(cid:35)(cid:160)(cid:35) (cid:16)(cid:14)(cid:18) (cid:16)(cid:14)(cid:18) (cid:16)(cid:14)(cid:17) (cid:16)(cid:14)(cid:17) (cid:16) (cid:16) (cid:16) (cid:17) (cid:18) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:16) (cid:17) (cid:18) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:41)(cid:47)(cid:44)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:41)(cid:47)(cid:44)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:65)(cid:73)(cid:17)(cid:24)(cid:18)(cid:18)(cid:24) (cid:66)(cid:74)(cid:18)(cid:25)(cid:19)(cid:19)(cid:26) Figure 29. Typ. V V @ V = 3.0 V (high Figure 30. Typ. V V @ V = 1.8 V (high DD - OH DD DD - OH DD sink ports) sink ports) (cid:18) (cid:17)(cid:14)(cid:23)(cid:21) (cid:16)(cid:14)(cid:21) (cid:13)(cid:20)(cid:16)(cid:160)(cid:35) (cid:13)(cid:20)(cid:16)(cid:160)(cid:35) (cid:18)(cid:21)(cid:160)(cid:35) (cid:17)(cid:14)(cid:21) (cid:18)(cid:21)(cid:160)(cid:35) (cid:16)(cid:14)(cid:20) (cid:25)(cid:16)(cid:160)(cid:35) (cid:0)(cid:13)(cid:0)(cid:54)(cid:59)(cid:54)(cid:61)(cid:54)(cid:47)(cid:40)(cid:0)(cid:36)(cid:36)(cid:16)(cid:17)(cid:14)(cid:14)(cid:23)(cid:18)(cid:21)(cid:21)(cid:17) (cid:25)(cid:17)(cid:16)(cid:19)(cid:160)(cid:16)(cid:35)(cid:160)(cid:35) (cid:0)(cid:13)(cid:0)(cid:54)(cid:59)(cid:54)(cid:61)(cid:54)(cid:47)(cid:40)(cid:0)(cid:36)(cid:36)(cid:16)(cid:16)(cid:14)(cid:14)(cid:18)(cid:19) (cid:17)(cid:19)(cid:16)(cid:160)(cid:35) (cid:16)(cid:14)(cid:21) (cid:16)(cid:14)(cid:18)(cid:21) (cid:16)(cid:14)(cid:17) (cid:16) (cid:16) (cid:18) (cid:20) (cid:22) (cid:24) (cid:17)(cid:16) (cid:17)(cid:18) (cid:17)(cid:20) (cid:17)(cid:22) (cid:17)(cid:24) (cid:18)(cid:16) (cid:16) (cid:41)(cid:47)(cid:40)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:16) (cid:17) (cid:18) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:41)(cid:47)(cid:40)(cid:0)(cid:59)(cid:77)(cid:33)(cid:61) (cid:65)(cid:73)(cid:17)(cid:18)(cid:24)(cid:19)(cid:16) (cid:66)(cid:74)(cid:18)(cid:25)(cid:19)(cid:20)(cid:18) 94/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters NRST pin Subject to general operating conditions for V and T unless otherwise specified. DD A Table 42. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage (1) - VSS - 0.8 VIH(NRST) NRST input high level voltage (1) - 1.4 - VDD I = 2 mA OL for 2.7 V ≤ V ≤ 3.6 - - V DD VOL(NRST) NRST output low level voltage (1) V 0.4 I = 1.5 mA OL - - for V < 2.7 V DD 10%V DD VHYST NRST input hysteresis(3) - (2) - - mV NRST pull-up equivalent resistor RPU(NRST) - 30 45 60 kΩ (1) VF(NRST) NRST input filtered pulse (3) - - - 50 ns VNF(NRST) NRST input not filtered pulse (3) - 300 - - 1. Data based on characterization results. 2. 200 mV min. 3. Data guaranteed by design. Figure 31. Typical NRST pull-up resistance R vs V PU DD (cid:25)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:24)(cid:24) (cid:21)(cid:24)(cid:131)(cid:38) (cid:159)(cid:64) (cid:27)(cid:24)(cid:131)(cid:38) (cid:78) (cid:72)(cid:3)(cid:62) (cid:24)(cid:19) (cid:70) (cid:81) (cid:68) (cid:86)(cid:76)(cid:86)(cid:87) (cid:23)(cid:24) (cid:72) (cid:83)(cid:3)(cid:85) (cid:88) (cid:88)(cid:79)(cid:79)(cid:16) (cid:23)(cid:19) (cid:51) (cid:22)(cid:24) (cid:22)(cid:19) (cid:20)(cid:17)(cid:27) (cid:21) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57) (cid:62)(cid:57)(cid:64) (cid:39)(cid:39)(cid:3) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:23)(cid:69) DocID15962 Rev 15 95/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 32. Typical NRST pull-up current I vs V pu DD (cid:20)(cid:21)(cid:19) (cid:16)(cid:23)(cid:19)(cid:131)(cid:38) (cid:20)(cid:19)(cid:19) (cid:21)(cid:24)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:36)(cid:64) (cid:27)(cid:19) (cid:151) (cid:81)(cid:87)(cid:3)(cid:62) (cid:88)(cid:85)(cid:85)(cid:72) (cid:25)(cid:19) (cid:70) (cid:83)(cid:3) (cid:88) (cid:88)(cid:79)(cid:79)(cid:16) (cid:23)(cid:19) (cid:51) (cid:21)(cid:19) (cid:19) (cid:20)(cid:17)(cid:27) (cid:20)(cid:17)(cid:28)(cid:24) (cid:21)(cid:17)(cid:20) (cid:21)(cid:17)(cid:21)(cid:24) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:24)(cid:24) (cid:21)(cid:17)(cid:26) (cid:21)(cid:17)(cid:27)(cid:24) (cid:22) (cid:22)(cid:17)(cid:20)(cid:24) (cid:22)(cid:17)(cid:22) (cid:22)(cid:17)(cid:23)(cid:24) (cid:22)(cid:17)(cid:25) (cid:3) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:21)(cid:24)(cid:69) The reset network shown in Figure 33 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V max. level specified IL(NRST) in Table 42. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF. Figure 33. Recommended NRST pin configuration (cid:57)(cid:39)(cid:39) (cid:53) (cid:51)(cid:56) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87) (cid:49)(cid:53)(cid:54)(cid:55) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87) (cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87) (cid:54)(cid:55)(cid:48)(cid:27) (cid:11)(cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:12) (cid:19)(cid:17)(cid:20)(cid:3)(cid:88)(cid:41) (cid:48)(cid:54)(cid:22)(cid:23)(cid:28)(cid:21)(cid:27)(cid:57)(cid:20) 96/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 9.3.8 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature, f frequency and V supply voltage SYSCLK DD conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43. SPI1 characteristics Symbol Parameter Conditions(1) Min Max Unit f Master mode 0 8 SCK SPI1 clock frequency 1/tc(SCK) Slave mode 0 8 MHz t SPI1 clock rise and fall r(SCK) Capacitive load: C = 30 pF - 30 t time f(SCK) t (2) NSS setup time Slave mode 4 x 1/f - su(NSS) SYSCLK t (2) NSS hold time Slave mode 80 - h(NSS) t (2) Master mode, w(SCKH) SCK high and low time 105 145 t (2) f = 8 MHz, f = 4 MHz w(SCKL) MASTER SCK t (2) Master mode 30 - su(MI) Data input setup time tsu(SI)(2) Slave mode 3 - t (2) Master mode 15 - h(MI) Data input hold time ns th(SI)(2) Slave mode 0 - t (2)(3) Data output access time Slave mode - 3x 1/f a(SO) SYSCLK t (2)(4) Data output disable time Slave mode 30 - dis(SO) t (2) Data output valid time Slave mode (after enable edge) - 60 v(SO) Master mode (after enable t (2) Data output valid time - 20 v(MO) edge) t (2) Slave mode (after enable edge) 15 - h(SO) Data output hold time Master mode (after enable t (2) 1 - h(MO) edge) 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results. 3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z. DocID15962 Rev 15 97/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 34. SPI1 timing diagram - slave mode and CPHA=0 (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:38)(cid:46)(cid:3)(cid:44)(cid:81)(cid:83) (cid:38)(cid:38)(cid:51)(cid:51)(cid:50)(cid:43)(cid:36)(cid:47)(cid:32)(cid:32)(cid:19)(cid:19) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:57)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:23)(cid:70) Figure 35. SPI1 timing diagram - slave mode and CPHA=1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:54)(cid:38)(cid:46)(cid:3)(cid:44)(cid:81) (cid:38)(cid:38)(cid:51)(cid:51)(cid:50)(cid:43)(cid:47)(cid:36)(cid:32)(cid:32)(cid:20)(cid:20) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25) (cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37) (cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37) (cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20) (cid:44)(cid:49) (cid:47)(cid:54)(cid:37) (cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 98/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 36. SPI1 timing diagram - master mode(1) (cid:40)(cid:73)(cid:71)(cid:72) (cid:46)(cid:51)(cid:51)(cid:0)(cid:73)(cid:78)(cid:80)(cid:85)(cid:84) (cid:84)(cid:67)(cid:8)(cid:51)(cid:35)(cid:43)(cid:9) (cid:85)(cid:84) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:16) (cid:80) (cid:85)(cid:84) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:16) (cid:47) (cid:43)(cid:0) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:16) (cid:51)(cid:35) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:17) (cid:85)(cid:84) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:17) (cid:80) (cid:85)(cid:84) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:16) (cid:47) (cid:43)(cid:0) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:17) (cid:51)(cid:35) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:17) (cid:84)(cid:83)(cid:85)(cid:8)(cid:45)(cid:41)(cid:9) (cid:84)(cid:84)(cid:87)(cid:87)(cid:8)(cid:8)(cid:51)(cid:51)(cid:35)(cid:35)(cid:43)(cid:43)(cid:40)(cid:44)(cid:9)(cid:9) (cid:84)(cid:84)(cid:82)(cid:70)(cid:8)(cid:8)(cid:51)(cid:51)(cid:35)(cid:35)(cid:43)(cid:43)(cid:9)(cid:9) (cid:45)(cid:41)(cid:51)(cid:47) (cid:45)(cid:51)(cid:34)(cid:41)(cid:46) (cid:34)(cid:41)(cid:52)(cid:22)(cid:0)(cid:41)(cid:46) (cid:44)(cid:51)(cid:34)(cid:0)(cid:41)(cid:46) (cid:41)(cid:46)(cid:48)(cid:53)(cid:52) (cid:84)(cid:72)(cid:8)(cid:45)(cid:41)(cid:9) (cid:45)(cid:47)(cid:51)(cid:41) (cid:45)(cid:51)(cid:34)(cid:0)(cid:47)(cid:53)(cid:52) (cid:34)(cid:41)(cid:52)(cid:17)(cid:0)(cid:47)(cid:53)(cid:52) (cid:44)(cid:51)(cid:34)(cid:0)(cid:47)(cid:53)(cid:52) (cid:47)(cid:53)(cid:52)(cid:48)(cid:53)(cid:52) (cid:84)(cid:86)(cid:8)(cid:45)(cid:47)(cid:9) (cid:84)(cid:72)(cid:8)(cid:45)(cid:47)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:19)(cid:22)(cid:54)(cid:18) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DocID15962 Rev 15 99/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 I2C - Inter IC control interface Subject to general operating conditions for V , f , and T unless otherwise specified. DD SYSCLK A The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 44. I2C characteristics Standard mode Fast mode I2C(1) I2C Symbol Parameter Unit Min(2) Max (2) Min (2) Max (2) tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 - 0 900 t r(SDA) ns SDA and SCL rise time - 1000 - 300 t r(SCL) t f(SDA) SDA and SCL fall time - 300 - 300 t f(SCL) th(STA) START condition hold time 4.0 - 0.6 - μs Repeated START condition setup tsu(STA) time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - μs STOP to START condition time (bus tw(STO:STA) free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 400 pF 1. f must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz). SYSCLK 2. Data based on standard I2C protocol requirement, not tested in production. Note: For speeds around 200 kHz, the achieved speed can have a± 5% tolerance For other speed ranges, the achieved speed can have a± 2% tolerance The above variations depend on the accuracy of the external components used. 100/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 37. Typical application with I2C bus and timing diagram 1) (cid:57)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39) (cid:23)(cid:17)(cid:26)(cid:78)(cid:159) (cid:23)(cid:17)(cid:26)(cid:78)(cid:159) (cid:20)(cid:19)(cid:19)(cid:159) (cid:54)(cid:39)(cid:36) (cid:44)(cid:21)(cid:38)(cid:3)(cid:37)(cid:56)(cid:54) (cid:20)(cid:19)(cid:19)(cid:159) (cid:54)(cid:38)(cid:47) (cid:54)(cid:55)(cid:48)(cid:27)(cid:47) (cid:53)(cid:72)(cid:83)(cid:72)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:86)(cid:87)(cid:68)(cid:85)(cid:87) (cid:54)(cid:87)(cid:68)(cid:85)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:55)(cid:36)(cid:12) (cid:87)(cid:90)(cid:11)(cid:54)(cid:55)(cid:50)(cid:29)(cid:54)(cid:55)(cid:36)(cid:12) (cid:54)(cid:39)(cid:36) (cid:54)(cid:87)(cid:68)(cid:85)(cid:87) (cid:87)(cid:73)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:54)(cid:87)(cid:82)(cid:83) (cid:54)(cid:38)(cid:47) (cid:87)(cid:75)(cid:11)(cid:54)(cid:55)(cid:36)(cid:12)(cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:47)(cid:43)(cid:12) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:47)(cid:47)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:47)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:47)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:55)(cid:50)(cid:12) (cid:48)(cid:54)(cid:22)(cid:21)(cid:25)(cid:21)(cid:19)(cid:57)(cid:21) 1. Measurement points are done at CMOS levels: 0.3 x V and 0.7 x V DD DD DocID15962 Rev 15 101/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.9 LCD controller (STM8L152xx only) In the following table, data is guaranteed by design. Not tested in production. Table 45. LCD characteristics Symbol Parameter Min Typ Max. Unit V LCD external voltage - - 3.6 V LCD V LCD internal reference voltage 0 - 2.6 - V LCD0 V LCD internal reference voltage 1 - 2.7 - V LCD1 V LCD internal reference voltage 2 - 2.8 - V LCD2 V LCD internal reference voltage 3 - 2.9 - V LCD3 V LCD internal reference voltage 4 - 3.0 - V LCD4 V LCD internal reference voltage 5 - 3.1 - V LCD5 V LCD internal reference voltage 6 - 3.2 - V LCD6 V LCD internal reference voltage 7 - 3.3 - V LCD7 C V external capacitance 0.1 - 2 µF EXT LCD Supply current(1) at V = 1.8 V - 3 - µA DD I DD Supply current(1) at V = 3 V - 3 - µA DD R (2) High value resistive network (low drive) - 6.6 - MΩ HN R (3) Low value resistive network (high drive) - 360 - kΩ LN V Segment/Common higher level voltage - - V V 33 LCDx V Segment/Common 2/3 level voltage - 2/3V - V 23 LCDx V Segment/Common 1/2 level voltage - 1/2V - V 12 LCDx V Segment/Common 1/3 level voltage - 1/3V - V 13 LCDx V Segment/Common lowest level voltage 0 - - V 0 1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels active, no LCD connected. 2. R is the total high value resistive network. HN 3. R is the total low value resistive network. LN VLCD external capacitor (STM8L152xx only) The application can achieve a stabilized LCD reference voltage by connecting an external capacitor C to the V pin. C is specified in Table 45. EXT LCD EXT 102/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters 9.3.10 Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 46. Reference voltage characteristics Symbol Parameter Conditions Min Typ Max. Unit Internal reference voltage I - - 1.4 - µA REFINT consumption ADC sampling time when reading T (1)(2) - - 5 10 µs S_VREFINT the internal reference voltage Internal reference voltage buffer I (2) - - 13.5 25 µA BUF consumption (used for ADC) V Reference voltage output - 1.202(3) 1.224 1.242(3) V REFINT out Internal reference voltage low I (2) power buffer consumption (used - - 730 1200 nA LPBUF for comparators or output) I (2) Buffer output current(4) - - - 1 µA REFOUT C Reference voltage output load - - - 50 pF REFOUT Internal reference voltage startup t - - 2 3 ms VREFINT time Internal reference voltage buffer t (2) - - - 10 µs BUFEN startup time once enabled (1) Accuracy of V stored in the ACC REFINT - - - ± 5 mV VREFINT VREFINT_Factory_CONV byte(5) Stability of V over REFINT -40 °C ≤ T ≤ 125 °C - 20 50 ppm/°C temperature A STAB VREFINT Stability of V over REFINT 0 °C ≤ T ≤ 50 °C - - 20 ppm/°C temperature A Stability of V after 1000 STAB REFINT - - - TBD ppm VREFINT hours 1. Defined when ADC output reaches its final value ±1/2LSB 2. Data guaranteed by design. 3. Tested in production at V = 3 V ±10 mV. DD 4. To guaranty less than 1% VREFOUT deviation. 5. Measured at V = 3 V ±10 mV. This value takes into account V accuracy and ADC conversion accuracy. DD DD DocID15962 Rev 15 103/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.11 Temperature sensor In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 47. TS characteristics Symbol Parameter Min Typ Max. Unit V (1) Sensor reference voltage at 90°C ±5 °C, 0.580 0.597 0.614 V 90 T V linearity with temperature - ±1 ±2 °C L SENSOR Avg_slope (2) Average slope 1.59 1.62 1.65 mV/°C I (2) Consumption - 3.4 6 µA DD(TEMP) T (2)(3) Temperature sensor startup time - - 10 µs START ADC sampling time when reading the T (2) 10 - - µs S_TEMP temperature sensor 1. Tested in production at V = 3 V ±10 mV. The 8 LSB of the V ADC conversion result are stored in the DD 90 TS_Factory_CONV_V90 byte. 2. Data guaranteed by design. 3. Defined for ADC output reaching its final value ±1/2LSB. 9.3.12 Comparator characteristics In the following table, data is guaranteed by design, not tested in production, unless otherwise specified. Table 48. Comparator 1 characteristics Symbol Parameter Min Typ Max(1) Unit VDDA Analog supply voltage 1.65 - 3.6 V T Temperature range -40 - 125 °C A R R value 300 400 500 400K 400K kΩ R R value 7.5 10 12.5 10K 10K VIN Comparator 1 input voltage range 0.6 - VDDA V VREFINT Internal reference voltage(2) 1.202 1.224 1.242 tSTART Comparator startup time - 7 10 µs t Propagation delay(3) - 3 10 d V Comparator offset error - ±3 ±10 mV offset I Current consumption(4) - 160 260 nA COMP1 1. Based on characterization. 2. Tested in production at V = 3 V ±10 mV. DD 3. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non- inverting input set to the reference. 4. Comparator consumption only. Internal reference voltage not included. 104/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters In the following table, data is guaranteed by design, not tested in production. Table 49. Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max(1) Unit VDDA Analog supply voltage - 1.65 - 3.6 V T Temperature range - -40 - 125 °C A VIN Comparator 2 input voltage range - 0 - VDDA V Fast mode - 15 20 tSTART Comparator startup time Slow mode - 20 25 Propagation delay in slow 1.65 V ≤ VDDA ≤ 2.7 V - 1.8 3.5 t µs d slow mode(2) 2.7 V ≤ V ≤ 3.6 V - 2.5 6 DDA 1.65 V ≤ V ≤ 2.7 V - 0.8 2 t Propagation delay in fast mode(2) DDA d fast 2.7 V ≤ V ≤ 3.6 V - 1.2 4 DDA V Comparator offset error - - ±4 ±20 mV offset Fast mode - 3.5 5 I Current consumption(3) µA COMP2 Slow mode - 0.5 2 1. Based on characterization. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non- inverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. DocID15962 Rev 15 105/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.13 12-bit DAC characteristics In the following table, data is guaranteed by design, not tested in production. Table 50. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit V Analog supply voltage - 1.8 - 3.6 V DDA VREF+ Reference supply voltage - 1.8 - VDDA V = 3.3 V, no REF+ load, middle code - 130 220 Current consumption on V (0x800) I REF+ VREF supply V = 3.3 V, no REF+ load, worst code - 220 350 (0x000) µA V = 3.3 V, no load, DDA - 210 320 Current consumption on V middle code (0x800) I DDA VDDA supply V = 3.3 V, no load, DDA - 320 520 worst code (0x000) T Temperature range - -40 - 125 °C A R Resistive load(1) (2) DACOUT buffer ON 5 - - kΩ L R Output impedance DACOUT buffer OFF - 8 10 kΩ O C Capacitive load(3) - - - 50 pF L DACOUT buffer ON 0.2 - V -0.2 V DAC_OUT DAC_OUT voltage(4) DDA DACOUT buffer OFF 0 - V -1 LSB V REF+ Settling time (full scale: for a 12- bit input code transition between tsettling the lowest and the highest input RL ≥5 kΩ, CL≤ 50 pF - 7 12 µs codes when DAC_OUT reaches the final value ±1LSB) Max frequency for a correct Update rate DwAheCn_ OsmUaTl l (v@ar9ia5t%io)n c ohfa tnhgee i nput RL ≥ 5 kΩ, CL ≤ 50 pF - 1 Msps code (from code i to i+1LSB). Wakeup time from OFF state. tWAKEUP Input code between lowest and RL ≥5 kΩ, CL≤ 50 pF - 9 15 µs highest possible codes. PSRR+ PVoDwDAe)r (ssutaptpicly D rCej emcetioansu rraetmio e(ntot) RL≥ 5 kΩ, CL≤ 50 pF - -60 -35 dB 1. Resistive load between DACOUT and GNDA. 2. Output on PF0 (48-pin package only). 3. Capacitive load at DACOUT pin. 4. It gives the output excursion of the DAC. 106/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters In the following table, data is based on characterization results, not tested in production. Table 51. DAC accuracy Symbol Parameter Conditions Typ Max Unit RL ≥5 kΩ, CL≤ 50 pF 1.5 3 DACOUT buffer ON(2) DNL Differential non linearity(1) No load 1.5 3 DACOUT buffer OFF RL ≥5 kΩ, CL≤ 50 pF 2 4 DACOUT buffer ON(2) INL Integral non linearity(3) 12-bit No load 2 4 LSB DACOUT buffer OFF RL ≥5 kΩ, CL≤ 50 pF ±10 ±25 DACOUT buffer ON(2) Offset Offset error(4) No load ±5 ±8 DACOUT buffer OFF Offset1 Offset error at Code 1 (5) DACOUT buffer OFF ±1.5 ±5 RL ≥5 kΩ, CL≤ 50 pF +0.1/-0.2 +0.2/-0.5 DACOUT buffer ON(2) Gain error Gain error(6) % No load +0/-0.2 +0/-0.4 DACOUT buffer OFF RL ≥5 kΩ, CL≤ 50 pF 12 30 DACOUT buffer ON(2) 12-bit TUE Total unadjusted error LSB No load 8 12 DACOUT buffer OFF 1. Difference between two consecutive codes - 1 LSB. 2. For 48-pin packages only. For 28-pin and 32-pin packages, DAC output buffer must be kept off and no load must be applied. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023. 4. Difference between the value measured at Code (0x800) and the ideal value = V /2. REF+ 5. Difference between the value measured at Code (0x001) and the ideal value. 6. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF when buffer is ON, and from Code giving 0.2 V and (V -0.2) V when buffer is OFF. DDA In the following table, data is guaranteed by design, not tested in production. Table 52. DAC output on PB4-PB5-PB6(1) Symbol Parameter Conditions Max Unit 2.7 V < VDD < 3.6 V 1.4 Internal resistance 2.4 V < VDD < 3.6 V 1.6 Rint between DAC output and kΩ PB4-PB5-PB6 output 2.0 V < VDD < 3.6 V 3.2 1.8 V < VDD < 3.6 V 8.2 1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing interface I/O switch registers. DocID15962 Rev 15 107/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.14 12-bit ADC1 characteristics In the following table, data is guaranteed by design, not tested in production. Table 53. ADC1 characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.8 - 3.6 V Reference supply 2.4 V ≤ VDDA≤ 3.6 V 2.4 - VDDA V V REF+ voltage 1.8 V ≤ VDDA≤ 2.4 V VDDA V VREF- Lower reference voltage - VSSA V Current on the VDDA IVDDA input pin - - 1000 1450 µA 700 - - µA Current on the VREF+ (peak)(1) IVREF+ input pin 400 450 - - µA (average)(1) Conversion voltage VAIN range - 0(2) - VREF+ V T Temperature range - -40 - 125 °C A External resistance on on PF0 fast channel - - RAIN VAIN on all other channels - - 50(3) kΩ Internal sample and hold on PF0 fast channel - - CADC capacitor 16 pF on all other channels - - 2.4 V≤ V ≤ 3.6 V DDA 0.320 - 16 MHz ADC sampling clock without zooming f ADC frequency 1.8 V≤ V ≤ 2.4 V DDA 0.320 - 8 MHz with zooming V on PF0 fast AIN - - 1(4)(5) MHz channel fCONV 12-bit conversion rate V on all other AIN - - 760(4)(5) kHz channels External trigger fTRIG frequency - - - tconv 1/fADC tLAT External trigger latency - - - 3.5 1/fSYSCLK 108/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Table 53. ADC1 characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit V on PF0 fast AIN channel 0.43(4)(5) - - µs V < 2.4 V DDA V on PF0 fast AIN channel 0.22(4)(5) - - µs tS Sampling time 2.4 V ≤ V ≤ 3.6 V DDA V on slow channels AIN 0.86(4)(5) - - µs V < 2.4 V DDA V on slow channels AIN 0.41(4)(5) - - µs 2.4 V ≤ V ≤ 3.6 V DDA - 12 + t 1/f S ADC tconv 12-bit conversion time 16 MHz 1(4) µs Wakeup time from OFF tWKUP state - - - 3 µs T = +25 °C - - 1(7) s A Time before a new t (6) T = +70 °C - - 20(7) ms IDLE conversion A T = +125 °C - - 2(7) ms A Internal reference refer to t - - - ms VREFINT voltage startup time Table 46 1. The current consumption through V is composed of two parameters: REF - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 2. V or V must be tied to ground. REF- DDA 3. Guaranteed by design. 4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ. 5. Value obtained for continuous conversion on fast channel. 6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t IDLE. 7. The t maximum value is ∞ on the “Z” revision code of the device. IDLE DocID15962 Rev 15 109/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 In the following three tables, data is guaranteed by characterization result, not tested in production. Table 54. ADC1 accuracy with V = 3.3 V to 2.5 V DDA Symbol Parameter Conditions Typ Max Unit f = 16 MHz 1 1.6 ADC DNL Differential non linearity f = 8 MHz 1 1.6 ADC f = 4 MHz 1 1.5 ADC f = 16 MHz 1.2 2 ADC INL Integral non linearity f = 8 MHz 1.2 1.8 LSB ADC f = 4 MHz 1.2 1.7 ADC f = 16 MHz 2.2 3.0 ADC TUE Total unadjusted error f = 8 MHz 1.8 2.5 ADC f = 4 MHz 1.8 2.3 ADC f = 16 MHz 1.5 2 ADC Offset Offset error f = 8 MHz 1 1.5 ADC f = 4 MHz 0.7 1.2 ADC LSB f = 16 MHz ADC Gain Gain error f = 8 MHz 1 1.5 ADC f = 4 MHz ADC Table 55. ADC1 accuracy with V = 2.4 V to 3.6 V DDA Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 1.7 3 LSB TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1.5 3 LSB Table 56. ADC1 accuracy with V = V + = 1.8 V to 2.4 V DDA REF Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB 110/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 38. ADC1 accuracy characteristics V V [1LSB = REF+(or D D A depending on package)] IDEAL 4096 4096 EG (1) Example of an actual transfer curve 4095 (2) The ideal transfer curve 4094 (3) End point correlation line 4093 (2) ET=Total Unadjusted Error: maximum deviation 7 ET (3) bEeOt=wOefefsne tth Ee rarocrt:u dael avinadti othne b iedtewael etrna nthsefe frir csut ravcetsu.al (1) transition and the first ideal one. 6 EG=Gain Error: deviation between the last ideal 5 transition and the last actual one. 4 EO EL EbeDt=wDeieffne raecnttuiaall Lsitneepasr iatyn dE rtrhoer :i dmeaaxl imonuem. deviation 3 ED EbeLt=wIneteeng raanl yL iancetauraitl yt raEnrrsoitri:o nm aanxdim tuhme ednedv iaptoioinnt 2 correlation line. 1 1LSBIDEAL 0 1 2 3 4 5 6 7 4093409440954096 VSSA VDDA ai14395b Figure 39. Typical connection diagram using the ADC (cid:54)(cid:55)(cid:48)(cid:27) (cid:57)(cid:39)(cid:39) (cid:54)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:75)(cid:82)(cid:79)(cid:71)(cid:3)(cid:36)(cid:39)(cid:38)(cid:3) (cid:57)(cid:55) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:25)(cid:57) (cid:53)(cid:36)(cid:44)(cid:49)(cid:11)(cid:20)(cid:12) (cid:36)(cid:44)(cid:49)(cid:91) (cid:53)(cid:36)(cid:39)(cid:38) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:57)(cid:55) (cid:57)(cid:36)(cid:44)(cid:49) (cid:38)(cid:83)(cid:68)(cid:85)(cid:68)(cid:86)(cid:76)(cid:87)(cid:76)(cid:70)(cid:3)(cid:11)(cid:21)(cid:12) (cid:19)(cid:17)(cid:25)(cid:57) (cid:38)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:44)(cid:47)(cid:147)(cid:24)(cid:19)(cid:81)(cid:36) (cid:68)(cid:76)(cid:20)(cid:26)(cid:19)(cid:28)(cid:19)(cid:73) 1. Refer to Table 53 for the values of R and C . AIN ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7 pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC DocID15962 Rev 15 111/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 Figure 40. Maximum dynamic current consumption on V supply pin during ADC REF+ conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700µA 300µA Table 57. R max for f = 16 MHz(1) AIN ADC R max (kohm) AIN Ts Ts Slow channels Fast channels (cycles) (µs) 2.4 V < V < 3.6 V 1.8 V < V < 2.4 V 2.4 V < V < 3.3 V 1.8 V < V < 2.4 V DDA DDA DDA DDA 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. Guaranteed by design. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42, depending on whether V is connected to V or not. Good quality ceramic 10 nF REF+ DDA capacitors should be used. They should be placed as close as possible to the chip. 112/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Figure 41. Power supply and reference decoupling (V not connected to V ) REF+ DDA (cid:54)(cid:55)(cid:48)(cid:27)(cid:47) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:85)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:39)(cid:39)(cid:36) (cid:54)(cid:88)(cid:83)(cid:83)(cid:79)(cid:92) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:54)(cid:54)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:68)(cid:76)(cid:20)(cid:26)(cid:19)(cid:22)(cid:20)(cid:70) Figure 42. Power supply and reference decoupling (V connected to V ) REF+ DDA (cid:54)(cid:55)(cid:48)(cid:27)(cid:47) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14)(cid:18)(cid:57)(cid:39)(cid:39)(cid:36) (cid:54)(cid:88)(cid:83)(cid:83)(cid:79)(cid:92) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14)(cid:18)(cid:57)(cid:39)(cid:39)(cid:36) (cid:68)(cid:76)(cid:20)(cid:26)(cid:19)(cid:22)(cid:21)(cid:70) DocID15962 Rev 15 113/142 115

Electrical parameters STM8L151x4/6, STM8L152x4/6 9.3.15 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to V and V DD SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 58. EMS data Level/ Symbol Parameter Conditions Class Voltage limits to be applied on VDD = 3.3 V, TA = +25 °C, VFESD any I/O pin to induce a functional fCPU= 16 MHz, 3B disturbance conforms to IEC 61000 Ftoa bset t raapnpsliieedn tt hvoroltuagghe 1b0u0rs pt Flim oints VDD = 3.3 V, TA = +25 °C, Using HSI 4A VEFTB V and V pins to induce a fCPU = 16 MHz, DD SS conforms to IEC 61000 Using HSE 2B functional disturbance Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin. 114/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Electrical parameters Table 59. EMI data (1) Max vs. Monitored Symbol Parameter Conditions Unit frequency band 16 MHz V = 3.6 V, 0.1 MHz to 30 MHz -3 DD TA = +25 °C, 30 MHz to 130 MHz 9 dBμV SEMI Peak level LQFP32 conforming to 130 MHz to 1 GHz 4 IEC61967-2 SAE EMI Level 2 - 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. Table 60. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Unit value (1) Electrostatic discharge voltage VESD(HBM) (human body model) 2000 T = +25 °C V Electrostatic discharge voltage A VESD(CDM) (charge device model) 500 1. Data based on characterization results. Static latch-up • LU: 3 complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 61. Electrical sensitivities Symbol Parameter Class LU Static latch-up class II DocID15962 Rev 15 115/142 115

Package information STM8L151x4/6, STM8L152x4/6 10 Package information 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10.2 LQFP48 package information Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33)(cid:33) (cid:17) (cid:33) (cid:67) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:43) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:20)(cid:24) (cid:17)(cid:19) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:17)(cid:18) (cid:69) (cid:21)(cid:34)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:18) 1. Drawing is not to scale. 116/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Table 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID15962 Rev 15 117/142 136

Package information STM8L151x4/6, STM8L152x4/6 Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint (cid:16)(cid:14)(cid:21)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:16)(cid:14)(cid:18)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:24) (cid:17)(cid:19) (cid:17) (cid:17)(cid:18) (cid:17)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:17)(cid:17)(cid:68) 1. Dimensions are expressed in millimeters. 118/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 45. LQFP48 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3) (cid:11)(cid:20)(cid:12) (cid:52)(cid:53)(cid:46)(cid:25)(cid:45)(cid:18)(cid:22)(cid:18) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:36)(cid:21)(cid:53)(cid:23) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:54)(cid:55)(cid:3)(cid:79)(cid:82)(cid:74)(cid:82) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:22)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID15962 Rev 15 119/142 136

Package information STM8L151x4/6, STM8L152x4/6 10.3 UFQFPN48 package information Figure 46. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:79)(cid:68)(cid:86)(cid:72)(cid:85)(cid:3)(cid:80)(cid:68)(cid:85)(cid:78)(cid:76)(cid:81)(cid:74)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39) (cid:36) (cid:40) (cid:40) (cid:55) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3) (cid:71)(cid:71)(cid:71) (cid:36)(cid:20) (cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:72) (cid:69) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:60) (cid:39) (cid:60) (cid:40)(cid:91)(cid:83)(cid:82)(cid:86)(cid:72)(cid:71)(cid:3)(cid:83)(cid:68)(cid:71)(cid:3) (cid:39)(cid:21) (cid:68)(cid:85)(cid:72)(cid:68) (cid:20) (cid:47) (cid:23)(cid:27) (cid:38)(cid:3)(cid:19)(cid:17)(cid:24)(cid:19)(cid:19)(cid:91)(cid:23)(cid:24)(cid:131) (cid:83)(cid:76)(cid:81)(cid:20)(cid:3)(cid:70)(cid:82)(cid:85)(cid:81)(cid:72)(cid:85) (cid:53)(cid:3)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:3)(cid:87)(cid:92)(cid:83)(cid:17) (cid:40)(cid:21) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:61) (cid:20) (cid:23)(cid:27) (cid:61) (cid:36)(cid:19)(cid:37)(cid:28)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 120/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information T able 63. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 47. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint (cid:23)(cid:14)(cid:19)(cid:16) (cid:22)(cid:14)(cid:18)(cid:16) (cid:20)(cid:24) (cid:19)(cid:23) (cid:17) (cid:19)(cid:22) (cid:16)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:22)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:22)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:22)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:17)(cid:18) (cid:18)(cid:21) (cid:17)(cid:19) (cid:18)(cid:20) (cid:16)(cid:14)(cid:21)(cid:16) (cid:16)(cid:14)(cid:23)(cid:21) (cid:16)(cid:14)(cid:21)(cid:21) (cid:21)(cid:14)(cid:24)(cid:16) (cid:33)(cid:16)(cid:34)(cid:25)(cid:63)(cid:38)(cid:48)(cid:63)(cid:54)(cid:18) 1. Dimensions are expressed in millimeters. DocID15962 Rev 15 121/142 136

Package information STM8L151x4/6, STM8L152x4/6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 48. UFQFPN48 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:25)(cid:45)(cid:18)(cid:22)(cid:18) (cid:36)(cid:21)(cid:54)(cid:23) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:54)(cid:55)(cid:3)(cid:79)(cid:82)(cid:74)(cid:82) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:23)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 122/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information 10.4 LQFP32 package information Figure 49. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33) (cid:33) (cid:17) (cid:67) (cid:33) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:43) (cid:36) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:18)(cid:20) (cid:17)(cid:23) (cid:18)(cid:21) (cid:17)(cid:22) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:19)(cid:18) (cid:25) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:24) (cid:69) (cid:22)(cid:55)(cid:64)(cid:46)(cid:38)(cid:64)(cid:55)(cid:19) 1. Drawing is not to scale. DocID15962 Rev 15 123/142 136

Package information STM8L151x4/6, STM8L152x4/6 Table 64. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. 124/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Figure 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint (cid:16)(cid:14)(cid:24)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:19)(cid:21) (cid:18)(cid:24) (cid:19)(cid:22) (cid:18)(cid:23) (cid:16)(cid:14)(cid:21)(cid:16) (cid:19)(cid:17)(cid:22)(cid:19) (cid:23)(cid:14)(cid:19)(cid:16) (cid:22)(cid:14)(cid:17)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:19) (cid:26) (cid:18) (cid:25) (cid:17)(cid:14)(cid:18)(cid:16) (cid:22)(cid:14)(cid:17)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:54)(cid:63)(cid:38)(cid:48)(cid:63)(cid:54)(cid:18) 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 51. LQFP32 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:52)(cid:53)(cid:46)(cid:25)(cid:45) (cid:18)(cid:22)(cid:18)(cid:44)(cid:21)(cid:53)(cid:23) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:54)(cid:55)(cid:3)(cid:79)(cid:82)(cid:74)(cid:82) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:24)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering DocID15962 Rev 15 125/142 136

Package information STM8L151x4/6, STM8L152x4/6 Samples to run qualification activity. 10.5 UFQFPN32 package information Figure 52. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline (cid:39) (cid:36) (cid:71)(cid:71)(cid:71) (cid:38) (cid:72) (cid:36)(cid:20) (cid:36)(cid:21) (cid:38) (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:39)(cid:20) (cid:69) (cid:72) (cid:40)(cid:21) (cid:69) (cid:40)(cid:20) (cid:40) (cid:20) (cid:47) (cid:22)(cid:21) (cid:39)(cid:21) (cid:47) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20)(cid:3)(cid:44)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:33)(cid:16)(cid:34)(cid:24)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:18) 1. Drawing is not to scale. 126/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Table 65. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.900 5.000 5.100 0.1929 0.1969 0.2008 E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 53. UFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint (cid:24)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:27)(cid:19) (cid:19)(cid:17)(cid:25)(cid:19) (cid:20)(cid:19) (cid:19)(cid:22) (cid:18) (cid:19)(cid:21) (cid:22)(cid:17)(cid:23)(cid:24) (cid:24)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:27)(cid:19) (cid:22)(cid:17)(cid:23)(cid:24) (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:25) (cid:18)(cid:24) (cid:26) (cid:18)(cid:23) (cid:19)(cid:17)(cid:26)(cid:24) (cid:22)(cid:17)(cid:27)(cid:19) (cid:36)(cid:19)(cid:37)(cid:27)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:21) 1. Dimensions are expressed in millimeters. DocID15962 Rev 15 127/142 136

Package information STM8L151x4/6, STM8L152x4/6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 54. UFQFPN32 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3) (cid:11)(cid:20)(cid:12) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:45)(cid:18)(cid:22)(cid:18)(cid:44)(cid:21) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:54)(cid:55)(cid:3)(cid:79)(cid:82)(cid:74)(cid:82) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51) (cid:39)(cid:82)(cid:87)(cid:3)(cid:11)(cid:83)(cid:76)(cid:81)(cid:3)(cid:20)(cid:12) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:25)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 128/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information 10.6 UFQFPN28 package information Figure 55. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline (cid:39) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:60) (cid:40) (cid:39) (cid:39)(cid:20) (cid:40)(cid:20) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:61) (cid:33)(cid:16)(cid:34)(cid:16)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:21) 1. Drawing is not to scale. T able 66. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data(1) millimeters inches Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - 0.000 0.050 - 0.0000 0.0020 D 3.900 4.000 4.100 0.1535 0.1575 0.1614 D1 2.900 3.000 3.100 0.1142 0.1181 0.1220 E 3.900 4.000 4.100 0.1535 0.1575 0.1614 E1 2.900 3.000 3.100 0.1142 0.1181 0.1220 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 L1 0.250 0.350 0.450 0.0098 0.0138 0.0177 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - DocID15962 Rev 15 129/142 136

Package information STM8L151x4/6, STM8L152x4/6 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 56. UFQFPN28 - 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint (cid:19)(cid:14)(cid:19)(cid:16) (cid:16)(cid:14)(cid:21)(cid:16) (cid:19)(cid:14)(cid:18)(cid:16) (cid:20)(cid:14)(cid:19)(cid:16) (cid:19)(cid:14)(cid:19)(cid:16) (cid:19)(cid:14)(cid:18)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:16)(cid:14)(cid:21)(cid:21) (cid:16)(cid:14)(cid:21)(cid:16) (cid:16)(cid:14)(cid:21)(cid:16) (cid:33)(cid:16)(cid:34)(cid:16)(cid:63)(cid:38)(cid:48)(cid:63)(cid:54)(cid:18) 1. Dimensions are expressed in millimeters. 130/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 57. UFQFPN28 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3) (cid:11)(cid:20)(cid:12) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:18)(cid:22)(cid:18)(cid:40)(cid:21)(cid:20) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:51) (cid:39)(cid:82)(cid:87)(cid:3)(cid:11)(cid:83)(cid:76)(cid:81)(cid:3)(cid:20)(cid:12) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:26)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID15962 Rev 15 131/142 136

Package information STM8L151x4/6, STM8L152x4/6 10.7 WLCSP28 package information Figure 58. WLCSP28 - 28-pin, 1.703 x 2.841 mm, 0.4 mm pitch wafer level chip scale package outline (cid:69)(cid:69)(cid:69)(cid:61) (cid:72)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:39) (cid:72) (cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:59) (cid:60) (cid:72) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:72)(cid:21) (cid:40) (cid:49)(cid:82)(cid:87)(cid:70)(cid:75) (cid:42) (cid:68)(cid:68)(cid:68) (cid:41) (cid:36)(cid:21) (cid:39)(cid:76)(cid:72)(cid:3)(cid:44)(cid:39) (cid:36) (cid:11)(cid:23)(cid:59)(cid:12) (cid:58)(cid:68)(cid:73)(cid:72)(cid:85)(cid:3)(cid:69)(cid:68)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:37)(cid:88)(cid:80)(cid:83)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:54)(cid:76)(cid:71)(cid:72)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:36)(cid:36) (cid:21) (cid:37)(cid:88)(cid:80)(cid:83) (cid:41)(cid:85)(cid:82)(cid:81)(cid:87)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:72)(cid:72)(cid:72)(cid:3)(cid:61) (cid:36)(cid:20) (cid:61) (cid:70)(cid:70)(cid:70) (cid:61)(cid:59)(cid:60) (cid:69)(cid:11)(cid:21)(cid:27)(cid:91)(cid:12) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:85)(cid:82)(cid:87)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:69)(cid:92)(cid:3)(cid:28)(cid:19)(cid:131) (cid:36)(cid:19)(cid:36)(cid:48)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. 132/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information Table 67. WLCSP28 - 28-pin, 1.703 x 2.841 mm, 0.4 mm pitch wafer level chip scale package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.540 0.570 0.600 0.0213 0.0224 0.0236 A1 - 0.190 - - 0.0075 - A2 - 0.380 - - 0.0150 - b(2) 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 1.668 1.703 1.738 0.0657 0.0670 0.0684 E 2.806 2.841 2.876 0.1105 0.1119 0.1132 e - 0.400 - - 0.0157 - e1 - 1.200 - - 0.0472 - e2 - 2.400 - - 0.0945 - F - 0.251 - - 0.0099 - G - 0.222 - - 0.0087 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. DocID15962 Rev 15 133/142 136

Package information STM8L151x4/6, STM8L152x4/6 Figure 59. WLCSP28 marking example (package top view) (cid:39)(cid:82)(cid:87)(cid:3)(cid:11)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:20)(cid:12) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87) (cid:11)(cid:20)(cid:12) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:25)(cid:45)(cid:21)(cid:20) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:26)(cid:27)(cid:27)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 134/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Package information 10.8 Thermal characteristics The maximum chip junction temperature (T ) must never exceed the values given in Jmax Table 18: General operating conditions on page 66. The maximum chip-junction temperature, T , in degree Celsius, may be calculated using Jmax the following equation: T = T + (P x Θ ) Jmax Amax Dmax JA Where: • T is the maximum ambient temperature in °C Amax • Θ is the package junction-to-ambient thermal resistance in °C/W JA • P is the sum of P and P (P = P + P ) Dmax INTmax I/Omax Dmax INTmax I/Omax • P is the product of I andV , expressed in Watts. This is the maximum chip INTmax DD DD internal power. • P represents the maximum power dissipation on output pins I/Omax Where: P =Σ (V *I ) + Σ((V -V )*I ), I/Omax OL OL DD OH OH taking into account the actual V /I andV /I of the I/Os at low and high level in OL OL OH OH the application. Table 68. Thermal characteristics(1) Symbol Parameter Value Unit Thermal resistance junction-ambient Θ 65 °C/W JA LQFP 48- 7 x 7 mm Thermal resistance junction-ambient Θ 32 °C/W JA UFQFPN 48- 7 x 7mm Thermal resistance junction-ambient Θ 59 °C/W JA LQFP 32 - 7 x 7 mm Thermal resistance junction-ambient Θ 38 °C/W JA UFQFPN 32 - 5 x 5 mm Thermal resistance junction-ambient Θ 118 °C/W JA UFQFPN28 - 4 x 4 mm Thermal resistance junction-ambient Θ 70 °C/W JA WLCSP28 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. DocID15962 Rev 15 135/142 136

Part numbering STM8L151x4/6, STM8L152x4/6 11 Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Figure 60. Medium-density STM8L15x ordering information scheme Example: STM8 L 151 C 4 U 6 TR Product class STM8 microcontroller Family type L = Low power Sub-family type 151 = Ultra-low-power 152 = Ultra-low-power with LCD Pin count C = 48 pins K = 32 pins G = 28 pins Program memory size 4 = 16 Kbyte 6 = 32 Kbyte Package U = UFQFPN T = LQFP Y = WLCSP Temperature range 3 = - 40 °C to 125 °C 7 = - 40 °C to 105 °C 6 = - 40 °C to 85 °C Delivery TR = Tape & Reel 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you. 136/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Revision history 12 Revision history Table 69. Document revision history Date Revision Changes 06-Aug-2009 1 Initial release Updated peripheral naming throughout document. Added Figure: STM8L151Cx 48-pin pinout (without LCD). Added capacitive sensing channels in Features. Updated PA7, PC0 and PC1 in Table: Medium density 10-Sep-2009 2 STM8L15x pin description. Changed CLK and REMAP register names. Changed description of WDGHALT. Added typical power consumption values in Table 18 to Table 26. Corrected VIH max value. Added WLCSP28 package Modified Figure: Memory map and added 2 notes. Modified Low power run mode in Section: Low power modes. Added Section: Unique ID. Modified Table: Interrupt mapping (added reserved area at address 0x00 8008) 11-Dec-2009 3 Modified OPT4 option bits in Table: Option byte addresses. Table: Option byte description: modified OPT0 description (“disable” instead of “enable”) and OPT1 description Added OPTBL option bytes Modified Section: Electrical parameters. Changed title of the document (STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6) Changed pinout (V , V , V , V instead of SS1 DD1 SS2 DD 2 VSS, VDD, VSSIO, VDDIO Changed packages Changed first page Modified note 1 in Table: Medium density STM8L15x pin description. Added note to PA7, PC0, PC1 and PE0 in Table: Medium density STM8L15x pin description. 02-Apr-2010 4 Modified Figure: Memory map. Modified Table: WLCSP28 – 28-pin wafer level chip scale package, package mechanical data (min and max columns swapped) Modified Figure: WLCSP28 – 28-pin wafer level chip scale package, package outline (A1 ball location) Renamed Rm, Lm and Cm EXTI_CONF replaced with EXTI_CONF1 in Table: General hardware register map. Updated Section: Electrical parameters. DocID15962 Rev 15 137/142 141

Revision history STM8L151x4/6, STM8L152x4/6 Table 69. Document revision history (continued) Date Revision Changes Modified Introduction and Description. Modified Table: Legend/abbreviation for table 5 and Table: Medium density STM8L15x pin description (for PA0, PA1, PB0 and PB4 and for reset states in the floating input column) Modified Figure: Low density STM8L151xx device block diagram, Figure: Low density STM8L15x clock tree diagram, Figure: Low power modes and Figure : Low power real-time clock. Modified CLK_PCKENR2 and CLK_HSICALR reset values in Table: General hardware register map. Modified notes below Figure: Memory map. Modified PA_CR1 reset value. Modified reset values for Px_IDR registers. Modified Table: Voltage characteristics and Table: Current characteristics. 23-Jul-2010 5 Modified V in Table: I/O static characteristics. IH Modified Table: Total current consumption in Wait mode. Modified Figure Typical application with I2C bus and timing diagram 1). Modified I value in Figure: Typical connection diagram L using the ADC1. Modified R and R in Table: LCD characteristics. H L Added graphs in Section: Electrical parameters. Modified note 3 below Table: Reference voltage characteristics. Modified note 1 below Table: TS characteristics. Changed V value in Table: ESD absolute ESD(CDM) maximum ratings. Updated notes for UFQFPN32 and UFQFPN48 packages. Modified note on true open drain I/Os and I/O level columns in Table: Medium density STM8L15x pin description. Remapping option removed for USART1_TX, USART1_RX, and USART1_CK on PC2, PC3 and PC4 in Table: Medium density STM8L15x pin description. Modified IDWDG_KR reset value in Table: General hardware register map. 11-Mar-2011 6 Replaced VREF_OUT with VREFINT and TIMx_TRIG with TIMx_ETR. Added Table: Factory conversion registers. Modified reset values for TIM1_DCR1, IWDG_KR, RTC_DR1, RTC_DR2, RTC_SPRERH, RTC_SPRERL, RTC_APRER, RTC_WUTRH, and RTC_WUTRL in Table: General hardware register map. Added notes to certain values in Section: Embedded reference voltage and Section: Temperature sensor. 138/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Revision history Table 69. Document revision history (continued) Date Revision Changes Modified OPT1 and OPT4 description in Table: Option byte description. Updated Section: Electrical parameters “standard I/Os” replaced with “high sink I//Os”. 11-Mar-2011 6 cont’d Updated R R descriptions in Table: LCD HN and HN characteristics. Added Tape & Reel option to Figure: Medium density STM8L15x ordering information scheme. Features: updated bullet point concerning capacitive sensing channels. Section: Low power modes: updated Wait mode and Halt mode definitions. Section: Clock management: added ‘kHz’ to 32.768 in the ‘System clock sources bullet point’. Section: System configuration controller and routing interface: replaced last sentence concerning management of charge transfer acquisition sequence. Added Section: Touchsensing Section Development support: updated the Bootloader. Table: Medium density STM8L15x pin description: added LQFP32 to second column (same pinout as UFQFPN32); “Timer X - trigger” replaced by “Timer X - external trigger”; added note at the end of this table concerning the slope control of all GPIO pins. Table: Interrupt mapping: merged footnotes 1 and 2; updated some of the source blocks and descriptions. Section: Option bytes: replaced PM0051 by PM0054 06-Sep-2011 7 and UM0320 by UM0470. Table: Option byte description: replaced the factory default setting (0xAA) for OPT0. NRST pin: updated text above the Figure; updated Figure: Recommended NRST pin configuration. Table: TS characteristics: removed typ and max values for the parameter T ; added min value for same. S_TEMP Table: Comparator 1 characteristics: added typ value for ‘Comparator offset error’; added footnote 1. Table: Comparator 2 characteristics: updated t , START t , t , V , I ; added footnotes 1. and 3. dslow dfast offset COMP2 Table: DAC characteristics: updated max value for DAC_OUT voltage (DACOUT buffer ON). Section: 12-bit ADC1 characteristics: updated. Replaced Figure: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline and Figure: UFQFPN48 7 x 7 mm recommended footprint (dimensions in mm). Figure: Medium density STM8L15x ordering information scheme: removed ‘TR = Tape & Reel”. DocID15962 Rev 15 139/142 141

Revision history STM8L151x4/6, STM8L152x4/6 Table 69. Document revision history (continued) Date Revision Changes Features: replaced “’Dynamic consumption’ with ‘Consumption’. Table: Medium density STM8L15x pin description: updated OD column of NRST/PA1 pin. Table: Interrupt mapping: removed tamper 1, tamper 2 and tamper 3. Figure: UFQFPN48 package outline: replaced. Table: UFQFPN48 package mechanical data: updated title. Figure: UFQFPN32 - 32-lead ultra thin fine pitch quad 10-Feb-2012 8 flat no-lead package outline (5 x 5): removed the line over A1. Figure: UFQFPN28 package outline: replaced to improve readability of UFQFPN28 package dimensions A, L, and L1. Figure: Recommended UFQFPN28 footprint (dimensions in mm): updated title. Figure: WLCSP28 package outline: updated title. Table: WLCSP28 package mechanical data: updated title. Updated Table: UFQFPN48 package mechanical data. Updated Figure: UFQFPN28 package outline, Figure: Recommended UFQFPN28 footprint (dimensions in 02-Mar-2012 9 mm) and Table: UFQFPN28 package mechanical data. Table: WLCSP28 package mechanical data: Min and Max values removed for e1, e2, e3, e4, F and G dimensions. Figure: SPI1 timing diagram - master mode(1): changed SCK signals to ‘output’ instead of ‘input’. 30-Mar-2012 10 Figure: Medium density STM8L15x ordering information scheme: added ‘Tape & reel’ to package section. 26-Apr-2012 11 Updated Table: WLCSP28 package mechanical data. Updated Table: WLCSP28 package mechanical data. Updated Table: Medium-density STM8L15x pin description. 12-Nov-2013 12 Updated Table 2: Medium density STM8L15x low power device features and peripheral counts. Added Figure: Recommended LQFP48 footprint and Figure: Recommended LQFP32 footprint. Changed the default setting value of OPT5 to 0x00 in Table: Option byte addresses. Added tTEMP ‘BOR detector enabled’ and ‘disabled’ 12-Aug-2013 13 characteristics in Table: Embedded reset and power control block characteristics. Updated E2, D2 and ddd in Table: UFQFPN48 package mechanical data 140/142 DocID15962 Rev 15

STM8L151x4/6, STM8L152x4/6 Revision history Table 69. Document revision history (continued) Date Revision Changes Added: – Figure 45: LQFP48 marking example (package top view), – Figure 48: UFQFPN48 marking example (package top view), – Figure 51: LQFP32 marking example (package top 21-Apr-2015 14 view), – Figure 54: UFQFPN32 marking example (package top view), – Figure 57: UFQFPN28 marking example (package top view), – Figure 59: WLCSP28 marking example (package top view). Changed symbol V to V in Table 47: TS 125 90 characteristics and updated related Min/Typ/Max values. Updated Section 9.2: Absolute maximum ratings. Updated table notes for Table 30, Table 31, Table 32, Table 33, Table 34, Table 36, Table 38, Table 42, 07-Apr-2017 15 Table 43, Table 46, Table 47, Table 48, Table 49, Table 53, Table 57, and Table 60. Updated device marking paragraphs in Section 10.2, Section 10.3, Section 10.4, Section 10.5, Section 10.6, and Section 10.7. DocID15962 Rev 15 141/142 141

STM8L151x4/6, STM8L152x4/6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 142/142 DocID15962 Rev 15

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