STM690, STM704, STM795 STM802, STM804, STM805, STM806 3 V supervisor with battery switchover Features ■ RST or RST outputs 8 ■ NVRAM supervisor for external LPSRAM ■ Chip enable gating (STM795 only) for external 1 LPSRAM (7 ns max prop delay) ■ Manual (push-button) reset input SO8 (M) ■ 200 ms (typ) t rec ■ Watchdog timer - 1.6 s (typ) ■ Automatic battery switchover ■ Low battery supply current - 0.4 µA (typ) ■ Power-fail comparator (PFI/PFO) ■ Low supply current - 40 µA (typ) TSSOP8 3x3 (DS)(1) ■ Guaranteed RST (RST) assertion down to V = 1.0 V CC ■ Operating temperature: –40 °C to 85 °C (industrial grade) 1. Contact local ST sales office for availability. ■ RoHS compliance – Lead-free components are compliant with the RoHS directive Table 1. Device summary Manual Watchdog Active- low Active- high Battery Power-fail Chip enable reset Input RST(1) RST(1) switchover comparator gating input STM690T/S/R ✓ ✓ ✓ ✓ STM704T/S/R ✓ ✓ ✓ ✓ STM795T/S/R ✓(2) ✓ ✓ STM802T/S/R ✓ ✓ ✓ ✓ STM804T/S/R ✓ ✓(2) ✓ ✓ STM805T/S/R ✓ ✓(2) ✓ ✓ STM806T/S/R ✓ ✓ ✓ ✓ 1. All RST outputs push-pull (unless otherwise noted). 2. Open drain output. August 2010 Doc ID 10519 Rev 9 1/42 www.st.com 1

Contents STM690, STM704, STM795, STM802, STM804, STM805, STM806 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.1 MR (manual reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.2 WDI (watchdog input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.3 RST (active-low reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.4 RST (active-high reset - open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.5 PFI (power-fail input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.6 PFO (power-fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.7 V (supply output voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 OUT 1.1.8 Vccsw (V switch output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CC 1.1.9 E (chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.10 E (conditional chip enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CON 1.1.11 V (backup battery input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 BAT 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Push-button reset input (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Watchdog input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . 14 2.4 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Chip enable gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 Chip enable input (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Chip enable output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 Power-fail input/output (NOT available on STM795) . . . . . . . . . . . . . . . . 17 2.9 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10 Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 19 2.11 Negative-going V transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CC 3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Contents 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 10519 Rev 9 3/42

List of tables STM690, STM704, STM795, STM802, STM804, STM805, STM806 List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38 Table 10. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 List of figures List of figures Figure 1. Logic diagram (STM690/802/804/805). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic diagram (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Logic diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. STM690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. STM704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. STM795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Block diagram (STM690/802/804/805). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Block diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Block diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Hardware hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Chip enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. Chip enable waveform (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . . 18 Figure 14. Using a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. V to V on-resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CC OUT Figure 16. V to V on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BAT OUT Figure 17. Supply current vs. temperature (no load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. V threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PFI Figure 20. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 21. Power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rec Figure 22. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 23. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 24. E to E on-resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CON Figure 25. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 26. Output voltage vs. load current (V = 5 V; V = 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 25 CC BAT A Figure 27. Output voltage vs. load current (V = 0 V; V = 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 26 CC BAT A Figure 28. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 29. RST output voltage vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 30. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 31. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 32. Maximum transient duration vs. reset threshold overdrive. . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 33. E to E propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CON Figure 34. E to E propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CON Figure 35. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 36. MR timing waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 37. Watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 38 Doc ID 10519 Rev 9 5/42

Description STM690, STM704, STM795, STM802, STM804, STM805, STM806 1 Description The STM690/704/795/802/804/805/806 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write- protect external LPSRAM. A precision voltage reference and comparator monitors the V CC input for an out-of-tolerance condition. When an invalid V condition occurs, the reset CC output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package. Figure 1. Logic diagram (STM690/802/804/805) VCC VBAT VOUT WDI STM690/ 802/804/ RST (RST)(1) PFI 805 PFO VSS AI08846 1. For STM804/805, reset output is active-high and open drain. Figure 2. Logic diagram (STM704/806) VCC VBAT VOUT MR STM704 RST STM806 PFI PFO VSS AI08847 6/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description Figure 3. Logic diagram (STM795) VCC VBAT VOUT VCCSW STM795 RST E ECON VSS AI08848 T able 2. Signal names MR Push-button reset input WDI Watchdog input RST Active-low reset output RST(1) Active-high reset output E(2) Chip enable input E (2) Conditioned chip enable output CON Vccsw(2) V switch output CC V Supply voltage output OUT V Supply voltage CC V Backup supply voltage BAT PFI Power-fail input PFO Power-fail output V Ground SS 1. Open drain for STM804/805 only. 2. STM795. Doc ID 10519 Rev 9 7/42

Description STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 4. STM690/802/804/805 connections SO8/TSSOP8 VOUT 1 8 VBAT (1) VCC 2 7 RST (RST) VSS 3 6 WDI PFI 4 5 PFO AI08849 1. For STM804/805, reset output is active-high and open drain. Figure 5. STM704/806 connections SO8/TSSOP8 VOUT 1 8 VBAT VCC 2 7 RST VSS 3 6 MR PFI 4 5 PFO AI08850 Figure 6. STM795 connections SO8/TSSOP8 VOUT 1 8 VBAT VCC 2 7 RST VCCSW 3 6 ECON VSS 4 5 E AI08851 8/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description 1.1 Pin descriptions 1.1.1 MR (manual reset) A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for t after MR returns high. This active-low input has an internal pull-up. It can be rec driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. 1.1.2 WDI (watchdog input) If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function cannot be disabled by allowing the WDI pin to float. 1.1.3 RST (active-low reset) Pulses low for t when triggered, and stays low whenever V is below the reset threshold rec CC or when MR is a logic low. It remains low for t after either V rises above the reset rec CC threshold, the watchdog triggers a reset, or MR goes from low to high. 1.1.4 RST (active-high reset - open drain) Pulses high for t when triggered, and stays high whenever V is above the reset rec CC threshold or when MR is a logic high. It remains high for t after either V falls below the rec CC reset threshold, the watchdog triggers a reset, or MR goes from high to low. 1.1.5 PFI (power-fail input) When PFI is less than V or when V falls below V (2.4 V), PFO goes low; otherwise, PFI CC SW PFO remains high. Connect to ground if unused. 1.1.6 PFO (power-fail output) When PFI is less than V , or V falls below V , PFO goes low; otherwise, PFO remains PFI CC SW high. Leave open if unused. Output type is push-pull. 1.1.7 V (supply output voltage) OUT When V is above the switchover voltage (V ), V is connected to V through CC SO OUT CC a P-channel MOSFET switch. When V falls below V , V connects to V . Connect CC SO BAT OUT to V if no battery is used. CC 1.1.8 Vccsw (V switch output) CC When V switches to battery, Vccsw is high. When V switches back to V , Vccsw is OUT OUT CC low. It can be used to drive gate of external PMOS transistor for I requirements OUT exceeding 75 mA. Output type is push-pull. Doc ID 10519 Rev 9 9/42

Description STM690, STM704, STM795, STM802, STM804, STM805, STM806 1.1.9 E (chip enable input) The input to the chip enable gating circuit. Connect to ground if unused. 1.1.10 E (conditional chip enable) CON E goes low only when E is low and reset is not asserted. If E is low when reset is CON CON asserted, E will remain low for 15 µs or until E goes high, whichever occurs first. In the CON disabled mode, E is pulled up to V . CON OUT 1.1.11 V (backup battery input) BAT When V falls below V , V switches from V to V . When V rises above V + CC SO OUT CC BAT CC SO hysteresis, V reconnects to V . V may exceed V . Connect to V if no battery is OUT CC BAT CC CC used. Table 3. P in description Pin Name Function STM690 STM704 STM804 STM795 STM802 STM806 STM805 — — 6 — MR Push-button reset input — 6 — 6 WDI Watchdog input 7 7 7 — RST Active-low reset output — — — 7 RST Active-high reset output — 4 4 4 PFI Power-fail input — 5 5 5 PFO Power-fail output (push-pull) 1 1 1 1 V Supply output for external LPSRAM OUT 2 2 2 2 V Supply voltage CC 3 — — — Vccsw V switch output (push-pull) CC 4 3 3 3 V Ground SS 5 — — — E Chip enable input 6 — — — E Conditioned chip enable output CON 8 8 8 8 V Backup battery input BAT 10/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description Figure 7. Block diagram (STM690/802/804/805) VCC VOUT VBAT VSO COMPARE VRST COMPARE WDI WATTICMHEDROG gentreercator RST (RST)(1) PFI VPFI COMPARE PFO AI07897 1. For STM804/805, reset output is active-high and open drain. Figure 8. Block diagram (STM704/806) VCC VOUT VBAT VSO COMPARE VRST COMPARE trec MR generator RST PFI VPFI COMPARE PFO AI07898 Doc ID 10519 Rev 9 11/42

Description STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 9. Block diagram (STM795) VCC VOUT VBAT VCCSW VSO COMPARE trec VRST COMPARE generator RST ECONOUTPUT CONTROL E ECON PFI VPFI COMPARE PFO AI08852 12/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description Figure 10. Hardware hookup Regulator VCCSW(2) Unregulated voltage VIN VCC VCC VOUT VCC VCC STM690/704/ LPSRAM 795/802/804/ 0.1 F 805/806 E E 0.1 F WDI(1) From microprocessor E(2) ECON(2) R1 PFI(3) PFO(3) To microprocessor NMI R2 MR(4) RST To microprocessor reset Push-button VBAT AI08853 1. For STM690/802/804/805. 2. For STM795 only. 3. Not available on STM795. 4. For STM704/806. Doc ID 10519 Rev 9 13/42

Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806 2 Operation 2.1 Reset output The STM690/704/795/802/804/805/806 supervisor asserts a reset signal to the MCU whenever V goes below the reset threshold (V ), a watchdog time-out occurs, or when CC RST the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM804/805) for 0 V < V < V if V is greater than 1 V. Without a backup CC RST BAT battery, RST is guaranteed valid down to V = 1 V. CC During power-up, once V exceeds the reset threshold an internal timer keeps RST low for CC the reset time-out period, t . After this interval RST returns high. rec If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays CC low for at least the reset time-out period (t ). Any time V goes below the reset threshold rec CC the internal timer clears. The reset timer starts when V returns above the reset threshold. CC 2.2 Push-button reset input (STM704/806) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see rec Figure36) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to V when CC not used. 2.3 Watchdog input (NOT available on STM704/795/806) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the watchdog input (WDI) within t (1.6 s typ), the reset is asserted. The internal WD watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns. If WDI is tied high or low, a reset pulse is triggered every 1.8 s (t + t ). WD rec The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure37). Note: Input frequency greater than 20 ns (50 MHz) will be filtered. 14/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation 2.4 Backup battery switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through V . With a backup battery installed with voltage V , the devices OUT BAT automatically switch the SRAM to the backup supply when V falls. CC Note: When the battery is first connected without V power applied, the device does not CC immediately provide battery backup voltage on V . Only after V exceeds V will the OUT CC RST switchover operate as described below. This mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery power is consumed by the device during storage and shipment. If the backup battery is not used, connect both V and V to V . BAT OUT CC This family of supervisors does not always connect V to V when V is greater than BAT OUT BAT V . V connects to V (through a 100 Ω switch) when V is below V (2.4 V) or CC BAT OUT CC SW V (whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V lithium cell) BAT to have a higher voltage than V . CC Assuming that V > 2.0 V, switchover at V ensures that battery backup mode is entered BAT SO before V gets too close to the 2.0 V minimum required to reliably retain data in most OUT external SRAMs. When V recovers, hysteresis is used to avoid oscillation around the V CC SO point. V is connected to V through a 3 Ω PMOS power switch. OUT CC Note: The backup battery may be removed while V is valid, assuming V is adequately CC BAT decoupled (0.1 µF typ), without danger of triggering a reset. T able 4. I/O status in battery backup Pin Status V Connected to V through internal switch OUT BAT V Disconnected from V CC OUT PFI Disabled PFO Logic low E High impedance E Logic high CON WDI Watchdog timer is disabled MR Disabled RST Logic low RST Logic high V Connected to V BAT OUT Vccsw Logic high (STM795) Doc ID 10519 Rev 9 15/42

Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806 2.5 Chip enable gating (STM795 only) Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series transmission gate from E to E (see Figure11). During normal operation (reset not CON asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short E propagation delay from E to E enables the STM795 to be used with CON most µPs. If E is low when reset asserts, E remains low for typically 10 µs to permit the CON current write cycle to complete. 2.6 Chip enable input (STM795 only) The chip enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when V passes the reset CC threshold, the chip enable transmission gate disables and E immediately becomes high impedance if the voltage at E is high. If E is low when reset asserts, the chip enable transmission gate will disable 10 µs after reset asserts (see Figure12). This permits the current write cycle to complete during power-down. Any time a reset is generated, the chip enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the first half of the reset time-out period (t /2). When the chip enable transmission gate is enabled, the impedance of E rec appears as a 40 Ω resistor in series with the load at E . The propagation delay through CON the chip enable transmission gate depends on V , the source impedance of the drive CC connected to E, and the loading on E . The chip enable propagation delay is production CON tested from the 50% point on E to the 50% point on E using a 50 Ω driver and a 50 pF CON load capacitance (see Figure35). For minimum propagation delay, minimize the capacitive load at E and use a low-output impedance driver. CON 2.7 Chip enable output (STM795 only) When the chip enable transmission gate is enabled, the impedance of E is equivalent to CON a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission gate is off and an active pull-up connects E to V (see Figure11). This pull-up turns CON OUT off when the transmission gate is enabled. Figure 11. Chip enable gating VCC trec COMPARE RST VRST generator VOUT ECON OUTPUT CONTROL E ECON AI08802 16/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation Figure 12. Chip enable waveform (STM795) VCC VRST VBAT ECON ½ trec ½ trec RST trec 10 µs trec E AI08855c 2.8 Power-fail input/output (NOT available on STM795) The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from the V comparator). If PFI is less than the power-fail threshold (V ), the Power-Fail RST PFI Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure10) to either the unregulated DC input (if it is available) or the regulated output of the V regulator. The voltage divider can be set up such that the voltage at PFI falls CC below V several milliseconds before the regulated V input to the STM690/704/795/802/ PFI CC 804/805/806 or the microprocessor drops below the minimum operating voltage. During battery backup, the power-fail comparator is turned off and PFO goes (or remains) low (see Figure13). This occurs after V drops below V (2.4 V). When power returns, CC SW the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to V and PFO left unconnected. PFO may be connected to MR on SS the STM704/806 so that a low voltage on PFI will generate a reset output. 2.9 Applications information These supervisor circuits are not short-circuit protected. Shorting V to ground - OUT excluding power-up transients such as charging a decoupling capacitor - destroys the device. Decouple both V and V pins to ground by placing 0.1 µF capacitors as close to CC BAT the device as possible. Doc ID 10519 Rev 9 17/42

Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806) VCC VRST VSW (2.4 V) trec PFO PFO follows PFI PFO follows PFI RST AI08861a 18/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation 2.10 Using a SuperCap™ as a backup power source SuperCaps™ are capacitors with extremely high capacitance values (e.g., order of 0.47 F) for their size. Figure14 shows how to use a SuperCap as a backup power source. The SuperCap may be connected through a diode to the V supply. Since V can exceed CC BAT V while V is above the reset threshold, there are no special precautions when using CC CC these supervisors with a Super-Cap. Figure 14. Using a SuperCap™ 5 V VCC VOUT To external SRAM STMXXX VBAT RST To µP GND AI08805 2.11 Negative-going V transients CC The STM690/704/795/802/804/805/806 supervisors are relatively immune to negative-going V transients (glitches). Figure32 was generated using a negative pulse applied to V , CC CC starting at V + 0.3 V and ending below the reset threshold by the magnitude indicated RST (comparator overdrive). The graph indicates the maximum pulse width a negative V CC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a V transient that goes 100 mV below the reset threshold and lasts 40 µs CC or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the V pin provides additional transient immunity. CC Doc ID 10519 Rev 9 19/42

Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806 3 Typical operating characteristics Note: Typical values are at T = 25 °C. A Figure 15. V to V on-resistance vs. temperature CC OUT 5.0 VCC = 3.0 V 4.0 ) VCC = 4.5 V e ( nc VCC = 5.5 V a sist 3.0 e n-r o T U 2.0 O V o t C C V 1.0 0.0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI10498 Figure 16. V to V on-resistance vs. temperature BAT OUT 160 140 ) ce ( 120 n a sist 100 e n-r o 80 T U VO 60 VBAT = 2.0 V to AT 40 VVBBAATT == 33..03 VV B V 20 VBAT = 3.6 V 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09140b 20/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics Figure 17. Supply current vs. temperature (no load) 30 25 20 A) µ ent ( 15 urr c y VCC = 2.7 V uppl 10 VCC = 3.0 V S VCC = 3.6 V VCC = 4.5 V VCC = 5.5 V 5 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09141b Figure 18. Battery current vs. temperature 1000 100 A) ent (n VVBBAATT == 23..00 VV urr VBAT = 3.6 V c ply 10 p u s y er att B 1 0.1 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI10499 Doc ID 10519 Rev 9 21/42

Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 19. V threshold vs. temperature PFI 1.270 1.265 1.260 VCC = 2.5 V VCC = 3.0 V d (V) 1.255 VVCCCC == 33..36 VV ol h s 1.250 e hr t FI 1.245 P V 1.240 1.235 1.230 1.225 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09142b Figure 20. Reset comparator propagation delay vs. temperature 30 28 26 s) 24 µ ay ( 22 el d n 20 o ati g a 18 p o Pr 16 14 12 10 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09143b 22/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics Figure 21. Power-up t vs. temperature rec 240 235 230 VCC = 3.0 V s) m 225 VCC = 4.5 V (c tre VCC = 5.5 V 220 215 210 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09144b Figure 22. Normalized reset threshold vs. temperature 1.004 1.002 d ol h s e hr set t 1.000 e d r e z ali m or 0.998 N 0.996 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09145b Doc ID 10519 Rev 9 23/42

Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 23. Watchdog time-out period vs. temperature 1.90 1.85 s) d ( 1.80 o eri p ut o 1.75 e- m og ti VCC = 3.0 V hd 1.70 VCC = 4.5 V atc VCC = 5.5 V W 1.65 1.60 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09146b Figure 24. E to E on-resistance vs. temperature CON 60 50 ) ce ( 40 n a st si e n-r 30 o N O C 20 VCC = 3.0 V o E VCC = 4.5 V E t VCC = 5.5 V 10 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09147b 24/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics Figure 25. PFI to PFO propagation delay vs. temperature 4.0 VCC = 3.0 V s) VCC = 3.6 V (µ 3.0 y VCC = 4.5 V a el d VCC = 5.5 V n o gati 2.0 a p o pr O F P o 1.0 FI t P 0.0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09148b Figure 26. Output voltage vs. load current (V = 5 V; V = 2.8 V; T = 25 °C) CC BAT A 5.00 4.98 V) ( T U O V 4.96 4.94 0 10 20 30 40 50 IOUT (mA) AI10496 Doc ID 10519 Rev 9 25/42

Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 27. Output voltage vs. load current (V = 0 V; V = 2.8 V; T = 25 °C) CC BAT A 2.80 2.78 2.76 V) 2.74 ( T U O 2.72 V 2.70 2.68 2.66 0.0 0.2 0.4 0.6 0.8 1.0 IOUT (mA) AI10497 Figure 28. RST output voltage vs. supply voltage 5 5 VRST VCC 4 4 3 3 V) V) (T (C S C R 2 2 V V 1 1 0 0 500 ms / div AI09149b 26/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics Figure 29. RST output voltage vs. supply voltage 5 5 VRST VCC 4 4 (V) 3 3 (V) C T C RS 2 2 V V 1 1 0 0 500 ms / div AI09150b Figure 30. Power-fail comparator response time (assertion) 5V PFO 1V/div 0V 1.3V PFI 500mV/div 0V 500ns/div AI09153b Doc ID 10519 Rev 9 27/42

Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 31. Power-fail comparator response time (de-assertion) 5V PFO 1V/div 0V 1.3V PFI 500mV/div 0V 500ns/div AI09154b Figure 32. Maximum transient duration vs. reset threshold overdrive 6000 5000 s) n (µ 4000 atio Reset occurs ur above the curve d 3000 nt e si n a Tr 2000 1000 0 0.001 0.01 0.1 1 10 Reset comparator overdrive, VRST – VCC (V) AI09156b 28/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics Figure 33. E to E propagation delay vs. temperature CON 4.0 s) 3.0 n y ( a el d n o ati g 2.0 a p o pr N O C E to E 1.0 VVVCCCCCC === 345...055 VVV 0.0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09157b Doc ID 10519 Rev 9 29/42

Maximum ratings STM690, STM704, STM795, STM802, STM804, STM805, STM806 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. T able 5. Absolute maximum ratings Symbol Parameter Value Unit T Storage temperature (V off) –55 to 150 °C STG CC T (1) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltage –0.3 to V +0.3 V IO CC V /V Supply voltage –0.3 to 6.0 V CC BAT I Output current 20 mA O P Power dissipation 320 mW D 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. 30/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived tests performed under the measurement conditions summarized in Table6. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. T able 6. Operating and AC measurement conditions STM690/704/795/ Parameter Unit 802/804/805/806 V /V supply voltage 1.0 to 5.5 V CC BAT Ambient operating temperature (T ) –40 to 85 °C A Input rise and fall times ≤ 55 ns Input pulse voltages 0.2 to 0.8 V V CC Input and output timing ref. voltages 0.3 to 0.7 V V CC Figure 34. E to E propagation delay test circuit CON VCC VCC VBAT 3.6 V STM690/704/ 25 equivalent 795/802/804/ source impedance 805/806 E ECON 50 50 cable (1) 50 pF CL 50 GND AI08854 1. C includes load capacitance and scope probe capacitance. L Figure 35. AC testing input/output waveforms 0.8 VCC 0.7 VCC 0.3 VCC 0.2 V CC AI02568 Doc ID 10519 Rev 9 31/42

DC and AC parameters STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 36. MR timing waveform MR tMLRL (1) RST tMLMH trec AI07837a 1. RST for STM805. Figure 37. Watchdog timing VCC trec RST tWD WDI AI07891 Table 7. D C and AC characteristics Alter- Sym Description Test condition(1) Min Typ Max Unit native V , CC Operating voltage T = –40 to +85 °C 1.1(3) 5.5 V V (2) A BAT Excluding I (V < 5.5 V) 40 60 µA OUT CC V supply current CC Excluding I (V < 3.6 V) 35 50 µA I OUT CC CC V supply current in battery Excluding I (V = 2.3 V, CC OUT BAT 25 35 µA backup mode V = 2.0 V, MR = V ) CC CC V supply current in battery I (4) BAT Excluding I (V = 3.6 V) 0.4 1.0 µA BAT backup mode OUT BAT V – V – I = 5 mA(5) CC CC V OUT1 0.03 0.015 V – V – V V voltage (active) I = 75 mA CC CC V OUT1 OUT OUT1 0.3 0.15 V – V – I = 250 µA, V > 2.5 V(5) CC CC V OUT1 CC 0.0015 0.0006 V – V – I = 250 µA, V = 2.3 V BAT BAT V OUT2 BAT 0.1 0.034 V V voltage (battery backup) OUT2 OUT V – I = 1 mA, V = 2.3 V BAT V OUT2 BAT 0.14 V to V on-resistance 3 4 Ω CC OUT 32/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters Table 7. DC and AC characteristics (continued) Alter- Sym Description Test condition(1) Min Typ Max Unit native V to V on-resistance 100 Ω BAT OUT STM704/806 only; Input leakage current (MR) 20 75 350 µA MR = 0 V, V = 3 V CC ILI Input leakage current (PFI) 0 V < V < V –20 2 +25 nA IN CC Input leakage current (WDI) 0 V < V < V –1 +1 µA IN CC STM804/805/795; ILO Output leakage current 0 V < V < V (6) –1 +1 µA IN CC V Input high voltage (MR, WDI) V (max) < V < 5.5 V 0.7 V V IH RST CC CC V Input low voltage (MR, WDI) V (max) < V < 5.5 V 0.3 V V IL RST CC CC Output low voltage (PFO, V = V (max), CC RST 0.3 V RST, RST, Vccsw) I = 3.2 mA SINK V OL V = V (max), Output low voltage (E ) CC RST 0.2 V V CON I = 1.6 mA, E = 0 V CC OUT I = 40 µA, OL V = 1.0 V, V = V , 0.3 V CC BAT CC VOL Output low voltage (RST) TA = 0 °C to 85 °C I = 200 µA, OL 0.3 V V = 1.2 V, V = V CC BAT CC Output high voltage (RST, I = 1 mA, SOURCE 2.4 V RST)(7) V = V (max) CC RST V = V (max), VOH Output high voltage (ECON) I C =C 1.6 RmSAT, E = V 0.8 VCC V OUT CC I = 75 µA, Output high voltage (PFO) SOURCE 0.8 V V V = V (max) CC CC RST V battery backup (Vccsw, I = 100 µA, OH SOURCE 0.8 V V RST) V = 0 V, V = 2.8 V BAT CC BAT V OHB I = 75 µA, V battery backup (E ) SOURCE 0.8 V V OH CON V = 0 V, V = 2.8 V BAT CC BAT Power-fail comparator (NOT available on STM795) STM802/ 1.212 1.237 1.262 V 804/806 PFI falling V PFI input threshold PFI (V < 3.6 V) CC STM690/ 1.187 1.237 1.287 V 704/805 PFI hysteresis PFI rising (V < 3.6 V) 10 20 mV CC t PFI to PFO propagation delay 2 µs PFD Doc ID 10519 Rev 9 33/42

DC and AC parameters STM690, STM704, STM795, STM802, STM804, STM805, STM806 Table 7. DC and AC characteristics (continued) Alter- Sym Description Test condition(1) Min Typ Max Unit native PFO output short to GND I V = 3.6 V, PFO = 0 V 0.1 0.75 2.0 mA SC current CC Battery switchover V > V V V BAT SW SW Power-down V < V V V Battery backup switchover BAT SW BAT voltage(8)(9) V > V V V BAT SW SW V Power-up SO V < V V V BAT SW BAT V 2.4 V SW Hysteresis 40 mV Reset thresholds V falling 3.00 3.075 3.15 V STM690T/ CC 704T/795T/ 805T V rising 3.00 3.085 3.17 V CC V falling 3.00 3.075 3.12 V STM802T/ CC 804T/806T V rising 3.00 3.085 3.14 V CC V falling 2.85 2.925 3.00 V STM690S/ CC 704S/795S/ 805S V rising 2.85 2.935 3.02 V CC V (10) Reset threshold RST V falling 2.88 2.925 3.00 V STM802S/ CC 804S/806S V rising 2.88 2.935 3.02 V CC V falling 2.55 2.625 2.70 V STM690R/ CC 704R/795R/ 805R V rising 2.55 2.635 2.72 V CC V falling 2.59 2.625 2.70 V STM802R/ CC 804R/806R V rising 2.59 2.635 2.72 V CC t RST pulse width V < 3.6 V 140 200 280 ms rec CC Push-button reset input (STM704/806) t t MR pulse width 100 20 ns MLMH MR t t MR to RST output delay 60 500 ns MLRL MRD Watchdog timer (NOT available on STM704/795/806) t Watchdog timeout period V (max) < V < 3.6 V 1.12 1.60 2.24 s WD RST CC WDI pulse width V (max) < V < 3.6 V 100 20 ns RST CC Chip enable gating (STM795 only) E to E resistance V = V (max) 46 Ω CON CC RST 34/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters Table 7. DC and AC characteristics (continued) Alter- Sym Description Test condition(1) Min Typ Max Unit native E to E propagation delay V = V (max) 2 7 ns CON CC RST Reset to E high delay 10 µs CON V = 3.6 V, disable mode, I E short circuit current CC 0.1 0.75 2.0 mA SC CON E = 0 V CON 1. Valid for ambient operating temperature: T = –40 to 85 °C; V = V (max) to 5.5 V; and V = 2.8 V (except where A CC RST BAT noted). 2. V supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, CC state of RST and RST tested at V = 3.6 V, and V = 5.5 V. The state of RST or RST and PFO is tested at V = V BAT CC CC CC (min). Either V or V can go to 0 V if the other is greater than 2.0 V. CC BAT 3. V (min) = 1.0 V for T = 0 °C to +85 °C. CC A 4. Tested at V = 3.6 V, V = 3.5 V and 0 V. BAT CC 5. Guaranteed by design. 6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted (output high impedance). 7. Not valid for STM795/804/805 (open drain). 8. When V > V > V , V remains connected to V until V drops below V . BAT CC SW OUT CC CC SW 9. When V > V > V , V remains connected to V until V drops below the battery voltage (V ) - 75 mV. SW CC BAT OUT CC CC BAT 10. The reset threshold tolerance is wider for V rising than for V falling due to the 10 mV (typ) hysteresis, which prevents CC CC internal oscillation. Doc ID 10519 Rev 9 35/42

Package mechanical data STM690, STM704, STM795, STM802, STM804, STM805, STM806 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 36/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Package mechanical data Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical drawing A2 A C B ddd e D 8 E H 1 A1 L SO-A T able 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data mm inches Symb Typ Min Max Typ Min Max A — 1.35 1.75 — 0.053 0.069 A1 — 0.10 0.25 — 0.004 0.010 B — 0.33 0.51 — 0.013 0.020 C — 0.19 0.25 — 0.007 0.010 D — 4.80 5.00 — 0.189 0.197 ddd — — 0.10 — — 0.004 E — 3.80 4.00 — 0.150 0.157 e 1.27 — — 0.050 — — H — 5.80 6.20 — 0.228 0.244 h — 0.25 0.50 — 0.010 0.020 L — 0.40 0.90 — 0.016 0.035 α — 0° 8° — 0° 8° N 8 8 Doc ID 10519 Rev 9 37/42

Package mechanical data STM690, STM704, STM795, STM802, STM804, STM805, STM806 Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline D 8 5 c E1 E 1 4 A1 L A A2 CP L1 b e TSSOP8BM T able 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data mm inches Symb Typ Min Max Typ Min Max A — — 1.10 — — 0.043 A1 — 0.05 0.15 — 0.002 0.006 A2 0.85 0.75 0.95 0.034 0.030 0.037 b — 0.25 0.40 — 0.010 0.016 c — 0.13 0.23 — 0.005 0.009 CP — — 0.10 — — 0.004 D 3.00 2.90 3.10 0.118 0.114 0.122 e 0.65 — — 0.026 — — E 4.90 4.65 5.15 0.193 0.183 0.203 E1 3.00 2.90 3.10 0.118 0.114 0.122 L 0.55 0.40 0.70 0.022 0.016 0.030 L1 0.95 — — 0.037 — — α — 0° 6° — 0° 6° N 8 8 38/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Part numbering 7 Part numbering T able 10. Ordering information scheme Example: STM690 T M 6 E Device type STM690/704/795/802/804/805/806 Reset threshold voltage T = STM690/704/795/805 = V = 3.00 V to 3.15 V RST STM802/804/806 = V = 3.00 V to 3.12 V RST S = STM690/704/795/805 = V = 2.85 V to 3.00 V RST STM802/804/806 = V = 2.88 V to 3.00 V RST R = STM690/704/795/805 = V = 2.55 V to 2.70 V RST STM802/804/806 = V = 2.59 V to 2.70 V RST Package M = SO8 DS(1)= TSSOP8 Temperature range 6 = –40 to 85 °C Shipping method E = ECOPACK® package, tubes F = ECOPACK® package, tape and reel 1. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 10519 Rev 9 39/42

Part numbering STM690, STM704, STM795, STM802, STM804, STM805, STM806 T able 11. Marking description Part number Reset threshold Package Topside marking SO8 STM690T 3.075 690T TSSOP8 SO8 STM690S 2.925 690S TSSOP8 SO8 STM690R 2.625 690R TSSOP8 SO8 STM704T 3.075 704T TSSOP8 SO8 STM704S 2.925 704S TSSOP8 SO8 STM704R 2.625 704R TSSOP8 SO8 STM795T 3.075 795T TSSOP8 SO8 STM795S 2.925 795S TSSOP8 SO8 STM795R 2.625 795R TSSOP8 SO8 STM802T 3.075 802T TSSOP8 SO8 STM802S 2.925 802S TSSOP8 SO8 STM802R 2.625 802R TSSOP8 SO8 STM804T 3.075 804T TSSOP8 SO8 STM804S 2.925 804S TSSOP8 SO8 STM804R 2.625 804R TSSOP8 SO8 STM805T 3.075 805T TSSOP8 SO8 STM805S 2.925 805S TSSOP8 SO8 STM805R 2.625 805R TSSOP8 SO8 STM806T 3.075 806T TSSOP8 SO8 STM806S 2.925 806S TSSOP8 SO8 STM806R 2.625 806R TSSOP8 40/42 Doc ID 10519 Rev 9

STM690, STM704, STM795, STM802, STM804, STM805, STM806 Revision history 8 Revision history T able 12. Document revision history Date Revision Changes 31-Oct-2003 1 Initial release. Reformatted; update characteristics (Figure1, 3, 4, 11, 13, 14, 37; 22-Dec-2003 2 Table1, 3, 4, 7, 9, 11). Added Typical operating characteristics (Figure17, 18, 20 to 26, 29, 16-Jan-2004 2.1 30 to 34). 07-Apr-2004 2.2 Updated characteristics (Figure13, 29, 30, Table1, 3, 7) 25-May-2004 3 Update characteristics (Table3, 7) Update package availability, pin description; promote document 02-Jul-2004 4 (Figure1, 14; Table3, 10) Clarify root part numbers, pin descriptions, update characteristics 29-Sep-2004 5 (Figure2, to, 11, 13, 14, 35; Table1, 3, 6, 7, 10) 25-Feb-2005 6 Update characteristics (Figure11, 16, to 35; Table7) 05-Apr-2006 7 Update characteristics (Figure13) Updated Section1.1.6, Section1.1.8, Figure10, 11, 19, Table3, 5, 7; 20-Nov-2009 8 added text to Section6. 18-Aug-2010 9 Updated Features, Section2.4: Backup battery switchover. Doc ID 10519 Rev 9 41/42

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