STM6519 Single-pin, push button Smart Reset™ Datasheet - production data Applications • Mobile phones, smartphones, PDAs • e-books • MP3 players • Games UDFN6 1.00 mm x 1.45 mm • Portable navigation devices • Any application that requires delayed reset push-button response for improved system stability Features • Operating voltage range 2 V to 5.5 V • Low supply current 1 μA • Integrated test mode • Single Smart Reset™ push-button input with fixed extended reset setup delay (t ) from SRC 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor • Push-button controlled reset pulse duration • Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed • Option 2: defined output reset pulse duration (t ), factory-programmed REC • Single reset output • Active-low or active-high • Push-pull or open drain with optional pull-up resistor • Fixed Smart Reset input logic voltage levels • Operating temperature: -40 °C to 85 °C • UDFN6 package 1.00 mm x 1.45 mm • ECOPACK®2 (RoHS compliant, Halogen-Free) June 2016 DocID022111 Rev 7 1/23 This is information on a product in full production. www.st.com

Contents STM6519 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CC 3.2 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SS 3.4 Smart Reset input (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 RST output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 8 4 Typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 UDFN6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.2 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 DocID022111 Rev 7

STM6519 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. UDFN6 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID022111 Rev 7 3/23 3

List of figures STM6519 List of figures Figure 1. STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. UDFN6 pin connections (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. STM6519 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Typical application diagram - input, output and STM6519 device in one voltage domain . . 9 Figure 5. Typical application diagram - STM6519 device in a different voltage domain than input and output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Typical application diagram in different voltage domains - SR input in V domain like BAT V totally disables the test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CC Figure 7. RST output without t option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REC Figure 8. RST output with t option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REC Figure 9. Supply current (I ) vs. temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CC A Figure 10. Smart Reset delay (t ) vs. temperature (T ), t = 4.0 s (typ.) . . . . . . . . . . . . . . . . . . 12 SRC A SRC Figure 11. Test mode entry voltage (V ) vs. temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TEST A Figure 12. Initial test mode time (t ) vs. temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SRC-INI A Figure 13. UDFN6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. UDFN6 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15. Carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. Package marking (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4/23 DocID022111 Rev 7

STM6519 Description 1 Description The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (t ), which ensures a safe reset and eliminates SRC the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push- button is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time t causes a hard reset of the SRC processor through the reset output. The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (t ). The reset output (RST) is asserted after the Smart Reset input is held active for the SRC selected t delay time. The RST output remains asserted either until the SR input goes to SRC inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for t (i.e. factory-programmed). The device fully operates REC over a broad V range from 2.0 V to 5.5 V. CC 1.1 Test mode After pulling SR up to V (V + 1.4 V) or above, the counter starts to count the initial TEST CC shortened t (42 ms, typ.). After t expires, the RST output either goes down for SRC-INI SRC-INI t (if t option is used) or stays low as long as overvoltage on SR is detected (if t REC REC REC option is not used). This is feedback, and the user only knows that the device is locked in test mode. Each time the SR input is connected to ground in test mode, a shortened t (t /128) is used instead of regular t (0.5 s - 10 s). In this way the device SRC-SHORT SRC SRC can be quickly tested without repeating test mode triggering. Return to normal mode is possible by performing a new startup of the device (i.e. V goes to 0 V and back to its CC original state). The advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full V range. CC DocID022111 Rev 7 5/23 22

Description STM6519 1.2 Logic diagram Figure 1. STM6519 logic diagram (cid:57)(cid:38)(cid:38) (cid:54)(cid:53) (cid:54)(cid:55)(cid:48)(cid:25)(cid:24)(cid:20)(cid:28) (cid:53)(cid:54)(cid:55) (cid:42)(cid:49)(cid:39) (cid:36)(cid:48)(cid:19)(cid:26)(cid:23)(cid:25)(cid:21) 1.3 Pin connections Figure 2. UDFN6 pin connections (top view) (cid:53)(cid:54)(cid:55) (cid:20) (cid:25) (cid:49)(cid:38)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48) (cid:57)(cid:54)(cid:54) (cid:21) (cid:24) (cid:49)(cid:38)(cid:11)(cid:20)(cid:12) (cid:25)(cid:24)(cid:20)(cid:28) (cid:54)(cid:53) (cid:22) (cid:23) (cid:57)(cid:38)(cid:38) (cid:56)(cid:39)(cid:41)(cid:49)(cid:25) (cid:36)(cid:48)(cid:19)(cid:26)(cid:23)(cid:25)(cid:22)(cid:57)(cid:20) 1. Not connected (not bonded); should be connected to V . SS 6/23 DocID022111 Rev 7

STM6519 Device overview 2 Device overview Table 1. Signal names Pin number Name Type Description 1 RST Output Reset output, active-low, open drain. 2 V Supply ground Ground SS 3 SR Input Smart Reset input, active-low. Positive supply voltage for the device. A 0.1 µF decoupling 4 V Supply voltage ceramic capacitor is recommended to be connected between V CC CC and V pins. SS 5 NC - Not connected (not bonded); should be connected to V . SS 6 NC - Not connected (not bonded); should be connected to V . SS Figure 3. STM6519 block diagram (cid:87) (cid:87)(cid:53)(cid:40)(cid:38) (cid:54)(cid:53) (cid:54)(cid:53)(cid:38) (cid:74)(cid:72)(cid:81)(cid:72)(cid:85)(cid:68)(cid:87)(cid:82)(cid:85) (cid:53)(cid:54)(cid:55) (cid:74)(cid:72)(cid:81)(cid:72)(cid:85)(cid:68)(cid:87)(cid:82)(cid:85) (cid:11)(cid:82)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:12) (cid:50)(cid:89)(cid:72)(cid:85)(cid:89)(cid:82)(cid:79)(cid:87)(cid:68)(cid:74)(cid:72)(cid:3)(cid:71)(cid:72)(cid:87)(cid:72)(cid:70)(cid:87)(cid:3) (cid:14)(cid:3)(cid:87)(cid:72)(cid:86)(cid:87)(cid:3)(cid:80)(cid:82)(cid:71)(cid:72)(cid:3)(cid:87)(cid:85)(cid:76)(cid:74)(cid:74)(cid:72)(cid:85) (cid:36)(cid:48)(cid:19)(cid:26)(cid:23)(cid:25)(cid:24)(cid:57)(cid:20) DocID022111 Rev 7 7/23 22

Pin descriptions STM6519 3 Pin descriptions 3.1 Power supply (V ) CC This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the V and V pins, as close to the CC SS STM6519 device as possible. 3.2 Power-up sequence In normal mode, if different input side (SR) and V voltage domains are used, power-on CC sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the SR input before the V power-up. CC However V and V(SR) rising at the same time is OK (e.g. if both are in the same voltage CC domain), the device will then safely start into normal operating mode, with RST output inactive (in High-Z mode for open-drain option). 3.3 Ground (V ) SS This is the ground pin for the device. 3.4 Smart Reset input (SR) Push-button Smart Reset input, active-low with optional pull-up resistor. SR input needs to be asserted for at least t to assert the reset output (RST). SRC By connecting a voltage higher than V + 1.4 V to the SR input the device enters test mode CC (see Section 1: Description on page 5 for more information). 3.5 Reset output (RST) RST is active-low or active-high, open drain or push-pull reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: • Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert) • Fixed, factory-programmed output reset pulse duration for t independent on Smart REC Reset input state. 3.6 RST output undervoltage behavior (for open-drain option) High-Z on RST output below the specified operating voltage range is guaranteed at V CC power-on or in case that valid V dropped while the device was idle, i.e. while both output CC and input were inactive. 8/23 DocID022111 Rev 7

STM6519 Typical application diagrams 4 Typical application diagrams Figure 4. Typical application diagram - input, output and STM6519 device in one voltage domain Figure 5. Typical application diagram - STM6519 device in a different voltage domain than input and output 1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage domains. To prevent entering test mode by creating a condition V(SR) > V + 1.1 V typ., V should be CC CC powered up before or together with voltage on the SR input. DocID022111 Rev 7 9/23 22

Typical application diagrams STM6519 Figure 6. Typical application diagram in different voltage domains - SR input in V BAT domain like V totally disables the test mode CC 10/23 DocID022111 Rev 7

STM6519 Timing diagrams 5 Timing diagrams Figure 7. RST output without t option REC 1. V should be powered up before or together with voltage on the SR input to prevent entering test mode by creating CC a condition V(SR) > V +1.1 V typ. CC Figure 8. RST output with t option REC 1. V should be powered up before or together with voltage on the SR input to prevent entering test mode by creating CC a condition V(SR) > V +1.1 V typ. CC DocID022111 Rev 7 11/23 22

Typical operating characteristics STM6519 6 Typical operating characteristics Figure 9. Supply current (I ) vs. temperature (T ) CC A (cid:19)(cid:17)(cid:25) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:17)(cid:24)(cid:3)(cid:57) (cid:19)(cid:17)(cid:24) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:21)(cid:17)(cid:19)(cid:3)(cid:57) (cid:19)(cid:17)(cid:23) (cid:19)(cid:17)(cid:22) (cid:19)(cid:17)(cid:21) (cid:19)(cid:17)(cid:20) (cid:19) (cid:16)(cid:23)(cid:19) (cid:16)(cid:21)(cid:19) (cid:19) (cid:21)(cid:19) (cid:23)(cid:19) (cid:25)(cid:19) (cid:27)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:15)(cid:3)(cid:55)(cid:36)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36)(cid:48)(cid:19)(cid:26)(cid:24)(cid:22)(cid:20) Figure 10. Smart Reset delay (t ) vs. temperature (T ), t = 4.0 s (typ.) SRC A SRC (cid:23)(cid:17)(cid:27) (cid:23)(cid:17)(cid:25) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:17)(cid:24)(cid:3)(cid:57) (cid:86)(cid:12) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:11) (cid:3)(cid:38) (cid:23)(cid:17)(cid:23) (cid:57)(cid:38)(cid:38)(cid:32)(cid:3)(cid:21)(cid:17)(cid:19)(cid:3)(cid:57) (cid:53) (cid:54) (cid:92)(cid:15)(cid:3)(cid:87) (cid:23)(cid:17)(cid:21) (cid:68) (cid:72)(cid:79) (cid:23)(cid:17)(cid:19) (cid:71) (cid:3) (cid:72)(cid:87) (cid:86) (cid:72) (cid:22)(cid:17)(cid:27) (cid:53) (cid:3) (cid:85)(cid:87) (cid:68) (cid:80) (cid:22)(cid:17)(cid:25) (cid:54) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:21) (cid:16)(cid:23)(cid:19) (cid:16)(cid:21)(cid:19) (cid:19) (cid:21)(cid:19) (cid:23)(cid:19) (cid:25)(cid:19) (cid:27)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:15)(cid:3)(cid:55)(cid:36)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36)(cid:48)(cid:19)(cid:26)(cid:24)(cid:22)(cid:21) 12/23 DocID022111 Rev 7

STM6519 Typical operating characteristics Figure 11. Test mode entry voltage (V ) vs. temperature (T ) TEST A (cid:20)(cid:17)(cid:22)(cid:19) (cid:57)(cid:12) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:17)(cid:19)(cid:3)(cid:57) (cid:11) (cid:3)(cid:55) (cid:20)(cid:17)(cid:21)(cid:24) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:54) (cid:40) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:21)(cid:17)(cid:19)(cid:3)(cid:57) (cid:55) (cid:57) (cid:72)(cid:15)(cid:3) (cid:20)(cid:17)(cid:21)(cid:19) (cid:74) (cid:68) (cid:82)(cid:79)(cid:87) (cid:89) (cid:20)(cid:17)(cid:20)(cid:24) (cid:92)(cid:3) (cid:85) (cid:87) (cid:81) (cid:72) (cid:72)(cid:3) (cid:20)(cid:17)(cid:20)(cid:19) (cid:71) (cid:82) (cid:80) (cid:3) (cid:86)(cid:87) (cid:20)(cid:17)(cid:19)(cid:24) (cid:72) (cid:55) (cid:20)(cid:17)(cid:19)(cid:19) (cid:16)(cid:23)(cid:19) (cid:16)(cid:21)(cid:19) (cid:19) (cid:21)(cid:19) (cid:23)(cid:19) (cid:25)(cid:19) (cid:27)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:15)(cid:3)(cid:55) (cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36) (cid:36)(cid:48)(cid:19)(cid:26)(cid:24)(cid:22)(cid:22) Figure 12. Initial test mode time (t ) vs. temperature (T ) SRC-INI A (cid:24)(cid:24) (cid:86)(cid:12) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:17)(cid:19)(cid:3)(cid:57) (cid:80) (cid:3)(cid:11)(cid:49)(cid:44) (cid:24)(cid:19) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:66)(cid:44) (cid:57)(cid:38)(cid:38)(cid:3)(cid:32)(cid:3)(cid:21)(cid:17)(cid:19)(cid:3)(cid:57) (cid:38) (cid:53) (cid:54) (cid:23)(cid:24) (cid:72)(cid:15)(cid:3)(cid:87) (cid:80) (cid:72)(cid:3)(cid:87)(cid:76) (cid:71) (cid:23)(cid:19) (cid:82) (cid:80) (cid:3) (cid:86)(cid:87) (cid:72) (cid:68)(cid:79)(cid:3)(cid:87) (cid:22)(cid:24) (cid:81)(cid:76)(cid:87)(cid:76) (cid:44) (cid:22)(cid:19) (cid:16)(cid:23)(cid:19) (cid:16)(cid:21)(cid:19) (cid:19) (cid:21)(cid:19) (cid:23)(cid:19) (cid:25)(cid:19) (cid:27)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:15)(cid:3)(cid:55)(cid:36)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36)(cid:48)(cid:19)(cid:26)(cid:24)(cid:22)(cid:23) DocID022111 Rev 7 13/23 22

Maximum ratings STM6519 7 Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 3: Operating and measurement conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE program and other relevant quality documents. Table 2. Absolute maximum ratings Symbol Parameter Value Unit T Storage temperature (V off) -55 to 150 °C STG CC T (1) Lead solder temperature for 10 seconds 260 °C SLD V Input or output voltage -0.3 to 5.5 V IO V Supply voltage -0.3 to 7 V CC ESD Electrostatic discharge protection, human body model (JESD22- V 2 kV HBM A114-B level 2) V Electrostatic discharge protection, charged device model, all pins 1 kV RCDM Electrostatic discharge protection, machine model, all pins V 200 V MM (JESD22-A115-A level A) Latch-up (V pin, SR reset input pin) EIA/JESD78 CC 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. 14/23 DocID022111 Rev 7

STM6519 DC and AC parameters 8 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in Table 4: DC and AC characteristics are derived from tests performed under the measurement conditions summarized in Table 3: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3. Operating and measurement conditions Symbol Parameter Value Unit V Supply voltage 2.0 to 5.5 V CC T Ambient operating temperature -40 to 85 °C A t , t Input rise and fall times ≤ 5 ns R F Input pulse voltages 0.2 to 0.8 V V CC Input and output timing reference voltages 0.3 to 0.7 V V CC DocID022111 Rev 7 15/23 22

DC and AC parameters STM6519 Table 4. DC and AC characteristics Symbol Parameter Test conditions(1) Min. Typ.(2) Max. Unit V Supply voltage 2.0 5.5 V CC SR = V , t and t I Supply current CC REC SRC 0.4 1.0 µA CC counter is not running V ≥ 4.5 V, sinking 3.2 mA 0.3 V CC V Reset output voltage low V ≥ 3.3 V, sinking 2.5 mA 0.3 V OL CC V ≥ 2.0 V, sinking 1 mA 0.3 V CC 0.85 1.28 1.71 ms Reset timeout delay, 66 100 134 ms t (device option) REC factory-programmed 140 210 280 ms 240 360 480 ms Internal output pull-up R (device option) 65 kΩ PUO resistor on RST V = 5.5 V, open drain RST I Output leakage current device option without output -0.1 0.1 µA LO pull-up resistor Smart Reset T = -40 to +85 °C 0.8 x t 1.2 x t t Smart Reset delay A SRC t (3) SRC s SRC SRC T = 25 °C 0.9 x t 1.1 x t A SRC SRC V SR input voltage low V -0.3 0.3 V IL SS V SR input voltage high 0.85 5.5 V IH Internal input pull-up R (device option) 65 kΩ PUI resistor on SR device option without input I SR input leakage current -0.1 0.1 µA LEAK pull-up resistor Input glitch immunity t s SRC Test mode V Test mode entry voltage V +0.9 V + 1.1 V + 1.4 V TEST CC CC CC t Initial test mode time 28 42 56 ms SRC-INI Shortened Smart Reset t t / 128 ms SRC-SHORT delay SRC 1. Valid for ambient operating temperature T = -40 to 85 °C, V = 2.0 to 5.5 V. A CC 2. Typical values are at 25 °C and V = 3.3 V unless otherwise noted. CC 3. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps. 16/23 DocID022111 Rev 7

STM6519 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 UDFN6 package information Figure 13. UDFN6 package outline (cid:39) (cid:49) (cid:40) (cid:20) (cid:21) (cid:36) (cid:36)(cid:20) (cid:20) (cid:21) (cid:47) (cid:78) (cid:72) (cid:69) (cid:56)(cid:39)(cid:41)(cid:49)(cid:16)(cid:25)(cid:47) DocID022111 Rev 7 17/23 22

Package information STM6519 Table 5. UDFN6 mechanical data Dimensions Symbol (mm) (inches) Note(1) Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0.000 0.0008 0.0020 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 D 1.40 1.45 1.50 0.0551 0.0571 0.0591 E 0.95 1.00 1.05 0.0374 0.0394 0.0413 e 0.45 0.50 0.55 0.0177 0.0197 0.0217 k 0.20 0.0079 L 0.30 0.35 0.40 0.0118 0.0138 0.0157 1. Package outline exclusive of any mold flashes dimensions and metal burrs. Figure 14. UDFN6 recommended footprint (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19)(cid:17)(cid:25)(cid:24) (cid:19)(cid:17)(cid:22)(cid:19) (cid:20)(cid:17)(cid:25)(cid:19) (cid:36)(cid:48)(cid:19)(cid:26)(cid:23)(cid:28)(cid:26) 18/23 DocID022111 Rev 7

STM6519 Package information 9.2 Tape and reel information Figure 15. Carrier tape (cid:36)(cid:48)(cid:19)(cid:26)(cid:23)(cid:28)(cid:20) 1. 10-sprocket hole pitch cumulative tolerance ±0.20. Figure 16. Pin 1 orientation (cid:56)(cid:86)(cid:72)(cid:85)(cid:3)(cid:71)(cid:76)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:82)(cid:73)(cid:3)(cid:73)(cid:72)(cid:72)(cid:71) (cid:36)(cid:48)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:57)(cid:20) DocID022111 Rev 7 19/23 22

Part numbering STM6519 10 Part numbering Table 6. Ordering information scheme Example: STM6519 A H A R UB 6 F Device type STM6519 Reset (V monitoring threshold) voltage V CC RST A = no V monitoring feature CC Smart Reset setup delay (t )(1) SRC C = factory programmable t = 1.5 s (typ.) SRC H = factory programmable t = 4.0 s (typ.) SRC L = factory programmable t = 6.0 s (typ.) SRC P = factory programmable t = 7.5 s (typ.) SRC U = factory programmable t = 10.0 s (typ.) SRC Inputs, outputs type(2) A = active-low SR input with no pull-up, active-low open drain RST output with no pull-up B = active-low SR input with pull-up, active-low open drain RST output with no pull-up Reset timeout period (t ) REC A = factory programmable t = 210 ms (typ.) REC B = factory programmable t = 360 ms (typ.) REC E = factory programmable t = 1.28 ms (typ.) REC F = factory programmable t = 100 ms (typ.) REC R = push-button controlled (no defined t ) REC Package UB = UDFN-6L Temperature range 6 = -40 °C to 85 °C Shipping method F = tape and reel 1. Smart Reset delay (t ) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities may apply. Contact SRC local sales office for availability. 2. Push-pull reset output type also available (active-low or active-high). SR input and open drain reset output available with optional pull-up resistor. Minimum order quantities may apply. Contact local sales office for availability. 20/23 DocID022111 Rev 7

STM6519 Package marking information 11 Package marking information Table 7. Package marking Smart Reset Output t Part number t (s) REC Package Topmark SRC inputs(1) type(2) option(3) STM6519ACARUB6F 1.5 AL OD, AL No t UDFN6 CA REC STM6519AHARUB6F 4.0 AL OD, AL No t UDFN6 HA REC STM6519ALARUB6F 6.0 AL OD, AL No t UDFN6 LA REC STM6519APAAUB6F 7.5 AL OD, AL 210 ms UDFN6 PB STM6519APARUB6F 7.5 AL OD, AL No t UDFN6 PA REC STM6519APBBUB6F 7.5 AL + pull-up OD, AL 360 ms UDFN6 PC STM6519AUARUB6F 10.0 AL OD, AL No t UDFN6 UA REC 1. AL = active-low. 2. OD = open drain, AL = active-low. 3. No t = push-button controlled reset pulse width, any other value represents typical value of t . REC REC Figure 17. Package marking (top view) (cid:36) (cid:37) (cid:36)(cid:3)(cid:32)(cid:3)(cid:71)(cid:82)(cid:87)(cid:3)(cid:11)(cid:83)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:85)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:12) (cid:37)(cid:3)(cid:32)(cid:3)(cid:80)(cid:68)(cid:85)(cid:78)(cid:76)(cid:81)(cid:74)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68)(cid:3)(cid:11)(cid:87)(cid:82)(cid:83)(cid:80)(cid:68)(cid:85)(cid:78)(cid:12) (cid:42)(cid:36)(cid:51)(cid:48)(cid:54)(cid:48)(cid:39)(cid:19)(cid:19)(cid:19)(cid:22)(cid:26) DocID022111 Rev 7 21/23 22

Revision history STM6519 12 Revision history Table 8. Document revision history Date Revision Changes 12-Aug-2011 1 Initial release. 22-Sep-2011 2 Updated Figure 5, Table 4, Table 7 and Table 8. 07-Oct-2011 3 Removed label “Preliminary data”. 27-Oct-2011 4 Updated Figure 3 and Table 1. 13-Jun-2012 5 Updated Features, Table 4, title of Section 9. Moved Figure 4 below Table 1. Added Section 3.2, Section 3.6, Figure 6 and Figure 7. 17-Jan-2013 6 Updated title of Figure 5. Updated Figure 8 and Figure 9 (added notes and minor modifications). Updated datasheet title 29-Jun-2016 7 Removed UDFN4 package from datasheet 22/23 DocID022111 Rev 7

STM6519 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID022111 Rev 7 23/23 23

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: STM6519ACARUB6F STM6519AHARUB6F STM6519ALARUB6F STM6519APARUB6F STM6519AUARUB6F STM6519APAAUB6F STM6519APBBUB6F