STM6513 Dual push-button Smart TM Reset with dual reset outputs and user-selectable setup delay Features ■ Dual Smart Reset push-button inputs with user-selectable extended reset setup delay (by three-state input logic): t = 2, 6, 10 s (min.) SRC ■ Capacitor-adjustable reset pulse duration (t ) REC1 ■ Power-on reset ■ Dual reset output (RST1 is active-high, push- pull type, RST2 is active-low, open-drain) TDFN8 (DG) ■ Factory-programmable thresholds to monitor 2 mm x 2 mm V in the range of 1.575 to 4.625 V typ. CC ■ Operating voltage 1.0 V (active-low output valid) to 5.5 V Applications ■ Low supply current 3 µA ■ Operating temperature: industrial grade –40 °C ■ Mobile phones, smartphones to +85 °C ■ e-books ■ TDFN8 package: 2 mm x 2 mm x 0.75 mm ■ MP3 players ■ RoHS compliant ■ Games ■ Portable navigation devices ■ Any application that requires delayed reset push-button(s) response for improved system stability. June 2010 Doc ID 16490 Rev 2 1/29 www.st.com 1

Contents STM6513 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CC 3.2 Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SS 3.3 Smart Reset inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 User-programmable Smart Reset delay (TSR pin) . . . . . . . . . . . . . . . . . . 8 3.5 Reset outputs (RST1, RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 Adjustable output reset timeout period input pin (TREC ) . . . . . . . . . . . 8 ADJ 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 Doc ID 16490 Rev 2

STM6513 List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. t programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 REC1 Table 3. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Possible V voltage thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CC Table 7. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 21 Table 8. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22 Table 9. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Reel dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 16490 Rev 2 3/29

List of figures STM6513 List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Smart Reset delay t vs. temperature and supply voltage V , SRC CC TSR = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SS Figure 7. Output reset timeout period t vs. temperature and supply voltage V REC2 CC (t option E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REC Figure 8. Supply current I vs. temperature and supply voltage V . . . . . . . . . . . . . . . . . . . . . . . 13 CC CC Figure 9. Reset voltage V (falling) vs. temperature RST (threshold option S, 2.925 V typ.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply voltage V . . . . . . 14 CC Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply voltage V . . . . . 15 CC Figure 12. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16. Reel dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 18. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 19. Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4/29 Doc ID 16490 Rev 2

STM6513 Description 1 Description The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken low simultaneously provide three user-selectable delayed Smart Reset setup time (t ) SRC options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when connected to ground, t = 2 s; when left open, t = 6 s; when connected to V , SRC SRC CC t = 10 s (all the times are minimum). There are two reset outputs, both going active SRC simultaneously after both the Smart Reset inputs were held active for the selected t SRC delay time. The first reset output, RST1, is active-high, push-pull; the second reset output, RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the output reset pulses is independently programmable: t is user-programmable (by REC1 external capacitor C ), t is factory-programmed to 210 ms (typ.), with the option of tREC REC2 360 ms typ. Additionally, the V is monitored and if it drops below the selected V CC RST threshold, both the reset outputs go active and remain so while V is below the V CC RST threshold, plus the defined duration of the reset pulse t on each output. REC Smart Reset devices The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset input delay (t ). Once the valid Smart Reset input levels and setup SRC delay are met, the device generates an output reset pulse with user-programmable timeout period (t ). REC The Smart Reset inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (t ) causes hard reset of SRC the processor through the reset outputs. The Smart Reset feature helps significantly increase system stability. The STM65xx family of Smart Reset devices consists of low current microprocessor reset circuits targeted at applications such as MP3 players, navigation, smartphones or mobile phones; generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart Reset inputs (SR). The delayed Smart Reset setup time (t ) options of 2 s, 6 s and 10 s SRC (all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than t , thus preventing SRC unwanted resets. The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without internal pull-up resistor or push-pull as output options, with factory- programmed or capacitor-adjustable or push-buttons defined output reset pulse duration, with or without power-on reset function. Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage V drops below the specified threshold. The CC reset output remains asserted for the reset timeout period (t ) after the monitored supply REC voltage goes above the specified threshold. Doc ID 16490 Rev 2 5/29

Description STM6513 Figure 1. Logic diagram VCC SR1 TRECADJ RST1 STM6513 SR0 RST2 TSR VSS AM00372 Figure 2. Pin connections RST1 1 8 VCC VSS 2 STM 7 SR0 6513 SR1 3 6 TRECADJ RST2 4 5 TSR AM00373 6/29 Doc ID 16490 Rev 2

STM6513 Device overview 2 Device overview T able 1. Signal names Symbol Input/output Description RST1 Output First reset output, active-high, push-pull. RST2 Output Second reset output, active-low, open-drain. SR0 Input Primary push-button Smart Reset input. Active-low. SR1 Input Secondary push-button Smart Reset input. Active-low. A Three-state Smart Reset input delay setup control. When connected to ground, t = 2 s; when left open, t = 6 s; when connected to SRC SRC V , t = 10 s (all times are minimum). TSR is a DC-type input, CC SRC TSR Input intended to be either permanently grounded, permanently connected to V or permanently left open. If left open, for improved system glitch CC immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic capacitor between the TSR and V pins. SS Input pin for t reset pulse duration adjustment. Connect an REC1 TREC Input external capacitor C to this pin to determine t ; t is factory- ADJ tREC REC1 REC2 programmed. Positive supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 µF decoupling ceramic V Supply CC capacitor is recommended to be connected between V and V CC SS pins. V Supply Ground SS Doc ID 16490 Rev 2 7/29

Pin descriptions STM6513 3 Pin descriptions 3.1 Power supply (V ) CC This pin is used to provide the power to the Smart Reset device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between V and V pins. CC SS 3.2 Ground (V ) SS This is the ground for the device and all supplies. 3.3 Smart Reset inputs (SR0, SR1) Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at least t to activate the reset outputs. When only one Smart Reset input is used, connect SRC the unused one permanently to V . SS 3.4 User-programmable Smart Reset delay (TSR pin) Used to allow the user to program the setup time before the push-buttons action is validated by reset output. Controlled by different voltage levels on the TSR pin: when connected to ground, t = 2 s; when left open, t = 6 s; when connected to V , t = 10 s SRC SRC CC SRC (all times are minimum). TSR is a DC-type input, intended to be either permanently grounded, permanently connected to V or permanently left open. If left open, for improved CC system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic capacitor between the TSR and V pins. SS 3.5 Reset outputs (RST1, RST2) Reset outputs, RST1 active-high, push-pull type, RST2 active-low, open-drain. 3.6 Adjustable output reset timeout period input pin (TREC ) ADJ The output reset timeout period (t ) on RST1 is adjustable by connecting an external REC1 capacitor C to the TREC pin. Calculated t and C examples are given in tREC ADJ REC tREC Table2. Refer also to Table5. 8/29 Doc ID 16490 Rev 2

STM6513 Pin descriptions Table 2. t programmed by an ideal external capacitor REC1 t (ms)(1)(2) REC1 Closest common C value (µF) tREC C value (µF) Min. Typ. Max. tREC 0.001 10 15 20 0.001 0.002 20 30 40 0.0022 0.01 100 150 200 0.01 0.014 140 210 280 0.015 0.028 280 420 560 0.027 0.056 560 840 1120 0.056 0.112 1120 1680 2240 0.12 1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external t programming capacitor REC (C ) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be tREC used and placed as close as possible to the TREC pin. Also an adequate low-leakage PCB ADJ environment should be ensured to prevent t accuracy from being affected. A recommended minimum REC value of C is 0.001 µF. tREC 2. In case of repeated activations of the internal t timer, an interval of 10 ms min. is needed between t REC REC intervals to fully discharge C , so that the next t is as specified. tREC REC1 Doc ID 16490 Rev 2 9/29

Block diagram STM6513 4 Block diagram Figure 3. Block diagram VCC tREC2 RST2 + – tREC1 RST1 VREF IREF TREC ADJ SR1 SR logic tSRC SR0 Three-state TSR selector Oscillator AM00374V2 10/29 Doc ID 16490 Rev 2

STM6513 Block diagram STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the microprocessor reset initiated by the STM6513 Smart Reset device: Figure 4. Typical application diagram VCC PMU VREG LD00 ... MCU LD07 Seq. (PU resistor) logic RST_n RST PWR POWER SW PS_hold KEY PS_hold VREG 100 kΩ GPIO1 GPIOn RST1 (PP) Forces PS_hold RST2 (OD) high during STM6513 reset period TSR SR0 TRECADJ SR1 KEYn CtREC KEY1 AM00375a Figure 5. Timing waveforms POR initiated Smart Reset™ initiated tSRC SR0, SR1 tREC2(210 ms) tREC2(210 ms) RST2 (OD) Factory - programmed RST1 (PP) by CtREC tREC1(~1 s) tREC1(~1 s) AM00376V2 Doc ID 16490 Rev 2 11/29

Typical operating characteristics STM6513 5 Typical operating characteristics Figure 6. Smart Reset delay t vs. temperature and supply voltage V , SRC CC TSR = V SS 3 2.9 2.8 2.7 2.6 2.5 tSRC [s] 2.4 2.3 2.2 2.1 2 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V AM00632 12/29 Doc ID 16490 Rev 2

STM6513 Typical operating characteristics Figure 7. Output reset timeout period t vs. temperature and supply voltage REC2 V (t option E) CC REC 280 260 240 220 tREC2 [ms] 200 180 160 140 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V AM00633 Figure 8. Supply current I vs. temperature and supply voltage V CC CC 6 5 4 3 ICC [µA] 2 1 0 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V AM00634 Doc ID 16490 Rev 2 13/29

Typical operating characteristics STM6513 Figure 9. Reset voltage V (falling) vs. temperature RST (threshold option S, 2.925 V typ.) 2.96 2.95 2.94 2.93 VRST,falling [V] 2.92 2.91 2.9 2.89 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] AM00635 Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply voltage V CC 10 8 6 4 2 ILI(TSR), LO [µA] 0 –60 –40 –20 0 20 40 60 80 100 120 140 –2 –4 –6 –8 –10 Temperature [˚C] 5.5 V 3.3 V 2 V AM00636 14/29 Doc ID 16490 Rev 2

STM6513 Typical operating characteristics Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply voltage V CC 10 8 6 4 2 ILI(TSR), HI [µA] 0 –60 –40 –20 0 20 40 60 80 100 120 140 –2 –4 –6 –8 –10 Temperature [˚C] 5.5 V 3.3 V 2 V AM00637 Doc ID 16490 Rev 2 15/29

Maximum rating STM6513 6 Maximum rating Stressing the device above the rating listed in the Table3: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. T able 3. Absolute maximum ratings Symbol Parameter Value Unit T Storage temperature (V off) –55 to +150 °C STG CC T (1) Lead solder temperature for 10 seconds 260 °C SLD θ Thermal resistance (junction to ambient) TDFN8 149.0 °C/W JA V Input or output voltage –0.3 to 5.5(2) V IO V Supply voltage –0.3 to 7 V CC 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 s. 2. For RST1 –0.3 to V +0.3 V only. CC 16/29 Doc ID 16490 Rev 2

STM6513 DC and AC parameters 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the Table5: DC and AC characteristics that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4.: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. T able 4. Operating and measurement conditions Parameter Value Unit V supply voltage 1.0 to 5.5 V CC Ambient operating temperature (T ) –40 to +85 °C A Input rise and fall times ≤ 5 ns Input pulse voltages 0.2 to 0.8 V V CC Input and output timing ref. voltages 0.3 to 0.7 V V CC Figure 12. AC testing input/output waveforms 0.8 VCC 0.7 VCC 0.2 VCC 0.3 VCC AM00478 Doc ID 16490 Rev 2 17/29

DC and AC parameters STM6513 Table 5. D C and AC characteristics Symbol Parameter Test conditions(1) Min. Typ.(2) Max. Units Reset output valid - active-low 1.0 5.5 V V Supply voltage range CC Reset output valid - active-high 1.2 5.5 V V = 3.0 V, TSR left open(3) 3 5 µA CC I Supply current (V ) CC CC V = 5.0 V, TSR left open 4 6 µA CC V ≥ 4.5 V, sinking 3.2 mA 0.3 V CC Reset output voltage V V ≥ 3.3 V, sinking 2.5 mA 0.3 V OL low CC V ≥ 1.0 V, sinking 0.1 mA 0.3 V CC V ≥ 4.5 V, I = 0.8 mA 0.8 V V CC SOURCE CC Reset output voltage V V ≥ 2.7 V, I = 0.5 mA 0.8 V V OH high, RST1 CC SOURCE CC V ≥ 1.2 V, I = 0.05 mA 0.8 V V CC SOURCE CC Fixed voltage trip –40 to +85 °C V –2.5% V V +2.5% V RST RST RST point for V V CC RST monitoring (refer to 25 °C V –2.0% V V +2.0% V RST RST RST Table6) L, M 0.5% V Hysteresis of V HYST RST T, S, R, Z, Y, W, V 1% V falling from (V + 100 mV) V to reset delay(4) CC RST 20 µs CC to (V - 100 mV) at 10 mV/µs RST Output reset timeout Option E 140 210 280 ms t period on RST2, REC2 factory-programmed Option F 240 360 480 ms User-adjustable output reset timeout 10 000 x 15 000 x 20 000 x t ms REC1 period on RST1 C (µF) C (µF) C (µF) tREC tREC tREC Refer to Table2. 18/29 Doc ID 16490 Rev 2

STM6513 DC and AC parameters Table 5. DC and AC characteristics (continued) Symbol Parameter Test conditions(1) Min. Typ.(2) Max. Units Smart Reset inputs (SRx) TSR = V 2 2.5 3 s SS t Smart Reset delay TSR = floating 6 7.5 9 s SRC TSR = V 10 12.5 15 s CC SR0, SR1 input V V –0.3 0.3 V V IL voltage low SS CC SR0, SR1 input V 0.7 V 5.5 V IH voltage high CC Input glitch Corresponds to the actual t t s immunity(5) SRC SRC Input leakage I current (SR0, SR1 –1 1 µA LI(SR) pins) Input leakage I –5 7 µA LI(TSR) current (TSR pin) 1. Valid for ambient operating temperature: T = –40 to +85 °C; V = 1.0 V to 5.5 V (except where noted). A CC 2. Typical value is at 25 °C and V = 3.3 V unless otherwise noted. CC 3. For devices with V < 3.0 V. RST 4. Guaranteed by design. 5. Input glitch immunity is equal to t (when both SR inputs are low), otherwise infinite. SRC Table 6. P ossible V voltage thresholds CC ±2.5% (–40 °C to +85 °C) ±2.0% (25 °C) V monitoring CC Typ. Unit threshold V RST Min. Max. Min. Max. L (falling) 4.625 4.509 4.741 4.533 4.718 V M (falling) 4.375 4.266 4.484 4.288 4.463 V T (falling) 3.075 2.998 3.152 3.014 3.137 V S (falling) 2.925 2.852 2.998 2.867 2.984 V R (falling) 2.625 2.559 2.691 2.573 2.678 V Z (falling) 2.313 2.255 2.371 2.267 2.359 V Y (falling) 2.188 2.133 2.243 2.144 2.232 V W (falling) 1.665 1.623 1.707 1.632 1.698 V V (falling) 1.575 1.536 1.614 1.544 1.607 V Doc ID 16490 Rev 2 19/29

Package mechanical data STM6513 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch D A B PIN 1 INDEX AREA E 0.10 C2x 0.10 C2x TOP VIEW 0.10 C A A1 C SEATING PLANE SIDE VIEW 0.08 C e PIN 1 INDEX AREA b 1 4 0.10 C A B Pin#1 ID L 8 5 BOTTOM VIEW TDFN-8L 20/29 Doc ID 16490 Rev 2

STM6513 Package mechanical data Table 7. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 1.9 2.00 2.1 0.075 0.079 0.083 BSC E 1.9 2.00 2.1 0.075 0.079 0.083 BSC e 0.50 0.020 L 0.45 0.55 0.65 0.018 0.022 0.026 Doc ID 16490 Rev 2 21/29

Package footprint STM6513 9 Package footprint Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b AM00441 T able 8. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Parameter Description Min. Nom. Max. L Contact length 1.05 — 1.15 b Contact width 0.25 — 0.30 E Max. land pattern Y-direction — 2.85 — E1 Contact gap spacing — 0.65 — D Max. land pattern X-direction — 1.75 — P Contact pitch — 0.5 — 22/29 Doc ID 16490 Rev 2

STM6513 Tape and reel information 10 Tape and reel information Figure 15. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 K0 Cofecnatevirtylines P1 User direction of feed AM03073v2 Table 9. C arrier tape dimensions Bulk Package W D E P P F A B K P T Unit 0 2 0 0 0 1 qty. 8.00 1.50 1.75 4.00 2.00 3.50 2.30 2.30 1.00 4.00 0.250 TDFN8 +0.30 +0.10/ mm 3000 ±0.10 ±0.10 ±0.10 ±0.05 ±0.05 ±0.05 ±0.05 ±0.10 ±0.05 –0.10 –0.00 Doc ID 16490 Rev 2 23/29

Tape and reel information STM6513 Figure 16. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radiu s Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 10. Reel dimensions Tape sizes A max. B min. C D min. N min. G T max. 8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.40 24/29 Doc ID 16490 Rev 2

STM6513 Tape and reel information Figure 17. Tape trailer/leader End Start Top No components Components 100mm min. No components cover tape TRAILER LEADER 160mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 18. Pin 1 orientation User direction of feed AM00442 Note: 1 Drawings are not to scale. 2 All dimensions are in mm, unless otherwise noted. Doc ID 16490 Rev 2 25/29

Part numbering STM6513 11 Part numbering Table 11. Ordering information scheme Example: STM6513 V E I E DG 6 F Device type STM6513 Reset (V monitoring threshold) voltage V CC RST L = 4.625 V (typ., falling) M = 4.375 V T = 3.075 V S = 2.925 V R = 2.625 V Z = 2.313 V Y = 2.188 V W = 1.665 V V = 1.575 V Smart Reset setup delay (t ); SRC presence of internal input pull-up on all Smart Reset inputs (SR0, SR1) E = 2 or 6 or 10 s min., user-programmed (three-state); no input pull-up Outputs type I = RST1 active-high, push-pull, RST2 active-low, open-drain, no pull-up Reset timeout period (t ) REC E = t user-programmable (external capacitor), t factory-programmed (210 ms typ.) REC1 REC2 F = t user-programmable (external capacitor), t factory-programmed (360 ms typ.) REC1 REC2 Package DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = –40 °C to +85 °C Shipping method F = ECOPACK® package, tape and reel For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you. 26/29 Doc ID 16490 Rev 2

STM6513 Package marking information 12 Package marking information Table 12. P ackage marking t Smart RST1 SRC t RST2 output t Full part number delay Reset V output REC1 REC2 Topmark RST programming type option control inputs type type STM6513VEIEDG6F TSR AL, NPU V AH, PP C AL, OD, NPU E 9AH tREC STM6513SEIEDG6F TSR AL, NPU S AH, PP C AL, OD, NPU E 9SH tREC STM6513REIEDG6F TSR AL, NPU R AH, PP C AL, OD, NPU E 9RH tREC Note: AL = active-low, AH = active-high; PP = push-pull, OD = open-drain, PU = internal pull-up resistor, NPU = no internal pull-up resistor. Figure 19. Package marking area, top view A B C D E Topmark A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark) AM00479 Doc ID 16490 Rev 2 27/29

Revision history STM6513 13 Revision history T able 13. Document revision history Date Revision Changes 22-Oct-2009 1 Initial release. Updated title, Features, Applications, replaced “smart reset” by “Smart Reset™” and “Smart Reset”, updated Section1, Table1, 21-Jun-2010 2 Section3, Table2, Figure3, Figure5, Figure6, Table3, Table5 to Table8, Table11 and Table12. 28/29 Doc ID 16490 Rev 2

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