STM32L151VD-X STM32L152VD-X ® ® Ultra-low-power 32-bit MCU ARM -based Cortex -M3 with 384KB Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC Datasheet - production data Features • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 °C to 105 °C temperature range LQFP100 (14 × 14 mm) WLCSP104 – 290 nA Standby mode (3 wakeup pins) (0.4 mm pitch) – 1.11 µA Standby mode + RTC • Up to 116 fast I/Os (102 I/Os 5V tolerant), all – 560 nA Stop mode (16 wakeup lines) mappable on 16 external interrupt vectors – 1.4 µA Stop mode + RTC • Memories – 11 µA Low-power run mode down to 4.6 µA – 384 Kbytes of Flash memory with ECC in Low-power sleep mode (with 2 banks of 192 Kbytes enabling RWW capability) – 195 µA/MHz Run mode – 80 Kbytes of RAM – 10 nA ultra-low I/O leakage – 16 Kbytes of true EEPROM with ECC – 8 µs wakeup time – 128-byte backup register • Core: ARM® Cortex®-M3 32-bit CPU • LCD driver (except STM32L151VD-X) up to – From 32 kHz up to 32 MHz max 8x40 segments, contrast adjustment, blinking – 1.25 DMIPS/MHz (Dhrystone 2.1) mode, step-up converter – Memory protection unit • Rich analog peripherals (down to 1.8 V) • Up to 23 capacitive sensing channels – 2x operational amplifiers • CRC calculation unit, 96-bit unique ID – 12-bit ADC 1 Msps up to 40 channels – 12-bit DAC 2 ch with output buffers • Reset and supply management – 2x ultra-low-power comparators – Low-power, ultrasafe BOR (brownout reset) (window mode and wakeup capability) with 5 selectable thresholds • DMA controller 12x channels – Ultra-low-power POR/PDR • 11x peripheral communication interfaces – Programmable voltage detector (PVD) – 1x USB 2.0 (internal 48 MHz PLL) • Clock sources – 5x USARTs – 1 to 24 MHz crystal oscillator – Up to 8x SPIs (2x I2S, 3x 16 Mbit/s) – 32 kHz oscillator for RTC with calibration – 2x I2Cs (SMBus/PMBus) – Internal 16 MHz oscillator factory trimmed • 11x timers: 1x 32-bit, 6x 16-bit with up to 4 RC(+/-1%) with PLL option IC/OC/PWM channels, 2x 16-bit basic timers, 2x watchdog timers (independent and window) – Internal low-power 37 kHz oscillator – Internal multispeed low-power 65 kHz to • Development support: serial wire debug, JTAG 4.2 MHz oscillator and trace – PLL for CPU clock and USB (48 MHz) • Pre-programmed bootloader – USB and USART supported August 2017 DocID027267 Rev 4 1/119 This is information on a product in full production. www.st.com

Contents STM32L151VD-X STM32L152VD-X Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 Internal voltage reference (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REFINT 3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26 3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 26 3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Contents 3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 28 3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29 3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 55 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DocID027267 Rev 4 3/119 4

Contents STM32L151VD-X STM32L152VD-X 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.1 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2 WLCSP104, 0.4 mm pitch wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 7.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 7.3.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X List of tables List of tables Table 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14 Table 3. CPU frequency range depending on dynamic voltage scaling. . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. Legend/abbreviations used in the pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7. STM32L151VD-X and STM32L152VD-X pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 10. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 11. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 12. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 13. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 14. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 15. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 16. Current consumption in Run mode, code with data processing running from Flash. . . . . . 59 Table 17. Current consumption in Run mode, code with data processing running from RAM. . . . . . 60 Table 18. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 19. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 20. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 21. Typical and maximum current consumptions in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . 64 Table 22. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 66 Table 23. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 24. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 25. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 26. Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 27. HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 28. LSE oscillator characteristics (f = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LSE Table 29. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 30. LSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 31. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 32. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 33. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 34. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 35. Flash memory and data EEPROM endurance and retention. . . . . . . . . . . . . . . . . . . . . . . 79 Table 36. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 37. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 38. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 39. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 40. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 41. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 42. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 43. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 44. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 45. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 46. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DocID027267 Rev 4 5/119 6

List of tables STM32L151VD-X STM32L152VD-X Table 47. SCL frequency (f = 32 MHz, V = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 89 PCLK1 DD Table 48. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 49. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 50. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 51. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 52. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 53. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 55. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 56. Maximum source impedance R max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 AIN Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 58. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 59. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 60. Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 61. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 62. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 63. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 64. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 108 Table 65. WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . 112 Table 66. WLCSP104, 0.4 mm pitch recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . 113 Table 67. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 68. STM32L151VD-X and STM32L152VD-X Ordering information scheme . . . . . . . . . . . . . 116 Table 69. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X List of figures List of figures Figure 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X block diagram . . . . . . . . . . . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3. STM32L152VD-X LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 4. STM32L151VD-X WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 6. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 7. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 9. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 12. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 13. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 14. Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 15. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 16. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 17. I2C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 18. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 19. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 20. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 21. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 22. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 23. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 26. Maximum dynamic current consumption on V supply pin during ADC REF+ conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 27. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 28. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline. . . . . . . . . . . . . . . 108 Figure 29. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 30. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 110 Figure 31. WLCSP104, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . 111 Figure 32. WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint. . . . . 112 Figure 33. WLCSP104, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . 113 Figure 34. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 35. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DocID027267 Rev 4 7/119 7

Introduction STM32L151VD-X STM32L152VD-X 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L151VD-X and STM32L152VD-X ultra-low-power ARM® Cortex®-M3 based microcontroller product line. The STM32L151VD-X and STM32L152VD-X devices are microcontrollers with a Flash memory density of 384 Kbytes. The ultra-low-power STM32L151VD-X and STM32L152VD-X family includes devices in 2 different package types: from 100 pins to 104 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L151VD-X and STM32L152VD-X microcontroller family suitable for a wide range of applications: • Medical and handheld equipment • Application control and user interface • PC peripherals, gaming, GPS and sport equipment • Alarm systems, wired and wireless sensors, video intercom • Utility metering This STM32L151VD-X and STM32L152VD-X datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The application note “Getting started with STM32L1xxxx hardware development” (AN3216) gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3 technical reference manual, available from the www.arm.com website. Figure 1 shows the general block diagram of the device family. 8/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Description 2 Description The ultra-low-power STM32L151VD-X and STM32L152VD-X devices incorporate the connectivity power of the universal serial bus (USB) with the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32L151VD-X and STM32L152VD-X devices offer two operational amplifiers, one 12-bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L151VD-X and STM32L152VD-X devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, two UARTs and an USB. The STM32L151VD-X and STM32L152VD-X devices offer up to 23 capacitive sensing channels to simply add a touch sensing functionality to any application. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller (except STM32L151VD-X) has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage. The ultra-low-power STM32L151VD-X and STM32L152VD-X devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C temperature ranges. A comprehensive set of power-saving modes allows the design of low-power applications. DocID027267 Rev 4 9/119 49

Description STM32L151VD-X STM32L152VD-X 2.1 Device overview Table 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X device features and peripheral counts Peripheral STM32L151VD-X STM32L152VD-X Flash (Kbytes) 384 Data EEPROM (Kbytes) 16 RAM (Kbytes) 80 32 bit 1 General- Timers 6 purpose Basic 2 SPI 8(3)(1) I2S 2 Communication I2C 2 interfaces USART 5 USB 1 GPIOs 83 Operational amplifiers 2 12-bit synchronized ADC 1 Number of channels 25 12-bit DAC 2 Number of channels 2 LCD (2) 1 COM x SEG 4x44 or 8x40 Comparators 2 Capacitive sensing channels 23 Max. CPU frequency 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option Operating voltage 1.65 V to 3.6 V without BOR option Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C Operating temperatures Junction temperature: –40 to + 110 °C LQFP100, Packages WLCSP104 1. 5 SPIs are USART configured in synchronous mode emulating SPI master. 2. STM32L152VD-X device only. 10/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Description Note: There is no FSMC and SDIO peripheral. 2.2 Ultra-low-power device continuum The ultra-low-power family offers a large choice of cores and features. From proprietary 8- bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many others will clearly allow to build very cost-optimized applications by reducing BOM. Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, the old applications can be upgraded to respond to the latest market features and efficiency demand. 2.2.1 Performance All the families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a very easy migration from one family to another: • Analog peripherals: ADC, DAC and comparators • Digital peripherals: RTC and some communication interfaces 2.2.3 Common system strategy. To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and STM32L162xx family uses a common architecture: • Same power supply range from 1.65 V to 3.6 V • Architecture optimized to reach ultra-low consumption both in low-power modes and Run mode • Fast startup strategy from low-power modes • Flexible system clock • Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector 2.2.4 Features ST ultra-low-power continuum also lies in feature compatibility: • More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm • Memory density ranging from 2 to 512 Kbytes DocID027267 Rev 4 11/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3 Functional overview Figure 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X block diagram (cid:55)(cid:53)(cid:36)(cid:38)(cid:40)(cid:38)(cid:46)(cid:15)(cid:3)(cid:55)(cid:53)(cid:36)(cid:38)(cid:40)(cid:39)(cid:19)(cid:15)(cid:3)(cid:55)(cid:53)(cid:36)(cid:38)(cid:40)(cid:39)(cid:20)(cid:15)(cid:3)(cid:55)(cid:53)(cid:36)(cid:38)(cid:40)(cid:39)(cid:21)(cid:15)(cid:3)(cid:55)(cid:53)(cid:36)(cid:38)(cid:40)(cid:39)(cid:23) (cid:45)(cid:55)(cid:36)(cid:42)(cid:3)(cid:9)(cid:3)(cid:54)(cid:58) (cid:83)(cid:69)(cid:88)(cid:86) (cid:55)(cid:85)(cid:68)(cid:70)(cid:72)(cid:3)(cid:38)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:85)(cid:3)(cid:40)(cid:55)(cid:48) (cid:57)(cid:39)(cid:39)(cid:3)(cid:38)(cid:50)(cid:53)(cid:40) (cid:35)(cid:3)(cid:51)(cid:57)(cid:50)(cid:39)(cid:58)(cid:39)(cid:3)(cid:40)(cid:22)(cid:53)(cid:22) (cid:57)(cid:39)(cid:39)(cid:22)(cid:22)(cid:32)(cid:20)(cid:17)(cid:25)(cid:24)(cid:57)(cid:3)(cid:87)(cid:82)(cid:3)(cid:22)(cid:17)(cid:25)(cid:57) (cid:49)(cid:45)(cid:55)(cid:53)(cid:54)(cid:55) (cid:57)(cid:50)(cid:47)(cid:55)(cid:17)(cid:3)(cid:53)(cid:40)(cid:42)(cid:17) (cid:57)(cid:86)(cid:86) (cid:45)(cid:45)(cid:55)(cid:55)(cid:48)(cid:38)(cid:46)(cid:54)(cid:3)(cid:3)(cid:18)(cid:18)(cid:3)(cid:3)(cid:54)(cid:54)(cid:68)(cid:45)(cid:58)(cid:58)(cid:55)(cid:45)(cid:86)(cid:55)(cid:3)(cid:38)(cid:39)(cid:39)(cid:36)(cid:39)(cid:47)(cid:50)(cid:36)(cid:41)(cid:44)(cid:46)(cid:55) (cid:48)(cid:51)(cid:56)(cid:41)(cid:80)(cid:68)(cid:49)(cid:91)(cid:29)(cid:57)(cid:3)(cid:22)(cid:48)(cid:44)(cid:38)(cid:21)(cid:22)(cid:3)(cid:48)(cid:3)(cid:38)(cid:43)(cid:51)(cid:93)(cid:56) (cid:54)(cid:39)(cid:76)(cid:92)(cid:69)(cid:86)(cid:69)(cid:88)(cid:87)(cid:88)(cid:86)(cid:72)(cid:86)(cid:80) (cid:48)(cid:68)(cid:87)(cid:85)(cid:76)(cid:91)(cid:3)(cid:24)(cid:48)(cid:3)(cid:18)(cid:3)(cid:24)(cid:54) (cid:40)(cid:40)(cid:51)(cid:53)(cid:50)(cid:48)(cid:82)(cid:69)(cid:79)(cid:54)(cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72)(cid:53)(cid:36)(cid:48)(cid:22)(cid:3)(cid:40)(cid:27)(cid:27)(cid:19)(cid:40)(cid:23)(cid:46)(cid:20)(cid:39)(cid:51)(cid:3)(cid:27)(cid:46)(cid:25)(cid:56)(cid:53)(cid:46)(cid:37)(cid:3)(cid:46)(cid:36)(cid:50)(cid:37)(cid:3)(cid:51)(cid:37)(cid:47)(cid:3)(cid:48)(cid:37)(cid:3)(cid:53)(cid:3)(cid:37)(cid:39)(cid:3)(cid:50)(cid:25)(cid:50)(cid:36)(cid:36)(cid:23)(cid:50)(cid:42)(cid:49)(cid:55)(cid:3)(cid:55)(cid:69)(cid:36)(cid:46)(cid:53)(cid:76)(cid:87)(cid:51)(cid:36)(cid:39)(cid:48)(cid:53) (cid:54)(cid:88)(cid:83)(cid:83)(cid:79)(cid:92)(cid:51)(cid:3)(cid:80)(cid:39)(cid:82)(cid:53)(cid:57)(cid:81)(cid:76)(cid:85)(cid:87)(cid:72)(cid:82)(cid:73)(cid:85)(cid:76)(cid:81)(cid:74) (cid:49)(cid:53)(cid:54)(cid:55) (cid:42)(cid:51)(cid:3)(cid:39)(cid:48)(cid:36)(cid:3)(cid:26)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:37)(cid:88)(cid:86)(cid:3) (cid:35)(cid:3)(cid:57)(cid:39)(cid:39)(cid:22)(cid:22) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:42)(cid:51)(cid:3)(cid:39)(cid:48)(cid:36)(cid:21)(cid:3)(cid:24)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:35)(cid:57)(cid:39)(cid:39)(cid:36) (cid:59)(cid:20)(cid:55)(cid:16)(cid:21)(cid:36)(cid:23)(cid:47)(cid:3)(cid:3)(cid:48)(cid:50)(cid:43)(cid:54)(cid:38)(cid:93) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:36)(cid:43)(cid:37)(cid:51)(cid:38)(cid:47)(cid:46) (cid:36)(cid:51)(cid:37)(cid:51)(cid:38)(cid:47)(cid:46) (cid:51)(cid:47)(cid:47)(cid:3)(cid:9) (cid:43)(cid:38)(cid:47)(cid:46) (cid:38)(cid:79)(cid:82)(cid:70)(cid:78) (cid:41)(cid:38)(cid:47)(cid:46) (cid:48)(cid:74)(cid:80)(cid:87) (cid:58)(cid:39)(cid:42)(cid:3)(cid:22)(cid:21)(cid:46) (cid:54)(cid:88)(cid:83)(cid:83)(cid:79)(cid:92) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:69)(cid:92) (cid:80)(cid:82)(cid:81)(cid:76)(cid:87)(cid:82)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:3) (cid:53)(cid:38)(cid:3)(cid:43)(cid:54)(cid:44) (cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72) (cid:57)(cid:39)(cid:39)(cid:36)(cid:3)(cid:18) (cid:57)(cid:54)(cid:54)(cid:36) (cid:37)(cid:50)(cid:53)(cid:3)(cid:18)(cid:3)(cid:37)(cid:74)(cid:68)(cid:83) (cid:37)(cid:50)(cid:53) (cid:53)(cid:38)(cid:3)(cid:48)(cid:54)(cid:44) (cid:59)(cid:55)(cid:36)(cid:47)(cid:3)(cid:22)(cid:21)(cid:3)(cid:78)(cid:43)(cid:93) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:51)(cid:57)(cid:39) (cid:44)(cid:81)(cid:87) (cid:35)(cid:53)(cid:57)(cid:38)(cid:39)(cid:3)(cid:47)(cid:39)(cid:54)(cid:36)(cid:44) (cid:50)(cid:54)(cid:53)(cid:38)(cid:55)(cid:22)(cid:38)(cid:21)(cid:66)(cid:66)(cid:50)(cid:50)(cid:56)(cid:56)(cid:55)(cid:55) (cid:38)(cid:68)(cid:83)(cid:17)(cid:3)(cid:86)(cid:72)(cid:81)(cid:86) (cid:48)(cid:43)(cid:93) (cid:53)(cid:36)(cid:55)(cid:58)(cid:38)(cid:3)(cid:56)(cid:57)(cid:21) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3) (cid:55)(cid:36)(cid:48)(cid:51)(cid:40)(cid:53) (cid:38)(cid:50)(cid:48)(cid:51)(cid:91)(cid:66)(cid:44)(cid:49)(cid:91) (cid:42)(cid:51)(cid:51)(cid:56)(cid:3)(cid:38)(cid:3)(cid:18)(cid:3)(cid:82)(cid:51)(cid:80)(cid:39)(cid:83) (cid:35)(cid:57)(cid:39)(cid:39)(cid:36) (cid:80)(cid:68)(cid:91)(cid:3)(cid:32)(cid:3)(cid:22)(cid:21)(cid:3) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3)(cid:76)(cid:81)(cid:53)(cid:87)(cid:72)(cid:72)(cid:85)(cid:74)(cid:73)(cid:68)(cid:3)(cid:20)(cid:70)(cid:21)(cid:72)(cid:27) (cid:51)(cid:36)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:36) (cid:36)(cid:43)(cid:37)(cid:29)(cid:3)(cid:3)(cid:41) (cid:57)(cid:47)(cid:38)(cid:39)(cid:3) (cid:35)(cid:47)(cid:38)(cid:57)(cid:39)(cid:39)(cid:3)(cid:39)(cid:37)(cid:22)(cid:82)(cid:22)(cid:82)(cid:86)(cid:87)(cid:72)(cid:85) (cid:57)(cid:47)(cid:38)(cid:39)(cid:3)(cid:32)(cid:3)(cid:21)(cid:17)(cid:24)(cid:57)(cid:3)(cid:87)(cid:82)(cid:3)(cid:22)(cid:17)(cid:25)(cid:57) (cid:51)(cid:37)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:37) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:21) (cid:23)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:51)(cid:38)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:38) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:22) (cid:23)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:51)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:39) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:23) (cid:23)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:51)(cid:40)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:40) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:54)(cid:3)(cid:11)(cid:22)(cid:21)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:12) (cid:23)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:51)(cid:43)(cid:62)(cid:21)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:43) (cid:53)(cid:59)(cid:15)(cid:3)(cid:55)(cid:59)(cid:15)(cid:3)(cid:38)(cid:55)(cid:54)(cid:15)(cid:3)(cid:53)(cid:55)(cid:54)(cid:15)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:51)(cid:41)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:41) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:21) (cid:54)(cid:80)(cid:68)(cid:85)(cid:87)(cid:38)(cid:68)(cid:85)(cid:71)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:22) (cid:53)(cid:59)(cid:15)(cid:3)(cid:55)(cid:59)(cid:15)(cid:3)(cid:38)(cid:55)(cid:54)(cid:15)(cid:3)(cid:53)(cid:55)(cid:54)(cid:15)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:51)(cid:42)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:42)(cid:51)(cid:44)(cid:50)(cid:3)(cid:51)(cid:50)(cid:53)(cid:55)(cid:3)(cid:42) (cid:54)(cid:80)(cid:68)(cid:85)(cid:87)(cid:38)(cid:68)(cid:85)(cid:71)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:40)(cid:59)(cid:55)(cid:17)(cid:44)(cid:55) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:23) (cid:53)(cid:59)(cid:15)(cid:3)(cid:55)(cid:59)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41) (cid:20)(cid:20)(cid:24)(cid:3)(cid:36)(cid:41) (cid:58)(cid:46)(cid:56)(cid:51) (cid:36)(cid:43)(cid:37)(cid:18)(cid:36)(cid:51)(cid:37)(cid:21) (cid:36)(cid:43)(cid:37)(cid:18)(cid:36)(cid:51)(cid:37)(cid:20) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:24) (cid:53)(cid:59)(cid:15)(cid:3)(cid:55)(cid:59)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41) (cid:54)(cid:38)(cid:48)(cid:46)(cid:50)(cid:15)(cid:3)(cid:54)(cid:49)(cid:44)(cid:54)(cid:15)(cid:3)(cid:48)(cid:54)(cid:3)(cid:44)(cid:68)(cid:54)(cid:86)(cid:50)(cid:3)(cid:36)(cid:15)(cid:41) (cid:54)(cid:51)(cid:44)(cid:20) (cid:21)(cid:91)(cid:11)(cid:27)(cid:91)(cid:20)(cid:25)(cid:69)(cid:54)(cid:76)(cid:87)(cid:51)(cid:12)(cid:44)(cid:21)(cid:18)(cid:44)(cid:21)(cid:54) (cid:48)(cid:48)(cid:50)(cid:38)(cid:54)(cid:46)(cid:44)(cid:15)(cid:15)(cid:3)(cid:3)(cid:54)(cid:48)(cid:39)(cid:44)(cid:54)(cid:3)(cid:68)(cid:50)(cid:86)(cid:15)(cid:3)(cid:3)(cid:36)(cid:54)(cid:41)(cid:38)(cid:46)(cid:15)(cid:49)(cid:54)(cid:54)(cid:15)(cid:58)(cid:54)(cid:15)(cid:3)(cid:38)(cid:46) (cid:53)(cid:59)(cid:15)(cid:3)(cid:55)(cid:59)(cid:15)(cid:3)(cid:38)(cid:55)(cid:54)(cid:15)(cid:3)(cid:53)(cid:55)(cid:54)(cid:15)(cid:3) (cid:54)(cid:80)(cid:68)(cid:85)(cid:87)(cid:38)(cid:68)(cid:85)(cid:71)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41) (cid:56)(cid:54)(cid:36)(cid:53)(cid:55)(cid:20) (cid:56)(cid:54)(cid:37)(cid:3)(cid:54)(cid:53)(cid:36)(cid:48)(cid:3)(cid:24)(cid:20)(cid:21)(cid:3)(cid:37) (cid:21)(cid:91)(cid:11)(cid:27)(cid:91)(cid:20)(cid:25)(cid:69)(cid:54)(cid:76)(cid:87)(cid:51)(cid:12)(cid:44)(cid:22)(cid:18)(cid:44)(cid:21)(cid:54) (cid:48)(cid:48)(cid:50)(cid:38)(cid:54)(cid:46)(cid:44)(cid:15)(cid:15)(cid:3)(cid:3)(cid:54)(cid:48)(cid:39)(cid:44)(cid:54)(cid:3)(cid:68)(cid:50)(cid:86)(cid:15)(cid:3)(cid:3)(cid:36)(cid:54)(cid:41)(cid:38)(cid:46)(cid:15)(cid:49)(cid:54)(cid:54)(cid:15)(cid:58)(cid:54)(cid:15)(cid:3)(cid:38)(cid:46) (cid:35)(cid:57)(cid:39)(cid:39)(cid:36) (cid:43)(cid:93) (cid:43)(cid:93) (cid:23)(cid:19)(cid:3)(cid:36)(cid:41) (cid:48) (cid:48) (cid:57)(cid:39)(cid:39)(cid:53)(cid:40)(cid:41)(cid:66)(cid:36)(cid:39)(cid:38)(cid:13) (cid:20)(cid:21)(cid:69)(cid:76)(cid:87)(cid:3)(cid:36)(cid:39)(cid:38) (cid:44)(cid:41) (cid:32)(cid:3)(cid:22)(cid:21)(cid:3) (cid:58)(cid:76)(cid:81)(cid:58)(cid:36)(cid:55)(cid:38)(cid:43)(cid:39)(cid:50)(cid:42) (cid:32)(cid:3)(cid:22)(cid:21)(cid:3) (cid:44)(cid:21)(cid:38)(cid:20) (cid:54)(cid:36)(cid:38)(cid:86)(cid:47)(cid:3)(cid:36)(cid:15)(cid:3)(cid:41)(cid:54)(cid:39)(cid:36) (cid:57)(cid:54)(cid:54)(cid:53)(cid:40)(cid:41)(cid:66)(cid:36)(cid:39)(cid:38)(cid:13) (cid:80)(cid:68)(cid:91)(cid:3) (cid:80)(cid:68)(cid:91)(cid:3) (cid:44)(cid:21)(cid:38)(cid:21) (cid:54)(cid:36)(cid:38)(cid:86)(cid:3)(cid:47)(cid:36)(cid:15)(cid:41)(cid:3)(cid:54)(cid:39)(cid:36)(cid:15)(cid:3)(cid:54)(cid:48)(cid:37)(cid:88)(cid:86)(cid:15)(cid:3)(cid:51)(cid:48)(cid:37)(cid:88)(cid:86) (cid:55)(cid:72)(cid:80)(cid:83)(cid:3)(cid:86)(cid:72)(cid:81)(cid:86)(cid:82)(cid:85) (cid:36)(cid:51)(cid:37)(cid:21)(cid:29)(cid:3)(cid:41) (cid:55)(cid:55)(cid:44)(cid:44)(cid:48)(cid:48)(cid:40)(cid:40)(cid:53)(cid:53)(cid:26)(cid:25) (cid:36)(cid:51)(cid:37)(cid:20)(cid:29)(cid:3)(cid:41) (cid:56)(cid:54)(cid:37)(cid:21)(cid:17)(cid:19)(cid:3)(cid:41)(cid:54)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:70)(cid:72) (cid:56)(cid:56)(cid:54)(cid:54)(cid:37)(cid:37)(cid:66)(cid:66)(cid:39)(cid:39)(cid:48)(cid:51) (cid:38)(cid:68)(cid:83)(cid:17)(cid:3)(cid:86)(cid:72)(cid:81)(cid:86)(cid:76)(cid:81)(cid:74) (cid:51)(cid:91) (cid:42)(cid:72)(cid:81)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:83)(cid:88)(cid:85)(cid:83)(cid:82)(cid:86)(cid:72) (cid:87)(cid:76)(cid:80)(cid:72)(cid:85)(cid:86) (cid:54)(cid:40)(cid:42)(cid:91) (cid:21)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79)(cid:86) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:28) (cid:50)(cid:51)(cid:36)(cid:48)(cid:51)(cid:20) (cid:47)(cid:38)(cid:39)(cid:3)(cid:27)(cid:91)(cid:23)(cid:19) (cid:38)(cid:50)(cid:48)(cid:91) (cid:35)(cid:57)(cid:39)(cid:39)(cid:36) (cid:20)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:20)(cid:19) (cid:50)(cid:51)(cid:36)(cid:48)(cid:51)(cid:21) (cid:20)(cid:21)(cid:69)(cid:76)(cid:87)(cid:3)(cid:39)(cid:36)(cid:38)(cid:20) (cid:39)(cid:36)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55)(cid:20)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41) (cid:20)(cid:3)(cid:70)(cid:75)(cid:68)(cid:81)(cid:81)(cid:72)(cid:79) (cid:55)(cid:44)(cid:48)(cid:40)(cid:53)(cid:20)(cid:20) (cid:44)(cid:44)(cid:44)(cid:41)(cid:41)(cid:41) (cid:20)(cid:21)(cid:69)(cid:76)(cid:87)(cid:3)(cid:39)(cid:36)(cid:38)(cid:21) (cid:39)(cid:36)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55)(cid:21)(cid:3)(cid:68)(cid:86)(cid:3)(cid:36)(cid:41) (cid:57)(cid:44)(cid:49)(cid:51) (cid:57)(cid:44)(cid:49)(cid:51) (cid:57)(cid:44)(cid:49)(cid:48) (cid:57)(cid:44)(cid:49)(cid:48) (cid:57)(cid:50)(cid:56)(cid:55) (cid:57)(cid:50)(cid:56)(cid:55) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:25)(cid:23)(cid:19)(cid:57)(cid:21) 12/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview 3.1 Low-power modes The ultra-low-power STM32L151VD-X and STM32L152VD-X devices support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply. There are three power consumption ranges: • Range 1 (V range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz DD • Range 2 (full V range), with a maximum CPU frequency of 16 MHz DD • Range 3 (full V range), with a maximum CPU frequency limited to 4 MHz (generated DD only with the multispeed internal RC oscillator clock source) Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. • Low-power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In low-power run mode, the clock frequency and the number of enabled peripherals are both limited. • Low-power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low-power mode to minimize the regulator’s operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. • Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the V domain are stopped, the CORE PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. DocID027267 Rev 4 13/119 49

Functional overview STM32L151VD-X STM32L152VD-X • Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. • Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire V domain is CORE powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. • Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V domain is powered off. The PLL, MSI CORE RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Table 2. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range(1) Operating power supply DAC and ADC Dynamic voltage scaling USB range operation range V = V = 1.65 to 1.71 V Not functional Not functional Range 2 or Range 3 DD DDA Range 1, Range 2 or V =V = 1.71 to 1.8 V(2) Not functional Not functional DD DDA Range 3 Conversion time up Range 1, Range 2 or V =V = 1.8 to 2.0 V Not functional DD DDA to 500 Ksps Range 3 14/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview Table 2. Functionalities depending on the operating power supply range (continued) Functionalities depending on the operating power supply range(1) Operating power supply DAC and ADC Dynamic voltage scaling USB range operation range Conversion time up Range 1, Range 2 or V =V = 2.0 to 2.4 V Functional(3) DD DDA to 500 Ksps Range 3 Conversion time up Range 1, Range 2 or V =V = 2.4 to 3.6 V Functional(3) DD DDA to 1 Msps Range 3 1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 43: I/O AC characteristics for more information about I/O speed. 2. CPU frequency changes from initial to final must respect “F initial < 4*F final” to limit V drop CPU CPU CORE due to current consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz. 3. Should be USB compliant from I/O voltage standpoint, the minimum V is 3.0 V. DD Table 3. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) Range 1 32 kHz to 16 MHz (0ws) 8 MHz to 16 MHz (1ws) Range 2 32 kHz to 8 MHz (0ws) 2.1MHz to 4.2 MHz (1ws) Range 3 32 kHz to 2.1 MHz (0ws) DocID027267 Rev 4 15/119 49

Functional overview STM32L151VD-X STM32L152VD-X Table 4. Functionalities depending on the working mode (from Run/active down to standby) Stop Standby Low- Low- Ips Run/Active Sleep power power Wakeup Wakeup Run Sleep capability capability CPU Y -- Y -- -- -- -- -- Flash Y Y Y Y -- -- -- -- RAM Y Y Y Y Y -- -- -- Backup Registers Y Y Y Y Y -- Y -- EEPROM Y Y Y Y Y -- -- -- Brown-out rest Y Y Y Y Y Y Y -- (BOR) DMA Y Y Y Y -- -- -- -- Programmable Voltage Detector Y Y Y Y Y Y Y -- (PVD) Power On Reset Y Y Y Y Y Y Y -- (POR) Power Down Rest Y Y Y Y Y -- Y -- (PDR) High Speed Y Y -- -- -- -- -- -- Internal (HSI) High Speed Y Y -- -- -- -- -- -- External (HSE) Low Speed Internal Y Y Y Y Y -- Y -- (LSI) Low Speed Y Y Y Y Y -- Y -- External (LSE) Multi-Speed Y Y Y Y -- -- -- -- Internal (MSI) Inter-Connect Y Y Y Y -- -- -- -- Controller RTC Y Y Y Y Y Y Y -- RTC Tamper Y Y Y Y Y Y Y Y Auto WakeUp Y Y Y Y Y Y Y Y (AWU) LCD Y Y Y Y Y -- -- -- USB Y Y -- -- -- Y -- -- USART Y Y Y Y Y (1) -- -- SPI Y Y Y Y -- -- -- -- I2C Y Y -- -- -- (1) -- -- 16/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview Table 4. Functionalities depending on the working mode (from Run/active down to standby) (continued) Stop Standby Low- Low- Ips Run/Active Sleep power power Wakeup Wakeup Run Sleep capability capability ADC Y Y -- -- -- -- -- -- DAC Y Y Y Y Y -- -- -- Tempsensor Y Y Y Y Y -- -- -- OP amp Y Y Y Y Y -- -- -- Comparators Y Y Y Y Y Y -- -- 16-bit and 32-bit Y Y Y Y -- -- -- -- Timers IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y -- -- -- -- Touch sensing Y Y -- -- -- -- -- -- Systic Timer Y Y Y Y -- -- -- GPIOs Y Y Y Y Y Y -- 3 pins Wakeup time to 0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs Run mode 0.53 µA 0.285 µA (no RTC) (no RTC) V =1.8V V =1.8V DD DD 1.2 µA 0.97 µA (with RTC) (with RTC) Consumption Down to 195 Down to 38 Down to Down to VDD=1.8V VDD=1.8V V =1.8 to 3.6 V µA/MHz (from µA/MHz (from (TDyDp) Flash) Flash) 11 µA 4.6 µA 0.56 µA 0.29 µA (no RTC) (no RTC) V =3.0V V =3.0V DD DD 1.4 µA 1.11 µA (with RTC) (with RTC) V =3.0V V =3.0V DD DD 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. ® ® 3.2 ARM Cortex -M3 core with MPU The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. DocID027267 Rev 4 17/119 49

Functional overview STM32L151VD-X STM32L152VD-X The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L151VD-X and STM32L152VD-X devices are compatible with all ARM tools and software. Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L151VD-X and STM32L152VD-X devices embed a nested vectored interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of ARM® Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support for tail-chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 Reset and supply management 3.3.1 Power supply schemes • V = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided DD externally through V pins. DD • V , V = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs SSA DDA and PLL (minimum voltage to be applied to V is 1.8 V when the ADC is used). V DDA DDA and V must be connected to V and V , respectively. SSA DD SS 3.3.2 Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. The device exists in two versions: • The version with BOR activated at power-on operates between 1.8 V and 3.6 V. • The other version without BOR operates between 1.65 V and 3.6 V. After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or DD not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the V min value becomes DD 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits DD the POR area. 18/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (V ) in Stop mode. The device remains in reset mode when REFINT V is below a specified threshold, V or V , without the need for any external DD POR/PDR BOR reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The device features an embedded programmable voltage detector (PVD) that monitors the V /V power supply and compares it to the V threshold. This PVD offers 7 different DD DDA PVD levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V /V drops below the V threshold and/or when DD DDA PVD V /V is higher than the V threshold. The interrupt service routine can then generate DD DDA PVD a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. • MR is used in Run mode (nominal regulation) • LPR is used in the Low-power run, Low-power sleep and Stop modes • Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). 3.3.4 Boot modes At startup, boot pins are used to select one of three boot options: • Boot from Flash memory • Boot from System memory • Boot from embedded RAM The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot mechanism is available through user option byte, to allow booting from bank 2 when bank 2 contains valid code. This dual boot capability can be used to easily implement a secure field software update mechanism. The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See Application note “STM32 microcontroller system memory boot mode” (AN2606) for details. DocID027267 Rev 4 19/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3.4 Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: three different clock sources can be used to drive the master clock SYSCLK: – 1-24 MHz high-speed external crystal (HSE), that can supply a PLL – 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy. • Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE) – 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. • RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. • USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. • Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. • Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. 20/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview Figure 2. Clock tree (cid:51)(cid:84)(cid:65)(cid:78)(cid:68)(cid:66)(cid:89)(cid:0)(cid:83)(cid:85)(cid:80)(cid:80)(cid:76)(cid:73)(cid:69)(cid:68)(cid:0)(cid:86)(cid:79)(cid:76)(cid:84)(cid:65)(cid:71)(cid:69)(cid:0)(cid:68)(cid:79)(cid:77)(cid:65)(cid:73)(cid:78) (cid:69)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69) (cid:55)(cid:65)(cid:84)(cid:67)(cid:72)(cid:68)(cid:79)(cid:71) (cid:55)(cid:65)(cid:84)(cid:67)(cid:72)(cid:68)(cid:79)(cid:71) (cid:44)(cid:51)(cid:41)(cid:0)(cid:50)(cid:35) (cid:44)(cid:51)(cid:41)(cid:0)(cid:84)(cid:69)(cid:77)(cid:80)(cid:79) (cid:44)(cid:51) (cid:50)(cid:52)(cid:35)(cid:0)(cid:69)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69) (cid:50)(cid:52)(cid:35) (cid:44)(cid:51)(cid:37)(cid:0)(cid:47)(cid:51)(cid:35) (cid:44)(cid:51)(cid:37)(cid:0)(cid:84)(cid:69)(cid:77)(cid:80)(cid:79) (cid:50)(cid:65)(cid:68)(cid:73)(cid:79)(cid:0)(cid:51)(cid:76)(cid:69)(cid:69)(cid:80)(cid:0)(cid:52)(cid:73)(cid:77)(cid:69)(cid:82) (cid:50)(cid:65)(cid:68)(cid:73)(cid:79)(cid:0)(cid:51)(cid:76)(cid:69)(cid:69)(cid:80)(cid:0)(cid:52)(cid:73)(cid:77)(cid:69)(cid:82)(cid:0)(cid:69)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69) (cid:44)(cid:51) (cid:44)(cid:51) (cid:44)(cid:51) (cid:44)(cid:51) (cid:32)(cid:54)(cid:36)(cid:36)(cid:35)(cid:47)(cid:50)(cid:37) (cid:35)(cid:43)(cid:63)(cid:44)(cid:35)(cid:36) (cid:17)(cid:0)(cid:45)(cid:40)(cid:90) (cid:44)(cid:35)(cid:36)(cid:0)(cid:69)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69) (cid:32)(cid:54)(cid:19)(cid:19) (cid:35)(cid:43)(cid:63)(cid:33)(cid:36)(cid:35) (cid:45)(cid:51)(cid:41)(cid:0)(cid:50)(cid:35) (cid:67)(cid:75)(cid:63)(cid:76)(cid:83)(cid:73) (cid:33)(cid:36)(cid:35)(cid:0)(cid:69)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69) (cid:67)(cid:75)(cid:63)(cid:76)(cid:83)(cid:69) (cid:76)(cid:69)(cid:86)(cid:69)(cid:76)(cid:0)(cid:83)(cid:72)(cid:73)(cid:70)(cid:84)(cid:69)(cid:82)(cid:83) (cid:32)(cid:54)(cid:36)(cid:36)(cid:35)(cid:47)(cid:50)(cid:37) (cid:15)(cid:0)(cid:17)(cid:12)(cid:18)(cid:12)(cid:20)(cid:12)(cid:24)(cid:12)(cid:17)(cid:22) (cid:45)(cid:35)(cid:47) (cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80) (cid:15)(cid:0)(cid:18)(cid:12)(cid:20)(cid:12)(cid:24)(cid:12)(cid:17)(cid:22) (cid:32)(cid:54)(cid:19)(cid:19) (cid:35)(cid:43)(cid:63)(cid:48)(cid:55)(cid:50) (cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80) (cid:40)(cid:51)(cid:41)(cid:0)(cid:50)(cid:35) (cid:35)(cid:43)(cid:63)(cid:38)(cid:35)(cid:44)(cid:43) (cid:76)(cid:69)(cid:86)(cid:69)(cid:76)(cid:0)(cid:83)(cid:72)(cid:73)(cid:70)(cid:84)(cid:69)(cid:82)(cid:83) (cid:78)(cid:79)(cid:84)(cid:0)(cid:8)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:0)(cid:79)(cid:82) (cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80) (cid:32)(cid:54)(cid:36)(cid:36)(cid:35)(cid:47)(cid:50)(cid:37) (cid:51)(cid:89)(cid:83)(cid:84)(cid:69)(cid:77)(cid:0) (cid:78)(cid:79)(cid:84)(cid:0)(cid:8)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:0)(cid:79)(cid:82) (cid:35)(cid:43)(cid:63)(cid:35)(cid:48)(cid:53) (cid:32)(cid:54)(cid:19)(cid:19) (cid:67)(cid:76)(cid:79)(cid:67)(cid:75) (cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:9) (cid:40)(cid:47)(cid:51)(cid:51)(cid:37)(cid:35) (cid:67)(cid:67)(cid:75)(cid:75)(cid:63)(cid:63)(cid:72)(cid:77)(cid:83)(cid:83)(cid:73)(cid:73) (cid:33)(cid:40)(cid:34) (cid:15)(cid:0)(cid:24) (cid:35)(cid:43)(cid:63)(cid:52)(cid:41)(cid:45)(cid:51)(cid:57)(cid:51) (cid:76)(cid:69)(cid:86)(cid:69)(cid:76)(cid:0)(cid:83)(cid:72)(cid:73)(cid:70)(cid:84)(cid:69)(cid:82)(cid:83) (cid:67)(cid:75)(cid:63)(cid:72)(cid:83)(cid:69) (cid:80)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:32)(cid:54)(cid:36)(cid:36)(cid:35)(cid:47)(cid:50)(cid:37) (cid:32)(cid:54)(cid:19)(cid:19) (cid:67)(cid:75)(cid:63)(cid:80)(cid:76)(cid:76) (cid:0)(cid:15)(cid:0)(cid:17)(cid:12)(cid:18)(cid:12)(cid:14)(cid:14)(cid:21)(cid:17)(cid:18) (cid:67)(cid:75)(cid:63)(cid:80)(cid:76)(cid:76)(cid:73)(cid:78)(cid:56)(cid:0)(cid:19)(cid:12)(cid:20)(cid:48)(cid:12)(cid:44)(cid:22)(cid:44)(cid:12)(cid:24)(cid:12)(cid:17)(cid:18) (cid:80)(cid:82)(cid:69)(cid:33)(cid:83)(cid:48)(cid:67)(cid:34)(cid:65)(cid:17)(cid:76)(cid:69)(cid:82) (cid:80)(cid:82)(cid:69)(cid:33)(cid:83)(cid:48)(cid:67)(cid:34)(cid:65)(cid:18)(cid:76)(cid:69)(cid:82) (cid:44)(cid:51) (cid:17)(cid:22)(cid:12)(cid:18)(cid:20)(cid:12)(cid:19)(cid:18)(cid:12)(cid:20)(cid:24) (cid:15)(cid:0)(cid:17)(cid:12)(cid:18)(cid:12)(cid:20)(cid:12)(cid:24)(cid:12)(cid:17)(cid:22) (cid:15)(cid:0)(cid:17)(cid:12)(cid:18)(cid:12)(cid:20)(cid:12)(cid:24)(cid:12)(cid:17)(cid:22) (cid:32)(cid:54)(cid:19)(cid:19) (cid:15)(cid:0)(cid:18)(cid:12)(cid:0)(cid:19)(cid:12)(cid:0)(cid:20) (cid:0)(cid:17)(cid:0)(cid:45)(cid:40)(cid:90)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75) (cid:68)(cid:69)(cid:84)(cid:69)(cid:67)(cid:84)(cid:79)(cid:82) (cid:76)(cid:69)(cid:86)(cid:69)(cid:76)(cid:0)(cid:83)(cid:72)(cid:73)(cid:70)(cid:84)(cid:69)(cid:82)(cid:83) (cid:35)(cid:76)(cid:79)(cid:67)(cid:75) (cid:40)(cid:51)(cid:37)(cid:0)(cid:80)(cid:82)(cid:69)(cid:83)(cid:69)(cid:78)(cid:84)(cid:0)(cid:79)(cid:82)(cid:0)(cid:78)(cid:79)(cid:84)(cid:32)(cid:54)(cid:36)(cid:36)(cid:35)(cid:47)(cid:50)(cid:37) (cid:83)(cid:79)(cid:85)(cid:82)(cid:67)(cid:69) (cid:44)(cid:51) (cid:67)(cid:79)(cid:78)(cid:84)(cid:82)(cid:79)(cid:76) (cid:85)(cid:83)(cid:66)(cid:69)(cid:78)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:8)(cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:9) (cid:35)(cid:43)(cid:63)(cid:53)(cid:51)(cid:34)(cid:20)(cid:24) (cid:67)(cid:75)(cid:63)(cid:85)(cid:83)(cid:66)(cid:0)(cid:29)(cid:0)(cid:54)(cid:67)(cid:79)(cid:0)(cid:15)(cid:0)(cid:18)(cid:0)(cid:8)(cid:54)(cid:67)(cid:79)(cid:0)(cid:77)(cid:85)(cid:83)(cid:84)(cid:0)(cid:66)(cid:69)(cid:0)(cid:65)(cid:84)(cid:90)(cid:0)(cid:25)(cid:9)(cid:22)(cid:0)(cid:45)(cid:40) (cid:84)(cid:73)(cid:77)(cid:69)(cid:82)(cid:25)(cid:69)(cid:78)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:8)(cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:9) (cid:35)(cid:43)(cid:63)(cid:52)(cid:41)(cid:45)(cid:52)(cid:39)(cid:47) (cid:73)(cid:70)(cid:0)(cid:8)(cid:33)(cid:48)(cid:34)(cid:17)(cid:0)(cid:80)(cid:82)(cid:69)(cid:83)(cid:67)(cid:0)(cid:29)(cid:0)(cid:17)(cid:9)(cid:88)(cid:17) (cid:69)(cid:76)(cid:83)(cid:69) (cid:88)(cid:18) (cid:65)(cid:80)(cid:66)(cid:17)(cid:0)(cid:80)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:78)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:8)(cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:9) (cid:35)(cid:43)(cid:63)(cid:33)(cid:48)(cid:34)(cid:17) (cid:65)(cid:80)(cid:66)(cid:18)(cid:0)(cid:80)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:78)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:8)(cid:78)(cid:79)(cid:84)(cid:0)(cid:68)(cid:69)(cid:69)(cid:80)(cid:83)(cid:76)(cid:69)(cid:69)(cid:80)(cid:9) (cid:35)(cid:43)(cid:63)(cid:33)(cid:48)(cid:34)(cid:18) (cid:45)(cid:51)(cid:17)(cid:24)(cid:21)(cid:24)(cid:19)(cid:54)(cid:17) DocID027267 Rev 4 21/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3.5 Low-power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 µs to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronization. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. 22/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview 3.7 Memories The STM32L151VD-X and STM32L152VD-X devices have the following features: • 80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). • The non-volatile memory is divided into three arrays: – 384 Kbytes of embedded Flash program memory – 16 Kbytes of data EEPROM – Options bytes Flash program and data EEPROM are divided into two banks, this enables writing in one bank while running code or reading data in the other bank. The options bytes are used to write-protect or read-out protect the memory (with 4 Kbytes granularity) and/or readout-protect the whole memory with the following options: – Level 0: no readout protection – Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected – Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 DMA (direct memory access) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC. DocID027267 Rev 4 23/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3.9 LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. • Internal step-up converter to guarantee functionality and contrast control irrespective of V . This converter can be deactivated, in which case the V pin is used to provide DD LCD the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • Phase inversion to reduce power consumption and EMI • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode 3.10 ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L151VD-X and STM32L152VD-X devices with up to 40 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 28 external channels in a group. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low-power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. 3.10.1 Temperature sensor The temperature sensor (TS) generates a voltage V that varies linearly with SENSE temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are 24/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview stored by ST in the system memory area, accessible in read-only mode. See Table 59: Temperature sensor calibration values. 3.10.2 Internal voltage reference (V ) REFINT The internal voltage reference (V ) provides a stable (bandgap) voltage output for the REFINT ADC and Comparators. V is internally connected to the ADC_IN17 input channel. It REFINT enables accurate monitoring of the V value (when no external voltage, VREF+, is DD available for ADC). The precise voltage of V is individually measured for each part by REFINT ST during production test and stored in the system memory area. It is accessible in read- only mode. See Table 14: Embedded internal reference voltage calibration values. 3.11 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: • Two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channels, independent or simultaneous conversions • DMA capability for each channel (including the underrun interrupt) • External triggers for conversion • Input reference voltage V REF+ Eight DAC trigger inputs are used in the STM32L151VD-X and STM32L152VD-X devices. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.12 Operational amplifier The STM32L151VD-X and STM32L152VD-X devices embed two operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. The operational amplifiers feature: • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input DocID027267 Rev 4 25/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3.13 Ultra-low-power comparators and reference voltage The STM32L151VD-X and STM32L152VD-X devices embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). • One comparator with fixed threshold • One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: – DAC output – External I/O – Internal reference voltage (V ) or a sub-multiple (1/4, 1/2, 3/4) REFINT Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 µA typical). 3.14 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage V . REFINT 3.15 Touch sensing The STM32L151VD-X and STM32L152VD-X devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 23 capacitive sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups (see Section 3.14: System configuration controller and routing interface). Reliable touch sensing functionality can be quickly and easily implemented using the free STM32L1xx STMTouch touch sensing firmware library. 26/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview 3.16 Timers and watchdogs The ultra-low-power STM32L151VD-X and STM32L152VD-X devices include seven general-purpose timers, two basic timers, and two watchdog timers. Table 5 compares the features of the general-purpose and basic timers. Table 5. Timer feature comparison DMA Counter Capture/compare Complementary Timer Counter type Prescaler factor request resolution channels outputs generation TIM2, Up, down, Any integer between TIM3, 16-bit Yes 4 No up/down 1 and 65536 TIM4 Up, down, Any integer between TIM5 32-bit Yes 4 No up/down 1 and 65536 Up, down, Any integer between TIM9 16-bit No 2 No up/down 1 and 65536 TIM10, Any integer between 16-bit Up No 1 No TIM11 1 and 65536 TIM6, Any integer between 16-bit Up Yes 0 No TIM7 1 and 65536 3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) There are seven synchronizable general-purpose timers embedded in the STM32L151VD-X and STM32L152VD-X devices (see Table 5 for differences). TIM2, TIM3, TIM4, TIM5 TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32- bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. DocID027267 Rev 4 27/119 49

Functional overview STM32L151VD-X STM32L152VD-X They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.16.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.16.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.16.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.16.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17 Communication interfaces 3.17.1 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) The three USART and two UART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals and are ISO 7816 compliant. All USART/UART interfaces can be served by the DMA controller. 28/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Functional overview 3.17.3 Serial peripheral interface (SPI) Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. 3.17.4 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The I2Ss can be served by the DMA controller. 3.17.5 Universal serial bus (USB) The STM32L151VD-X and STM32L152VD-X devices embed a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.18 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. DocID027267 Rev 4 29/119 49

Functional overview STM32L151VD-X STM32L152VD-X 3.19 Development support 3.19.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. 3.19.2 Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L151VD-X and STM32L152VD-X device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 30/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Pin descriptions 4 Pin descriptions Figure 3. STM32L152VD-X LQFP100 pinout (cid:36)(cid:36)(cid:63)(cid:19)(cid:0)(cid:0)(cid:51)(cid:51)(cid:63)(cid:19)(cid:0)(cid:0)(cid:37)(cid:17)(cid:0)(cid:0)(cid:37)(cid:16)(cid:0)(cid:0)(cid:34)(cid:25)(cid:0)(cid:0)(cid:34)(cid:24)(cid:0)(cid:0)(cid:47)(cid:47)(cid:52)(cid:16)(cid:0)(cid:0)(cid:34)(cid:23)(cid:0)(cid:0)(cid:34)(cid:22)(cid:0)(cid:0)(cid:34)(cid:21)(cid:0)(cid:0)(cid:34)(cid:20)(cid:0)(cid:0)(cid:34)(cid:19)(cid:0)(cid:0)(cid:36)(cid:23)(cid:0)(cid:0)(cid:36)(cid:22)(cid:0)(cid:0)(cid:36)(cid:21)(cid:0)(cid:0)(cid:36)(cid:20)(cid:0)(cid:0)(cid:36)(cid:19)(cid:0)(cid:0)(cid:36)(cid:18)(cid:0)(cid:0)(cid:36)(cid:17)(cid:0)(cid:0)(cid:36)(cid:16)(cid:0)(cid:0)(cid:35)(cid:17)(cid:18)(cid:0)(cid:0)(cid:35)(cid:17)(cid:17)(cid:0)(cid:0)(cid:35)(cid:17)(cid:16)(cid:0)(cid:0)(cid:33)(cid:17)(cid:21)(cid:0)(cid:0)(cid:33)(cid:17)(cid:20)(cid:0) (cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:34)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48) (cid:16) (cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22) (cid:17)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:23)(cid:23)(cid:23)(cid:23) (cid:48)(cid:37)(cid:18) (cid:17) (cid:23)(cid:21) (cid:54)(cid:36)(cid:36)(cid:63)(cid:18)(cid:0) (cid:48)(cid:37)(cid:19) (cid:18) (cid:23)(cid:20) (cid:54)(cid:51)(cid:51)(cid:63)(cid:18)(cid:0)(cid:0) (cid:48)(cid:37)(cid:20) (cid:19) (cid:23)(cid:19) (cid:48)(cid:40)(cid:18)(cid:0)(cid:0) (cid:48)(cid:37)(cid:21) (cid:20) (cid:23)(cid:18) (cid:48)(cid:33)(cid:17)(cid:19) (cid:0)(cid:0) (cid:48)(cid:37)(cid:22)(cid:13)(cid:55)(cid:43)(cid:53)(cid:48)(cid:19) (cid:21) (cid:23)(cid:17) (cid:48)(cid:33)(cid:17)(cid:18) (cid:54)(cid:44)(cid:35)(cid:36) (cid:22) (cid:23)(cid:16) (cid:48)(cid:33)(cid:17)(cid:17) (cid:48)(cid:35)(cid:17)(cid:19)(cid:13)(cid:55)(cid:43)(cid:53)(cid:48)(cid:18) (cid:23) (cid:22)(cid:25) (cid:48)(cid:33)(cid:17)(cid:16) (cid:48)(cid:35)(cid:17)(cid:20)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:41)(cid:46) (cid:24) (cid:22)(cid:24) (cid:48)(cid:33)(cid:25) (cid:48)(cid:35)(cid:17)(cid:21)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:47)(cid:53)(cid:52) (cid:25) (cid:22)(cid:23) (cid:48)(cid:33)(cid:24) (cid:54)(cid:51)(cid:51)(cid:63)(cid:21) (cid:17)(cid:16) (cid:22)(cid:22) (cid:48)(cid:35)(cid:25)(cid:0)(cid:0) (cid:54)(cid:36)(cid:36)(cid:63)(cid:21) (cid:17)(cid:17) (cid:22)(cid:21) (cid:48)(cid:35)(cid:24)(cid:0)(cid:0) (cid:48)(cid:40)(cid:16)(cid:13)(cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46) (cid:17)(cid:18) (cid:22)(cid:20) (cid:48)(cid:35)(cid:23)(cid:0)(cid:0) (cid:48)(cid:40)(cid:17)(cid:13)(cid:47)(cid:51)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52) (cid:17)(cid:19) (cid:44)(cid:49)(cid:38)(cid:48)(cid:17)(cid:16)(cid:16) (cid:22)(cid:19) (cid:48)(cid:35)(cid:22)(cid:0)(cid:0) (cid:46)(cid:50)(cid:51)(cid:52) (cid:17)(cid:20) (cid:22)(cid:18) (cid:48)(cid:36)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:35)(cid:16) (cid:17)(cid:21) (cid:22)(cid:17) (cid:48)(cid:36)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17) (cid:17)(cid:22) (cid:22)(cid:16) (cid:48)(cid:36)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:35)(cid:18) (cid:17)(cid:23) (cid:21)(cid:25) (cid:48)(cid:36)(cid:17)(cid:18)(cid:0)(cid:0) (cid:48)(cid:35)(cid:19) (cid:17)(cid:24) (cid:21)(cid:24) (cid:48)(cid:36)(cid:17)(cid:17)(cid:0)(cid:0) (cid:54)(cid:51)(cid:51)(cid:33) (cid:17)(cid:25) (cid:21)(cid:23) (cid:48)(cid:36)(cid:17)(cid:16)(cid:0)(cid:0) (cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:18)(cid:16) (cid:21)(cid:22) (cid:48)(cid:36)(cid:25)(cid:0)(cid:0) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:18)(cid:17) (cid:21)(cid:21) (cid:48)(cid:36)(cid:24)(cid:0)(cid:0) (cid:54)(cid:36)(cid:36)(cid:33) (cid:18)(cid:18) (cid:21)(cid:20) (cid:48)(cid:34)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:33)(cid:16)(cid:13)(cid:55)(cid:43)(cid:53)(cid:48)(cid:17) (cid:18)(cid:19) (cid:21)(cid:19) (cid:48)(cid:34)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:33)(cid:17) (cid:18)(cid:20) (cid:21)(cid:18) (cid:48)(cid:34)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:33)(cid:18) (cid:18)(cid:21) (cid:21)(cid:17) (cid:48)(cid:34)(cid:17)(cid:18)(cid:0)(cid:0) (cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16) (cid:18)(cid:18)(cid:18)(cid:18)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:21) (cid:19)(cid:20)(cid:20)(cid:20)(cid:21)(cid:22)(cid:23)(cid:20)(cid:21)(cid:16)(cid:17)(cid:18)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:16)(cid:17)(cid:17)(cid:17) (cid:33)(cid:63)(cid:63)(cid:33)(cid:33)(cid:33)(cid:33)(cid:35)(cid:35)(cid:34)(cid:34)(cid:34)(cid:37)(cid:37)(cid:37)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:63)(cid:63) (cid:48)(cid:51)(cid:36)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:34)(cid:34)(cid:51)(cid:36) (cid:51)(cid:36) (cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:51)(cid:36) (cid:54)(cid:54) (cid:54)(cid:54) (cid:65)(cid:73)(cid:17)(cid:21)(cid:22)(cid:25)(cid:18)(cid:67) 1. This figure shows the package top view. DocID027267 Rev 4 31/119 49

Pin descriptions STM32L151VD-X STM32L152VD-X Figure 4. STM32L151VD-X WLCSP104 ballout (cid:1005) (cid:1006) (cid:1007) (cid:1008) (cid:1009) (cid:1010) (cid:1011) (cid:1012) (cid:1013) (cid:4) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1006) (cid:87)(cid:24)(cid:1004) (cid:87)(cid:24)(cid:1008) (cid:87)(cid:24)(cid:1011) (cid:87)(cid:17)(cid:1008) (cid:87)(cid:17)(cid:1009) (cid:17)(cid:75)(cid:75)(cid:100)(cid:1004) (cid:87)(cid:28)(cid:1005) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1007) (cid:17) (cid:87)(cid:4)(cid:1005)(cid:1009) (cid:87)(cid:18)(cid:1005)(cid:1006) (cid:87)(cid:24)(cid:1009) (cid:87)(cid:24)(cid:1010) (cid:87)(cid:17)(cid:1007) (cid:87)(cid:17)(cid:1011) (cid:87)(cid:28)(cid:1004) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1007) (cid:87)(cid:28)(cid:1009) (cid:87)(cid:18)(cid:1005)(cid:1007)(cid:3) (cid:18) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1006) (cid:87)(cid:18)(cid:1005)(cid:1005) (cid:87)(cid:24)(cid:1006) (cid:87)(cid:24)(cid:1007) (cid:87)(cid:17)(cid:1010) (cid:87)(cid:17)(cid:1013) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1007) (cid:87)(cid:28)(cid:1008) (cid:116)(cid:60)(cid:104)(cid:87)(cid:1006) (cid:24) (cid:87)(cid:44)(cid:1006) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1006) (cid:87)(cid:4)(cid:1005)(cid:1008) (cid:87)(cid:24)(cid:1005) (cid:87)(cid:17)(cid:1012) (cid:87)(cid:28)(cid:1006) (cid:87)(cid:28)(cid:1007) (cid:87)(cid:75)(cid:18)(cid:94)(cid:1005)(cid:18)(cid:1008)(cid:1007)(cid:1006)(cid:47)(cid:69) (cid:87)(cid:75)(cid:18)(cid:94)(cid:1005)(cid:18)(cid:1009)(cid:1007)(cid:1006)(cid:75)(cid:104)(cid:100) (cid:28) (cid:87)(cid:4)(cid:1005)(cid:1005) (cid:87)(cid:4)(cid:1005)(cid:1006) (cid:87)(cid:4)(cid:1005)(cid:1007) (cid:87)(cid:18)(cid:1005)(cid:1004) (cid:87)(cid:116)(cid:28)(cid:60)(cid:1010)(cid:104)(cid:87)(cid:1007) (cid:115)(cid:62)(cid:18)(cid:24) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1009) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1009) (cid:87)(cid:44)(cid:1004) (cid:87)(cid:44)(cid:1005) (cid:38) (cid:87)(cid:4)(cid:1013) (cid:87)(cid:4)(cid:1005)(cid:1004) (cid:87)(cid:4)(cid:1012) (cid:87)(cid:18)(cid:1013) (cid:87)(cid:18)(cid:1004) (cid:69)(cid:90)(cid:94)(cid:100) (cid:75)(cid:94)(cid:18)(cid:47)(cid:69) (cid:75)(cid:94)(cid:18)(cid:75)(cid:104)(cid:100) (cid:39) (cid:87)(cid:18)(cid:1011) (cid:87)(cid:18)(cid:1012) (cid:87)(cid:24)(cid:1005)(cid:1009) (cid:87)(cid:24)(cid:1005)(cid:1005) (cid:115)(cid:24)(cid:24)(cid:4) (cid:115)(cid:90)(cid:28)(cid:38)(cid:1085) (cid:87)(cid:18)(cid:1007) (cid:87)(cid:18)(cid:1006) (cid:44) (cid:87)(cid:18)(cid:1010) (cid:87)(cid:24)(cid:1005)(cid:1007) (cid:87)(cid:24)(cid:1005)(cid:1006) (cid:87)(cid:24)(cid:1012) (cid:87)(cid:4)(cid:1010) (cid:87)(cid:4)(cid:1007) (cid:115)(cid:90)(cid:28)(cid:38)(cid:882) (cid:87)(cid:18)(cid:1005) (cid:58) (cid:87)(cid:24)(cid:1005)(cid:1008) (cid:87)(cid:24)(cid:1013) (cid:87)(cid:17)(cid:1005)(cid:1007) (cid:87)(cid:17)(cid:1005)(cid:1006) (cid:87)(cid:28)(cid:1005)(cid:1004) (cid:87)(cid:17)(cid:1004) (cid:87)(cid:4)(cid:1008) (cid:87)(cid:4)(cid:1006) (cid:115)(cid:94)(cid:94)(cid:4) (cid:60) (cid:87)(cid:24)(cid:1005)(cid:1004) (cid:87)(cid:17)(cid:1005)(cid:1009) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1005) (cid:87)(cid:28)(cid:1005)(cid:1009) (cid:87)(cid:28)(cid:1005)(cid:1007) (cid:87)(cid:17)(cid:1005) (cid:87)(cid:4)(cid:1011) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1008) (cid:87)(cid:4)(cid:1004) (cid:116)(cid:60)(cid:104)(cid:87)(cid:1005) (cid:62) (cid:87)(cid:17)(cid:1005)(cid:1008) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1005) (cid:87)(cid:17)(cid:1005)(cid:1005) (cid:87)(cid:28)(cid:1005)(cid:1008) (cid:87)(cid:28)(cid:1005)(cid:1005) (cid:87)(cid:28)(cid:1011) (cid:87)(cid:18)(cid:1008) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1008) (cid:87)(cid:4)(cid:1005) (cid:68) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1005) (cid:87)(cid:17)(cid:1005)(cid:1004) (cid:87)(cid:28)(cid:1005)(cid:1006) (cid:87)(cid:28)(cid:1013) (cid:87)(cid:28)(cid:1012) (cid:87)(cid:17)(cid:1006) (cid:87)(cid:18)(cid:1009) (cid:87)(cid:4)(cid:1009) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1008) (cid:48)(cid:54)(cid:89)(cid:23)(cid:20)(cid:19)(cid:19)(cid:28)(cid:57)(cid:20) 1. This figure shows the package top view. 32/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Pin descriptions Table 6. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function Pin name during and after reset is the same as the actual pin name S Supply pin Pin type I Input only pin I/O Input / output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O I/O structure B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during Notes and after reset Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions Table 7. STM32L151VD-X and STM32L152VD-X pin definitions Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl TIM3_ETR/LCD_SEG38/ 1 D6 PE2 I/O FT PE2 - TRACECLK TIM3_CH1/LCD_SEG39/ 2 D7 PE3 I/O FT PE3 - TRACED0 3 C8 PE4 I/O FT PE4 TIM3_CH2/TRACED1 - 4 B9 PE5 I/O FT PE5 TIM9_CH1/TRACED2 - PE6- WKUP3/ 5 E6 I/O FT PE6 TIM9_CH2/TRACED3 WKUP3 RTC_TAMP3 6 E7 V (3) S - V - - LCD LCD WKUP2/RTC_TA 7 C9 PC13-WKUP2 I/O FT PC13 - MP1/RTC_TS/ RTC_OUT DocID027267 Rev 4 33/119 49

Pin descriptions STM32L151VD-X STM32L152VD-X Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl PC14- 8 D8 I/O TC PC14 - OSC32_IN OSC32_IN(4) PC15- 9 D9 I/O TC PC15 - OSC32_OUT OSC32_OUT 10 E8 V S V - - SS_5 SS_5 11 E9 V S V - - DD_5 DD_5 12 F8 PH0-OSC_IN(5) I/O TC PH0 - OSC_IN PH1- 13 F9 I/O TC PH1 - OSC_OUT OSC_OUT(5) 14 F7 NRST I/O RST NRST - - ADC_IN10/ 15 F6 PC0 I/O FT PC0 LCD_SEG18 COMP1_INP ADC_IN11/ 16 H9 PC1 I/O FT PC1 LCD_SEG19 COMP1_INP ADC_IN12/ 17 G9 PC2 I/O FT PC2 LCD_SEG20 COMP1_INP ADC_IN13/ 18 G8 PC3 I/O TC PC3 LCD_SEG21 COMP1_INP 19 J9 V S - V - - SSA SSA 20 H8 V S - V - - REF- REF- 21 G7 V S - V - - REF+ REF+ 22 G6 V S - V - - DDA DDA TIM2_CH1_ETR/ WKUP1/RTC_TA 23 K9 PA0-WKUP1 I/O FT PA0 TIM5_CH1/ MP2/ADC_IN0/ USART2_CTS COMP1_INP TIM2_CH2/TIM5_CH2/ ADC_IN1/ 24 L9 PA1 I/O FT PA1 USART2_RTS/ COMP1_INP/ LCD_SEG0 OPAMP1_VINP TIM2_CH3/TIM5_CH3/ ADC_IN2/ 25 J8 PA2 I/O FT PA2 TIM9_CH1/ COMP1_INP/ USART2_TX/LCD_SEG1 OPAMP1_VINM 34/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Pin descriptions Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl TIM2_CH4/TIM5_CH4/ ADC_IN3/ 26 H7 PA3 I/O TC PA3 TIM9_CH2/ COMP1_INP/ USART2_RX/LCD_SEG2 OPAMP1_VOUT 27 K8 V S - V - - SS_4 SS_4 L8, 28 V S - V - - M9 DD_4 DD_4 SPI1_NSS/SPI3_NSS/ ADC_IN4/ 29 J7 PA4 I/O TC PA4 I2S3_WS/ DAC_OUT1/ USART2_CK COMP1_INP ADC_IN5/ TIM2_CH1_ETR/ 30 M8 PA5 I/O TC PA5 DAC_OUT2/ SPI1_SCK COMP1_INP TIM3_CH1/TIM10_CH1/S ADC_IN6/ 31 H6 PA6 I/O FT PA6 PI1_MISO/ COMP1_INP/ LCD_SEG3 OPAMP2_VINP TIM3_CH2/TIM11_CH1/ ADC_IN7/ 32 K7 PA7 I/O FT PA7 SPI1_MOSI/ COMP1_INP/ LCD_SEG4 OPAMP2_VINM ADC_IN14/ 33 L7 PC4 I/O FT PC4 LCD_SEG22 COMP1_INP ADC_IN15/ 34 M7 PC5 I/O FT PC5 LCD_SEG23 COMP1_INP ADC_IN8/ COMP1_INP/ 35 J6 PB0 I/O TC PB0 TIM3_CH3/LCD_SEG5 OPAMP2_VOUT/ VREF_OUT ADC_IN9/ 36 K6 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6 COMP1_INP/ VREF_OUT PB2/ 37 M6 PB2 I/O FT BOOT1 ADC_IN0b BOOT1 ADC_IN22/ 38 L6 PE7 I/O TC PE7 - COMP1_INP ADC_IN23/ 39 M5 PE8 I/O TC PE8 - COMP1_INP DocID027267 Rev 4 35/119 49

Pin descriptions STM32L151VD-X STM32L152VD-X Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl ADC_IN24/ 40 M4 PE9 I/O TC PE9 TIM2_CH1_ETR COMP1_INP ADC_IN25/ 41 J5 PE10 I/O TC PE10 TIM2_CH2 COMP1_INP 42 L5 PE11 I/O FT PE11 TIM2_CH3 - 43 M3 PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS - 44 K5 PE13 I/O FT PE13 SPI1_SCK - 45 L4 PE14 I/O FT PE14 SPI1_MISO - 46 K4 PE15 I/O FT PE15 SPI1_MOSI - TIM2_CH3/I2C2_SCL/ 47 M2 PB10 I/O FT PB10 USART3_TX/ - LCD_SEG10 TIM2_CH4/I2C2_SDA/ 48 L3 PB11 I/O FT PB11 USART3_RX/ - LCD_SEG11 L2, 49 V S - V - - M1 SS_1 SS_1 50 K3 V S - V - - DD_1 DD_1 TIM10_CH1/I2C2_SMBA/ SPI2_NSS/I2S2_WS/ ADC_IN18/ 51 J4 PB12 I/O FT PB12 USART3_CK/ COMP1_INP LCD_SEG12 TIM9_CH1/SPI2_SCK/ I2S2_CK/ ADC_IN19/ 52 J3 PB13 I/O FT PB13 USART3_CTS/ COMP1_INP LCD_SEG13 TIM9_CH2/SPI2_MISO/ ADC_IN20/ 53 L1 PB14 I/O FT PB14 USART3_RTS/ COMP1_INP LCD_SEG14 TIM11_CH1/SPI2_MOSI/ ADC_IN21/ 54 K2 PB15 I/O FT PB15 I2S2_SD/ COMP1_INP/ LCD_SEG15 RTC_REFIN USART3_TX/ 55 H4 PD8 I/O FT PD8 - LCD_SEG28 36/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Pin descriptions Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl USART3_RX/ 56 J2 PD9 I/O FT PD9 - LCD_SEG29 USART3_CK/ 57 K1 PD10 I/O FT PD10 - LCD_SEG30 USART3_CTS/ 58 G4 PD11 I/O FT PD11 - LCD_SEG31 TIM4_CH1/ 59 H3 PD12 I/O FT PD12 USART3_RTS/ - LCD_SEG32 60 H2 PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33 - 61 J1 PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34 - 62 G3 PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35 - TIM3_CH1/I2S2_MCK/ 63 H1 PC6 I/O FT PC6 - LCD_SEG24 TIM3_CH2/I2S3_MCK/ 64 G1 PC7 I/O FT PC7 - LCD_SEG25 65 G2 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 - 66 F4 PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 - USART1_CK/MCO/ 67 F3 PA8 I/O FT PA8 - LCD_COM0 USART1_TX / 68 F1 PA9 I/O FT PA9 - LCD_COM1 USART1_RX / 69 F2 PA10 I/O FT PA10 - LCD_COM2 USART1_CTS/ 70 E1 PA11 I/O FT PA11 USB_DM SPI1_MISO USART1_RTS/ 71 E2 PA12 I/O FT PA12 USB_DP SPI1_MOSI JTMS- 72 E3 PA13 I/O FT JTMS-SWDIO - SWDIO 73 D1 PH2 I/O FT PH2 - - D2, 74 V S - V - - A1 SS_2 SS_2 DocID027267 Rev 4 37/119 49

Pin descriptions STM32L151VD-X STM32L152VD-X Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl 75 C1 V S - V - - DD_2 DD_2 JTCK- 76 D3 PA14 I/O FT JTCK-SWCLK - SWCLK TIM2_CH1_ETR/ SPI1_NSS/SPI3_NSS/ 77 B1 PA15 I/O FT JTDI - I2S3_WS/LCD_SEG17/ JTDI SPI3_SCK/I2S3_CK/ USART3_TX/ UART4_TX/ 78 E4 PC10 I/O FT PC10 - LCD_SEG28/ LCD_SEG40/LCD_COM4 SPI3_MISO/USART3_RX/ UART4_RX/ 79 C2 PC11 I/O FT PC11 - LCD_SEG29/ LCD_SEG41/LCD_COM5 SPI3_MOSI/I2S3_SD/ USART3_CK/ 80 B2 PC12 I/O FT PC12 UART5_TX/LCD_SEG30/ - LCD_SEG42/ LCD_COM6 TIM9_CH1/SPI2_NSS/ 81 A2 PD0 I/O FT PD0 - I2S2_WS 82 D4 PD1 I/O FT PD1 SPI2_SCK/I2S2_CK - TIM3_ETR/UART5_RX/ 83 C3 PD2 I/O FT PD2 LCD_SEG31/ LCD_SEG43/LCD_COM7 SPI2_MISO/ 84 C4 PD3 I/O FT PD3 USART2_CTS SPI2_MOSI/I2S2_SD/ 85 A3 PD4 I/O FT PD4 USART2_RTS 86 B3 PD5 I/O FT PD5 USART2_TX 87 B4 PD6 I/O FT PD6 USART2_RX 88 A4 PD7 I/O FT PD7 TIM9_CH2/USART2_CK TIM2_CH2/SPI1_SCK/ 89 B5 PB3 I/O FT JTDO SPI3_SCK/ I2S3_CK/ COMP2_INM LCD_SEG7/JTDO 38/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Pin descriptions Table 7. STM32L151VD-X and STM32L152VD-X pin definitions (continued) Pins Pin functions e 1) ur Main LQFP100 WLCSP104 Pin name (Pin Type I / O struct funr(eacsfttieoetrn) (2) Alternate functions Afudndcittiioonnasl TIM3_CH1/SPI1_MISO/ 90 A5 PB4 I/O FT NJTRST SPI3_MISO/ COMP2_INP LCD_SEG8/NJTRST TIM3_CH2/I2C1_SMBA/ SPI1_MOSI/ 91 A6 PB5 I/O FT PB5 COMP2_INP SPI3_MOSI/I2S3_SD/ LCD_SEG9 TIM4_CH1/I2C1_SCL/ COMP2_INP 92 C5 PB6 I/O FT PB6 USART1_TX TIM4_CH2/I2C1_SDA/ COMP2_INP/ 93 B6 PB7 I/O FT PB7 USART1_RX PVD_IN 94 A7 BOOT0 I B BOOT0 - - TIM4_CH3/TIM10_CH1/ 95 D5 PB8 I/O FT PB8 I2C1_SCL/ - LCD_SEG16 TIM4_CH4/ 96 C6 PB9 I/O FT PB9 TIM11_CH1/I2C1_SDA/ - LCD_COM3 TIM4_ETR/TIM10_CH1/ 97 B7 PE0 I/O FT PE0 - LCD_SEG36 98 A8 PE1 I/O FT PE1 TIM11_CH1/LCD_SEG37 - 99 C7 V S - V - - SS_3 SS_3 B8, 100 V S - V - - A9 DD_3 DD_3 1. I = input, O = output, S = supply. 2. Function availability depends on the chosen device. 3. Applicable to STM32L152xD-X devices only. In STM32L151xD-X devices, this pin should be connected to V . DD 4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038). 5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off). The HSE has priority over the GPIO function. DocID027267 Rev 4 39/119 49

4 Alternate functions P 0/1 in 1 d 9 e s Table 8. Alternate function input/output c r ip Digital alternate function number t io n . . s AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 AFIO11 AFIO14 AFIO15 . . Port name Alternate function TIM3/4/ TIM9/ USART1/2/ UART4/ SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM 5 10/11 3 5 EVENT BOOT0 BOOT0 - - - - - - - - - - - - OUT NRST NRST - - - - - - - - - - - - - D o PA0-WKUP1 - TIM2_CH1_ TIM5_CH1 - - - - USART2_CTS - - - - TIMx_IC1 EVENT c ETR OUT ID 02 PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS - - SEG0 - TIMx_IC2 EVENT 7 OUT 2 6 7 EVENT R PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX - - SEG1 - TIMx_IC3 OUT e v 4 PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - SEG2 - TIMx_IC4 EVENT OUT SPI3_NSS EVENT PA4 - - - - - SPI1_NSS USART2_CK - - - - TIMx_IC1 I2S3_WS OUT S TIM2_CH1_ EVENT T PA5 - - - - SPI1_SCK - - - - - - TIMx_IC2 M ETR OUT 3 2 EVENT L PA6 - - TIM3_CH1 TIM10_CH1 - SPI1_MISO - - - - SEG3 - TIMx_IC3 OUT 1 5 1 EVENT V PA7 - - TIM3_CH2 TIM11_CH1 - SPI1_MOSI - - - - SEG4 - TIMx_IC4 OUT D - X PA8 MCO - - - - - - USART1_CK - - COM0 - TIMx_IC1 EVENT S OUT T M PA9 - - - - - - - USART1_TX - - COM1 - TIMx_IC2 EVENT 3 OUT 2 L 1 PA10 - - - - - - - USART1_RX - - COM2 - TIMx_IC3 EVENT 5 OUT 2 V D - X

Table 8. Alternate function input/output (continued) S T M Digital alternate function number 3 2 L . . 1 AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 AFIO11 AFIO14 AFIO15 5 . . 1 V Port name D Alternate function -X S TIM3/4/ TIM9/ USART1/2/ UART4/ T SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM M 5 10/11 3 5 3 2 L EVENT 1 PA11 - - - - - SPI1_MISO - USART1_CTS - - - - TIMx_IC4 5 OUT 2 V EVENT D PA12 - - - - - SPI1_MOSI - USART1_RTS - - - - TIMx_IC1 OUT -X JTMS- EVENT PA13 - - - - - - - - - - - TIMx_IC2 SWDIO OUT D JTCK- EVEN o PA14 SWCLK - - - - - - - - - - - TIMx_IC3 TOUT c ID 02 PA15 JTDI TEITMR2 _CH1_ - - - SPI1_NSS SI2PSI33__WNSSS - - - SEG17 - TIMx_IC4 ETOVEUNT 7 2 6 EVEN 7 PB0 - - TIM3_CH3 - - - - - - - SEG5 - - R TOUT e v EVENT 4 PB1 - - TIM3_CH4 - - - - - - - SEG6 - - OUT EVENT PB2 BOOT1 - - - - - - - - - - - - OUT SPI3_SCK EVENT PB3 JTDO TIM2_CH2 - - - SPI1_SCK - - - SEG7 - - I2S3_CK OUT EVENT PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO - - - SEG8 - - OUT I2C1_ SPI3_MOSI EVENT PB5 - - TIM3_CH2 - SPI1_MOSI - - - SEG9 - - SMBA I2S3_SD OUT EVENT PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - - - - OUT P in PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - - EVENT d OUT e s EVENT c PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - - SEG16 - - r OUT ip 41/11 tion 9 s

4 Table 8. Alternate function input/output (continued) P 2/1 in 1 Digital alternate function number d 9 e s . . c AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 . AFIO11 . AFIO14 AFIO15 rip t Port name io n Alternate function s TIM3/4/ TIM9/ USART1/2/ UART4/ SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM 5 10/11 3 5 EVENT PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - - - COM3 - - OUT EVENT PB10 - TIM2_CH3 - - I2C2_SCL - - USART3_TX - - SEG10 - - OUT EVENT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - SEG11 - - OUT D I2C2_SM SPI2_NSS EVENT o PB12 - - - TIM10_CH1 BA I2S2_WS - USART3_CK - - SEG12 - - OUT c ID 02 PB13 - - - TIM9_CH1 - SI2PSI22__CSKCK - USART3_CTS - - SEG13 - - EOVUETNT 7 2 6 EVENT 7 PB14 - - - TIM9_CH2 - SPI2_MISO - USART3_RTS - - SEG14 - - R OUT e v SPI2_MOSI EVENT 4 PB15 - - - TIM11_CH1 - I2S2_SD - - - - SEG15 - - OUT EVENT PC0 - - - - - - - - - - SEG18 - TIMx_IC1 OUT S PC1 - - - - - - - - - - SEG19 - TIMx_IC2 EVENT T OUT M 3 EVENT 2 PC2 - - - - - - - - - - SEG20 - TIMx_IC3 L OUT 1 5 EVENT 1 PC3 - - - - - - - - - - SEG21 - TIMx_IC4 V OUT D - EVENT X PC4 - - - - - - - - - - SEG22 - TIMx_IC1 OUT S T EVENT M PC5 - - - - - - - - - - SEG23 - TIMx_IC2 OUT 3 2 L EVENT 1 PC6 - - TIM3_CH1 - - I2S2_MCK - - - - SEG24 - TIMx_IC3 OUT 5 2 V D - X

Table 8. Alternate function input/output (continued) S T M Digital alternate function number 3 2 L . . 1 AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 AFIO11 AFIO14 AFIO15 5 . . 1 V Port name D Alternate function -X S TIM3/4/ TIM9/ USART1/2/ UART4/ T SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM M 5 10/11 3 5 3 2 L EVENT 1 PC7 - - TIM3_CH2 - - - I2S3_MCK - - - SEG25 - TIMx_IC4 5 OUT 2 V EVENT D PC8 - - TIM3_CH3 - - - - - - - SEG26 - TIMx_IC1 OUT -X EVENT PC9 - - TIM3_CH4 - - - - - - - SEG27 - TIMx_IC2 OUT Do PC10 - - - - - - SPI3_SCK USART3_TX UART4_TX - CSEOGM248/ / - TIMx_IC3 EVENT c I2S3_CK OUT ID SEG40 0 2 COM5/ 7 EVENT 2 PC11 - - - - - - SPI3_MISO USART3_RX UART4_RX - SEG29 - TIMx_IC4 67 /SEG41 OUT R ev PC12 - - - - - - SPI3_MOSI USART3_CK UART5_TX - CSEOGM360/ / - TIMx_IC1 EVENT 4 I2S3_SD SEG42 OUT EVENT PC13-WKUP2 - - - - - - - - - - - - TIMx_IC2 OUT PC14 EVENT - - - - - - - - - - - - TIMx_IC3 OSC32_IN OUT PC15 EVENT - - - - - - - - - - - - TIMx_IC4 OSC32_OUT OUT SPI2_NSS EVENT PD0 - - - TIM9_CH1 - - - - - - - TIMx_IC1 I2S2_WS OUT SPI2 SCK EVENT PD1 - - - - - - - - - - - TIMx_IC2 I2S2_CK OUT P in COM7/ EVENT d PD2 - - TIM3_ETR - - - - - UART5_RX - SSEEGG3413/ - TIMx_IC3 OUT es c r 43/11 PD3 - - - - - SPI2_MISO - USART2_CTS - - - - TIMx_IC4 EOVUETNT iption 9 s

4 Table 8. Alternate function input/output (continued) P 4/1 in 1 Digital alternate function number d 9 e s . . c AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 . AFIO11 . AFIO14 AFIO15 rip t Port name io n Alternate function s TIM3/4/ TIM9/ USART1/2/ UART4/ SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM 5 10/11 3 5 SPI2_MOSI EVENT PD4 - - - - - - USART2_RTS - - - - TIMx_IC1 I2S2_SD OUT EVENT PD5 - - - - - - - USART2_TX - - - - TIMx_IC2 OUT EVENT PD6 - - - - - - - USART2_RX - - - - TIMx_IC3 OUT D EVENT o PD7 - - - TIM9_CH2 - - - USART2_CK - - - - TIMx_IC4 OUT c ID 02 PD8 - - - - - - - USART3_TX - - SEG28 - TIMx_IC1 EOVUETNT 7 2 6 EVENT 7 PD9 - - - - - - - USART3_RX - - SEG29 - TIMx_IC2 R OUT e v EVENT 4 PD10 - - - - - - - USART3_CK - - SEG30 - TIMx_IC3 OUT EVENT PD11 - - - - - - - USART3_CTS - - SEG31 - TIMx_IC4 OUT S PD12 - - TIM4_CH1 - - - - USART3_RTS - - SEG32 - TIMx_IC1 EVENT T OUT M 3 EVENT 2 PD13 - - TIM4_CH2 - - - - - - - SEG33 - TIMx_IC2 L OUT 1 5 EVENT 1 PD14 - - TIM4_CH3 - - - - - - - SEG34 - TIMx_IC3 V OUT D - EVENT X PD15 - - TIM4_CH4 - - - - - - - SEG35 - TIMx_IC4 OUT S T EVENT M PE0 - - TIM4_ETR TIM10_CH1 - - - - - - SEG36 - TIMx_IC1 OUT 3 2 L EVENT 1 PE1 - - - TIM11_CH1 - - - - - - SEG37 - TIMx_IC2 OUT 5 2 V D - X

Table 8. Alternate function input/output (continued) S T M Digital alternate function number 3 2 L . . 1 AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 AFIO11 AFIO14 AFIO15 5 . . 1 V Port name D Alternate function -X S TIM3/4/ TIM9/ USART1/2/ UART4/ T SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM M 5 10/11 3 5 3 2 L EVENT 1 PE2 TRACECK - TIM3_ETR - - - - - - - SEG 38 - TIMx_IC3 5 OUT 2 V EVENT D PE3 TRACED0 - TIM3_CH1 - - - - - - - SEG 39 - TIMx_IC4 OUT -X EVENT PE4 TRACED1 - TIM3_CH2 - - - - - - - - - TIMx_IC1 OUT D EVENT o PE5 TRACED2 - - TIM9_CH1 - - - - - - - - TIMx_IC2 OUT c ID 02 PWEK6U- P3 TRACED3 - - TIM9_CH2 - - - - - - - - TIMx_IC3 EOVUETNT 7 2 6 EVENT 7 PE7 - - - - - - - - - - - - TIMx_IC4 R OUT e v EVENT 4 PE8 - - - - - - - - - - - - TIMx_IC1 OUT TIM2_CH1_ EVENT PE9 - - - - - - - - - - - TIMx_IC2 ETR OUT EVENT PE10 - TIM2_CH2 - - - - - - - - - - TIMx_IC3 OUT EVENT PE11 - TIM2_CH3 - - - - - - - - - - TIMx_IC4 OUT EVENT PE12 - TIM2_CH4 - - - SPI1_NSS - - - - - - TIMx_IC1 OUT EVENT PE13 - - - - - SPI1_SCK - - - - - - TIMx_IC2 OUT P in PE14 - - - - - SPI1_MISO - - - - - - TIMx_IC3 EVENT d OUT e s EVENT c PE15 - - - - - SPI1_MOSI - - - - - - TIMx_IC4 r OUT ip 45/11 tion 9 s

4 Table 8. Alternate function input/output (continued) P 6/1 in 1 Digital alternate function number d 9 e s . . c AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 . AFIO11 . AFIO14 AFIO15 rip t Port name io n Alternate function s TIM3/4/ TIM9/ USART1/2/ UART4/ SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM 5 10/11 3 5 EVENT PF0 - - - - - - - - - - - - - OUT EVENT PF1 - - - - - - - - - - - - - OUT EVENT PF2 - - - - - - - - - - - - - OUT D EVENT o PF3 - - - - - - - - - - - - - OUT c ID 02 PF4 - - - - - - - - - - - - - EOVUETNT 7 2 6 EVENT 7 PF5 - - - - - - - - - - - - - R OUT e v EVENT 4 PF6 - - TIM5_ETR - - - - - - - - - - OUT EVENT PF7 - - TIM5_CH2 - - - - - - - - - - OUT S PF8 - - TIM5_CH3 - - - - - - - - - - EVENT T OUT M 3 EVENT 2 PF9 - - TIM5_CH4 - - - - - - - - - - L OUT 1 5 EVENT 1 PF10 - - - - - - - - - - - - - V OUT D - EVENT X PF11 - - - - - - - - - - - - - OUT S T EVENT M PF12 - - - - - - - - - - - - - OUT 3 2 L EVENT 1 PF13 - - - - - - - - - - - - - OUT 5 2 V D - X

Table 8. Alternate function input/output (continued) S T M Digital alternate function number 3 2 L . . 1 AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 AFIO11 AFIO14 AFIO15 5 . . 1 V Port name D Alternate function -X S TIM3/4/ TIM9/ USART1/2/ UART4/ T SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM M 5 10/11 3 5 3 2 L EVENT 1 PF14 - - - - - - - - - - - - - 5 OUT 2 V EVENT D PF15 - - - - - - - - - - - - - OUT -X EVENT PG0 - - - - - - - - - - - - - OUT D EVENT o PG1 - - - - - - - - - - - - - OUT c ID 02 PG2 - - - - - - - - - - - - - EOVUETNT 7 2 6 EVENT 7 PG3 - - - - - - - - - - - - - R OUT e v EVENT 4 PG4 - - - - - - - - - - - - - OUT EVENT PG5 - - - - - - - - - - - - - OUT EVENT PG6 - - - - - - - - - - - - - OUT EVENT PG7 - - - - - - - - - - - - - OUT EVENT PG8 - - - - - - - - - - - - - OUT EVENT PG9 - - - - - - - - - - - - - OUT P in PG10 - - - - - - - - - - - - - EVENT d OUT e s EVENT c PG11 - - - - - - - - - - - - - r OUT ip 47/11 tion 9 s

4 Table 8. Alternate function input/output (continued) P 8/1 in 1 Digital alternate function number d 9 e s . . c AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8 . AFIO11 . AFIO14 AFIO15 rip t Port name io n Alternate function s TIM3/4/ TIM9/ USART1/2/ UART4/ SYSTEM TIM2 I2C1/2 SPI1/2 SPI3 - LCD - CPRI SYSTEM 5 10/11 3 5 EVENT PG12 - - - - - - - - - - - - - OUT EVENT PG13 - - - - - - - - - - - - - OUT EVENT PG14 - - - - - - - - - - - - - OUT D EVENT o PG15 - - - - - - - - - - - - - OUT c ID 0 PH0OSC_IN - - - - - - - - - - - - - - 2 7 2 PH1OSC_OUT - - - - - - - - - - - - - - 6 7 R PH2 - - - - - - - - - - - - - - e v 4 S T M 3 2 L 1 5 1 V D - X S T M 3 2 L 1 5 2 V D - X

STM32L151VD-X STM32L152VD-X Memory mapping 5 Memory mapping Figure 5. Memory map (cid:36)(cid:51)(cid:37)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:86)(cid:83)(cid:68)(cid:70)(cid:72) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:25)(cid:26)(cid:41)(cid:41) (cid:36)(cid:45)(cid:33)(cid:18) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:25)(cid:23)(cid:19)(cid:19) (cid:36)(cid:45)(cid:33)(cid:17) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:25)(cid:19)(cid:19)(cid:19) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:23)(cid:19)(cid:19)(cid:19) (cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:0)(cid:41)(cid:78)(cid:84)(cid:69)(cid:82)(cid:70)(cid:65)(cid:67)(cid:69) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:22)(cid:38)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:22)(cid:27)(cid:19)(cid:19) (cid:50)(cid:35)(cid:35) (cid:19)(cid:91)(cid:41)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:22)(cid:23)(cid:19)(cid:19) (cid:38)(cid:53)(cid:38) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:22)(cid:19)(cid:19)(cid:19) (cid:26) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:21)(cid:19)(cid:19)(cid:19) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:40)(cid:19)(cid:20)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:16)(cid:88)(cid:20)(cid:16)(cid:16)(cid:18)(cid:0)(cid:0)(cid:17)(cid:35)(cid:16)(cid:16) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:39) (cid:19)(cid:91)(cid:40)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:38)(cid:82)(cid:85)(cid:87)(cid:51)(cid:72)(cid:72)(cid:91)(cid:85)(cid:16)(cid:76)(cid:48)(cid:83)(cid:75)(cid:22)(cid:72)(cid:3)(cid:44)(cid:85)(cid:81)(cid:68)(cid:87)(cid:79)(cid:72)(cid:86)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:20)(cid:27)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:38) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:20)(cid:23)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:40) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:20)(cid:19)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:37) (cid:25) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:38)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:36) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:27)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:35) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:23)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:34) (cid:19)(cid:91)(cid:38)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:48)(cid:79)(cid:82)(cid:84)(cid:0)(cid:33) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:22)(cid:38)(cid:19)(cid:19) (cid:53)(cid:51)(cid:33)(cid:50)(cid:52)(cid:17) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:22)(cid:27)(cid:19)(cid:19) (cid:24) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:22)(cid:23)(cid:19)(cid:19) (cid:51)(cid:48)(cid:41)(cid:17) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:22)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:36)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:21)(cid:38)(cid:19)(cid:19) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:21)(cid:27)(cid:19)(cid:19) (cid:33)(cid:36)(cid:35) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:21)(cid:23)(cid:19)(cid:19) (cid:23) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:20)(cid:23)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:17)(cid:17) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:20)(cid:23)(cid:19)(cid:19) (cid:19)(cid:91)(cid:27)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:19)(cid:91)(cid:91)(cid:20)(cid:20)(cid:41)(cid:41)(cid:41)(cid:41)(cid:27)(cid:27)(cid:3)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19)(cid:28)(cid:27)(cid:41)(cid:19) (cid:50)(cid:83)(cid:87)(cid:76)(cid:37)(cid:82)(cid:68)(cid:81)(cid:81)(cid:37)(cid:78)(cid:92)(cid:3)(cid:21)(cid:87)(cid:72)(cid:86) (cid:19)(cid:19)(cid:91)(cid:91)(cid:23)(cid:23)(cid:19)(cid:19)(cid:19)(cid:19)(cid:20)(cid:20)(cid:3)(cid:3)(cid:19)(cid:19)(cid:38)(cid:27)(cid:19)(cid:19)(cid:19)(cid:19) (cid:52)(cid:52)(cid:41)(cid:45)(cid:41)(cid:45)(cid:17)(cid:25)(cid:16) (cid:22) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:27)(cid:3)(cid:19)(cid:19)(cid:21)(cid:19) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:19)(cid:23)(cid:19)(cid:19) (cid:37)(cid:56)(cid:52)(cid:41) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:27)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:50)(cid:83)(cid:87)(cid:37)(cid:76)(cid:82)(cid:68)(cid:81)(cid:81)(cid:37)(cid:78)(cid:3)(cid:92)(cid:20)(cid:87)(cid:72)(cid:86) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:51)(cid:82)(cid:69)(cid:57)(cid:83)(cid:51)(cid:69)(cid:35)(cid:82)(cid:86)(cid:38)(cid:69)(cid:39)(cid:68) (cid:19)(cid:91)(cid:25)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:27)(cid:19)(cid:19)(cid:19) (cid:35)(cid:47)(cid:45)(cid:48)(cid:0)(cid:11)(cid:0)(cid:50)(cid:41) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:19)(cid:3)(cid:21)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:26)(cid:38)(cid:19)(cid:19) (cid:54)(cid:92)(cid:86)(cid:82)(cid:87)(cid:69)(cid:72)(cid:83)(cid:80)(cid:69)(cid:82)(cid:3)(cid:86)(cid:80)(cid:69)(cid:68)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:26)(cid:27)(cid:19)(cid:19) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:21) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:19)(cid:3)(cid:20)(cid:19)(cid:19)(cid:19) (cid:37)(cid:68)(cid:81)(cid:78)(cid:3)(cid:21) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:26)(cid:23)(cid:19)(cid:19) (cid:39)(cid:36)(cid:38)(cid:20)(cid:3)(cid:9)(cid:3)(cid:21) (cid:48)(cid:55)(cid:50) (cid:54)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:26)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:37)(cid:68)(cid:81)(cid:78)(cid:3)(cid:20) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:25)(cid:23)(cid:19)(cid:19) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:25)(cid:19)(cid:19)(cid:19) (cid:24)(cid:20)(cid:21)(cid:3)(cid:69)(cid:92)(cid:87)(cid:72)(cid:3)(cid:56)(cid:54)(cid:37) (cid:53)(cid:51)(cid:34)(cid:0)(cid:50)(cid:69)(cid:71)(cid:73)(cid:83)(cid:84)(cid:69)(cid:82)(cid:83) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:24)(cid:38)(cid:19)(cid:19) (cid:20) (cid:82)(cid:69)(cid:83)(cid:69)(cid:82)(cid:86)(cid:69)(cid:68) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:24)(cid:27)(cid:19)(cid:19) (cid:41)(cid:18)(cid:35)(cid:18) (cid:41)(cid:18)(cid:35)(cid:17) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:24)(cid:23)(cid:19)(cid:19) (cid:19)(cid:91)(cid:21)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:54)(cid:53)(cid:36)(cid:48) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:27)(cid:3)(cid:23)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:24)(cid:19)(cid:19)(cid:19) (cid:53)(cid:33)(cid:50)(cid:52)(cid:21) (cid:39)(cid:68)(cid:87)(cid:68)(cid:40)(cid:40)(cid:51)(cid:53)(cid:50)(cid:48) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:23)(cid:38)(cid:19)(cid:19) (cid:53)(cid:33)(cid:50)(cid:52)(cid:20) (cid:19) (cid:89)(cid:49)(cid:82)(cid:82)(cid:79)(cid:68)(cid:81)(cid:87)(cid:76)(cid:16)(cid:79)(cid:72) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:27)(cid:3)(cid:21)(cid:19)(cid:19)(cid:19) (cid:37)(cid:68)(cid:81)(cid:78)(cid:3)(cid:21) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:23)(cid:27)(cid:19)(cid:19) (cid:53)(cid:53)(cid:51)(cid:51)(cid:33)(cid:33)(cid:50)(cid:50)(cid:52)(cid:52)(cid:18)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:23)(cid:23)(cid:19)(cid:19) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:39)(cid:68)(cid:87)(cid:68)(cid:40)(cid:40)(cid:51)(cid:53)(cid:50)(cid:48) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:37)(cid:68)(cid:81)(cid:78)(cid:3)(cid:20) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:23)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:27)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:51)(cid:48)(cid:41)(cid:19) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:26)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:22)(cid:38)(cid:19)(cid:19) (cid:51)(cid:48)(cid:41)(cid:18) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:22)(cid:27)(cid:19)(cid:19) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:22)(cid:23)(cid:19)(cid:19) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:23)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:37)(cid:68)(cid:81)(cid:78)(cid:3)(cid:21) (cid:41)(cid:55)(cid:36)(cid:39) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:22)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:22)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:21)(cid:38)(cid:19)(cid:19) (cid:55)(cid:55)(cid:36)(cid:39) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:41)(cid:37)(cid:79)(cid:68)(cid:68)(cid:86)(cid:81)(cid:75)(cid:78)(cid:3)(cid:3)(cid:80)(cid:20)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:21)(cid:27)(cid:19)(cid:19) (cid:50)(cid:52)(cid:35) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:21)(cid:23)(cid:19)(cid:19) (cid:44)(cid:35)(cid:36) (cid:36)(cid:79)(cid:76)(cid:68)(cid:86)(cid:72)(cid:71)(cid:3)(cid:87)(cid:82)(cid:3)(cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:82)(cid:85)(cid:3)(cid:86)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3) (cid:85)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:71)(cid:72)(cid:83)(cid:72)(cid:81)(cid:71)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:81)(cid:3) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:20)(cid:38)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:37)(cid:50)(cid:50)(cid:55)(cid:3)(cid:83)(cid:76)(cid:81)(cid:86) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:20)(cid:23)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:23) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:20)(cid:19)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:22) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:38)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:21) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:27)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:20) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:23)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:52)(cid:41)(cid:45)(cid:18) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:25)(cid:22)(cid:28)(cid:57)(cid:20) DocID027267 Rev 4 49/119 49

Electrical characteristics STM32L151VD-X STM32L152VD-X 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V . SS 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the A DD 1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not DD tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 6. Pin loading conditions Figure 7. Pin input voltage (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:57) (cid:44)(cid:49) (cid:68)(cid:76)(cid:20)(cid:26)(cid:27)(cid:24)(cid:20)(cid:70) (cid:68)(cid:76)(cid:20)(cid:26)(cid:27)(cid:24)(cid:21)(cid:71) 50/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.1.6 Power supply scheme Figure 8. Power supply scheme (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:69)(cid:92)(cid:16)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:85)(cid:92) (cid:11)(cid:47)(cid:54)(cid:40)(cid:15)(cid:53)(cid:55)(cid:38)(cid:15)(cid:58)(cid:68)(cid:78)(cid:72)(cid:16)(cid:88)(cid:83)(cid:3) (cid:79)(cid:82)(cid:74)(cid:76)(cid:70)(cid:15)(cid:3)(cid:53)(cid:55)(cid:38)(cid:3)(cid:69)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3) (cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:86)(cid:12) (cid:50)(cid:56)(cid:55) (cid:72)(cid:85) (cid:75)(cid:76)(cid:73)(cid:87) (cid:44)(cid:50) (cid:42)(cid:51)(cid:3)(cid:44)(cid:18)(cid:50)(cid:86) (cid:44)(cid:49) (cid:72)(cid:89)(cid:72)(cid:79)(cid:3)(cid:86) (cid:47)(cid:82)(cid:74)(cid:76)(cid:70) (cid:46)(cid:72)(cid:85)(cid:11)(cid:81)(cid:38)(cid:72)(cid:51)(cid:79)(cid:3)(cid:56)(cid:79)(cid:82)(cid:15)(cid:74)(cid:3)(cid:76)(cid:70)(cid:3) (cid:47) (cid:39)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79)(cid:3)(cid:9)(cid:3) (cid:57) (cid:48)(cid:72)(cid:80)(cid:82)(cid:85)(cid:76)(cid:72)(cid:86)(cid:12)(cid:3)(cid:3) (cid:39)(cid:39) (cid:57) (cid:39)(cid:39) (cid:53)(cid:72)(cid:74)(cid:88)(cid:79)(cid:68)(cid:87)(cid:82)(cid:85) (cid:49)(cid:3)(cid:238)(cid:3)(cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41)(cid:3)(cid:14)(cid:3) (cid:20)(cid:3)(cid:238)(cid:3)(cid:23)(cid:17)(cid:26)(cid:3)(cid:151)(cid:41) (cid:57) (cid:54)(cid:54) (cid:57) (cid:39)(cid:39)(cid:36) (cid:57) (cid:39)(cid:39)(cid:36) (cid:57) (cid:53)(cid:40)(cid:41) (cid:57) (cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41)(cid:3) (cid:53)(cid:40)(cid:41)(cid:14) (cid:36)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74)(cid:29)(cid:3) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:41) (cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41)(cid:3) (cid:36)(cid:39)(cid:38)(cid:18) (cid:50)(cid:54)(cid:38)(cid:15)(cid:51)(cid:47)(cid:47)(cid:15)(cid:38)(cid:50)(cid:48)(cid:51)(cid:15) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:39)(cid:36)(cid:38) (cid:171)(cid:17) (cid:57) (cid:54)(cid:54)(cid:36) (cid:49)(cid:3)(cid:177)(cid:3)(cid:81)(cid:88)(cid:80)(cid:69)(cid:72)(cid:85)(cid:3)(cid:82)(cid:73)(cid:3) (cid:57) (cid:18)(cid:57) (cid:3)(cid:83)(cid:68)(cid:76)(cid:85)(cid:86) (cid:39)(cid:39) (cid:54)(cid:54) (cid:48)(cid:54)(cid:22)(cid:21)(cid:23)(cid:25)(cid:20)(cid:57)(cid:22) DocID027267 Rev 4 51/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.1.7 Optional LCD power supply scheme Figure 9. Optional LCD power supply scheme (cid:57) (cid:57)(cid:54)(cid:40)(cid:47) (cid:39)(cid:39) (cid:49)(cid:3)(cid:91)(cid:3)(cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:39)(cid:39)(cid:20)(cid:18)(cid:21)(cid:18)(cid:17)(cid:17)(cid:17)(cid:18)(cid:49) (cid:54)(cid:87)(cid:72)(cid:83)(cid:16)(cid:88)(cid:83) (cid:38)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:14)(cid:3)(cid:20)(cid:3)(cid:91)(cid:3)(cid:20)(cid:19)(cid:3)(cid:151)(cid:41) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:20) (cid:57) (cid:47)(cid:38)(cid:39) (cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41) (cid:47)(cid:38)(cid:39) (cid:57) (cid:47)(cid:38)(cid:39) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:21) (cid:38) (cid:40)(cid:59)(cid:55) (cid:57) (cid:54)(cid:54)(cid:20)(cid:18)(cid:21)(cid:18)(cid:17)(cid:17)(cid:17)(cid:18)(cid:49) (cid:48)(cid:54)(cid:22)(cid:21)(cid:23)(cid:25)(cid:21)(cid:57)(cid:21) 1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open. 2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter. 6.1.8 Current consumption measurement Figure 10. Current consumption measurement scheme (cid:36) (cid:49)(cid:3)(cid:91)(cid:3)(cid:57) (cid:14) (cid:49)(cid:3)(cid:91)(cid:3)(cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41) (cid:39)(cid:39) (cid:14)(cid:20)(cid:3)(cid:91)(cid:3)(cid:20)(cid:19)(cid:3)(cid:151)(cid:41) (cid:16) (cid:49)(cid:3)(cid:91)(cid:3)(cid:57) (cid:54)(cid:54) (cid:57) (cid:47)(cid:38)(cid:39) (cid:57) (cid:39)(cid:39)(cid:36) (cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:14)(cid:20)(cid:3)(cid:151)(cid:41) (cid:57) (cid:53)(cid:40)(cid:41)(cid:16) (cid:57) (cid:54)(cid:54)(cid:36) (cid:48)(cid:54)(cid:22)(cid:22)(cid:19)(cid:21)(cid:27)(cid:57)(cid:20) 52/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics, Table 10: Current characteristics, and Table 11: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Voltage characteristics Symbol Ratings Min Max Unit External main supply voltage V –V –0.3 4.0 DD SS (including V and V )(1) DDA DD V Input voltage on five-volt tolerant pin V − 0.3 V +4.0 V (2) SS DD IN Input voltage on any other pin V − 0.3 4.0 SS |ΔV | Variations between different V power pins - 50 DDx DD mV |V − V | Variations between all different ground pins(3) - 50 SSX SS V –V Allowed voltage difference for V > V - 0.4 V REF+ DDA REF+ DDA Electrostatic discharge voltage V see Section 6.3.11 ESD(HBM) (human body model) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power supply, in the DD DDA SS SSA permitted range. 2. V maximum must always be respected. Refer to Table 10 for maximum allowed injected current values. IN 3. Include V pin. REF- Table 10. Current characteristics Symbol Ratings Max. Unit I Total current into sum of all V power lines (source)(1) 100 VDD(Σ) DD_x I (2) Total current out of sum of all V ground lines (sink)(1) 100 VSS(Σ) SS_x I Maximum current into each V power pin (source)(1) 70 VDD(PIN) DD_x I Maximum current out of each VSS_x ground pin (sink)(1) -70 VSS(PIN) Output current sunk by any I/O and control pin 25 I IO Output current sourced by any I/O and control pin - 25 mA Total output current sunk by sum of all IOs and control pins(2) 60 ΣI IO(PIN) Total output current sourced by sum of all IOs and control pins(2) -60 Injected current on five-volt tolerant I/O(4), RST and B pins -5/+0 I (3) INJ(PIN) Injected current on any other pin (5) ± 5 ΣI Total injected current (sum of all I/O and control pins)(6) ± 25 INJ(PIN) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power supply, in the DD DDA SS SSA permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17. DocID027267 Rev 4 53/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 4. Positive current injection is not possible on these I/Os. A negative injection is induced by V <V . I must never be IN SS INJ(PIN) exceeded. Refer to Table 9 for maximum allowed input voltage values. 5. A positive injection is induced by V > V while a negative injection is induced by V < V . I must never be IN DD IN SS INJ(PIN) exceeded. Refer to Table 9: Voltage characteristics for the maximum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the positive and INJ(PIN) negative injected currents (instantaneous values). Table 11. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range –65 to +150 °C STG T Maximum junction temperature 150 °C J 6.3 Operating conditions 6.3.1 General operating conditions Table 12. General operating conditions Symbol Parameter Conditions Min Max Unit f Internal AHB clock frequency - 0 32 HCLK f Internal APB1 clock frequency - 0 32 MHz PCLK1 f Internal APB2 clock frequency - 0 32 PCLK2 BOR detector disabled 1.65 3.6 BOR detector enabled, at 1.8 3.6 V Standard operating voltage power on V DD BOR detector disabled, after 1.65 3.6 power on Analog operating voltage 1.65 3.6 (ADC and DAC not used) Must be the same voltage as V (1) V DDA Analog operating voltage VDD(2) 1.8 3.6 (ADC or DAC used) FT pins; 2.0 V ≤ V -0.3 5.5(3) DD FT pins; V < 2.0 V -0.3 5.25(3) DD V I/O input voltage V IN BOOT0 pin 0 5.5 Any other pin -0.3 V +0.3 DD Power dissipation at TA = 85 °C for LQFP100 package - 465 P mW D suffix 6 or TA = 105 °C for suffix 7(4) WLCSP104 package - 435 Ambient temperature for 6 suffix version Maximum power dissipation(5) –40 85 TA °C Ambient temperature for 7 suffix version Maximum power dissipation –40 105 6 suffix version –40 105 TJ Junction temperature range °C 7 suffix version –40 110 1. When the ADC is used, refer to Table 54: ADC characteristics. 54/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 2. It is recommended to power V and V from the same source. A maximum difference of 300 mV between V and DD DDA DD V can be tolerated during power-up . DDA 3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled. 4. If T is lower, higher P values are allowed as long as T does not exceed T max (see Table 67: Thermal characteristics A D J J on page 114). 5. In low-power dissipation state, T can be extended to -40°C to 105°C temperature range as long as T does not exceed T A J J max (see Table 67: Thermal characteristics on page 114). 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the conditions summarized in Table 12. Table 13. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit ∞ BOR detector enabled 0 - V rise time rate DD BOR detector disabled 0 - 1000 t (1) µs/V VDD BOR detector enabled 20 - ∞ V fall time rate DD BOR detector disabled 0 - 1000 V rising, BOR enabled - 2 3.3 T (1) Reset temporization DD ms RSTTEMPO V rising, BOR disabled(2) 0.4 0.7 1.6 DD Power on/power down reset Falling edge 1 1.5 1.65 V POR/PDR threshold Rising edge 1.3 1.5 1.65 Falling edge 1.67 1.7 1.74 V Brown-out reset threshold 0 BOR0 Rising edge 1.69 1.76 1.8 V Falling edge 1.87 1.93 1.97 V Brown-out reset threshold 1 BOR1 Rising edge 1.96 2.03 2.07 Falling edge 2.22 2.30 2.35 V Brown-out reset threshold 2 BOR2 Rising edge 2.31 2.41 2.44 DocID027267 Rev 4 55/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 13. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Falling edge 2.45 2.55 2.6 V Brown-out reset threshold 3 BOR3 Rising edge 2.54 2.66 2.7 Falling edge 2.68 2.8 2.85 V Brown-out reset threshold 4 BOR4 Rising edge 2.78 2.9 2.95 Programmable voltage detector Falling edge 1.8 1.85 1.88 V PVD0 threshold 0 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 V PVD threshold 1 PVD1 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 V PVD threshold 2 V PVD2 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 V PVD threshold 3 PVD3 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 V PVD threshold 4 PVD4 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 V PVD threshold 5 PVD5 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 V PVD threshold 6 PVD6 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - Vhyst Hysteresis voltage All BOR and PVD mV - 100 - thresholds excepting BOR0 1. Guaranteed by characterization results. 2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details. 56/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.3 Embedded internal reference voltage The parameters given in Table 15 are based on characterization results, unless otherwise specified. Table 14. Embedded internal reference voltage calibration values Calibration value name Description Memory address Raw data acquired at VREFINT_CAL temperature of 30 °C ±5 °C 0x1FF8 00F8 - 0x1FF8 00F9 V = 3 V ±10 mV DDA Table 15. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit V (1) Internal reference voltage – 40 °C < T < +110 °C 1.202 1.224 1.242 V REFINT out J Internal reference current I - - 1.4 2.3 µA REFINT consumption T Internal reference startup time - - 2 3 ms VREFINT V and V voltage during V DDA REF+ - 2.99 3 3.01 V VREF_MEAS V factory measure REFINT Including uncertainties Accuracy of factory-measured V A REF due to ADC and - - ±5 mV VREF_MEAS value(2) V /V values DDA REF+ T (3) Temperature coefficient –40 °C < T < +110 °C - 25 100 ppm/°C Coeff J A (3) Long-term stability 1000 hours, T= 25 °C - - 1000 ppm Coeff V (3) Voltage coefficient 3.0 V < V < 3.6 V - - 2000 ppm/V DDCoeff DDA ADC sampling time when reading T (3) - 4 - - µs S_vrefint the internal reference voltage Startup time of reference voltage T (3) - - - 10 µs ADC_BUF buffer for ADC Consumption of reference voltage I (3) - - 13.5 25 µA BUF_ADC buffer for ADC I (3) VREF_OUT output current (4) - - - 1 µA VREF_OUT C (3) VREF_OUT output load - - - 50 pF VREF_OUT Consumption of reference voltage I (3) - - 730 1200 nA LPBUF buffer for VREF_OUT and COMP V (3) 1/4 reference voltage - 24 25 26 REFINT_DIV1 % V (3) 1/2 reference voltage - 49 50 51 REFINT_DIV2 V REFINT V (3) 3/4 reference voltage - 74 75 76 REFINT_DIV3 1. Guaranteed by test in production. 2. The internal V value is individually measured in production and stored in dedicated EEPROM bytes. REF 3. Guaranteed by characterization results. 4. To guarantee less than 1% VREF_OUT deviation. DocID027267 Rev 4 57/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.4 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless otherwise specified. The current consumption values are derived from tests performed under ambient temperature T = 25 °C and V supply voltage conditions summarized in A DD Table 12: General operating conditions, unless otherwise specified. The MCU is placed under the following conditions: • All I/O pins are configured in analog input mode • All peripherals are disabled except when explicitly mentioned. • The Flash memory access time, 64-bit access and prefetch is adjusted depending on f frequency and voltage range to provide the best CPU performance. HCLK • When the peripherals are enabled f = f = f . APB1 APB2 AHB • When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or HSE = 16 MHz (if HSE bypass mode is used). • The HSE user clock applied to OSCI_IN input follows the characteristic specified in Table 25: High-speed external user clock characteristics. • For maximum current consumption V = V = 3.6 V is applied to all supply pins. DD DDA • For typical current consumption V = V = 3.0 V is applied to all supply pins if not DD DDA specified otherwise. 58/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 16. Current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions f Typ Max(1) Unit HCLK 1 MHz 225 500 Range 3, V =1.2 CORE 2 MHz 420 750 µA V VOS[1:0] = 11 4 MHz 780 1200 f = f up to HSE HCLK 4 MHz 0.98 1.6 16 MHz included, Range 2, V =1.5 f = f /2 CORE 8 MHz 1.85 2.9 HSE HCLK V VOS[1:0] = 10 above 16 MHz (PLL ON)(2) 16 MHz 3.6 5.2 Supply IDD current in 8 MHz 2.2 3.5 (Run Run mode, Range 1, VCORE=1.8 16 MHz 4.4 6.5 mA from code V VOS[1:0] = 01 Flash) executed 32 MHz 8.6 12 from Flash Range 2, V =1.5 CORE 16 MHz 3.6 5.2 HSI clock source V VOS[1:0] = 10 (16 MHz) Range 1, V =1.8 CORE 32 MHz 8.7 12.3 V VOS[1:0] = 01 MSI clock, 65 kHz 65 kHz 42 145 Range 3, V =1.2 MSI clock, 524 kHz CORE 524 kHz 135 250 µA V VOS[1:0] = 11 MSI clock, 4.2 MHz 4.2 MHz 820 1200 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). DocID027267 Rev 4 59/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 17. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter Conditions f Typ Max(1) Unit HCLK 1 MHz 200 470 Range 3, V =1.2 V 2 MHz 360 780 µA CORE VOS[1:0] = 11 4 MHz 685 1200 f = f up to HSE HCLK 4 MHz 0.80 1.5 16 MHz included, Range 2, f = f /2 V =1.5 V 8 MHz 1.6 3 HSE HCLK CORE above 16 MHz VOS[1:0] = 10 (PLL ON)(2) 16 MHz 3.1 5 Supply current Range 1, 8 MHz 1.9 3.5 IDD in Run mode, VCORE=1.8 V 16 MHz 3.7 5.55 (Run code executed VOS[1:0] = 01 mA from from RAM, 32 MHz 7.55 10.9 RAM) Flash switched Range 2, off V =1.5 V 16 MHz 3.15 4.8 CORE HSI clock source VOS[1:0] = 10 (16 MHz) Range 1, V =1.8 V 32 MHz 7.75 11.7 CORE VOS[1:0] = 01 MSI clock, 65 kHz 65 kHz 40 130 Range 3, MSI clock, 524 kHz V =1.2 V 524 kHz 115 215 µA CORE VOS[1:0] = 11 MSI clock, 4.2 MHz 4.2 MHz 715 1100 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 60/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 18. Current consumption in Sleep mode Symbol Parameter Conditions f Typ Max(1) Unit HCLK 1 MHz 51 220 Range 3, V =1.2 V 2 MHz 81 300 CORE VOS[1:0] = 11 4 MHz 140 380 f = f up to HSE HCLK 4 MHz 175 500 16 MHz included, Range 2, f = f /2 V =1.5 V 8 MHz 330 700 HSE HCLK CORE above 16 MHz (PLL VOS[1:0] = 10 ON)(2) 16 MHz 625 1100 8 MHz 395 800 Range 1, Supply current V =1.8 V 16 MHz 760 1250 CORE in Sleep VOS[1:0] = 01 mode, Flash 32 MHz 1700 2700 OFF Range 2, V =1.5 V 16 MHz 670 1100 CORE HSI clock source VOS[1:0] = 10 (16 MHz) Range 1, V =1.8 V 32 MHz 1750 2700 CORE VOS[1:0] = 01 MSI clock, 65 kHz 65 kHz 19 92 Range 3, MSI clock, 524 kHz V =1.2 V 524 kHz 33 110 CORE VOS[1:0] = 11 MSI clock, 4.2 MHz 4.2 MHz 150 273 I (Sleep) µA DD 1 MHz 63 250 Range 3, V =1.2 V 2 MHz 93 300 CORE VOS[1:0] = 11 4 MHz 155 380 f = f up to HSE HCLK 4 MHz 190 500 16 MHz included, Range 2, f = f /2 V =1.5 V 8 MHz 340 700 HSE HCLK CORE above 16 MHz (PLL VOS[1:0] = 10 Supply current ON)(2) 16 MHz 640 1120 in Sleep 8 MHz 410 800 Range 1, mode, Flash V =1.8 V 16 MHz 770 1300 ON CORE VOS[1:0] = 01 32 MHz 1750 2700 Range 2, V =1.5 V 16 MHz 690 1160 CORE HSI clock source VOS[1:0] = 10 (16 MHz) Range 1, V =1.8 V 32 MHz 1750 2800 CORE VOS[1:0] = 01 Supply current MSI clock, 65 kHz 65 kHz 31 105 Range 3, in Sleep MSI clock, 524 kHz V =1.2V 524 kHz 45 125 mode, Flash CORE VOS[1:0] = 11 ON MSI clock, 4.2 MHz 4.2 MHz 160 290 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) DocID027267 Rev 4 61/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 19. Current consumption in Low-power run mode Symbol Parameter Conditions Typ Max(1) Unit T = -40 °C to 25 °C 11 16 A MSI clock, 65 kHz T = 85 °C 36.2 40 f = 32 kHz A All HCLK T = 105 °C 65.4 102 peripherals A OFF, code T =-40 °C to 25 °C 16.5 23 A executed MSI clock, 65 kHz T = 85 °C 41.9 48 from RAM, f = 65 kHz A HCLK Flash T = 105 °C 72.1 108 A switched OFF, VDD TA = -40 °C to 25 °C 30 45 from 1.65 V MSI clock, 131 kHz TA = 55 °C 36.1 48 to 3.6 V fHCLK = 131 kHz TA = 85 °C 55.7 66 Supply IDD (LP current in TA = 105 °C 86.6 125 Run) Low-power TA = -40 °C to 25 °C 26 40.5 run mode MSI clock, 65 kHz T = 85 °C 53.2 67 µA f = 32 kHz A HCLK T = 105 °C 92.1 120 All A peripherals T = -40 °C to 25 °C 33 49 A OFF, code MSI clock, 65 kHz executed f = 65 kHz TA = 85 °C 60.2 75 HCLK from Flash, T = 105 °C 95.6 130 A V from DD 1.65 V to TA = -40 °C to 25 °C 48.5 71 3.6 V MSI clock, 131 kHz TA = 55 °C 54.7 75 fHCLK = 131 kHz TA = 85 °C 76.1 95 T = 105 °C 112 140 A Max allowed V from I max current in DD DD 1.65 V to - - - 200 (LP Run) Low-power 3.6 V run mode 1. Guaranteed by characterization results, unless otherwise specified. 62/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 20. Current consumption in Low-power sleep mode Symbol Parameter Conditions Typ Max(1) Unit MSI clock, 65 kHz f = 32 kHz T = -40 °C to 25 °C 5.5 - HCLK A Flash OFF T = -40 °C to 25 °C 18.5 21 MSI clock, 65 kHz A f = 32 kHz T = 85 °C 26.8 29 HCLK A Flash ON T = 105 °C 37 47 A All peripherals T = -40 °C to 25 °C 18.5 21 OFF, V from MSI clock, 65 kHz A DD 1.65 V to 3.6 V f = 65 kHz, T = 85 °C 27.2 29 HCLK A Flash ON T = 105 °C 37.3 47 A T = -40 °C to 25 °C 21.5 25 A MSI clock, 131 kHz T = 55 °C 23.7 26 Supply f = 131 kHz, A HCLK IDD current in Flash ON TA = 85 °C 29.8 32 (LP Sleep) Low-power T = 105 °C 39.7 50 sleep mode A TA = -40 °C to 25 °C 18.5 21 µA MSI clock, 65 kHz T = 85 °C 26.8 29 f = 32 kHz A HCLK T = 105 °C 38.3 47 A T = -40 °C to 25 °C 18.5 21 TIM9 and A USART1 MSI clock, 65 kHz T = 85 °C 27.2 29 enabled, Flash fHCLK = 65 kHz A ON, VDD from TA = 105 °C 38.5 47 1.65 V to 3.6 V T = -40 °C to 25 °C 21.5 25 A MSI clock, 131 kHz TA = 55 °C 23.7 26 fHCLK = 131 kHz TA = 85 °C 29.8 32 T = 105 °C 41.2 50 A Max allowed I max V from 1.65 V DD current in DD - - - 200 (LP Sleep) to 3.6 V Low-power sleep mode 1. Guaranteed by characterization results, unless otherwise specified. DocID027267 Rev 4 63/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 21. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions Typ Max(1) Unit T = -40°C to 25°C A 1.18 - V = 1.8 V DD T = -40°C to 25°C 1.4 4 LCD A OFF T = 55°C 3.02 6 A T = 85°C 7.44 11 A RTC clocked by LSI T = 105°C 15.5 27 or LSE external clock A (32.768kHz), T = -40°C to 25°C 1.5 6 A regulator in LP mode, LCD HSI and HSE OFF ON TA = 55°C 4.65 7 (no independent (static T = 85°C 9.07 13 watchdog) duty)(2) A T = 105°C 15.6 31 A T = -40°C to 25°C 3.9 10 A LCD T = 55°C 5.19 11 A ON (1/8 duty)(3) TA= 85°C 9.8 17 T = 105°C 18.4 48 A T = -40°C to 25°C 1.65 - A Supply current in IDD (Stop Stop mode with RTC LCD TA = 55°C 3.32 - µA with RTC) enabled OFF T = 85°C 7.83 - A T = 105°C 16 - A T = -40°C to 25°C 1.75 - A LCD ON TA = 55°C 4.9 - (static RTC clocked by LSE T = 85°C 9.41 - duty)(2) A external quartz T = 105°C 15.8 - (32.768kHz), A regulator in LP mode, T = -40°C to 25°C 4.1 - A HSI and HSE OFF LCD T = 55°C 5.53 - (no independent A ON (1/8 watchdog(4) duty)(3) TA= 85°C 10 - T = 105°C 18.5 - A T = -40°C to 25°C A 1.33 - V = 1.8V DD LCD T = -40°C to 25°C A 1.62 - OFF V = 3.0V DD T = -40°C to 25°C A 1.87 - V = 3.6V DD 64/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 21. Typical and maximum current consumptions in Stop mode (continued) Symbol Parameter Conditions Typ Max(1) Unit Regulator in LP mode, HSI and HSE OFF, independent T = -40°C to 25°C 1.8 2.2 A watchdog and LSI enabled Supply current in T = -40°C to 25°C 0.560 1.5 I (Stop) Stop mode (RTC A µA DD disabled) Regulator in LP mode, LSI, HSI T = 55°C 2.18 4 A and HSE OFF (no independent watchdog) TA= 85°C 6.6 12 T = 105°C 14.9 26 A MSI = 4.2 MHz 2 - I Supply current during DD (WU from wakeup from Stop MSI = 1.05 MHz T = -40°C to 25°C 1.45 - mA A Stop) mode MSI = 65 kHz(5) 1.45 - 1. Guaranteed by characterization results, unless otherwise specified. 2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. 3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part of the wakeup period, the current corresponds the Run mode current. DocID027267 Rev 4 65/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 22. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) Unit T = -40 °C to 25 °C A 0.865 - V = 1.8 V DD T = -40 °C to 25 °C 1.11 1.9 RTC clocked by LSI (no A independent watchdog) T = 55 °C 1.72 2.2 A T = 85 °C 2.12 4 A IDD Supply current in TA = 105 °C 2.54 8.3(2) (Standby Standby mode with RTC with RTC) enabled TA = -40 °C to 25 °C 0.97 - V = 1.8 V DD RTC clocked by LSE T = -40 °C to 25 °C 1.28 - external quartz (no A µA independent T = 55 °C 2.01 - A watchdog)(3) T = 85 °C 2.5 - A T = 105 °C 2.98 - A Independent watchdog T = -40 °C to 25 °C 1 1.7 and LSI enabled A Supply current in T = -40 °C to 25 °C 0.29 1 I A DD Standby mode (RTC (Standby) disabled) Independent watchdog TA = 55 °C 0.96 1.3 and LSI OFF T = 85 °C 1.38 3 A T = 105 °C 1.98 7(2) A I Supply current during DD (WU from wakeup time from - T = -40 °C to 25 °C 1 - mA A Standby) Standby mode 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at V or V (no load) DD SS • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on 66/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 23. Peripheral current consumption(1) Typical consumption, V = 3.0 V, T = 25 °C DD A Range 1, Range 2, Range 3, Peripheral Unit V = V = V = Low-power CORE CORE CORE 1.8 V 1.5 V 1.2 V sleep and run VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 TIM2 12.0 10.0 8.0 10.0 TIM3 10.5 8.8 7.0 8.8 TIM4 10.4 8.8 7.0 8.8 TIM5 13.8 11.5 9.1 11.5 TIM6 3.9 3.0 2.5 3.0 TIM7 3.8 3.3 2.6 3.3 LCD 4.2 3.6 2.8 3.6 WWDG 2.9 2.5 2.1 2.5 SPI2 5.4 4.4 3.5 4.4 SPI3 5.5 4.6 3.7 4.6 µA/MHz APB1 USART2 7.6 6.2 4.9 6.2 (fHCLK) USART3 7.6 6.2 5.0 6.2 USART4 7.3 6.1 4.8 6.1 USART5 7.6 6.3 5.0 6.3 I2C1 7.3 6.1 4.8 6.1 I2C2 7.2 5.9 4.7 5.9 USB 13.0 11.2 8.9 11.2 PWR 2.6 2.3 1.9 2.3 DAC 5.9 5.0 4.0 5.0 COMP 3.9 3.3 2.6 3.3 DocID027267 Rev 4 67/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 23. Peripheral current consumption(1) (continued) Typical consumption, V = 3.0 V, T = 25 °C DD A Range 1, Range 2, Range 3, Peripheral Unit V = V = V = Low-power CORE CORE CORE 1.8 V 1.5 V 1.2 V sleep and run VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 SYSCFG & RI 2.9 2.4 2.0 2.4 TIM9 8.2 6.9 5.5 6.9 TIM10 6.2 5.1 4.1 5.1 TIM11 6.2 5.1 4.1 5.1 APB2 ADC(2) 9.5 7.9 6.2 7.9 SPI1 4.8 3.9 3.2 3.9 USART1 8.2 6.9 5.4 6.9 GPIOA 6.3 5.3 4.1 5.3 GPIOB 6.3 5.3 4.1 5.3 GPIOC 6.3 5.2 4.1 5.2 GPIOD 8.1 6.8 5.4 6.8 GPIOE 6.7 5.7 4.5 5.7 µA/MHz GPIOF 5.9 4.9 3.9 4.9 (fHCLK) GPIOG 7.2 6.1 4.9 6.1 AHB GPIOH 1.7 1.4 1.1 1.4 CRC 0.8 0.7 0.5 0.7 FLASH 21.6 18.1 16.0 - (3) DMA1 16.8 14.5 11.5 14.5 DMA2 15.7 13.6 10.8 13.6 All enabled 222 184 160 165.9 I 0.4 DD (RTC) I 3.1 DD (LCD) I (4) 1450 DD (ADC) I (5) 340 DD (DAC) I 0.16 µA DD (COMP1) Slow mode 2 I DD (COMP2) Fast mode 5 I (6) 2.6 DD (PVD / BOR) I 0.25 DD (IWDG) 1. Data based on differential I measurement between all peripherals OFF an one peripheral with clock enabled, in the DD following conditions: f = 32 MHz (range 1), f = 16 MHz (range 2), f = 4 MHz (range 3), f = 64kHz (Low- HCLK HCLK HCLK HCLK power run/sleep), f = f , f = f , default prescaler value for each peripheral. The CPU is in Sleep mode in APB1 HCLK APB2 HCLK both cases. No I/O pins toggling. 2. HSI oscillator is OFF for this measure. 68/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 6. Including supply current of internal reference voltage. 6.3.5 Wakeup time from low-power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: • Sleep mode: the clock source is the clock that was set before entering Sleep mode • Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode • Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under the conditions summarized in Table 12. Table 24. Low-power mode wakeup timings Symbol Parameter Conditions Typ Max(1) Unit t Wakeup from Sleep mode f = 32 MHz 0.4 - WUSLEEP HCLK f = 262 kHz HCLK 46 - Flash enabled Wakeup from Low-power sleep t WUSLEEP_LP mode, fHCLK = 262 kHz fHCLK = 262 kHz 46 - Flash switched OFF Wakeup from Stop mode, regulator in Run mode f = f = 4.2 MHz 8.2 - HCLK MSI ULP bit = 1 and FWU bit = 1 f = f = 4.2 MHz HCLK MSI 7.7 8.9 Voltage range 1 and 2 f = f = 4.2 MHz µs HCLK MSI 8.2 13.1 Voltage range 3 t WUSTOP Wakeup from Stop mode, fHCLK = fMSI = 2.1 MHz 10.2 13.4 regulator in low-power mode f = f = 1.05 MHz 16 20 HCLK MSI ULP bit = 1 and FWU bit = 1 f = f = 524 kHz 31 37 HCLK MSI f = f = 262 kHz 57 66 HCLK MSI f = f = 131 kHz 112 123 HCLK MSI f = MSI = 65 kHz 221 236 HCLK Wakeup from Standby mode f = MSI = 2.1 MHz 58 104 ULP bit = 1 and FWU bit = 1 HCLK t WUSTDBY Wakeup from Standby mode f = MSI = 2.1 MHz 2.6 3.25 ms FWU bit = 0 HCLK 1. Guaranteed by characterization, unless otherwise specified DocID027267 Rev 4 69/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.6 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform is shown in Figure 11. Table 25. High-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CSS is on or 1 8 32 MHz User external clock source PLL is used f HSE_ext frequency CSS is off, PLL 0 8 32 MHz not used V OSC_IN input pin high level voltage 0.7V - V HSEH DD DD V V OSC_IN input pin low level voltage V - 0.3V HSEL SS DD t w(HSEH) OSC_IN high or low time 12 - - t - w(HSEL) ns t r(HSE) OSC_IN rise or fall time - - 20 t f(HSE) C OSC_IN input capacitance - 2.6 - pF in(HSE) 1. Guaranteed by design. Figure 11. High-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:43)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:43)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:43)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:23)(cid:57)(cid:21) 70/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a low- speed external clock source, and under the conditions summarized in Table 12. Table 26. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit User external clock source f 1 32.768 1000 kHz LSE_ext frequency OSC32_IN input pin high level V 0.7V - V LSEH voltage DD DD V OSC32_IN input pin low level V - V - 0.3V LSEL voltage SS DD t w(LSEH) OSC32_IN high or low time 465 - - t w(LSEL) ns t r(LSE) OSC32_IN rise or fall time - - 10 t f(LSE) C OSC32_IN input capacitance - - 0.6 - pF IN(LSE) 1. Guaranteed by design. Figure 12. Low-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:47)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:47)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:47)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:24)(cid:57)(cid:21) High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 27. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID027267 Rev 4 71/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 27. HSE oscillator characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit f Oscillator frequency - 1 24 MHz OSC_IN R Feedback resistor - - 200 - kΩ F Recommended load capacitance versus C equivalent serial R = 30 Ω - 20 - pF S resistance of the crystal (R )(3) S V = 3.3 V, DD I HSE driving current V = V with 30 pF - - 3 mA HSE IN SS load C = 20 pF 2.5 (startup) - - HSE oscillator power fOSC = 16 MHz 0.7 (stabilized) I mA DD(HSE) consumption C = 10 pF 2.5 (startup) - - fOSC = 16 MHz 0.46 (stabilized) Oscillator g Startup 3.5 - - mA /V m transconductance t (4) Startup time V is stabilized - 1 - ms SU(HSE) DD 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is SU(HSE) reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For C and C , it is recommended to use high-quality external ceramic capacitors in the L1 L2 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 13). C and C are usually the L1 L2 same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C . PCB and MCU pin capacitance must be included (10 pF L1 L2 can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . Refer to the application note AN2867 “Oscillator design guide for ST L1 L2 microcontrollers” available from the ST website www.st.com. 72/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 13. HSE oscillator circuit diagram (cid:53)(cid:80) (cid:73)(cid:43)(cid:54)(cid:40)(cid:3)(cid:87)(cid:82)(cid:3)(cid:70)(cid:82)(cid:85)(cid:72) (cid:47)(cid:80) (cid:38)(cid:50) (cid:53)(cid:41) (cid:38)(cid:47)(cid:20) (cid:38)(cid:80) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:74)(cid:80) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:38)(cid:82)(cid:81)(cid:86)(cid:88)(cid:80)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79) (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:38)(cid:47)(cid:21) (cid:68)(cid:76)(cid:20)(cid:27)(cid:21)(cid:22)(cid:24)(cid:69) Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 28. LSE oscillator characteristics (f = 32.768 kHz)(1) LSE Symbol Parameter Conditions Min Typ Max Unit Low speed external oscillator f - - 32.768 - kHz LSE frequency R Feedback resistor - - 1.2 - MΩ F Recommended load capacitance C(2) versus equivalent serial R = 30 kΩ - 8 - pF S resistance of the crystal (R )(3) S I LSE driving current V = 3.3 V, V = V - - 1.1 µA LSE DD IN SS V = 1.8 V - 450 - DD LSE oscillator current I V = 3.0 V - 600 - nA DD (LSE) consumption DD V = 3.6V - 750 - DD g Oscillator transconductance - 3 - - µA/V m t (4) Startup time V is stabilized - 1 - s SU(LSE) DD 1. Guaranteed by characterization results. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details. S 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized SU(LSE) 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DocID027267 Rev 4 73/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Note: For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to L1 L2 15 pF range selected to match the requirements of the crystal or resonator (see Figure 14). C and C are usually the same size. The crystal manufacturer typically specifies a load L1 L2, capacitance which is the series combination of C and C . L1 L2 Load capacitance C has the following formula: C = C x C / (C + C ) + C where L L L1 L2 L1 L2 stray C is the pin capacitance and board or trace PCB-related capacitance. Typically, it is stray between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended L1 L2 to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load L capacitance of 12.5 pF. Example: if the user chooses a resonator with a load capacitance of C = 6 pF and L C = 2 pF, then C = C = 8 pF. stray L1 L2 Figure 14. Typical application with a 32.768 kHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:3) (cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:73)(cid:47)(cid:54)(cid:40) (cid:37)(cid:76)(cid:68)(cid:86)(cid:3) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93)(cid:3) (cid:53) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:71)(cid:3) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:41) (cid:74)(cid:68)(cid:76)(cid:81) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:47)(cid:20)(cid:91)(cid:91) (cid:38)(cid:47)(cid:21) (cid:68)(cid:76)(cid:20)(cid:26)(cid:27)(cid:24)(cid:22)(cid:69) 74/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.7 Internal clock source characteristics The parameters given in Table 29 are derived from tests performed under the conditions summarized in Table 12. High-speed internal (HSI) RC oscillator Table 29. HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit f Frequency V = 3.0 V - 16 - MHz HSI DD HSI user-trimmed Trimming code is not a multiple of 16 - ± 0.4 0.7 % (1)(2) TRIM resolution Trimming code is a multiple of 16 - - ± 1.5 % V = 3.0 V, T = 25 °C -1(3) - 1(3) % DDA A V = 3.0 V, T = 0 to 55 °C -1.5 - 1.5 % DDA A Accuracy of the VDDA = 3.0 V, TA = -10 to 70 °C -2 - 2 % ACCHSI(2) factory-calibrated VDDA = 3.0 V, TA = -10 to 85 °C -2.5 - 2 % HSI oscillator V = 3.0 V, T = -10 to 105 °C -4 - 2 % DDA A V = 1.65 V to 3.6 V DDA -4 - 3 % T = -40 to 105 °C A HSI oscillator t (2) - - 3.7 6 µs SU(HSI) startup time HSI oscillator I (2) - - 100 140 µA DD(HSI) power consumption 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Guaranteed by characterization results. 3. Guaranteed by test in production. Low-speed internal (LSI) RC oscillator Table 30. LSI oscillator characteristics Symbol Parameter Min Typ Max Unit f (1) LSI frequency 26 38 56 kHz LSI LSI oscillator frequency drift D (2) -10 - 4 % LSI 0°C ≤ T ≤ 105°C A t (3) LSI oscillator startup time - - 200 µs su(LSI) I (3) LSI oscillator power consumption - 400 510 nA DD(LSI) 1. Guaranteed by test in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design. DocID027267 Rev 4 75/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Multi-speed internal (MSI) RC oscillator Table 31. MSI oscillator characteristics Symbol Parameter Condition Typ Max Unit MSI range 0 65.5 - MSI range 1 131 - kHz MSI range 2 262 - Frequency after factory calibration, done at f MSI range 3 524 - MSI V = 3.3 V and T = 25 °C DD A MSI range 4 1.05 - MSI range 5 2.1 - MHz MSI range 6 4.2 - ACC Frequency error after factory calibration - ±0.5 - % MSI MSI oscillator frequency drift D (1) - ±3 - % TEMP(MSI) 0 °C ≤ T ≤ 105 °C A MSI oscillator frequency drift D (1) - - 2.5 %/V VOLT(MSI) 1.65 V ≤ V ≤ 3.6 V, T = 25 °C DD A MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - I (2) MSI oscillator power consumption MSI range 3 2.5 - µA DD(MSI) MSI range 4 4.5 - MSI range 5 8 - MSI range 6 15 - MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6 - t MSI oscillator startup time µs SU(MSI) MSI range 5 5 - MSI range 6, Voltage range 1 3.5 - and 2 MSI range 6, 5 - Voltage range 3 76/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 31. MSI oscillator characteristics (continued) Symbol Parameter Condition Typ Max Unit MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 t (2) MSI oscillator stabilization time µs STAB(MSI) MSI range 5 - 2 MSI range 6, Voltage range 1 - 2 and 2 MSI range 3, - 3 Voltage range 3 Any range to - 4 range 5 f MSI oscillator frequency overshoot MHz OVER(MSI) Any range to - 6 range 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Guaranteed by characterization results. DocID027267 Rev 4 77/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.8 PLL characteristics The parameters given in Table 32 are derived from tests performed under the conditions summarized in Table 12. Table 32. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 2 - 24 MHz f PLL_IN PLL input clock duty cycle 45 - 55 % f PLL output clock 2 - 32 MHz PLL_OUT PLL lock time t PLL input = 16 MHz - 115 160 µs LOCK PLL VCO = 96 MHz Jitter Cycle-to-cycle jitter - - ± 600 ps I (PLL) Current consumption on V - 220 450 DDA DDA µA I (PLL) Current consumption on V - 120 150 DD DD 1. Guaranteed by characterization results. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f . PLL_OUT 6.3.9 Memory characteristics The characteristics are given at T = -40 to 105 °C unless otherwise specified. A RAM memory Table 33. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode(1) STOP mode (or RESET) 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). 78/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Flash memory and data EEPROM Table 34. Flash memory and data EEPROM characteristics Symbol Parameter Conditions Min Typ Max(1) Unit Operating voltage V - 1.65 - 3.6 V DD Read / Write / Erase Programming/ erasing Erasing - 3.28 3.94 t time for byte / word / ms prog double word / half-page Programming - 3.28 3.94 Average current during the whole programming / - 600 - µA erase operation IDD Maximum current (peak) TA = 25 °C, VDD = 3.6 V during the whole - 1.5 2.5 mA programming / erase operation 1. Guaranteed by design. Table 35. Flash memory and data EEPROM endurance and retention Value Symbol Parameter Conditions Unit Min(1) Typ Max Cycling (erase / write) 10 - - Program memory T = -40°C to N (2) A kcycles CYC Cycling (erase / write) 105 °C 300 - - EEPROM data memory Data retention (program memory) after 30 - - 10 kcycles at T = 85 °C A T = +85 °C RET Data retention (EEPROM data memory) 30 - - after 300 kcycles at T = 85 °C t (2) A years RET Data retention (program memory) after 10 - - 10 kcycles at T = 105 °C A T = +105 °C RET Data retention (EEPROM data memory) 10 - - after 300 kcycles at T = 105 °C A 1. Guaranteed by characterization results. 2. Characterization is done according to JEDEC JESD22-A117. DocID027267 Rev 4 79/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and DD V through a 100 pF capacitor, until a functional disturbance occurs. This test is SS compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 36. They are based on the EMS levels and classes defined in application note AN1709. Table 36. EMS characteristics Level/ Symbol Parameter Conditions Class V = 3.3 V, LQFP100, T = +25 °C, Voltage limits to be applied on any I/O pin to DD A V f = 32 MHz 4B FESD induce a functional disturbance HCLK conforms to IEC 61000-4-2 V = 3.3 V, LQFP100, T = +25 Fast transient voltage burst limits to be DD A °C, V applied through 100 pF on V and V 4A EFTB DD SS f = 32 MHz pins to induce a functional disturbance HCLK conforms to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. 80/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 37. EMI characteristics Max vs. frequency range Monitored Symbol Parameter Conditions 4 MHz 16 MHz 32 MHz Unit frequency band voltage voltage voltage range 3 range 2 range 1 V = 3.6 V, 0.1 to 30 MHz -14 -6 -4 DD TA = 25 °C, 30 to 130 MHz -11 0 9 dBµV SEMI Peak level LQFP100 package 130 MHz to 1GHz -7 -1 9 compliant with IEC 61967-2 SAE EMI Level 1 2 2.5 - 6.3.11 Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard. Table 38. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) Electrostatic T = +25 °C, conforming V discharge voltage A 2 2000 V ESD(HBM) to JESD22-A114 (human body model) Electrostatic LQFP100 C4 500 T = +25 °C, conforming V discharge voltage A V ESD(CDM) (charge device model) to ANSI/ESD STM5.3.1. WLCSP104 C3 250 1. Guaranteed by characterization results. DocID027267 Rev 4 81/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 39. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +105 °C conforming to JESD78A II level A A 6.3.12 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard pins) should be avoided during normal product operation. DD However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator frequency deviation, LCD levels). The test results are given in the Table 40. Table 40. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on all 5 V tolerant (FT) pins -5 (1) NA(2) I Injected current on BOOT0 -0 NA(2) mA INJ Injected current on any other pin -5 (1) +5 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 2. Injection is not possible. 82/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL compliant. Table 41. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit TC and FT I/O - - 0.3 V (1)(2) DD V Input low level voltage IL BOOT0 - - 0.14 V (2) DD TC I/O 0.45 V +0.38(2) - - DD V Input high level voltage FT I/O 0.39 V +0.59(2) - - V IH DD BOOT0 0.15 V +0.56(2) - - DD I/O Schmitt trigger voltage TC and FT I/O - 10% VDD(3) - V hys hysteresis(2) BOOT0 - 0.01 - V ≤ V ≤ V SS IN DD - - ±50 I/Os with LCD V ≤ V ≤ V SS IN DD I/Os with analog - - ±50 switches V ≤ V ≤ V SS IN DD nA I/Os with analog - - ±50 Ilkg Input leakage current (4) switches and LCD V ≤ V ≤ V SS IN DD - - ±250 I/Os with USB V ≤ V ≤ V SS IN DD - - ±50 TC and FT I/Os FT I/O - - ±10 µA V ≤ V ≤ 5V DD IN Weak pull-up equivalent R V = V 25 45 65 kΩ PU resistor(5)(1) IN SS Weak pull-down equivalent R V = V 25 45 65 kΩ PD resistor(5) IN DD C I/O pin capacitance - - 5 - pF IO 1. Guaranteed by test in production. 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). DocID027267 Rev 4 83/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA with the non-standard V /V specifications given in Table 42. OL OH In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on V plus the maximum Run DD, consumption of the MCU sourced on V cannot exceed the absolute maximum rating DD, I (see Table 10). VDD(Σ) • The sum of the currents sunk by all the I/Os on V plus the maximum Run SS consumption of the MCU sunk on V cannot exceed the absolute maximum rating SS I (see Table 10). VSS(Σ) Output voltage levels Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL compliant. Table 42. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL(1)(2) Output low level voltage for an I/O pin IIO = 8 mA - 0.4 VOH(2)(3) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V VDD-0.4 - VOL (3)(4) Output low level voltage for an I/O pin IIO = 4 mA - 0.45 V VOH (3)(4) Output high level voltage for an I/O pin 1.65 V < VDD < 3.6 V VDD-0.45 - VOL(1)(4) Output low level voltage for an I/O pin IIO = 20 mA - 1.3 VOH(3)(4) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V VDD-1.3 - 1. The I current sunk by the device must always respect the absolute maximum rating specified in Table 10 IO and the sum of I (I/O ports and control pins) must not exceed I . IO VSS 2. Guaranteed by test in production. 3. The I current sourced by the device must always respect the absolute maximum rating specified in IO Table 10 and the sum of I (I/O ports and control pins) must not exceed I . IO VDD 4. Guaranteed by characterization results. 84/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 15 and Table 43, respectively. Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under the conditions summarized in Table 12. Table 43. I/O AC characteristics(1) OSPEEDRx [1:0] bit Symbol Parameter Conditions Min Max(2) Unit value(1) C = 50 pF, V = 2.7 V to 3.6 V - 400 f Maximum frequency(3) L DD kHz max(IO)out C = 50 pF, V = 1.65 V to 2.7 V - 400 L DD 00 tf(IO)out Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 625 ns tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 625 C = 50 pF, V = 2.7 V to 3.6 V - 2 f Maximum frequency(3) L DD MHz max(IO)out C = 50 pF, V = 1.65 V to 2.7 V - 1 L DD 01 tf(IO)out Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 ns tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 250 C = 50 pF, V = 2.7 V to 3.6 V - 10 F Maximum frequency(3) L DD MHz max(IO)out C = 50 pF, V = 1.65 V to 2.7 V - 2 L DD 10 tf(IO)out Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 25 ns tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 125 C = 30 pF, V = 2.7 V to 3.6 V - 50 F Maximum frequency(3) L DD MHz max(IO)out C = 50 pF, V = 1.65 V to 2.7 V - 8 L DD 11 tf(IO)out Output rise and fall time CL = 30 pF, VDD = 2.7 V to 3.6 V - 5 tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 30 ns Pulse width of external - t signals detected by the - 8 - EXTIpw EXTI controller 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. The maximum frequency is defined in Figure 15. DocID027267 Rev 4 85/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Figure 15. I/O AC characteristics definition (cid:25)(cid:16)(cid:5) (cid:17)(cid:16)(cid:5) (cid:21)(cid:16)(cid:5) (cid:21)(cid:16)(cid:5) (cid:17)(cid:16)(cid:5) (cid:25)(cid:16)(cid:5) (cid:37)(cid:56)(cid:52)(cid:37)(cid:50)(cid:46)(cid:33)(cid:44) (cid:84)(cid:82)(cid:8)(cid:41)(cid:47)(cid:9)(cid:79)(cid:85)(cid:84) (cid:84)(cid:70)(cid:8)(cid:41)(cid:47)(cid:9)(cid:79)(cid:85)(cid:84) (cid:47)(cid:53)(cid:52)(cid:48)(cid:53)(cid:52) (cid:47)(cid:46)(cid:0)(cid:21)(cid:16)(cid:80)(cid:38) (cid:52) (cid:45)(cid:65)(cid:88)(cid:73)(cid:77)(cid:85)(cid:77)(cid:0)(cid:70)(cid:82)(cid:69)(cid:81)(cid:85)(cid:69)(cid:78)(cid:67)(cid:89)(cid:0)(cid:73)(cid:83)(cid:0)(cid:65)(cid:67)(cid:72)(cid:73)(cid:69)(cid:86)(cid:69)(cid:68)(cid:0)(cid:73)(cid:70)(cid:0)(cid:8)(cid:84)(cid:82)(cid:0)(cid:11)(cid:0)(cid:84)(cid:70)(cid:9)(cid:0)(cid:148)(cid:0)(cid:18)(cid:15)(cid:19)(cid:9)(cid:52)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:73)(cid:70)(cid:0)(cid:84)(cid:72)(cid:69)(cid:0)(cid:68)(cid:85)(cid:84)(cid:89)(cid:0)(cid:67)(cid:89)(cid:67)(cid:76)(cid:69)(cid:0)(cid:73)(cid:83)(cid:0)(cid:8)(cid:20)(cid:21)(cid:13)(cid:21)(cid:21)(cid:5)(cid:9)(cid:0) (cid:87)(cid:72)(cid:69)(cid:78)(cid:0)(cid:76)(cid:79)(cid:65)(cid:68)(cid:69)(cid:68)(cid:0)(cid:66)(cid:89)(cid:0)(cid:21)(cid:16)(cid:80)(cid:38) (cid:0) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:19)(cid:17)(cid:67) 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R (see Table 44) PU Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 12. Table 44. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit NRST input low level V (1) - - - 0.3 V IL(NRST) voltage DD NRST input high V (1) - 0.39V +0.59 - - IH(NRST) level voltage DD V I = 2 mA OL - - V (1) NRST output low 2.7 V < VDD < 3.6 V 0.4 OL(NRST) level voltage I = 1.5 mA OL - - 1.65 V < V < 2.7 V DD NRST Schmitt trigger V (1) - - 10%V (2) - mV hys(NRST) voltage hysteresis DD Weak pull-up R V = V 25 45 65 kΩ PU equivalent resistor(3) IN SS NRST input filtered V (1) - - - 50 ns F(NRST) pulse NRST input not V (3) - 350 - - ns NF(NRST) filtered pulse 1. Guaranteed by design. 2. With a minimum of 200 mV. 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 86/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 16. Recommended NRST pin protection (cid:57) (cid:39)(cid:39) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:11)(cid:20)(cid:12) (cid:49)(cid:53)(cid:54)(cid:55)(cid:11)(cid:21)(cid:12) (cid:53)(cid:51)(cid:56) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:20)(cid:3)(cid:151)(cid:41) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:47)(cid:20)(cid:91)(cid:91) (cid:68)(cid:76)(cid:20)(cid:26)(cid:27)(cid:24)(cid:23)(cid:69) 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table 44. Otherwise the reset will not be taken into account by the device. 6.3.15 TIM timer characteristics The parameters given in the Table 45 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction characteristics (output compare, input capture, external clock, PWM output). Table 45. TIMx(1) characteristics Symbol Parameter Conditions Min Max Unit - 1 - t TIMxCLK t Timer resolution time res(TIM) f = 32 MHz 31.25 - ns TIMxCLK Timer external clock - 0 fTIMxCLK/2 MHz f EXT frequency on CH1 to CH4 f = 32 MHz 0 16 MHz TIMxCLK Res Timer resolution - 16 bit TIM 16-bit counter clock - 1 65536 t TIMxCLK period when internal clock t COUNTER is selected (timer’s f = 32 MHz 0.0312 2048 µs TIMxCLK prescaler disabled) - - 65536 × 65536 t TIMxCLK t Maximum possible count MAX_COUNT f = 32 MHz - 134.2 s TIMxCLK 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. DocID027267 Rev 4 87/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.16 Communications interfaces I2C interface characteristics The device I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 46. Refer also to Section 6.3.13: I/O port characteristics for more details on the input/output ction characteristics (SDA and SCL). Table 46. I2C characteristics Standard mode Fast mode I2C(1)(2) I2C(1)(2) Symbol Parameter Unit Min Max Min Max t SCL clock low time 4.7 - 1.3 - w(SCLL) µs t SCL clock high time 4.0 - 0.6 - w(SCLH) t SDA setup time 250 - 100 - su(SDA) t SDA data hold time - 3450(3) - 900(3) h(SDA) tr(SDA) SDA and SCL rise time - 1000 - 300 ns t r(SCL) t f(SDA) SDA and SCL fall time - 300 - 300 t f(SCL) t Start condition hold time 4.0 - 0.6 - h(STA) µs Repeated Start condition t 4.7 - 0.6 - su(STA) setup time t Stop condition setup time 4.0 - 0.6 - μs su(STO) Stop to Start condition time t 4.7 - 1.3 - μs w(STO:STA) (bus free) Capacitive load for each bus C - 400 - 400 pF b line Pulse width of spikes that t are suppressed by the 0 50(4) 0 50(4) ns SP analog filter 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above t . SP(max) 88/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 17. I2C bus AC waveforms and measurement circuit (cid:115)(cid:24)(cid:24)(cid:890)(cid:47)(cid:1006)(cid:18) (cid:115)(cid:24)(cid:24)(cid:890)(cid:47)(cid:1006)(cid:18) (cid:90)(cid:87) (cid:90)(cid:87) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:62)(cid:1005)(cid:454)(cid:454) (cid:90)(cid:94) (cid:94)(cid:24)(cid:4) (cid:47)(cid:1006)(cid:18)(cid:3)(cid:271)(cid:437)(cid:400) (cid:90)(cid:94) (cid:94)(cid:18)(cid:62) (cid:94)(cid:100)(cid:4)(cid:90)(cid:100)(cid:3)(cid:90)(cid:28)(cid:87)(cid:28)(cid:4)(cid:100)(cid:28)(cid:24) (cid:94)(cid:100)(cid:4)(cid:90)(cid:100) (cid:94)(cid:100)(cid:4)(cid:90)(cid:100) (cid:410)(cid:400)(cid:437)(cid:894)(cid:94)(cid:100)(cid:4)(cid:895) (cid:94)(cid:24)(cid:4) (cid:410)(cid:296)(cid:894)(cid:94)(cid:24)(cid:4)(cid:895) (cid:410)(cid:396)(cid:894)(cid:94)(cid:24)(cid:4)(cid:895) (cid:410)(cid:400)(cid:437)(cid:894)(cid:94)(cid:24)(cid:4)(cid:895) (cid:94)(cid:100)(cid:75)(cid:87) (cid:410)(cid:400)(cid:437)(cid:894)(cid:94)(cid:100)(cid:4)(cid:855)(cid:94)(cid:100)(cid:75)(cid:895) (cid:410)(cid:346)(cid:894)(cid:94)(cid:100)(cid:4)(cid:895) (cid:410)(cid:449)(cid:894)(cid:94)(cid:18)(cid:60)(cid:62)(cid:895) (cid:410)(cid:346)(cid:894)(cid:94)(cid:24)(cid:4)(cid:895) (cid:94)(cid:18)(cid:62) (cid:410)(cid:449)(cid:894)(cid:94)(cid:18)(cid:60)(cid:44)(cid:895) (cid:410)(cid:396)(cid:894)(cid:94)(cid:18)(cid:60)(cid:895) (cid:410)(cid:296)(cid:894)(cid:94)(cid:18)(cid:60)(cid:895) (cid:410)(cid:400)(cid:437)(cid:894)(cid:94)(cid:100)(cid:75)(cid:895) (cid:258)(cid:349)(cid:1005)(cid:1011)(cid:1012)(cid:1009)(cid:1009)(cid:272) 1. R = series protection resistor. S 2. R = external pull-up resistor. P 3. V is the I2C bus power supply. DD_I2C 4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 47. SCL frequency (f = 32 MHz, V = V = 3.3 V)(1)(2) PCLK1 DD DD_I2C I2C_CCR value f (kHz) SCL R = 4.7 kΩ P 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 1. R = External pull-up resistance, f = I2C speed. P SCL 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external components used to design the application. DocID027267 Rev 4 89/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under the conditions summarized in Table 12. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 48. SPI characteristics(1) Symbol Parameter Conditions Min Max(2) Unit Master mode - 16 f SCK SPI clock frequency Slave mode - 16 1/t MHz c(SCK) Slave transmitter - 12(3) t (2) r(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF - 6 ns t (2) f(SCK) DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 % t NSS setup time Slave mode 4t - su(NSS) HCLK t NSS hold time Slave mode 2t - h(NSS) HCLK t (2) w(SCKH) SCK high and low time Master mode t /2 − 5 t /2 +3 t (2) SCK SCK w(SCKL) t (2) Master mode 5 - su(MI) Data input setup time t (2) Slave mode 6 - su(SI) th(MI)(2) Master mode 5 - ns Data input hold time t (2) Slave mode 5 - h(SI) t (4) Data output access time Slave mode 0 3t a(SO) HCLK t (2) Data output valid time Slave mode - 33 v(SO) t (2) Data output valid time Master mode - 6.5 v(MO) t (2) Slave mode 17 - h(SO) Data output hold time t (2) Master mode 0.5 - h(MO) 1. The characteristics above are given for voltage range 1. 2. Guaranteed by characterization results. 3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%. 4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 90/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 18. SPI timing diagram - slave mode and CPHA = 0 Figure 19. SPI timing diagram - slave mode and CPHA = 1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:81) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:46)(cid:3)(cid:76) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:43)(cid:12) (cid:38) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:47)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:3)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24)(cid:69) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. DocID027267 Rev 4 91/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Figure 20. SPI timing diagram - master mode(1) (cid:43)(cid:76)(cid:74)(cid:75) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:86)(cid:88)(cid:11)(cid:48)(cid:44)(cid:12) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:48)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:89)(cid:11)(cid:48)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:48)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:25)(cid:70) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. 92/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics USB characteristics The USB interface is USB-IF certified (full speed). Table 49. USB startup time Symbol Parameter Max Unit t (1) USB transceiver startup time 1 µs STARTUP 1. Guaranteed by design. Table 50. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit Input levels V USB operating voltage - 3.0 3.6 V DD V (2) Differential input sensitivity I(USB_DP, USB_DM) 0.2 - DI V (2) Differential common mode range Includes V range 0.8 2.5 V CM DI V (2) Single ended receiver threshold - 1.3 2.0 SE Output levels V (3) Static output level low R of 1.5 kΩ to 3.6 V(4) - 0.3 OL L V V (3) Static output level high R of 15 kΩ to V (4) 2.8 3.6 OH L SS 1. All the voltages are measured from the local ground potential. 2. Guaranteed by characterization results. 3. Guaranteed by test in production. 4. RL is the load connected on the USB drivers. Figure 21. USB timings: definition of data signal rise and fall time (cid:38)(cid:85)(cid:82)(cid:86)(cid:86)(cid:3)(cid:82)(cid:89)(cid:72)(cid:85) (cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:86) (cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:86) (cid:57)(cid:38)(cid:53)(cid:54) (cid:57)(cid:54)(cid:54) (cid:87)(cid:73) (cid:87)(cid:85) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:26)(cid:69) Table 51. USB: full speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit t Rise time(2) C = 50 pF 4 20 ns r L t Fall Time(2) C = 50 pF 4 20 ns f L t Rise/ fall time matching t/t 90 110 % rfm r f V Output signal crossover voltage 1.3 2.0 V CRS DocID027267 Rev 4 93/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). I2S characteristics Table 52. I2S characteristics Symbol Parameter Conditions Min Max Unit f I2S Main Clock Output 256 x 8K 256xFs (1) MHz MCK Master data: 32 bits - 64xFs f I2S clock frequency MHz CK Slave data: 32 bits - 64xFs D I2S clock frequency duty cycle Slave receiver, 48KHz 30 70 % CK t I2S clock rise time 8 r(CK) Capacitive load CL=30pF - t I2S clock fall time 8 f(CK) t WS valid time Master mode 4 24 v(WS) t WS hold time Master mode 0 - h(WS) t WS setup time Slave mode 15 - su(WS) t WS hold time Slave mode 0 - h(WS) t Data input setup time Master receiver 8 - su(SD_MR) t Data input setup time Slave receiver 9 - su(SD_SR) ns t Master receiver 5 - h(SD_MR) Data input hold time t Slave receiver 4 - h(SD_SR) Slave transmitter t Data output valid time - 64 v(SD_ST) (after enable edge) Slave transmitter t Data output hold time 22 - h(SD_ST) (after enable edge) Master transmitter t Data output valid time - 12 v(SD_MT) (after enable edge) Master transmitter t Data output hold time 8 - h(SD_MT) (after enable edge) 1. The maximum for 256xFs is 8 MHz Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), f , f and D values. These values reflect only the digital peripheral MCK CK CK behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. 94/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 22. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 23. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID027267 Rev 4 95/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 6.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 54 are guaranteed by design. Table 53. ADC clock frequency Symbol Parameter Conditions Min Max Unit V V 16 REF+ = DDA V < V REF+ DDA 8 2.4 V ≤ V ≤ 3.6 V V > 2.4 V DDA REF+ Voltage fADC AfreDqCu ecnloccyk range 1 & 2 VVRREEFF++ <≤ 2V.4D DVA 0.480 4 MHz V V 8 1.8 V ≤ V ≤ 2.4 V REF+ = DDA DDA V < V 4 REF+ DDA Voltage range 3 4 Table 54. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V Power supply - 1.8 - 3.6 DDA V Positive reference voltage - 1.8(1) - V V REF+ DDA V Negative reference voltage - - V - REF- SSA I Current on the V input pin - - 1000 1450 VDDA DDA µA Peak - 700 I (2) Current on the V input pin 400 VREF REF Average - 450 V Conversion voltage range(3) - 0(4) - V V AIN REF+ Direct channels - - 1 12-bit sampling rate Msps Multiplexed channels - - 0.76 Direct channels - - 1.07 10-bit sampling rate Msps Multiplexed channels - - 0.8 f S Direct channels - - 1.23 8-bit sampling rate Msps Multiplexed channels - - 0.89 Direct channels - - 1.45 6-bit sampling rate Msps Multiplexed channels - - 1 96/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Table 54. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Direct channels 0.25 - - 2.4 V ≤ V ≤ 3.6 V DDA Multiplexed channels 0.56 - - 2.4 V ≤ V ≤ 3.6 V DDA µs t (5) Sampling time Direct channels S 0.56 - - 1.8 V ≤ V ≤ 2.4 V DDA Multiplexed channels 1 - - 1.8 V ≤ V ≤ 2.4 V DDA - 4 - 384 1/f ADC f = 16 MHz 1 - 24.75 µs ADC Total conversion time tCONV (including sampling time) - 4 to 384 (sampling phase) +12 1/f (successive approximation) ADC Internal sample and hold Direct channels - - C 16 pF ADC capacitor Multiplexed channels - - External trigger frequency 12-bit conversions - - Tconv+1 1/fADC f TRIG Regular sequencer 6/8/10-bit conversions - - Tconv 1/f ADC External trigger frequency 12-bit conversions - - Tconv+2 1/fADC f TRIG Injected sequencer 6/8/10-bit conversions - - Tconv+1 1/f ADC R (6) Signal source impedance - - 50 kΩ AIN Injection trigger conversion fADC = 16 MHz 219 - 281 ns t lat latency - 3.5 - 4.5 1/f ADC Regular trigger conversion fADC = 16 MHz 156 - 219 ns t latr latency - 2.5 - 3.5 1/f ADC t Power-up time - - - 3.5 µs STAB 1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 3. V can be internally connected to V and V can be internally connected to V , depending on the package. REF+ DDA REF- SSA Refer to Section 4: Pin descriptions for further details. 4. V or V must be tied to ground. SSA REF- 5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 56: Maximum source impedance RAIN max. 6. External impedance has another high value limitation when using short sampling time as defined in Table 56: Maximum source impedance RAIN max. DocID027267 Rev 4 97/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 55. ADC accuracy(1)(2) Symbol Parameter Test conditions Min(3) Typ Max(3) Unit ET Total unadjusted error - 2.5 4 EO Offset error 2.4 V ≤ VDDA ≤ 3.6 V - 1 2 EG Gain error 2.4 V ≤ VREF+ ≤ 3.6 V - 1.5 3.5 LSB f = 8 MHz, R = 50 Ω ADC AIN ED Differential linearity error T = -40 to 105 °C - 1 2 A EL Integral linearity error - 2.2 3 ENOB Effective number of bits 9.2 10 - bits 2.4 V ≤ VDDA ≤ 3.6 V SINAD Signal-to-noise and VDDA = VREF+ 57.5 62 - distortion ratio f = 16 MHz, R = 50 Ω ADC AIN SNR Signal-to-noise ratio TA = -40 to 105 °C 57.5 62 - dB F =10kHz input THD Total harmonic distortion - -70 -65 ENOB Effective number of bits 9.2 10 - bits 1.8 V ≤ VDDA ≤ 2.4 V SINAD Signal-to-noise and VDDA = VREF+ 57.5 62 - distortion ratio f = 8 MHz or 4 MHz, R = 50 Ω ADC AIN SNR Signal-to-noise ratio TA = -40 to 105 °C 57.5 62 - dB F =10kHz input THD Total harmonic distortion - -70 -65 ET Total unadjusted error - 4 6.5 EO Offset error 2.4 V ≤ VDDA ≤ 3.6 V - 1.5 4 EG Gain error 1.8 V ≤ VREF+ ≤ 2.4 V - 3.5 6 LSB f = 4 MHz, R = 50 Ω ADC AIN ED Differential linearity error T = -40 to 105 °C - 1 2 A EL Integral linearity error - 2.5 3 ET Total unadjusted error - 2 3 EO Offset error 1.8 V ≤ VDDA ≤ 2.4 V - 1 1.5 EG Gain error 1.8 V ≤ VREF+ ≤ 2.4 V - 1.5 2 LSB f = 4 MHz, R = 50 Ω ADC AIN ED Differential linearity error T = -40 to 105 °C - 1 2 A EL Integral linearity error - 2.2 3 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for I and ΣI in Section 6.3.12 does not affect the ADC INJ(PIN) INJ(PIN) accuracy. 3. Guaranteed by characterization results. 98/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics Figure 24. ADC accuracy characteristics (cid:62)(cid:20)(cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:39)(cid:40)(cid:36)(cid:47)(cid:3)(cid:32)(cid:3)(cid:57)(cid:23)(cid:53)(cid:19)(cid:40)(cid:28)(cid:41)(cid:14)(cid:25) (cid:11)(cid:82)(cid:85)(cid:3)(cid:3)(cid:3)(cid:3)(cid:57)(cid:23)(cid:3)(cid:3)(cid:19)(cid:39)(cid:3)(cid:3)(cid:28)(cid:39)(cid:3)(cid:3)(cid:25)(cid:36)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:71)(cid:72)(cid:83)(cid:72)(cid:81)(cid:71)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:81)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:12) (cid:40)(cid:42) (cid:11)(cid:20)(cid:12)(cid:3)(cid:40)(cid:91)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:82)(cid:73)(cid:3)(cid:68)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:24) (cid:11)(cid:21)(cid:12)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:23) (cid:11)(cid:22)(cid:12)(cid:3)(cid:40)(cid:81)(cid:71)(cid:3)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72) (cid:23)(cid:19)(cid:28)(cid:22) (cid:11)(cid:21)(cid:12) (cid:40)(cid:55)(cid:3)(cid:32)(cid:3)(cid:55)(cid:82)(cid:87)(cid:68)(cid:79)(cid:3)(cid:88)(cid:81)(cid:68)(cid:71)(cid:77)(cid:88)(cid:86)(cid:87)(cid:72)(cid:71)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:40)(cid:55) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72)(cid:86)(cid:17) (cid:26) (cid:11)(cid:22)(cid:12) (cid:40)(cid:50)(cid:3)(cid:32)(cid:3)(cid:50)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79) (cid:11)(cid:20)(cid:12) (cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:25) (cid:40)(cid:42)(cid:3)(cid:32)(cid:3)(cid:42)(cid:68)(cid:76)(cid:81)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79) (cid:24) (cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:23) (cid:40)(cid:50) (cid:40)(cid:47) (cid:40)(cid:39)(cid:3)(cid:32)(cid:3)(cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:86)(cid:87)(cid:72)(cid:83)(cid:86)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:22) (cid:40)(cid:39) (cid:40)(cid:47)(cid:3)(cid:32)(cid:3)(cid:44)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:21) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:81)(cid:92)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:72)(cid:81)(cid:71)(cid:16)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87) (cid:20)(cid:3)(cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:39)(cid:40)(cid:36)(cid:47) (cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:17) (cid:20) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:23)(cid:19)(cid:28)(cid:22)(cid:23)(cid:19)(cid:28)(cid:23)(cid:23)(cid:19)(cid:28)(cid:24)(cid:23)(cid:19)(cid:28)(cid:25) (cid:57)(cid:54)(cid:54)(cid:36) (cid:57)(cid:39)(cid:39)(cid:36) (cid:68)(cid:76)(cid:20)(cid:23)(cid:22)(cid:28)(cid:24)(cid:72) Figure 25. Typical connection diagram using the ADC (cid:57)(cid:39)(cid:39)(cid:36) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:47)(cid:91)(cid:91) (cid:54)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:75)(cid:82)(cid:79)(cid:71)(cid:3) (cid:36)(cid:39)(cid:38)(cid:3)(cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:53)(cid:36)(cid:44)(cid:49)(cid:11)(cid:20)(cid:12) (cid:36)(cid:44)(cid:49)(cid:91) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:44)(cid:47)(cid:147)(cid:3)(cid:24)(cid:19)(cid:3)(cid:81)(cid:36) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:38)(cid:83)(cid:68)(cid:85)(cid:68)(cid:86)(cid:76)(cid:87)(cid:76)(cid:70) (cid:57)(cid:36)(cid:44)(cid:49) (cid:38)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:26)(cid:27)(cid:24)(cid:25)(cid:72) 1. Refer to Table 56: Maximum source impedance RAIN max for the value of R and Table 54: ADC AIN characteristics for the value of C . ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7 pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC DocID027267 Rev 4 99/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Figure 26. Maximum dynamic current consumption on V supply pin during ADC REF+ conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700µA 300µA MS36686V1 Table 56. Maximum source impedance R max(1) AIN R max (kΩ) AIN Ts Ts (cycles) Multiplexed channels Direct channels (µs) f =16 MHz(2) ADC 2.4 V < V < 3.6 V 1.8 V < V < 2.4 V 2.4 V < V < 3.6 V 1.8 V < V < 2.4 V DDA DDA DDA DDA 0.25 Not allowed Not allowed 0.7 Not allowed 4 0.5625 0.8 Not allowed 2.0 1.0 9 1 2.0 0.8 4.0 3.0 16 1.5 3.0 1.8 6.0 4.5 24 3 6.8 4.0 15.0 10.0 48 6 15.0 10.0 30.0 20.0 96 12 32.0 25.0 50.0 40.0 192 24 50.0 50.0 50.0 50.0 384 1. Guaranteed by design. 2. Number of samples calculated for f = 16 MHz. For f = 8 and 4 MHz the number of sampling cycles can be reduced ADC ADC with respect to the minimum sampling time Ts (µs), General PCB design guidelines Power supply decoupling should be performed as shown in Figure 8. The applicable procedure depends on whether V is connected to V or not. The 100 nF capacitors REF+ DDA should be ceramic (good quality). They should be placed as close as possible to the chip. 100/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.18 DAC electrical specifications Data guaranteed by design, unless otherwise specified. Table 57. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit V Analog supply voltage - 1.8 - 3.6 DDA V Reference supply VREF+ must always be below 1.8 - 3.6 V REF+ voltage V DDA V Lower reference voltage - V REF- SSA Current consumption on No load, middle code (0x800) - 130 220 I (1) V supply DDVREF+ REF+ V = 3.3 V No load, worst code (0x000) - 220 350 REF+ µA Current consumption on No load, middle code (0x800) - 210 320 I (1) V supply DDA DDA V = 3.3 V No load, worst code (0xF1C) - 320 520 DDA Connected to 5 - - R Resistive load DAC output VSSA kΩ L buffer ON Conected to 25 - - V DDA C (2) Capacitive load DAC output buffer ON - - 50 pF L R Output impedance DAC output buffer OFF 12 16 20 kΩ O DAC output buffer ON 0.2 - V – 0.2 V DDA Voltage on DAC_OUT V DAC_OUT output V – DAC output buffer OFF 0.5 - REF+ mV 1LSB C ≤ 50 pF, R ≥ 5 kΩ L L - 1.5 3 Differential non DAC output buffer ON DNL(1) linearity(3) No R , C ≤ 50 pF L L - 1.5 3 DAC output buffer OFF C ≤ 50 pF, R ≥ 5 kΩ L L - 2 4 DAC output buffer ON INL(1) Integral non linearity(4) No RL, CL ≤ 50 pF - 2 4 LSB DAC output buffer OFF C ≤ 50 pF, R ≥ 5 kΩ L L - ±10 ±25 Offset error at code DAC output buffer ON Offset(1) 0x800 (5) No R , C ≤ 50 pF L L - ±5 ±8 DAC output buffer OFF Offset error at code No R , C ≤ 50 pF Offset1(1) L L - ±1.5 ±5 0x001(6) DAC output buffer OFF DocID027267 Rev 4 101/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 57. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit V = 3.3V DDA V = 3.0V REF+ -20 -10 0 T = 0 to 50 °C A Offset error temperature DAC output buffer OFF dOffset/dT(1) µV/°C coefficient (code 0x800) V = 3.3V DDA V = 3.0V REF+ 0 20 50 T = 0 to 50 °C A DAC output buffer ON C ≤ 50 pF, R ≥ 5 kΩ L L - +0.1 / -0.2% +0.2 / -0.5% DAC output buffer ON Gain(1) Gain error(7) % No R , C ≤ 50 pF L L - +0 / -0.2% +0 / -0.4% DAC output buffer OFF V = 3.3V DDA V = 3.0V REF+ -10 -2 0 T = 0 to 50 °C A Gain error temperature DAC output buffer OFF dGain/dT(1) µV/°C coefficient V = 3.3V DDA V = 3.0V REF+ -40 -8 0 T = 0 to 50 °C A DAC output buffer ON C ≤ 50 pF, R ≥ 5 kΩ L L - 12 30 DAC output buffer ON TUE(1) Total unadjusted error LSB No R , C ≤ 50 pF L L - 8 12 DAC output buffer OFF Settling time (full scale: for a 12-bit code transition between the t lowest and the highest C ≤ 50 pF, R ≥ 5 kΩ - 7 12 µs SETTLING L L input codes till DAC_OUT reaches final value ±1LSB Max frequency for a correct DAC_OUT change (95% of final Update rate C ≤ 50 pF, R ≥ 5 kΩ - - 1 Msps value) with 1 LSB L L variation in the input code Wakeup time from off state (setting the ENx bit t C ≤ 50 pF, R ≥ 5 kΩ - 9 15 µs WAKEUP in the DAC Control L L register)(8) V supply rejection DDA PSRR+ ratio (static DC C ≤ 50 pF, R ≥ 5 kΩ - -60 -35 dB L L measurement) 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 102/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = V /2. REF+ 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 27. 12-bit buffered /non-buffered DAC (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:18)(cid:49)(cid:82)(cid:81)(cid:16)(cid:69)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:3)(cid:39)(cid:36)(cid:38) (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:11)(cid:20)(cid:12) (cid:53)(cid:47) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87)(cid:3) (cid:39)(cid:36)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55)(cid:91) (cid:71)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79)(cid:3)(cid:87)(cid:82)(cid:3) (cid:68)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74)(cid:3) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85)(cid:3) (cid:38) (cid:47) (cid:65)(cid:73)(cid:17)(cid:23)(cid:17)(cid:21)(cid:23)(cid:54)(cid:19) 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.19 Operational amplifier characteristics Table 58. Operational amplifier characteristics Symbol Parameter Condition(1) Min(2) Typ Max(2) Unit CMIR Common mode input range - 0 - V DD Maximum - - - ±15 calibration range VI Input offset voltage mV OFFSET After offset - - - ±1.5 calibration Input offset voltage Normal mode - - - ±40 µV/°C ΔVI OFFSET drift Low-power mode - - - ±80 Dedicated input - - 1 IIB Input current bias General purpose 75 °C nA - - 10 input Normal mode - - - 500 I Drive current µA LOAD Low-power mode - - - 100 Normal mode No load, - 100 220 I Consumption µA DD quiescent mode Low-power mode - 30 60 Common mode Normal mode - - -85 - CMRR dB rejection ration Low-power mode - - -90 - DocID027267 Rev 4 103/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X Table 58. Operational amplifier characteristics (continued) Symbol Parameter Condition(1) Min(2) Typ Max(2) Unit Power supply Normal mode - -85 - PSRR DC dB rejection ratio Low-power mode - -90 - Normal mode 400 1000 3000 V >2.4 V DD Low-power mode 150 300 800 GBW Bandwidth kHZ Normal mode 200 500 2200 V <2.4 V DD Low-power mode 70 150 800 V >2.4 V DD Normal mode (between 0.1 V and - 700 - V -0.1 V) DD SR Slew rate Low-power mode V >2.4 V - 100 - V/ms DD Normal mode - 300 - V <2.4 V DD Low-power mode - 50 - Normal mode 55 100 - AO Open loop gain dB Low-power mode 65 110 - Normal mode 4 - - R Resistive load V <2.4 V kΩ L DD Low-power mode 20 - - C Capacitive load - - - 50 pF L V - VOH High saturation Normal mode 1D0D0 - - SAT voltage Low-power mode ILOAD = max or VDD-50 - - mV R = min L Low saturation Normal mode - - 100 VOL SAT voltage Low-power mode - - 50 ϕm Phase margin - - 60 - ° GM Gain margin - - -12 - dB Offset trim time: during calibration, t minimum time needed between two - - 1 - ms OFFTRIM steps to have 1 mV accuracy C ≤ 50 pf, Normal mode L - 10 - R ≥ 4 kΩ L t Wakeup time µs WAKEUP C ≤ 50 pf, Low-power mode L - 30 - R ≥ 20 kΩ L 1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when V is below 2 V. Otherwise to the full DD ambient temperature range (-40 °C to 85 °C, -40 °C to 105 °C). 2. Guaranteed by characterization results. 104/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.20 Temperature sensor characteristics Table 59. Temperature sensor calibration values Calibration value name Description Memory address TS ADC raw data acquired at TS_CAL1 temperature of 30 °C ±5 °C 0x1FF8 00FA - 0x1FF8 00FB V = 3 V ±10 mV DDA TS ADC raw data acquired at TS_CAL2 temperature of 110 °C ±5 °C 0x1FF8 00FE - 0x1FF8 00FF V = 3 V ±10 mV DDA Table 60. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit T (1) V linearity with temperature - ±1 ±2 °C L SENSE Avg_Slope(1) Average slope 1.48 1.61 1.75 mV/°C V Voltage at 110°C ±5°C(2) 612 626.8 641.5 mV 110 I (3) Current consumption - 3.4 6 µA DDA(TEMP) t (3) Startup time - - 10 START µs ADC sampling time when reading the T (3) 4 - - S_temp temperature 1. Guaranteed by characterization results. 2. Measured at V = 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte. DD 3. Guaranteed by design. 6.3.21 Comparator Table 61. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit V Analog supply voltage - 1.65 3.6 V DDA R R value - - 400 - 400K 400K kΩ R R value - - 10 - 10K 10K Comparator 1 input V - 0.6 - V V IN voltage range DDA t Comparator startup time - - 7 10 START µs td Propagation delay(2) - - 3 10 Voffset Comparator offset - - ±3 ±10 mV V = 3.6 V Comparator offset DDA V = 0 V d /dt variation in worst voltage IN+ 0 1.5 10 mV/1000 h Voffset stress conditions VIN- = VREFINT T = 25 °C A I Current consumption(3) - - 160 260 nA COMP1 DocID027267 Rev 4 105/119 107

Electrical characteristics STM32L151VD-X STM32L152VD-X 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non- inverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Table 62. Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max(1) Unit V Analog supply voltage - 1.65 - 3.6 V DDA V Comparator 2 input voltage range - 0 - V V IN DDA Fast mode - 15 20 t Comparator startup time START Slow mode - 20 25 1.65 V ≤ V ≤ 2.7 V - 1.8 3.5 t Propagation delay(2) in slow mode DDA µs d slow 2.7 V ≤ V ≤ 3.6 V - 2.5 6 DDA 1.65 V ≤ V ≤ 2.7 V - 0.8 2 t Propagation delay(2) in fast mode DDA d fast 2.7 V ≤ V ≤ 3.6 V - 1.2 4 DDA V Comparator offset error - ±4 ±20 mV offset V = 3.3V DDA T = 0 to 50 °C A dThreshold/ Threshold voltage temperature V- =V , ppm REFINT - 15 100 dt coefficient 3/4 V , /°C REFINT 1/2 V , REFINT 1/4 V . REFINT Fast mode - 3.5 5 I Current consumption(3) µA COMP2 Slow mode - 0.5 2 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non- inverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 106/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Electrical characteristics 6.3.22 LCD controller The device embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the V voltage. An external capacitor C must be connected to the DD ext V pin to decouple this converter. LCD Table 63. LCD controller characteristics Symbol Parameter Min Typ Max Unit V LCD external voltage - - 3.6 LCD V LCD internal reference voltage 0 - 2.6 - LCD0 V LCD internal reference voltage 1 - 2.73 - LCD1 V LCD internal reference voltage 2 - 2.86 - LCD2 V LCD internal reference voltage 3 - 2.98 - V LCD3 V LCD internal reference voltage 4 - 3.12 - LCD4 V LCD internal reference voltage 5 - 3.26 - LCD5 V LCD internal reference voltage 6 - 3.4 - LCD6 V LCD internal reference voltage 7 - 3.55 - LCD7 C V external capacitance 0.1 - 2 µF ext LCD Supply current at V = 2.2 V - 3.3 - I (1) DD µA LCD Supply current at V = 3.0 V - 3.1 - DD R (2) Low drive resistive network overall value 5.28 6.6 7.92 MΩ Htot R (2) High drive resistive network total value 192 240 288 kΩ L V Segment/Common highest level voltage - - V V 44 LCD V Segment/Common 3/4 level voltage - 3/4 V - 34 LCD V Segment/Common 2/3 level voltage - 2/3 V - 23 LCD V Segment/Common 1/2 level voltage - 1/2 V - 12 LCD V V Segment/Common 1/3 level voltage - 1/3 V - 13 LCD V Segment/Common 1/4 level voltage - 1/4 V - 14 LCD V Segment/Common lowest level voltage 0 - - 0 Segment/Common level voltage error ΔVxx(3) - - ± 50 mV T = -40 to 105 °C A 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 2. Guaranteed by design. 3. Guaranteed by characterization results. DocID027267 Rev 4 107/119 107

Package information STM32L151VD-X STM32L152VD-X 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information Figure 28. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:33) (cid:18) (cid:17) (cid:33) (cid:33) (cid:67) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:44) (cid:33)(cid:17) (cid:43) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:23)(cid:21) (cid:21)(cid:17) (cid:21)(cid:16) (cid:23)(cid:22) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:17) (cid:18)(cid:21) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:69) (cid:17)(cid:44)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:21) 1. Drawing is not to scale. Table 64. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 108/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Package information Table 64. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 29. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint (cid:23)(cid:21) (cid:21)(cid:17) (cid:23)(cid:22) (cid:21)(cid:16) (cid:16)(cid:14)(cid:21) (cid:16)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:17)(cid:20)(cid:14)(cid:19) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:17)(cid:14)(cid:18) (cid:17) (cid:18)(cid:21) (cid:17)(cid:18)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:48)(cid:54)(cid:22)(cid:23)(cid:20)(cid:26)(cid:28)(cid:57)(cid:20) 1. Dimensions are in millimeters. DocID027267 Rev 4 109/119 118

Package information STM32L151VD-X STM32L152VD-X LQFP100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 30. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:47)(cid:20)(cid:24)(cid:21) (cid:57)(cid:39)(cid:55)(cid:25)(cid:59)(cid:3)(cid:3)(cid:3)(cid:53) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3) (cid:76)(cid:81)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:25)(cid:23)(cid:22)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 110/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Package information 7.2 WLCSP104, 0.4 mm pitch wafer level chip scale package information Figure 31. WLCSP104, 0.4 mm pitch wafer level chip scale package outline (cid:72)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:69)(cid:69)(cid:69)(cid:61) (cid:41) (cid:42) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:72)(cid:21) (cid:72) (cid:36)(cid:22) (cid:72) (cid:36)(cid:21) (cid:36) (cid:37)(cid:82)(cid:87)(cid:87)(cid:82)(cid:80)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:37)(cid:88)(cid:80)(cid:83)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:54)(cid:76)(cid:71)(cid:72)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:59) (cid:60) (cid:39) (cid:37)(cid:88)(cid:80)(cid:83) (cid:36)(cid:22) (cid:40) (cid:72)(cid:72)(cid:72) (cid:61) (cid:36)(cid:20) (cid:85)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72) (cid:145)(cid:69)(cid:3)(cid:3) (cid:145)(cid:272)(cid:272)(cid:272) (cid:48) (cid:61) (cid:59) (cid:60) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74) (cid:61) (cid:36)(cid:20)(cid:3)(cid:82)(cid:85)(cid:76)(cid:72)(cid:81)(cid:87)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:145)(cid:282)(cid:282)(cid:282)(cid:48) (cid:61) (cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:68)(cid:68)(cid:68) (cid:61) (cid:53)(cid:82)(cid:87)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:28)(cid:19)(cid:131) (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:58)(cid:68)(cid:73)(cid:72)(cid:85)(cid:3)(cid:69)(cid:68)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:4)(cid:1004)(cid:122)(cid:122)(cid:890)(cid:68)(cid:28)(cid:890)(cid:115)(cid:1006) 1. Drawing is not to scale. DocID027267 Rev 4 111/119 118

Package information STM32L151VD-X STM32L152VD-X T able 65. WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.023 A1 - 0.175 - - 0.0069 - A2 - 0.38 - - 0.015 - A3(2) - 0.025 - - 0.001 - ø b(3) 0.22 0.25 0.28 0.0087 0.0098 0.011 D 4.06 4.095 4.13 0.1598 0.1612 0.1626 E 5.059 5.094 5.129 0.1992 0.2006 0.2019 e - 0.4 - - 0.0157 - e1 - 3.2 - - 0.126 - e2 - 4.4 - - 0.1732 - F - 0.447 - - 0.0176 - G - 0.347 - - 0.0137 - aaa - - 0.1 - - 0.0039 bbb - - 0.1 - - 0.0039 ccc - - 0.1 - - 0.0039 ddd - - 0.05 - - 0.002 eee - - 0.05 - - 0.002 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 32. WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:48)(cid:54)(cid:20)(cid:27)(cid:28)(cid:25)(cid:24)(cid:57)(cid:21) 112/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Package information Table 66. WLCSP104, 0.4 mm pitch recommended PCB design rules Dimension Recommended values Pitch 0.4 260 µm max. (circular) Dpad 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. WLCSP104 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 33. WLCSP104, 0.4 mm pitch wafer level chip scale package top view example (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:20)(cid:19)(cid:45)(cid:18)(cid:22)(cid:18)(cid:55)(cid:37)(cid:58)(cid:23)(cid:57) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:51) (cid:37)(cid:68)(cid:79)(cid:79)(cid:3)(cid:36)(cid:20) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:22)(cid:25)(cid:25)(cid:23)(cid:23)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID027267 Rev 4 113/119 118

Package information STM32L151VD-X STM32L152VD-X 7.3 Thermal characteristics The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated J using the following equation: T max = T max + (P max × Θ ) J A D JA Where: • T max is the maximum ambient temperature in °C, A • Θ is the package junction-to-ambient thermal resistance, in °C/W, JA • P max is the sum of P max and P max (P max = P max + P max), D INT I/O D INT I/O • P max is the product of I andV , expressed in Watts. This is the maximum chip INT DD DD internal power. P max represents the maximum power dissipation on output pins where: I/O PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 67. Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction-ambient 43 LQFP100 - 14 x 14 mm / 0.5 mm pitch Θ °C/W JA Thermal resistance junction-ambient 46 WLCSP104 - 0.400 mm pitch Figure 34. Thermal resistance suffix 6 (cid:22)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:21)(cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:38)(cid:381)(cid:396)(cid:271)(cid:349)(cid:282)(cid:282)(cid:286)(cid:374)(cid:3)(cid:258)(cid:396)(cid:286)(cid:258)(cid:100)(cid:58)(cid:3)(cid:1093)(cid:3)(cid:100)(cid:58)(cid:3)(cid:373)(cid:258)(cid:454) (cid:21)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:51)(cid:39)(cid:3)(cid:11)(cid:80)(cid:58)(cid:12) (cid:116)(cid:62)(cid:18)(cid:94)(cid:87)(cid:1005)(cid:1004)(cid:1008)(cid:3)(cid:1005)(cid:1004)(cid:454)(cid:1005)(cid:1004)(cid:3)(cid:373)(cid:373) (cid:20)(cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:62)(cid:89)(cid:38)(cid:87)(cid:3)(cid:1005)(cid:1004)(cid:1004)(cid:3)(cid:1005)(cid:1008)(cid:454)(cid:1005)(cid:1008)(cid:3)(cid:373)(cid:373) (cid:20)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:19)(cid:19) (cid:20)(cid:19)(cid:19) (cid:26)(cid:24) (cid:24)(cid:19) (cid:21)(cid:24) (cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:25)(cid:23)(cid:20)(cid:57)(cid:20) 114/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Package information Figure 35. Thermal resistance suffix 7 (cid:22)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:21)(cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:38)(cid:381)(cid:396)(cid:271)(cid:349)(cid:282)(cid:282)(cid:286)(cid:374)(cid:3)(cid:258)(cid:396)(cid:286)(cid:258)(cid:100)(cid:58)(cid:3)(cid:1093)(cid:3)(cid:100)(cid:58)(cid:3)(cid:373)(cid:258)(cid:454) (cid:21)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:51)(cid:39)(cid:3)(cid:11)(cid:80)(cid:58)(cid:12) (cid:116)(cid:62)(cid:18)(cid:94)(cid:87)(cid:1005)(cid:1004)(cid:1008)(cid:3)(cid:1005)(cid:1004)(cid:454)(cid:1005)(cid:1004)(cid:3)(cid:373)(cid:373) (cid:20)(cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:62)(cid:89)(cid:38)(cid:87)(cid:3)(cid:1005)(cid:1004)(cid:1004)(cid:3)(cid:1005)(cid:1008)(cid:454)(cid:1005)(cid:1008)(cid:3)(cid:373)(cid:373) (cid:20)(cid:19)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:24)(cid:19)(cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:19)(cid:19) (cid:20)(cid:19)(cid:24) (cid:26)(cid:24) (cid:24)(cid:19) (cid:21)(cid:24) (cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:25)(cid:23)(cid:21)(cid:57)(cid:20) 7.3.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID027267 Rev 4 115/119 118

Ordering information STM32L151VD-X STM32L152VD-X 8 Ordering information Ta b le 68. STM32L151VD-X and STM32L152VD-X Ordering information scheme Example: STM32 L 151 V D Y 6 X D TR Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low-power Device subfamily 151: Devices without LCD 152: Devices with LCD Pin count V = 100/104 pins Flash memory size D=384 Kbytes of Flash memory Package T = LQFP Y = WLCSP104 Temperature range 6 = Industrial temperature range, –40 to 85 °C 7 = Industrial temperature range, –40 to 105 °C Options X = device generation X Options No character = V range: 1.8 to 3.6 V and BOR enabled DD D = V range: 1.65 to 3.6 V and BOR disabled DD Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the nearest ST sales office. 116/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X Revision History 9 Revision History Table 69. Document revision history Date Revision Changes 22-Jan-2015 1 Initial release. Updated Section 7: Package information structure: paragraph titles and paragraph heading level. Updated Section 7.1: LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information removing gate mark in Figure 30. Updated Section 7: Package information for LQFP100 & WLCSP104 package device marking adding text in for device orientation versus pin 1 / ball A1 identifier. Updated Figure 31: WLCSP104, 0.4 mm pitch wafer level chip scale package outline. Updated Table 65: WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data. 28-Apr-2015 2 Added Figure 32: WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint. Added Table 66: WLCSP104, 0.4 mm pitch recommended PCB design rules. Updated Table 7: STM32L151VD-X and STM32L152VD-X pin definitions ADC inputs. Updated Table 15: Embedded internal reference voltage temperature coefficient at 100ppm/°C and table footnote 3: “guaranteed by design” changed by “guaranteed by characterization results”. Updated Table 62: Comparator 2 characteristics new maximum threshold voltage temperature coefficient at 100ppm/°C. DocID027267 Rev 4 117/119 118

Revision History STM32L151VD-X STM32L152VD-X Table 69. Document revision history (continued) Date Revision Changes Updated cover page putting eight SPIs in the peripheral communication interface list. Updated Table 1: Ultra-low-power STM32L151VD-X and STM32L152VD-X device features and peripheral counts SPI and I2S lines. 12-Feb-2016 3 Updated Table 38: ESD absolute maximum ratings CDM class. Updated all the notes, removing ‘not tested in production’. Updated Table 9: Voltage characteristics adding note about V pin. REF- Updated Table 4: Functionalities depending on the working mode (from Run/active down to standby) LSI and LSE functionalities putting “Y” in Standby mode. Updated Table 41: I/O static characteristics pull-up and pull-down values. Updated Table 44: NRST pin characteristics pull-up values. Updated Section 7: Package information adding information about other optional marking or inset/upset marks. Updated note 1 below all the package device marking figures. Updated Section 7: Package information replacing “Marking of engineering samples” by “device marking”. Updated Nested vectored interrupt controller (NVIC) in Section 3.2: ARM® Cortex®-M3 core with MPU about process state automatically saved. Updated Table 2: Functionalities depending on the operating power 28-Aug-2017 4 supply range removing I/O operation column and adding note about GPIO speed. Updated Table 40: I/O current injection susceptibility note by ‘injection is not possible’. Updated Figure 16: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Table 57: DAC characteristics resistive load. Updated Section 3.1: Low-power modes Low-power run mode (MSI) RC oscillator clock. Updated Table 4: Functionalities depending on the working mode (from Run/active down to standby) disabling I2C functionality in Low- power Run and Low-power Sleep modes. 118/119 DocID027267 Rev 4

STM32L151VD-X STM32L152VD-X IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID027267 Rev 4 119/119 119

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: STM32L151QDH6 STM32L151VDT6 STM32L151RDT6TR STM32L152RDT6 STM32L152VDT6 STM32L152ZDT6 STM32L151RDT6 STM32L151ZDT6 STM32L152QDH6 STM32L151RDY6TR STM32L152RDY6TR STM32L151QDH6TR STM32L151RDT7 STM32L152VDT6TR STM32L151VDT7X STM32L151VDY6XTR STM32L152VDT6X