STM32F373xx ® ® ARM Cortex -M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM, timers, 4 ADCs (16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 2.0-3.6 V Datasheet - production data Features (cid:41)(cid:37)(cid:42)(cid:36) • Core: ARM® 32-bit Cortex®-M4 CPU (72 MHz max), single-cycle multiplication and HW LQFP48 (7 × 7 mm) division, DSP instruction with FPU (floating- LQFP64 (10 × 10 mm) UFBGA100 (7 x 7 mm) LQFP100 (14 × 14 mm) point unit) and MPU (memory protection unit) • 17 timers • 1.25 DMIPS/MHz (Dhrystone 2.1) – Two 32-bit timers and three 16-bit timers • Memories with up to 4 IC/OC/PWM or pulse counters – 64 to 256Kbytes of Flash memory – Two 16-bit timers with up to 2 IC/OC/PWM – 32Kbytes of SRAM with HW parity check or pulse counters • CRC calculation unit – Four 16-bit timers with up to 1 IC/OC/PWM or pulse counter • Reset and power management – Independent and system watchdog timers – Voltage range: 2.0 to 3.6V – SysTick timer: 24-bit down counter – Power-on/Power down reset (POR/PDR) – Three 16-bit basic timers to drive the DAC – Programmable voltage detector (PVD) • Calendar RTC with Alarm and periodic wakeup – Low power modes: Sleep, Stop, Standby from Stop/Standby – V supply for RTC and backup registers BAT • Communication interfaces • Clock management – CAN interface (2.0B Active) – 4 to 32MHz crystal oscillator – Two I2Cs supporting Fast Mode Plus – 32kHz oscillator for RTC with calibration (1Mbit/s) with 20 mA current sink, – Internal 8MHz RC with x16 PLL option SMBus/PMBus, wakeup from STOP – Internal 40kHz oscillator – Three USARTs supporting synchronous • Up to 84 fast I/Os mode, modem control, ISO/IEC7816, LIN, IrDA, auto baud rate, wakeup feature – All mappable on external interrupt vectors – Three SPIs (18 Mbit/s) with 4 to 16 – Up to 45 I/Os with 5 V tolerant capability programmable bit frames, muxed I2S • 12-channel DMA controller – HDMI-CEC bus interface • One 12-bit, 1.0 µs ADC (up to 16 channels) – USB 2.0 full speed interface – Conversion range: 0 to 3.6 V • Serial wire devices, JTAG, Cortex®-M4 ETM – Separate analog supply from 2.4 up to 3.6 • 96-bit unique ID • Three 16-bit Sigma Delta ADC – Separate analog supply from 2.2 to 3.6 V, Table 1. Device summary up to 21 single/ 11 diff channels Reference Part numbers • Three 12-bit DAC channels • Two fast rail-to-rail analog comparators with STM32F373C8, STM32F373R8, STM32F373V8, STM32F373CB, programmable input and output STM32F373xx STM32F373RB, STM32F373VB, • Up to 24 capacitive sensing channels STM32F373CC, STM32F373RC, STM32F373VC June 2016 DocID022691 Rev 7 1/137 This is information on a product in full production. www.st.com

Contents STM32F373xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM® Cortex®-M4 core with embedded Flash and SRAM . . . . . . . . . . . 13 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 14 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17 3.11.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 17 3.12 12-bit analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12.2 Internal voltage reference (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REFINT 3.12.3 V battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BAT 3.13 16-bit sigma delta analog-to-digital converters (SDADC) . . . . . . . . . . . . . 19 3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17.1 General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19) . . . . . 23 2/137 DocID022691 Rev 7

STM32F373xx Contents 3.17.2 Basic timers (TIM6, TIM7, TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24 3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 26 3.21 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 27 3.22 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.26 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 58 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 59 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DocID022691 Rev 7 3/137 4

Contents STM32F373xx 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.15 NRST characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.21 V monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 BAT 6.3.22 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.23 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.24 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.25 SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 128 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4/137 DocID022691 Rev 7

STM32F373xx List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Capacitive sensing GPIOs available on STM32F373xx devices . . . . . . . . . . . . . . . . . . . . 20 Table 4. No. of capacitive sensing channels available on STM32F373xx devices. . . . . . . . . . . . . . 21 Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Comparison of I2C analog and digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. STM32F373xx I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. STM32F373xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. STM32F373xx SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Legend/abbreviations used in the pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 11. STM32F373xx pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 12. Alternate functions for port PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 13. Alternate functions for port PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. Alternate functions for port PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 15. Alternate functions for port PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 16. Alternate functions for port PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 17. Alternate functions for port PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 18. STM32F373xx peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 25. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 26. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 27. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 28. Typical and maximum current consumption from V supply at V = 3.6 V . . . . . . . . . . 61 DD DD Table 29. Typical and maximum current consumption from V supply . . . . . . . . . . . . . . . . . . . . . 63 DDA Table 30. Typical and maximum V consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 63 DD Table 31. Typical and maximum V consumption in Stop and Standby modes. . . . . . . . . . . . . . . 64 DDA Table 32. Typical and maximum current consumption from V supply. . . . . . . . . . . . . . . . . . . . . . 64 BAT Table 33. Typical current consumption in Run mode, code with data processing running from Flash66 Table 34. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 67 Table 35. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 36. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39. Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 40. HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 41. LSE oscillator characteristics (f = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LSE Table 42. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 43. LSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 44. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 45. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 46. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 47. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 48. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DocID022691 Rev 7 5/137 6

List of tables STM32F373xx Table 49. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 51. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 52. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 53. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 54. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 55. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 56. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 57. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 58. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 59. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 60. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 61. R max for f = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SRC ADC Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 64. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 65. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 66. TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 67. V monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 BAT Table 68. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 69. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 70. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 71. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 72. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 73. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 74. SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 75. VREFSD+ pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 76. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 77. UFBGA100 recommended PCB design rules (0.5mm pitch BGA) . . . . . . . . . . . . . . . . . 116 Table 78. LQPF100 - 100-pin, 14 x 14mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 79. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 80. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 81. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 82. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 83. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6/137 DocID022691 Rev 7

STM32F373xx List of figures List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. STM32F373xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 3. STM32F373xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 4. STM32F373xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 5. STM32F373xx UFBGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 6. STM32F373xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 7. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 8. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 11. Typical V current consumption (LSE and RTC ON/LSEDRV[1:0]='00') . . . . . . . . . . . . 65 BAT Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 13. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 14. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 15. Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 16. HSI oscillator accuracy characterization results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 17. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . 86 Figure 19. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 21. I2C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 24. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 25. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 26. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 27. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 29. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 30. Maximum V scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . 104 REFINT Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 32. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 33. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . 116 Figure 34. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 35. LQFP100 - 100-pin, 14 x 14mm low-profile quad flat package outline . . . . . . . . . . . . . . 118 Figure 36. LQFP100 - 100-pin, 14 x 14mm low-profile quad flat recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 37. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 38. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 121 Figure 39. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 40. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 41. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 124 Figure 42. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 43. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 DocID022691 Rev 7 7/137 8

List of figures STM32F373xx Figure 44. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 D A 8/137 DocID022691 Rev 7

STM32F373xx Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F373xx microcontrollers. This STM32F373xx datasheet should be read in conjunction with the RM0313 reference manual. The reference manual is available from the STMicroelectronics website www.st.com. For information on the Cortex®-M4 with FPU core, please refer to: • Cortex®-M4 with FPU Technical Reference Manual, available from www.arm.com. • STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214) available from www.st.com. DocID022691 Rev 7 9/137 47

Description STM32F373xx 2 Description The STM32F373xx family is based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 72MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an Embedded Trace Macrocell™ (ETM). The family incorporates high-speed embedded memories (up to 256Kbyte of Flash memory, up to 32Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32F373xx devices offer one fast 12-bit ADC (1Msps), three 16-bit Sigma delta ADCs, two comparators, two DACs (DAC1 with 2 channels and DAC2 with 1 channel), a low-power RTC, 9 general-purpose 16-bit timers, two general-purpose 32-bit timers, three basic timers. They also feature standard and advanced communication interfaces: two I2Cs, three SPIs, all with muxed I2Ss, three USARTs, CAN and USB. The STM32F373xx family operates in the -40 to +85°C and -40 to +105°C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F373xx family offers devices in five packages ranging from 48 pins to 100 pins. The set of included peripherals changes with the device chosen. 10/137 DocID022691 Rev 7

STM32F373xx Description Table 2. Device overview STM32F STM32F STM32F Peripheral 373Cx 373Rx 373Vx Flash (Kbytes) 64 128 256 64 128 256 64 128 256 SRAM (Kbytes) 16 24 32 16 24 32 16 24 32 General 9 (16-bit) Timers purpose 2 (32 bit) Basic 3 (16-bit) SPI/I2S 3 I2C 2 Comm. USART 3 interfaces CAN 1 USB 1 Normal I/Os 36 52 84 (TC,TTa) GPIOs 5 volts Tolerant I/Os 20 28 45 (FT, Ftf) 12-bit ADCs 1 16-bit ADCs 3 Sigma- Delta 12-bit DACs outputs 3 Analog comparator 2 Capacitive sensing 14 17 24 channels Max. CPU frequency 72 MHz Main operating voltage 2.0 to 3.6 V 16-bit SDADC operating voltage 2.2 to 3.6 V Ambient operating temperature: Operating temperature - 40 to 85 °C / - 40 to 105 °C Junction temperature: - -40 to 125 °C LQFP100, Packages LQFP48 LQFP64 UFBGA100(1) 1. UFBGA100 package available on 256-KB versions only. DocID022691 Rev 7 11/137 47

Description STM32F373xx Figure 1. Block diagram (cid:52)(cid:82)(cid:65)(cid:67)(cid:69)(cid:0) (cid:42)(cid:52)(cid:33)(cid:39)(cid:0)(cid:6)(cid:0)(cid:51)(cid:55) (cid:48)(cid:66)(cid:85)(cid:83) (cid:35)(cid:79)(cid:78)(cid:84)(cid:82)(cid:79)(cid:76)(cid:76)(cid:69)(cid:82) (cid:54)(cid:39)(cid:39)(cid:20)(cid:27) (cid:0)(cid:54)(cid:47)(cid:48)(cid:44)(cid:47)(cid:52)(cid:55)(cid:14)(cid:0)(cid:50)(cid:37)(cid:50)(cid:37)(cid:39)(cid:14) (cid:54)(cid:36)(cid:36)(cid:29)(cid:18)(cid:0)(cid:84)(cid:79)(cid:0)(cid:19)(cid:14)(cid:22)(cid:54) (cid:42)(cid:52)(cid:42)(cid:50)(cid:52)(cid:51)(cid:36)(cid:52)(cid:41) (cid:41)(cid:66)(cid:85)(cid:83) (cid:79)(cid:66)(cid:76) (cid:65)(cid:67)(cid:69)(cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:0)(cid:85)(cid:80)(cid:0)(cid:84)(cid:79)(cid:0)(cid:18)(cid:21)(cid:22)(cid:0)(cid:43)(cid:34) (cid:19)(cid:14)(cid:19)(cid:54)(cid:0)(cid:52)(cid:47)(cid:0)(cid:17)(cid:14)(cid:24)(cid:54) (cid:54)(cid:54)(cid:54) (cid:42)(cid:42)(cid:52)(cid:52)(cid:45)(cid:35)(cid:51)(cid:43)(cid:15)(cid:15)(cid:51)(cid:51)(cid:55)(cid:55)(cid:65)(cid:42)(cid:52)(cid:83)(cid:36)(cid:35)(cid:0)(cid:36)(cid:33)(cid:33)(cid:44)(cid:47)(cid:43)(cid:38)(cid:52) (cid:35)(cid:47)(cid:50)(cid:70)(cid:52)(cid:80)(cid:37)(cid:68)(cid:56)(cid:91)(cid:26)(cid:0)(cid:45)(cid:23)(cid:18)(cid:20)(cid:0)(cid:45)(cid:35)(cid:0)(cid:40)(cid:48)(cid:90)(cid:53) (cid:36)(cid:66)(cid:85)(cid:83) (cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:41)(cid:78)(cid:84)(cid:69)(cid:82)(cid:70) (cid:22)(cid:20)(cid:0)(cid:66)(cid:73)(cid:84) (cid:50)(cid:48)(cid:69)(cid:47)(cid:83)(cid:50)(cid:69)(cid:84) (cid:51)(cid:35)(cid:53)(cid:51)(cid:48)(cid:57)(cid:53)(cid:37)(cid:39)(cid:48)(cid:39)(cid:50)(cid:44)(cid:48)(cid:54)(cid:50)(cid:44)(cid:41)(cid:51)(cid:57)(cid:41)(cid:0)(cid:47)(cid:46) (cid:46)(cid:50)(cid:37)(cid:51)(cid:37)(cid:52) (cid:46)(cid:46)(cid:54)(cid:54)(cid:41)(cid:41)(cid:35)(cid:35) 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AF: alternate function on I/O pins. 12/137 DocID022691 Rev 7

STM32F373xx Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 core with embedded Flash and SRAM The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded ARM core, the STM32F373xx family is compatible with all ARM tools and software. Figure1 shows the general block diagram of the STM32F373xx family. 3.2 Memory protection unit The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: • Outstanding processing performance combined with fast interrupt handling • Enhanced system debug with extensive breakpoint and trace capabilities • Efficient processor core, system and memories • Ultralow power consumption with integrated sleep modes • Platform security robustness with optional integrated memory protection unit (MPU). With its embedded ARM core, the STM32F373xx devices are compatible with all ARM development tools and software. DocID022691 Rev 7 13/137 47

Functional overview STM32F373xx 3.3 Embedded Flash memory All STM32F373xx devices feature up to 256Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 3.4 Cyclic redundancy check (CRC) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Embedded SRAM All STM32F373xx devices feature up to 32Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Boot modes At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device firmware upgrade). 14/137 DocID022691 Rev 7

STM32F373xx Functional overview 3.7 Power management 3.7.1 Power supply schemes • VDD: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins, and can be 2.0 to 3.6V. • VDDA = 2.0 to 3.6V: – external analog power supplies for Reset blocks, RCs and PLL – supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be applied to V is 2.4V when the 12-bit ADC and DAC are used). DDA • V and V = 2.2 to 3.6 V: supply voltages for SDADC1/2 and SDADCD3 DDSD12 DDSD3 sigma delta ADCs. Independent from V /V . DD DDA • V = 1.65 to 3.6V: power supply for RTC, external clock 32kHz oscillator and backup BAT registers when VDD is not present. 3.7.2 Power supply supervisor • The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The POR monitors only the V supply voltage. DD During the startup phase it is required that V should arrive first and be greater than DDA or equal to V . DD • The PDR monitors both the V and V supply voltages, however the V power DD DDA DDA supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V is higher than or DDA equal to V . DD The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR), and power-down. • The MR mode is used in the nominal regulation mode (Run) • The LPR mode is used in Stop mode. • The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The voltage regulator is always enabled after reset. It is disabled in Standby mode. DocID022691 Rev 7 15/137 47

Functional overview STM32F373xx 3.7.4 Low-power modes The STM32F373xx supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USARTs, the I2Cs, the CEC, the USB wakeup, the COMPx and the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 3.8 Clocks and startup System clock selection is performed on startup, however the internal RC 8MHz oscillator is selected as default CPU clock on reset. An external 4-32MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72MHz, while the maximum allowed frequency of the low speed APB domain is 36MHz. 3.9 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 16/137 DocID022691 Rev 7

STM32F373xx Functional overview Do not reconfigure GPIO pins which are not present on 48 and 64 pin packages to the analog mode. Additional current consumption in the range of tens of µA per pin can be observed if V is higher than V . DDA DDIO 3.10 Direct memory access (DMA) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC, SDADCs, general-purpose timers. 3.11 Interrupts and events 3.11.1 Nested vectored interrupt controller (NVIC) The STM32F373xx devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.11.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 84 GPIOs can be connected to the 16 external interrupt lines. DocID022691 Rev 7 17/137 47

Functional overview STM32F373xx 3.12 12-bit analog-to-digital converter (ADC) The 12-bit analog-to-digital converter is based on a successive approximation register (SAR) architecture. It has up to 16 external channels (AIN15:0) and 3 internal channels (temperature sensor, voltage reference, V voltage measurement) performing BAT conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the timers (TIMx) can be internally connected to the ADC start and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.12.1 Temperature sensor The temperature sensor (TS) generates a voltage V that varies linearly with SENSE temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. See Table65: Temperature sensor calibration values on page105. 3.12.2 Internal voltage reference (V ) REFINT The internal voltage reference (V ) provides a stable (bandgap) voltage output for the REFINT ADC and Comparators. V is internally connected to the ADC_IN17 input channel. The REFINT precise voltage of V is individually measured for each part by ST during production REFINT test and stored in the system memory area. It is accessible in read-only mode. 3.12.3 V battery voltage monitoring BAT This embedded hardware feature allows the application to measure the V battery voltage BAT using the internal ADC channel ADC_IN18. As the V voltage may be higher than V , BAT DDA and thus outside the ADC input range, the V pin is internally connected to a divider by 2. BAT As a consequence, the converted digital value is half the V voltage. BAT 18/137 DocID022691 Rev 7

STM32F373xx Functional overview 3.13 16-bit sigma delta analog-to-digital converters (SDADC) Three 16-bit sigma-delta analog-to-digital converters are embedded in the STM32F373xx. They have up to two separate supply voltages allowing the analog function voltage range to be independent from the STM32F373xx power supply. They share up to 21 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11). The conversion speed is up to 16.6 ksps for each SDADC when converting multiple channels and up to 50 ksps per SDADC if single channel conversion is used. There are two conversion modes: single conversion mode or continuous mode, capable of automatically scanning any number of channels. The data can be automatically stored in a system RAM buffer, reducing the software overhead. A timer triggering system can be used in order to control the start of conversion of the three SDADCs and/or the 12-bit fast ADC. This timing control is very flexible, capable of triggering simultaneous conversions or inserting a programmable delay between the ADCs. Up to two external reference pins (VREFSD+, VREFSD-) and an internal 1.2/1.8 V reference can be used in conjunction with a programmable gain (x0.5 to x32) in order to fine-tune the input voltage range of the SDADC. VREFSD - pin is used as negative signal reference in case of single-ended input mode. 3.14 Digital-to-analog converter (DAC) The devices feature two 12-bit buffered DACs with three output channels that can be used to convert three digital signals into three analog voltage signal outputs. The internal structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital Interface supports the following features: • Two DAC converters with three output channels: – DAC1 with two output channels – DAC2 with one output channel. • 8-bit or 10-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation (DAC1 only) • Triangular wave generation (DAC1 only) • Dual DAC channel independent or simultaneous conversions (DAC1 only) • DMA capability for each channel • External triggers for conversion DocID022691 Rev 7 19/137 47

Functional overview STM32F373xx 3.15 Fast comparators (COMP) The STM32F373xx embeds 2 comparators with rail-to-rail inputs and high-speed output. The reference voltage can be internal or external (delivered by an I/O). The threshold can be one of the following: • DACs channel outputs • External I/O • Internal reference voltage (V ) or submultiple (1/4 V , 1/2 V and 3/4 REFINT REFINT REFINT V ) REFINT The comparators can be combined into a window comparator. Both comparators can wake up the device from Stop mode and generate interrupts and breaks for the timers. 3.16 Touch sensing controller (TSC) The devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect the presence of a finger near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. Up to 24 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are organized in 8 acquisition groups, with up to 4 I/Os in each group. Table 3. Capacitive sensing GPIOs available on STM32F373xx devices Capacitive sensing Capacitive sensing Pin Group Pin name Group signal name signal name name TSC_G1_IO1 PA0 TSC_G5_IO1 PB3 TSC_G1_IO2 PA1 TSC_G5_IO2 PB4 1 5 TSC_G1_IO3 PA2 TSC_G5_IO3 PB6 TSC_G1_IO4 PA3 TSC_G5_IO4 PB7 TSC_G2_IO1 PA4(1) TSC_G6_IO1 PB14 TSC_G2_IO2 PA5(1) TSC_G6_IO2 PB15 2 6 TSC_G2_IO3 PA6(1) TSC_G6_IO3 PD8 TSC_G2_IO4 PA7 TSC_G6_IO4 PD9 20/137 DocID022691 Rev 7

STM32F373xx Functional overview Table 3. Capacitive sensing GPIOs available on STM32F373xx devices (continued) Capacitive sensing Capacitive sensing Pin Group Pin name Group signal name signal name name TSC_G3_IO1 PC4 TSC_G7_IO1 PE2 TSC_G3_IO2 PC5 TSC_G7_IO2 PE3 3 7 TSC_G3_IO3 PB0 TSC_G7_IO3 PE4 TSC_G3_IO4 PB1 TSC_G7_IO4 PE5 TSC_G4_IO1 PA9 TSC_G8_IO1 PD12 TSC_G4_IO2 PA10 TSC_G8_IO2 PD13 4 8 TSC_G4_IO3 PA13 TSC_G8_IO3 PD14 TSC_G4_IO4 PA14 TSC_G8_IO4 PD15 1. This GPIO offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O. Table 4. No. of capacitive sensing channels available on STM32F373xx devices Number of capacitive sensing channels Analog I/O group STM32F373Cx STM32F373Rx STM32F373Vx G1 3 3 3 G2 2 3 3 G3 1 3 3 G4 3 3 3 G5 3 3 3 G6 2 2 3 G7 0 0 3 G8 0 0 3 Number of capacitive 14 17 24 sensing channels DocID022691 Rev 7 21/137 47

Functional overview STM32F373xx 3.17 Timers and watchdogs The STM32F373xx includes two 32-bit and nine 16-bit general-purpose timers, three basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 5. Timer feature comparison Capture/ Counter Counter Prescaler DMA request Complementary Timer type Timer compare resolution type factor generation outputs channels Any integer General- TIM2 Up, Down, 32-bit between 1 Yes 4 0 purpose TIM5 Up/Down and 65536 TIM3, Any integer General- Up, Down, TIM4, 16-bit between 1 Yes 4 0 purpose Up/Down TIM19 and 65536 Any integer General- TIM12 16-bit Up between 1 No 2 0 purpose and 65536 Any integer General- TIM15 16-bit Up between 1 Yes 2 1 purpose and 65536 Any integer General- TIM13, 16-bit Up between 1 No 1 0 purpose TIM14 and 65536 Any integer General- TIM16, 16-bit Up between 1 Yes 1 1 purpose TIM17 and 65536 TIM6, Any integer Basic TIM7, 16-bit Up between 1 Yes 0 0 TIM18 and 65536 22/137 DocID022691 Rev 7

STM32F373xx Functional overview 3.17.1 General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19) There are eleven synchronizable general-purpose timers embedded in the STM32F373xx (see Table5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, 3, 4, 5 and 19 These five timers are full-featured general-purpose timers: – TIM2 and TIM5 have 32-bit auto-reload up/downcounters and 32-bit prescalers – TIM3, 4, and 19 have 16-bit auto-reload up/downcounters and 16-bit prescalers These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general- purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM12, 13, 14, 15, 16, 17 These six timers general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM12 has 2 channels – TIM13 and TIM14 have 1 channel – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.17.2 Basic timers (TIM6, TIM7, TIM18) These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. DocID022691 Rev 7 23/137 47

Functional overview STM32F373xx 3.17.3 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.17.4 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB1 clock (PCLK1) derived from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17.5 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source 3.18 Real-time clock (RTC) and backup registers The RTC and the backup registers are supplied through a switch that takes power either from VDD supply when present or through the VBAT pin. The backup registers are thirty two 32-bit registers used to store 128 bytes of user application data. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The RTC is an independent BCD timer/counter. Its main features are the following: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28th, 29th (leap year), 30th and 31st day of the month. • 2 programmable alarms with wake up from Stop and Standby mode capability. • Periodic wakeup unit with programmable resolution and period. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Digital calibration circuit with 1ppm resolution, to compensate for quartz crystal inaccuracy. • 3 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection. • Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection. 24/137 DocID022691 Rev 7

STM32F373xx Functional overview • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC clock sources can be: • A 32.768 kHz external crystal • A resonator or oscillator • The internal low-power RC oscillator (typical frequency of 40 kHz) • The high-speed external clock divided by 32 2 3.19 Inter-integrated circuit interface (I C) Two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes with 20mA output drive. They support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 6. Comparison of I2C analog and digital filters - Analog filter Digital filter Pulse width of Programmable length from 1 to 15 ≥ 50 ns suppressed spikes I2C peripheral clocks 1. Extra filtering capability vs. Benefits Available in Stop mode standard requirements. 2. Stable length Wakeup from Stop on address Variations depending on Drawbacks match is not available when digital temperature, voltage, process filter is enabled In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeout verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the application to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller Refer to Table7 for the differences between I2C1 and I2C2. Table 7. STM32F373xx I2C implementation I2C features(1) I2C1 I2C2 7-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X Independent clock X X DocID022691 Rev 7 25/137 47

Functional overview STM32F373xx Table 7. STM32F373xx I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X X Wakeup from STOP X X 1. X = supported. 3.20 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F373xx embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). All USARTs interfaces are able to communicate at speeds of up to 9Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode, Smartcard mode (ISO/IEC 7816 compliant), autobaudrate feature and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Refer to Table8 for the features of USART1, USART2 and USART3. Table 8. STM32F373xx USART implementation USART modes/features(1) USART1 USART2 USART3 Hardware flow control for modem X X X Continuous communication using DMA X X X Multiprocessor communication X X X Synchronous mode X X X Smartcard mode X X X Single-wire half-duplex communication X X X IrDA SIR ENDEC block X X X LIN mode X X X Dual clock domain and wakeup from Stop mode X X X Receiver timeout interrupt X X X Modbus communication X X X Auto baud rate detection X X X Driver Enable X X X 1. X = supported. 26/137 DocID022691 Rev 7

STM32F373xx Functional overview 3.21 Serial peripheral interface (SPI)/Inter-integrated sound 2 interfaces (I S) Three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in full- duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8kHz up to 192kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces can operate in half-duplex mode only. Refer to Table9 for the features between SPI1, SPI2 and SPI3. Table 9. STM32F373xx SPI/I2S implementation SPI features(1) SPI1 SPI2 SPI3 Hardware CRC calculation X X X Rx/Tx FIFO X X X NSS pulse mode X X X I2S mode X X X TI mode X X X I2S full-duplex mode - - - 1. X = supported. 3.22 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception. 3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. DocID022691 Rev 7 27/137 47

Functional overview STM32F373xx 3.24 Universal serial bus (USB) The STM32F373xx embeds an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.25 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.26 Embedded trace macrocell™ The ARM embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F373xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 28/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description 4 Pinouts and pin description Figure 2. STM32F373xx LQFP48 pinout (cid:39)(cid:66)(cid:20) (cid:54)(cid:66)(cid:20) (cid:28) (cid:27) (cid:50)(cid:55)(cid:19) (cid:26) (cid:25)(cid:3)(cid:3)(cid:3)(cid:3) (cid:24) (cid:23) (cid:22) (cid:20)(cid:24) (cid:20)(cid:23) (cid:39) (cid:54) (cid:37) (cid:37) (cid:50) (cid:37) (cid:37) (cid:37) (cid:37) (cid:37) (cid:36) (cid:36) (cid:57) (cid:57) (cid:51) (cid:51) (cid:37) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:23)(cid:27) (cid:23)(cid:26) (cid:23)(cid:25) (cid:23)(cid:24) (cid:23)(cid:23) (cid:23)(cid:22) (cid:23)(cid:21) (cid:23)(cid:20) (cid:23)(cid:19) (cid:22)(cid:28) (cid:22)(cid:27) (cid:22)(cid:26) (cid:57)(cid:37)(cid:36)(cid:55) (cid:20) (cid:22)(cid:25) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:20)(cid:22) (cid:21) (cid:22)(cid:24) (cid:51)(cid:41)(cid:25) (cid:51)(cid:38)(cid:20)(cid:23)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:22) (cid:22)(cid:23) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:38)(cid:20)(cid:24)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:23) (cid:22)(cid:22) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:24) (cid:22)(cid:21) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:25)(cid:3)(cid:3)(cid:3)(cid:3) (cid:22)(cid:20) (cid:51)(cid:36)(cid:20)(cid:19) (cid:47)(cid:52)(cid:41)(cid:51)(cid:23)(cid:27) (cid:49)(cid:53)(cid:54)(cid:55) (cid:26)(cid:3)(cid:3)(cid:3)(cid:3) (cid:22)(cid:19) (cid:51)(cid:36)(cid:28) (cid:57)(cid:54)(cid:54)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:27)(cid:3)(cid:3)(cid:3)(cid:3) (cid:21)(cid:28) (cid:51)(cid:36)(cid:27) (cid:57)(cid:39)(cid:39)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:28)(cid:3)(cid:3)(cid:3)(cid:3) (cid:21)(cid:27) (cid:51)(cid:39)(cid:27) (cid:51)(cid:36)(cid:19) (cid:20)(cid:19) (cid:21)(cid:26) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:36)(cid:20) (cid:20)(cid:20) (cid:21)(cid:25) (cid:51)(cid:37)(cid:20)(cid:23) (cid:51)(cid:36)(cid:21) (cid:20)(cid:21) (cid:21)(cid:24) (cid:57)(cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:14) (cid:20)(cid:22) (cid:20)(cid:23) (cid:20)(cid:24) (cid:20)(cid:25) (cid:20)(cid:26) (cid:20)(cid:27) (cid:20)(cid:28) (cid:21)(cid:19) (cid:21)(cid:20) (cid:21)(cid:21) (cid:21)(cid:22) (cid:21)(cid:23) (cid:51)(cid:36)(cid:22) (cid:51)(cid:36)(cid:23) (cid:51)(cid:36)(cid:24) (cid:51)(cid:36)(cid:25) (cid:57)(cid:39)(cid:39)(cid:66)(cid:21)(cid:51)(cid:37)(cid:19) (cid:51)(cid:37)(cid:20) (cid:51)(cid:37)(cid:21) (cid:51)(cid:40)(cid:27) (cid:51)(cid:40)(cid:28) (cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:16) (cid:57)(cid:39)(cid:39)(cid:54)(cid:39) (cid:57) (cid:39)(cid:18) (cid:54) (cid:54) (cid:54) (cid:57) (cid:48)(cid:54)(cid:22)(cid:20)(cid:19)(cid:23)(cid:21)(cid:57)(cid:22) 1. The above figure shows the package top view. DocID022691 Rev 7 29/137 47

Pinouts and pin description STM32F373xx Figure 3. STM32F373xx LQFP64 pinout (cid:39)(cid:66)(cid:20)(cid:54)(cid:66)(cid:20) (cid:28)(cid:3)(cid:3)(cid:3)(cid:3)(cid:27)(cid:3)(cid:3)(cid:3)(cid:3)(cid:50)(cid:55)(cid:19)(cid:3)(cid:3)(cid:3)(cid:3)(cid:26)(cid:3)(cid:3)(cid:3)(cid:3)(cid:25)(cid:3)(cid:3)(cid:3)(cid:3)(cid:24)(cid:3)(cid:3)(cid:3)(cid:3)(cid:23)(cid:3)(cid:3)(cid:3)(cid:3)(cid:22)(cid:3)(cid:3)(cid:3)(cid:3)(cid:21)(cid:3)(cid:3)(cid:3)(cid:3)(cid:20)(cid:21)(cid:20)(cid:20)(cid:20)(cid:19)(cid:20)(cid:24)(cid:20)(cid:23) (cid:39)(cid:54) (cid:37)(cid:37)(cid:50)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:39)(cid:38)(cid:38)(cid:38)(cid:36)(cid:36) (cid:57)(cid:57) (cid:51)(cid:51)(cid:37)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:25)(cid:23) (cid:25)(cid:22) (cid:25)(cid:21) (cid:25)(cid:20) (cid:25)(cid:19) (cid:24)(cid:28) (cid:24)(cid:27) (cid:24)(cid:26) (cid:24)(cid:25) (cid:24)(cid:24) (cid:24)(cid:23) (cid:24)(cid:22) (cid:24)(cid:21) (cid:24)(cid:20) (cid:24)(cid:19) (cid:23)(cid:28) (cid:57)(cid:37)(cid:36)(cid:55) (cid:20) (cid:23)(cid:27) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:20)(cid:22) (cid:21) (cid:23)(cid:26) (cid:51)(cid:41)(cid:25) (cid:51)(cid:38)(cid:20)(cid:23)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:22) (cid:23)(cid:25) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:38)(cid:20)(cid:24)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:23) (cid:23)(cid:24) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:41)(cid:19)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:24) (cid:23)(cid:23) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:41)(cid:20)(cid:3)(cid:16)(cid:3)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:25)(cid:3)(cid:3) (cid:23)(cid:22) (cid:51)(cid:36)(cid:20)(cid:19) (cid:49)(cid:53)(cid:54)(cid:55) (cid:26)(cid:3)(cid:3) (cid:23)(cid:21) (cid:51)(cid:36)(cid:28) (cid:51)(cid:38)(cid:19) (cid:27)(cid:3)(cid:3) (cid:23)(cid:20) (cid:51)(cid:36)(cid:27) (cid:51)(cid:38)(cid:20) (cid:28)(cid:3)(cid:3) (cid:44)(cid:49)(cid:38)(cid:48)(cid:22)(cid:20) (cid:23)(cid:19) (cid:51)(cid:38)(cid:28) (cid:51)(cid:38)(cid:21) (cid:20)(cid:19) (cid:22)(cid:28) (cid:51)(cid:38)(cid:27) (cid:51)(cid:38)(cid:22) (cid:20)(cid:20) (cid:22)(cid:27) (cid:51)(cid:38)(cid:26) (cid:57)(cid:54)(cid:54)(cid:36)(cid:18)(cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:20)(cid:21) (cid:22)(cid:26) (cid:51)(cid:38)(cid:25) (cid:57)(cid:39)(cid:39)(cid:36) (cid:20)(cid:22) (cid:22)(cid:25) (cid:51)(cid:39)(cid:27) (cid:51)(cid:36)(cid:19) (cid:20)(cid:23) (cid:22)(cid:24) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:36)(cid:20) (cid:20)(cid:24) (cid:22)(cid:23) (cid:51)(cid:37)(cid:20)(cid:23) (cid:51)(cid:36)(cid:21) (cid:20)(cid:25) (cid:22)(cid:22) (cid:57)(cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:14) (cid:20)(cid:26) (cid:20)(cid:27) (cid:20)(cid:28) (cid:21)(cid:19) (cid:21)(cid:20) (cid:21)(cid:21) (cid:21)(cid:22) (cid:21)(cid:23) (cid:21)(cid:24) (cid:21)(cid:25) (cid:21)(cid:26) (cid:21)(cid:27) (cid:21)(cid:28) (cid:22)(cid:19) (cid:22)(cid:20) (cid:22)(cid:21) (cid:53)(cid:40)(cid:41)(cid:14)(cid:51)(cid:36)(cid:22) (cid:39)(cid:39)(cid:66)(cid:21)(cid:51)(cid:36)(cid:23)(cid:51)(cid:36)(cid:24)(cid:51)(cid:36)(cid:25)(cid:51)(cid:36)(cid:26)(cid:51)(cid:38)(cid:23)(cid:51)(cid:38)(cid:24)(cid:51)(cid:37)(cid:19)(cid:51)(cid:37)(cid:20)(cid:51)(cid:37)(cid:21)(cid:51)(cid:40)(cid:27)(cid:51)(cid:40)(cid:28)(cid:40)(cid:41)(cid:54)(cid:39)(cid:16)(cid:39)(cid:39)(cid:54)(cid:39) (cid:57) (cid:57) (cid:53)(cid:57) (cid:57) (cid:39)(cid:18) (cid:54) (cid:54) (cid:54) (cid:57) (cid:45)(cid:51)(cid:19)(cid:17)(cid:16)(cid:20)(cid:21)(cid:54)(cid:17) 1. The above figure shows the package top view. 30/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description Figure 4. STM32F373xx LQFP100 pinout (cid:36)(cid:36)(cid:63)(cid:17)(cid:51)(cid:51)(cid:63)(cid:17)(cid:37)(cid:17)(cid:0)(cid:0)(cid:37)(cid:16)(cid:0)(cid:0)(cid:34)(cid:25)(cid:0)(cid:0)(cid:34)(cid:24)(cid:0)(cid:0)(cid:47)(cid:47)(cid:52)(cid:16)(cid:0)(cid:0)(cid:34)(cid:23)(cid:0)(cid:0)(cid:34)(cid:22)(cid:0)(cid:0)(cid:34)(cid:21)(cid:0)(cid:0)(cid:34)(cid:20)(cid:0)(cid:0)(cid:34)(cid:19)(cid:0)(cid:0)(cid:36)(cid:23)(cid:0)(cid:0)(cid:36)(cid:22)(cid:0)(cid:0)(cid:36)(cid:21)(cid:0)(cid:0)(cid:36)(cid:20)(cid:0)(cid:0)(cid:36)(cid:19)(cid:0)(cid:0)(cid:36)(cid:18)(cid:0)(cid:0)(cid:36)(cid:17)(cid:0)(cid:0)(cid:36)(cid:16)(cid:0)(cid:0)(cid:35)(cid:17)(cid:18)(cid:0)(cid:0)(cid:35)(cid:17)(cid:17)(cid:0)(cid:0)(cid:35)(cid:17)(cid:16)(cid:0)(cid:0)(cid:33)(cid:17)(cid:21)(cid:0)(cid:0)(cid:33)(cid:17)(cid:20)(cid:0) (cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:34)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48) (cid:16) (cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22) (cid:17)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:25)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:24)(cid:23)(cid:23)(cid:23)(cid:23) (cid:48)(cid:37)(cid:18) (cid:17) (cid:23)(cid:21) (cid:54)(cid:36)(cid:36)(cid:63)(cid:19) (cid:48)(cid:37)(cid:19) (cid:18) (cid:23)(cid:20) (cid:54)(cid:51)(cid:51)(cid:63)(cid:19) (cid:48)(cid:37)(cid:20) (cid:19) (cid:23)(cid:19) (cid:48)(cid:38)(cid:22) (cid:48)(cid:37)(cid:21) (cid:20) (cid:23)(cid:18) (cid:48)(cid:33)(cid:17)(cid:19)(cid:0)(cid:0)(cid:0) (cid:48)(cid:37)(cid:22) (cid:21) (cid:23)(cid:17) (cid:48)(cid:33)(cid:17)(cid:18)(cid:0)(cid:0)(cid:0) (cid:54)(cid:34)(cid:33)(cid:52) (cid:22) (cid:23)(cid:16) (cid:48)(cid:33)(cid:17)(cid:17)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17)(cid:19) (cid:23) (cid:22)(cid:25) (cid:48)(cid:33)(cid:17)(cid:16)(cid:0)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17)(cid:20)(cid:0)(cid:13)(cid:0)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:41)(cid:46) (cid:24) (cid:22)(cid:24) (cid:48)(cid:33)(cid:25)(cid:0) (cid:0) (cid:48)(cid:35)(cid:17)(cid:21)(cid:0)(cid:13)(cid:0)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:47)(cid:53)(cid:52) (cid:25) (cid:22)(cid:23) (cid:48)(cid:33)(cid:24)(cid:0)(cid:0)(cid:0) (cid:48)(cid:38)(cid:25) (cid:17)(cid:16) (cid:22)(cid:22) (cid:48)(cid:35)(cid:25)(cid:0)(cid:0) (cid:48)(cid:38)(cid:17)(cid:16) (cid:17)(cid:17) (cid:22)(cid:21) (cid:48)(cid:35)(cid:24)(cid:0)(cid:0) (cid:48)(cid:38)(cid:16)(cid:13)(cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46) (cid:17)(cid:18) (cid:22)(cid:20) (cid:48)(cid:35)(cid:23)(cid:0)(cid:0) (cid:48)(cid:38)(cid:17)(cid:13)(cid:47)(cid:51)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52) (cid:17)(cid:19) (cid:44)(cid:49)(cid:38)(cid:48)(cid:17)(cid:16)(cid:16) (cid:22)(cid:19) (cid:48)(cid:35)(cid:22)(cid:0)(cid:0) (cid:46)(cid:50)(cid:51)(cid:52) (cid:17)(cid:20) (cid:22)(cid:18) (cid:48)(cid:36)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:35)(cid:16) (cid:17)(cid:21) (cid:22)(cid:17) (cid:48)(cid:36)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17) (cid:17)(cid:22) (cid:22)(cid:16) (cid:48)(cid:36)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:35)(cid:18) (cid:17)(cid:23) (cid:21)(cid:25) (cid:48)(cid:36)(cid:17)(cid:18)(cid:0)(cid:0) (cid:48)(cid:35)(cid:19) (cid:17)(cid:24) (cid:21)(cid:24) (cid:48)(cid:36)(cid:17)(cid:17)(cid:0)(cid:0) (cid:48)(cid:38)(cid:18) (cid:17)(cid:25) (cid:21)(cid:23) (cid:48)(cid:36)(cid:17)(cid:16)(cid:0)(cid:0) (cid:54)(cid:51)(cid:51)(cid:33)(cid:15)(cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:18)(cid:16) (cid:21)(cid:22) (cid:48)(cid:36)(cid:25)(cid:0)(cid:0) (cid:54)(cid:36)(cid:36)(cid:33) (cid:18)(cid:17) (cid:21)(cid:21) (cid:48)(cid:36)(cid:24)(cid:0)(cid:0) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:18)(cid:18) (cid:21)(cid:20) (cid:48)(cid:34)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:33)(cid:16) (cid:18)(cid:19) (cid:21)(cid:19) (cid:48)(cid:34)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:33)(cid:17) (cid:18)(cid:20) (cid:21)(cid:18) (cid:54)(cid:50)(cid:37)(cid:38)(cid:51)(cid:0)(cid:36)(cid:11) (cid:48)(cid:33)(cid:18) (cid:18)(cid:21) (cid:21)(cid:17) (cid:54)(cid:36)(cid:36)(cid:51)(cid:0)(cid:0)(cid:36)(cid:19) (cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16) (cid:18)(cid:18)(cid:18)(cid:18)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:21) (cid:19)(cid:20)(cid:18)(cid:20)(cid:21)(cid:22)(cid:23)(cid:20)(cid:21)(cid:16)(cid:17)(cid:18)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:16)(cid:36)(cid:13)(cid:36)(cid:18) (cid:33)(cid:38)(cid:63)(cid:33)(cid:33)(cid:33)(cid:33)(cid:35)(cid:35)(cid:34)(cid:34)(cid:34)(cid:37)(cid:37)(cid:37)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:51)(cid:51)(cid:17) (cid:48)(cid:48)(cid:36)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:34)(cid:38)(cid:51)(cid:36) (cid:36) (cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:37)(cid:51)(cid:51) (cid:54) (cid:50)(cid:54)(cid:36) (cid:54) (cid:36) (cid:54) (cid:45)(cid:51)(cid:19)(cid:18)(cid:17)(cid:22)(cid:18)(cid:54)(cid:17) DocID022691 Rev 7 31/137 47

Pinouts and pin description STM32F373xx Figure 5. STM32F373xx UFBGA100 ballout (cid:18) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:18)(cid:17) (cid:18)(cid:18) (cid:18)(cid:19) (cid:33) (cid:48)(cid:37)(cid:19) (cid:48)(cid:37)(cid:17) (cid:48)(cid:34)(cid:24) (cid:34)(cid:47)(cid:47)(cid:52)(cid:16) (cid:48)(cid:36)(cid:23) (cid:48)(cid:36)(cid:21) (cid:48)(cid:34)(cid:20) (cid:48)(cid:34)(cid:19) (cid:48)(cid:33)(cid:17)(cid:21) (cid:48)(cid:33)(cid:17)(cid:20) (cid:48)(cid:33)(cid:17)(cid:19) (cid:48)(cid:33)(cid:17)(cid:18) (cid:34) (cid:48)(cid:37)(cid:20) (cid:48)(cid:37)(cid:18) (cid:48)(cid:34)(cid:25) (cid:48)(cid:34)(cid:23) (cid:48)(cid:34)(cid:22) (cid:48)(cid:36)(cid:22) (cid:48)(cid:36)(cid:20) (cid:48)(cid:36)(cid:19) (cid:48)(cid:36)(cid:17) (cid:48)(cid:35)(cid:17)(cid:18) (cid:48)(cid:35)(cid:17)(cid:16) (cid:48)(cid:33)(cid:17)(cid:17) (cid:35) (cid:48)(cid:35)(cid:17)(cid:19) (cid:48)(cid:37)(cid:21) (cid:48)(cid:37)(cid:16) (cid:54)(cid:36)(cid:36)(cid:63)(cid:17) (cid:48)(cid:34)(cid:21) (cid:48)(cid:36)(cid:18) (cid:48)(cid:36)(cid:16) (cid:48)(cid:35)(cid:17)(cid:17) (cid:48)(cid:38)(cid:22) (cid:48)(cid:33)(cid:17)(cid:16) (cid:36) (cid:48)(cid:35)(cid:17)(cid:20) (cid:48)(cid:37)(cid:22) (cid:54)(cid:51)(cid:51)(cid:63)(cid:17) (cid:48)(cid:33)(cid:25) (cid:48)(cid:33)(cid:24) (cid:48)(cid:35)(cid:25) (cid:37) (cid:48)(cid:35)(cid:17)(cid:21) (cid:54)(cid:34)(cid:33)(cid:52) (cid:48)(cid:38)(cid:20) (cid:48)(cid:35)(cid:24) (cid:48)(cid:35)(cid:23) (cid:48)(cid:35)(cid:22) (cid:38) (cid:48)(cid:38)(cid:16) (cid:48)(cid:38)(cid:25) (cid:54)(cid:51)(cid:51)(cid:63)(cid:19) (cid:54)(cid:51)(cid:51)(cid:51)(cid:36) (cid:39) (cid:48)(cid:38)(cid:17) (cid:48)(cid:38)(cid:17)(cid:16) (cid:54)(cid:36)(cid:36)(cid:63)(cid:19) (cid:54)(cid:36)(cid:36)(cid:51)(cid:36)(cid:17)(cid:18) (cid:40) (cid:48)(cid:35)(cid:16) (cid:46)(cid:50)(cid:51)(cid:52) (cid:54)(cid:36)(cid:36)(cid:63)(cid:18) (cid:48)(cid:36)(cid:17)(cid:21) (cid:48)(cid:36)(cid:17)(cid:20) (cid:48)(cid:36)(cid:17)(cid:19) (cid:42) (cid:48)(cid:38)(cid:18) (cid:48)(cid:35)(cid:17) (cid:48)(cid:35)(cid:18) (cid:48)(cid:36)(cid:17)(cid:18) (cid:48)(cid:36)(cid:17)(cid:17) (cid:48)(cid:36)(cid:17)(cid:16) (cid:43) (cid:54)(cid:51)(cid:51)(cid:33)(cid:15) (cid:48)(cid:35)(cid:19) (cid:48)(cid:33)(cid:18) (cid:48)(cid:33)(cid:21) (cid:48)(cid:35)(cid:20) (cid:48)(cid:36)(cid:25) (cid:48)(cid:36)(cid:24) (cid:48)(cid:34)(cid:17)(cid:21) (cid:48)(cid:34)(cid:17)(cid:20) (cid:54)(cid:50)(cid:37)(cid:38)(cid:51)(cid:36)(cid:11) (cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:44) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:48)(cid:33)(cid:16) (cid:48)(cid:33)(cid:19) (cid:48)(cid:33)(cid:22) (cid:48)(cid:35)(cid:21) (cid:48)(cid:34)(cid:18) (cid:48)(cid:37)(cid:24) (cid:48)(cid:37)(cid:17)(cid:16) (cid:48)(cid:37)(cid:17)(cid:18) (cid:48)(cid:34)(cid:17)(cid:16) (cid:54)(cid:50)(cid:37)(cid:38)(cid:51)(cid:36)(cid:13) (cid:54)(cid:36)(cid:36)(cid:51)(cid:36)(cid:19) (cid:45) (cid:54)(cid:36)(cid:36)(cid:33) (cid:48)(cid:33)(cid:17) (cid:48)(cid:33)(cid:20) (cid:48)(cid:33)(cid:23) (cid:48)(cid:34)(cid:16) (cid:48)(cid:34)(cid:17) (cid:48)(cid:37)(cid:23) (cid:48)(cid:37)(cid:25) (cid:48)(cid:37)(cid:17)(cid:17) (cid:48)(cid:37)(cid:17)(cid:19) (cid:48)(cid:37)(cid:17)(cid:20) (cid:48)(cid:37)(cid:17)(cid:21) (cid:45)(cid:51)(cid:19)(cid:17)(cid:16)(cid:20)(cid:25)(cid:54)(cid:17) 1. The above figure shows the package top view. 32/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description Table 10. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function Pin name during and after reset is the same as the actual pin name S Supply pin Pin type I Input only pin I/O Input / output pin FT 5V tolerant I/O FTf 5V tolerant I/O, FM+ capable TTa 3.3V tolerant I/O directly connected to ADC I/O structure TC Standard 3.3V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during Notes and after reset Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions Table 11. STM32F373xx pin definitions Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L UF L L I/ 1 B2 - - PE2 I/O FT (2) TSC_G7_IO1, TRACECLK - 2 A1 - - PE3 I/O FT (2) TSC_G7_IO2, TRACED0 - 3 B1 - - PE4 I/O FT (2) TSC_G7_IO3, TRACED1 - 4 C2 - - PE5 I/O FT (2) TSC_G7_IO4, TRACED2 - 5 D2 - - PE6 I/O FT (2) TRACED3 WKUP3, RTC_TAMPER3 6 E2 1 1 VBAT S - - Backup power supply WKUP2, ALARM_OUT, 7 C1 2 2 PC13(1) I/O TC - - CALIB_OUT, TIMESTAMP, RTC_TAMPER1 DocID022691 Rev 7 33/137 47

Pinouts and pin description STM32F373xx Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U PC14 - 8 D1 3 3 I/O TC - - OSC32_IN OSC32_IN(1) PC15 - 9 E1 4 4 I/O TC - - OSC32_OUT OSC32_OUT(1) 10 F2 - - PF9 I/O FT (2) TIM14_CH1 - 11 G2 - - PF10 I/O FT (2) - - 12 F1 5 5 PF0 - OSC_IN I/O FTf - I2C2_SDA OSC_IN PF1 - 13 G1 6 6 I/O FTf - I2C2_SCL OSC_OUT OSC_OUT 14 H2 7 7 NRST I/O RST - Device reset input / internal reset output (active low) 15 H1 8 - PC0 I/O TTa (2) TIM5_CH1_ETR ADC_IN10 16 J2 9 - PC1 I/O TTa (2) TIM5_CH2 ADCIN11 SPI2_MISO/I2S2_MCK, 17 J3 10 - PC2 I/O TTa (2) ADC_IN12 TIM5_CH3 SPI2_MOSI/I2S2_SD, 18 K2 11 - PC3 I/O TTa (2) ADC_IN13 TIM5_CH4 19 J1 - - PF2 I/O FT (2) I2C2_SMBA - 20 K1 12 8 VSSA/VREF- S - - Analog ground Analog power supply / Reference voltage for ADC, COMP, - - - 9 VDDA/VREF+ S - (2) DAC 21 M1 13 - VDDA S - (2) Analog power supply 22 L1 17 - VREF+ S - (2) Reference voltage for ADC, COMP, DAC USART2_CTS, TIM2_CH1_ETR, RTC_ TAMPER2, WKUP1, 23 L2 14 10 PA0 I/O TTa - TIM5_CH1_ETR, TIM19_CH1, ADC_IN0, COMP1_INM TSC_G1_IO1, COMP1_OUT SPI3_SCK/I2S3_CK, USART2_RTS, TIM2_CH2, 24 M2 15 11 PA1 I/O TTa - TIM15_CH1N, TIM5_CH2, ADC_IN1, COMP1_INP TIM19_CH2, TSC_G1_IO2, RTC_REFIN 34/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U COMP2_OUT, SPI3_MISO/I2S3_MCK, ADC_IN2, 25 K3 16 12 PA2 I/O TTa - USART2_TX, TIM2_CH3, COMP2_INM TIM15_CH1, TIM5_CH3, TIM19_CH3, TSC_G1_IO3 SPI3_MOSI/I2S3_SD, USART2_RX, TIM2_CH4, 26 L3 18 13 PA3 I/O TTa - ADC_IN3, COMP2_INP TIM15_CH2, TIM5_CH4, TIM19_CH4, TSC_G1_IO4 27 E3 - - PF4 I/O FT (2) - 28 H3 19 17 VDD_2 S - - Digital power supply SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, 29 M3 20 14 PA4 I/O TTa - ADC_IN4, DAC1_OUT1 USART2_CK, TIM3_CH2, TIM12_CH1, TSC_G2_IO1, SPI1_SCK/I2S1_CK, CEC, 30 K4 21 15 PA5 I/O TTa - TIM2_CH1_ETR, TIM14_CH1, ADC_IN5, DAC1_OUT2 TIM12_CH2, TSC_G2_IO2 SPI1_MISO/I2S1_MCK, COMP1_OUT, TIM3_CH1, 31 L4 22 16 PA6 I/O TTa - ADC_IN6, DAC2_OUT1, TIM13_CH1, TIM16_CH1, TSC_G2_IO3 TSC_G2_IO4, TIM14_CH1, SPI1_MOSI/I2S1_SD, 32 M4 23 - PA7 I/O TTa (2) ADC_IN7 TIM17_CH1, TIM3_CH2, COMP2_OUT TIM13_CH1, TSC_G3_IO1, 33 K5 24 - PC4 I/O TTa (2) ADC_IN14 USART1_TX 34 L5 25 - PC5 I/O TTa (2) TSC_G3_IO2, USART1_RX ADC_IN15 SPI1_MOSI/I2S1_SD, 35 M5 26 18 PB0 I/O TTa - TIM3_CH3, TSC_G3_IO3, ADC_IN8, SDADC1_AIN6P TIM3_CH2 ADC_IN9, SDADC1_AIN5P, 36 M6 27 19 PB1 I/O TTa - TIM3_CH4, TSC_G3_IO4 SDADC1_AIN6M SDADC1_AIN4P, 37 L6 28 20 PB2 I/O TC (3) - SDADC2_AIN6P DocID022691 Rev 7 35/137 47

Pinouts and pin description STM32F373xx Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U SDADC1_AIN3P, (3) SDADC1_AIN4M, 38 M7 - - PE7 I/O TC - (2) SDADC2_AIN5P, SDADC2_AIN6M SDADC1_AIN8P, 39 L7 29 21 PE8 I/O TC (3) - SDADC2_AIN8P SDADC1_AIN7P, SDADC1_AIN8M, 40 M8 30 22 PE9 I/O TC (3) - SDADC2_AIN7P, SDADC2_AIN8M (3) 41 L8 - - PE10 I/O TC - SDADC1_AIN2P (2) SDADC1_AIN1P, (3) 42 M9 - - PE11 I/O TC - SDADC1_AIN2M, (2) SDADC2_AIN4P SDADC1_AIN0P, (3) 43 L9 - - PE12 I/O TC - SDADC2_AIN3P, (2) SDADC2_AIN4M (3) SDADC1_AIN0M , 44 M10 - - PE13 I/O TC - (2) SDADC2_AIN2P (3) SDADC2_AIN1P, 45 M11 - - PE14 I/O TC - (2) SDADC2_AIN2M (3) 46 M12 - - PE15 I/O TC USART3_RX SDADC2_AIN0P (2) SPI2_SCK/I2S2_CK, (3) 47 L10 - - PB10 I/O TC USART3_TX, CEC, SDADC2_AIN0M (2) TSC_SYNC, TIM2_CH3 External reference voltage for SDADC1, SDADC2, SDADC3 48 L11 - - VREFSD- S - (2) (negative input), negative SDADC analog input in SDADC single ended mode 49 F12 - - VSSSD S - (2) SDADC1, SDADC2, SDADC3 ground SDADC1, SDADC2, SDADC3 ground / External reference VSSSD/ - - 31 23 S - - voltage for SDADC1, SDADC2, SDADC3 (negative input), VREFSD- negative SDADC analog input in SDADC single ended mode 50 G12 - - VDDSD12 S - (2) SDADC1 and SDADC2 power supply - - 32 24 VDDSD S - - SDADC1, SDADC2, SDADC3 power supply 36/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U 51 L12 - - VDDSD3 S - (2) SDADC3 power supply External reference voltage for SDADC1, SDADC2, SDADC3 52 K12 33 25 VREFSD+ S - - (positive input) SPI2_MISO/I2S2_MCK, 53 K11 34 26 PB14 I/O TC (4) USART3_RTS, TIM15_CH1, SDADC3_AIN8P TIM12_CH1, TSC_G6_IO1 SPI2_MOSI/I2S2_SD, TIM15_CH1N, TIM15_CH2, SDADC3_AIN7P, 54 K10 35 27 PB15 I/O TC (4) TIM12_CH2, TSC_G6_IO2, SDADC3_AIN8M RTC_REFIN SPI2_SCK/I2S2_CK, 55 K9 36 28 PD8 I/O TC (4) SDADC3_AIN6P USART3_TX, TSC_G6_IO3 (4) SDADC3_AIN5P, 56 K8 - - PD9 I/O TC USART3_RX, TSC_G6_IO4 (2) SDADC3_AIN6M (4) 57 J12 - - PD10 I/O TC USART3_CK SDADC3_AIN4P (2) (4) SDADC3_AIN3P, 58 J11 - - PD11 I/O TC USART3_CTS (2) SDADC3_AIN4M (4) USART3_RTS, TIM4_CH1, 59 J10 - - PD12 I/O TC SDADC3_AIN2P (2) TSC_G8_IO1 (4) SDADC3_AIN1P, 60 H12 - - PD13 I/O TC TIM4_CH2, TSC_G8_IO2 (2) SDADC3_AIN2M (4) 61 H11 - - PD14 I/O TC TIM4_CH3, TSC_G8_IO3 SDADC3_AIN0P (2) (4) 62 H10 - - PD15 I/O TC TIM4_CH4, TSC_G8_IO4 SDADC3_AIN0M (2) TIM3_CH1, 63 E12 37 - PC6 I/O FT (2) - SPI1_NSS/I2S1_WS TIM3_CH2, 64 E11 38 - PC7 I/O FT (2) - SPI1_SCK/I2S1_CK, SPI1_MISO/I2S1_MCK, 65 E10 39 - PC8 I/O FT (2) - TIM3_CH3 SPI1_MOSI/I2S1_SD, 66 D12 40 - PC9 I/O FT (2) - TIM3_CH4 DocID022691 Rev 7 37/137 47

Pinouts and pin description STM32F373xx Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U SPI2_SCK/I2S2_CK, I2C2_SMBA, USART1_CK, 67 D11 41 29 PA8 I/O FT - - TIM4_ETR, TIM5_CH1_ETR, MCO SPI2_MISO/I2S2_MCK, I2C2_SCL, USART1_TX, 68 D10 42 30 PA9 I/O FTf - - TIM2_CH3, TIM15_BKIN, TIM13_CH1, TSC_G4_IO1 SPI2_MOSI/I2S2_SD, I2C2_SDA, USART1_RX, 69 C12 43 31 PA10 I/O FTf - - TIM2_CH4, TIM17_BKIN, TIM14_CH1, TSC_G4_IO2 SPI2_NSS/I2S2_WS, SPI1_NSS/I2S1_WS, 70 B12 44 32 PA11 I/O FT - USART1_CTS, CAN_RX, - TIM4_CH1, USB_DM, TIM5_CH2, COMP1_OUT SPI1_SCK/I2S1_CK, USART1_RTS, CAN_TX, 71 A12 45 33 PA12 I/O FT - USB_DP, TIM16_CH1, - TIM4_CH2, TIM5_CH3, COMP2_OUT SPI1_MISO/I2S1_MCK, USART3_CTS, IR_OUT, 72 A11 46 34 PA13 I/O FT - TIM16_CH1N, TIM4_CH3, - TIM5_CH4, TSC_G4_IO3, SWDIO-JTMS SPI1_MOSI/I2S1_SD, 73 C11 47 35 PF6 I/O FTf - USART3_RTS, TIM4_CH4, - I2C2_SCL 74 F11 - - VSS_3 S - (2) Ground 75 G11 - - VDD_3 S - (2) Digital power supply - - 48 36 PF7 I/O FTf - I2C2_SDA, USART2_CK - I2C1_SDA, TIM12_CH1, 76 A10 49 37 PA14 I/O FTf - - TSC_G4_IO4, SWCLK-JTCK 38/137 DocID022691 Rev 7

STM32F373xx Pinouts and pin description Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, 77 A9 50 38 PA15 I/O FTf - - I2C1_SCL, TIM2_CH1_ETR, TIM12_CH2, TSC_SYNC, JTDI SPI3_SCK/I2S3_CK, 78 B11 51 - PC10 I/O FT (2) - USART3_TX, TIM19_CH1 SPI3_MISO/I2S3_MCK, 79 C10 52 - PC11 I/O FT (2) - USART3_RX, TIM19_CH2 SPI3_MOSI/I2S3_SD, 80 B10 53 - PC12 I/O FT (2) - USART3_CK, TIM19_CH3 81 C9 - - PD0 I/O FT (2) CAN_RX, TIM19_CH4 - 82 B9 - - PD1 I/O FT (2) CAN_TX, TIM19_ETR - 83 C8 54 - PD2 I/O FT (2) TIM3_ETR - SPI2_MISO/I2S2_MCK, 84 B8 - - PD3 I/O FT (2) - USART2_CTS SPI2_MOSI/I2S2_SD, 85 B7 - - PD4 I/O FT (2) - USART2_RTS 86 A6 - - PD5 I/O FT (2) USART2_TX - SPI2_NSS/I2S2_WS, 87 B6 - - PD6 I/O FT (2) - USART2_RX SPI2_SCK/I2S2_CK, 88 A5 - - PD7 I/O FT (2) - USART2_CK SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART2_TX, TIM2_CH2, 89 A8 55 39 PB3 I/O FT - - TIM3_ETR, TIM4_ETR, TIM13_CH1, TSC_G5_IO1, JTDO-TRACESWO SPI1_MISO/I2S1_MCK, SPI3_MISO/I2S3_MCK, USART2_RX, TIM16_CH1, 90 A7 56 40 PB4 I/O FT - - TIM3_CH1, TIM17_BKIN, TIM15_CH1N, TSC_G5_IO2, NJTRST DocID022691 Rev 7 39/137 47

Pinouts and pin description STM32F373xx Table 11. STM32F373xx pin definitions (continued) Pin numbers Pin functions e r Pin name u QFP100 BGA100 QFP64 QFP48 (funcretisoent )after tPypine O struct Notes Alternate function Additional functions L F L L I/ U SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, 91 C5 57 41 PB5 I/O FT - I2C1_SMBAl, USART2_CK, - TIM16_BKIN, TIM3_CH2, TIM17_CH1, TIM19_ETR I2C1_SCL, USART1_TX, TIM16_CH1N, TIM3_CH3, 92 B5 58 42 PB6 I/O FTf - - TIM4_CH1, TIM19_CH1, TIM15_CH1, TSC_G5_IO3 I2C1_SDA, USART1_RX, TIM17_CH1N, TIM3_CH4, 93 B4 59 43 PB7 I/O FTf - - TIM4_CH2, TIM19_CH2, TIM15_CH2, TSC_G5_IO4 94 A4 60 44 BOOT0 I B - Boot memory selection SPI2_SCK/I2S2_CK, I2C1_SCL, USART3_TX, 95 A3 61 45 PB8 I/O FTf - CAN_RX, CEC, TIM16_CH1, - TIM4_CH3, TIM19_CH3, COMP1_OUT, TSC_SYNC SPI2_NSS/I2S2_WS, I2C1_SDA, USART3_RX, 96 B3 62 46 PB9 I/O FTf - CAN_TX, IR_OUT, - TIM17_CH1, TIM4_CH4, TIM19_CH4, COMP2_OUT 97 C3 - - PE0 I/O FT (2) USART1_TX, TIM4_ETR - 98 A2 - - PE1 I/O FT (2) USART1_RX - 99 D3 63 47 VSS_1 S - - Ground 100 C4 64 48 VDD_1 S - - Digital power supply 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED) After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0313 reference manual. 2. When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode. 3. these pins are powered by VDDSD12. 4. these pins are powered by VDDSD3. 40/137 DocID022691 Rev 7

4 P 1/1 Table 12. Alternate functions for port PA in 3 o 7 Pin u AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF14 AF15 ts Name a n TIM2_ TIM5_ d TSC_ COMP1 TIM19 EVENT p PA0 - CH1_ CH1_ G1_IO1 - - - USART2_CTS _OUT - - _CH1 - OUT in ETR ETR d e s RTC_ TIM2_ TIM5_ TSC_ SPI3_SCK/ TIM15_ TIM19 EVENT c PA1 - - USART2_RTS - - - r REFIN CH2 CH2 G1_IO2 I2S3_CK CH1N _CH2 OUT ip t TIM2_ TIM5_ TSC_ SPI3_MISO/ COMP2 TIM15_ TIM19 EVENT io PA2 - - - USART2_TX - - n CH3 CH3 G1_IO3 I2S3_MCK _OUT CH1 _CH3 OUT TIM2_ TIM5_ TSC_ SPI3_MOSI TIM15_ TIM19 EVENT PA3 - - - USART2_RX - - - CH4 CH4 G1_IO4 /I2S3_SD CH2 _CH4 OUT TIM3_ TSC_ SPI1_NSS/ SPI3_NSS/ TIM12 EVENT PA4 - - - USART2_CK - - - - D CH2 G2_IO1 I2S1_WS I2S3_WS _CH1 OUT o c ID TIM2_ TSC_ SPI1_SCK/ TIM14_ TIM12 EVENT 0 PA5 - CH1_ - - - CEC - - - 2 G2_IO2 I2S1_CK CH1 _CH2 OUT 2 ETR 6 9 1 R PA6 - TIM16_ TIM3_ TSC_ - SPI1_MISO - - COMP1 TIM13_ - - - EVENT e CH1 CH1 G2_IO3 /I2S1_MCK _OUT CH1 OUT v 7 TIM17_ TIM3_ TSC_ SPI1_MOSI COMP2 TIM14_ EVENT PA7 - - - - - - - CH1 CH2 G2_IO4 /I2S1_SD _OUT CH1 OUT TIM5_ I2C2_ SPI2_SCK/ TIM4_ EVENT PA8 MCO - CH1_ - - USART1_CK - - - - SMBA I2S2_CK ETR OUT ETR TIM13 TSC_ I2C2_ SPI2_MISO TIM15_ TIM2_ EVENT PA9 - - - USART1_TX - - - _CH1 G4_IO1 SCL /I2S2_MCK BKIN CH3 OUT TIM17_ TSC_ I2C2_ SPI2_MOSI TIM14_ TIM2_ EVENT PA10 - - - USART1_RX - - - BKIN G4_IO2 SDA /I2S2_SD CH1 CH4 OUT TIM5_ SPI2_NSS/ SPI1_NSS/ COMP1 CAN_ TIM4_ EVENT S PA11 - - - - USART1_CTS - - T CH2 I2S2_WS I2S1_WS _OUT RX CH1 OUT M 3 TIM16_ TIM5_ SPI1_SCK/ COMP2 TIM4_ EVENT 2 PA12 - - - - USART1_RTS CAN_TX - - F CH1 CH3 I2S1_CK _OUT CH2 OUT 3 7 3 x x

4 Table 12. Alternate functions for port PA (continued) P 2/1 in 3 Pin o 7 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF14 AF15 u Name t s a SWDIO TIM16_ TIM5_ TSC_ SPI1_MISO TIM4_ EVENT n PA13 - IR-OUT USART3_CTS - - - - d -JTMS CH1N CH4 G4_IO3 /I2S1_MCK CH3 OUT p in PA14 SWCLK - - TSC_ I2C1_ - - - - - TIM12 - - EVENT d -JTCK G4_IO4 SDA _CH1 OUT e s c PA15 JTDI TIM2_ - TSC_ I2C1_ SPI1_NSS/ SPI3_NSS/ - - - TIM12 - - EVENT rip CH1_ETR SYNC SCL I2S1_WS I2S3_WS _CH2 OUT tio n D o c ID 0 2 2 6 9 1 R e v 7 S T M 3 2 F 3 7 3 x x

4 P 3/1 Table 13. Alternate functions for port PB in 3 o 7 u Pin ts Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF15 a n d TSC_ SPI_MOSI/ TIM3_ p PB0 - - TIM3_CH3 G3_IO3 - I2S1_SD - - - - CH2 - EVENTOUT in d e PB1 - - TIM3_CH4 TGS3C_I_O4 - - - - - - - - EVENTOUT scr ip PB2 - - - - - - - - - - - - EVENTOUT tio n JTDO- TIM2_ TSC_ SPI1_SCK/ SPI3_SCK/ TIM13_ TIM3_ PB3 TIM4_ETR - USART2_TX - - EVENTOUT TRACESWO CH2 G5_IO1 I2S1_CK I2S3_CK CH1 ETR TIM16_ TSC_ SPI1_MISO SPI3_MISO/ TIM15_ TIM17 PB4 NJTRST TIM3_CH1 - USART2_RX - - EVENTOUT CH1 G5_IO2 /I2S1_MCK I2S3_MCK CH1N _BKIN D TIM16_ I2C1_ SPI1_MOSI SPI3_MOSI TIM17 TIM19 oc PB5 - BKIN TIM3_CH2 - SMBA /I2S1_SD /I2S3_SD USART2_CK - - _CH1 _ETR EVENTOUT ID 0 TIM16_ TSC_ I2C1_ TIM15_ TIM3_ TIM19 2 PB6 - TIM4_CH1 - - USART1_TX - EVENTOUT 26 CH1N G5_IO3 SCL CH1 CH3 _CH1 9 1 R PB7 - TIM17_ TIM4_CH2 TSC_ I2C1_ - - USART1_RX - TIM15_ TIM3_ TIM19 EVENTOUT e CH1N G5_IO4 SDA CH2 CH4 _CH2 v 7 TIM16_ TSC_ I2C1_ SPI2_SCK/ COMP1 CAN_ TIM19 PB8 - TIM4_CH3 CEC USART3_TX - EVENTOUT CH1 SYNC SCL I2S2_CK _OUT RX _CH3 TIM17_ I2C1_ SPI2_NSS/ COMP2 CAN_ TIM19 PB9 - TIM4_CH4 - IR-OUT USART3_RX - EVENTOUT CH1 SDA I2S2_WS _OUT TX _CH4 TIM2_ TSC_ SPI2_SCK/ PB10 - - - CEC USART3_TX - - - - EVENTOUT CH3 SYNCH I2S2_CK TIM15_ TSC_ SPI2_MISO TIM12_ PB14 - - - - USART3_RTS - - - EVENTOUT CH1 G6_IO1 /I2S2_MCK CH1 TIM15_ TIM15_ TSC_ SPI2_MOSI TIM12_ PB15 RTC_REFIN - - - - - - EVENTOUT CH2 CH1N G6_IO2 /I2S2_SD CH2 S T M 3 2 F 3 7 3 x x

4 Table 14. Alternate functions for port PC P 4/1 in 3 Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 o 7 u t s PC0 - EVENTOUT TIM5_CH1_ETR - - - - - a n PC1 - EVENTOUT TIM5_CH2 - - - - - d p PC2 - EVENTOUT TIM5_CH3 - - SPI2_MISO/I2S2_MCK - - in d e PC3 - EVENTOUT TIM5_CH4 - - SPI2_MOSI/I2S2_SD - - s c r PC4 - EVENTOUT TIM13_CH1 TSC_G3_IO1 - - - USART1_TX ip t PC5 - EVENTOUT - TSC_G3_IO2 - - - USART1_RX io n PC6 - EVENTOUT TIM3_CH1 - - SPI1_NSS/I2S1_WS - - PC7 - EVENTOUT TIM3_CH2 - - SPI1_SCK/I2S1_CK - - PC8 - EVENTOUT TIM3_CH3 - - SPI1_MISO/I2S1_MCK - - D PC9 - EVENTOUT TIM3_CH4 - - SPI1_MOSI/I2S1_SD - - o c ID PC10 - EVENTOUT TIM19_CH1 - - - SPI3_SCK/I2S3_CK USART3_TX 0 2 2 PC11 - EVENTOUT TIM19_CH2 - - - SPI3_MISO/I2S3_MCK USART3_RX 6 9 1 PC12 - EVENTOUT TIM19_CH3 - - - SPI3_MOSI/I2S3_SD USART3_CK R e v PC13 - - - - - - - - 7 PC14 - - - - - - - - PC15 - - - - - - - - S T M 3 2 F 3 7 3 x x

4 Table 15. Alternate functions for port PD P 5/1 in 37 Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ou t s PD0 - EVENTOUT TIM19_CH4 - - - - CAN_RX a n d PD1 - EVENTOUT TIM19_ETR - - - - CAN_TX p in PD2 - EVENTOUT TIM3_ETR - - - - - d e PD3 - EVENTOUT - - - SPI2_MISO/I2S2_MCK - USART2_CTS s c r PD4 - EVENTOUT - - - SPI2_MOSI/I2S2_SD - USART2_RTS ip t io PD5 - EVENTOUT - - - - - USART2_TX n PD6 - EVENTOUT - - - SPI2_NSS/I2S2_WS - USART2_RX PD7 - EVENTOUT - - - SPI2_SCK/I2S2_CK - USART2_CK PD8 - EVENTOUT - TSC_G6_IO3 - SPI2_SCK/I2S2_CK - USART3_TX D PD9 - EVENTOUT - TSC_G6_IO4 - - - USART3_RX o c ID PD10 - EVENTOUT - - - - - USART3_CK 0 2 2 PD11 - EVENTOUT - - - - - USART3_CTS 6 9 1 R PD12 - EVENTOUT TIM4_CH1 TSC_G8_IO1 - - - USART3_RTS e v PD13 - EVENTOUT TIM4_CH2 TSC_G8_IO2 - - - - 7 PD14 - EVENTOUT TIM4_CH3 TSC_G8_IO3 - - - - PD15 - EVENTOUT TIM4_CH4 TSC_G8_IO4 - - - - S T M 3 2 F 3 7 3 x x

4 Table 16. Alternate functions for port PE P 6/1 in 37 Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ou t s PE0 - EVENTOUT TIM4_ETR - - - - USART1_TX a n d PE1 - EVENTOUT - - - - - USART1_RX p in PE2 TRACECLK EVENTOUT - TSC_G7_IO1 - - - - d e PE3 TRACED0 EVENTOUT - TSC_G7_IO2 - - - - s c r PE4 TRACED1 EVENTOUT - TSC_G7_IO3 - - - - ip t io PE5 TRACED2 EVENTOUT - TSC_G7_IO4 - - - - n PE6 TRACED3 EVENTOUT - - - - - - PE7 - EVENTOUT - - - - - - PE8 - EVENTOUT - - - - - - D PE9 - EVENTOUT - - - - - - o c ID PE10 - EVENTOUT - - - - - - 0 2 2 PE11 - EVENTOUT - - - - - - 6 9 1 R PE12 - EVENTOUT - - - - - - e v PE13 - EVENTOUT - - - - - - 7 PE14 - EVENTOUT - - - - - - PE15 - EVENTOUT - - - - - USART3_RX S T M 3 2 F 3 7 3 x x

4 Table 17. Alternate functions for port PF P 7/1 in 37 Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ou t s PF0 - - - - I2C2_SDA - - - a n d PF1 - - - - I2C2_SCL - - - p in PF2 - EVENTOUT - - I2C2_SMBA - - - d e PF4 - EVENTOUT - - - - - - s c r PF6 - EVENTOUT TIM4_CH4 - I2C2_SCL SPI1_MOSI/I2S1_SD - USART3_RTS ip t io PF7 - EVENTOUT - - I2C2_SDA - - USART2_CK n PF9 - EVENTOUT TIM14_CH1 - - - - - PF10 - EVENTOUT - - - - - - D o c ID 0 2 2 6 9 1 R e v 7 S T M 3 2 F 3 7 3 x x

Memory mapping STM32F373xx 5 Memory mapping Figure 6. STM32F373xx memory map (cid:19)(cid:91)(cid:41)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:23)(cid:27)(cid:19)(cid:19)(cid:3)(cid:20)(cid:26)(cid:41)(cid:41) (cid:36)(cid:43)(cid:37)(cid:21) (cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91)(cid:16)(cid:48)(cid:23)(cid:3) (cid:26) (cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3) (cid:19)(cid:91)(cid:23)(cid:27)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:40)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:23)(cid:22)(cid:41)(cid:41) (cid:36)(cid:43)(cid:37)(cid:20) (cid:25) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:38)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:25)(cid:38)(cid:19)(cid:19) (cid:36)(cid:51)(cid:37)(cid:21) (cid:24) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:36)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:36)(cid:19)(cid:19)(cid:19) (cid:36)(cid:51)(cid:37)(cid:20) (cid:23) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:27)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:22) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:25)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:27)(cid:19)(cid:19) (cid:21) (cid:54)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:39)(cid:27)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:20) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:23)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:21)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:54)(cid:53)(cid:36)(cid:48) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19) (cid:38)(cid:50)(cid:39)(cid:40) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:23)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:15)(cid:3)(cid:86)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3) (cid:82)(cid:85)(cid:3)(cid:54)(cid:53)(cid:36)(cid:48)(cid:15)(cid:3)(cid:71)(cid:72)(cid:83)(cid:72)(cid:81)(cid:71)(cid:76)(cid:81)(cid:74)(cid:3) (cid:82)(cid:81)(cid:3)(cid:37)(cid:50)(cid:50)(cid:55)(cid:3)(cid:70)(cid:82)(cid:81)(cid:73)(cid:76)(cid:74)(cid:88)(cid:85)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:24)(cid:28)(cid:57)(cid:20) 48/137 DocID022691 Rev 7

STM32F373xx Memory mapping Table 18. STM32F373xx peripheral register boundary addresses(1) Bus Boundary address Size Peripheral 0x4800 1400 - 0x4800 17FF 1KB GPIOF 0x4800 1000 - 0x4800 13FF 1KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1KB GPIOD AHB2 0x4800 0800 - 0x4800 0BFF 1KB GPIOC 0x4800 0400 - 0x4800 07FF 1KB GPIOB 0x4800 0000 - 0x4800 03FF 1KB GPIOA - 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 3 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH memory interface AHB1 0x4002 1400 - 0x4002 1FFF 3KB Reserved 0x4002 1000 - 0x4002 13FF 1KB RCC 0x4002 0800- 0x4002 0FFF 2KB Reserved 0x4002 0400 - 0x4002 07FF 1KB DMA2 0x4002 0000 - 0x4002 03FF 1KB DMA1 - 0x4001 6C00 - 0x4001 FFFF 37KB Reserved DocID022691 Rev 7 49/137 51

Memory mapping STM32F373xx Table 18. STM32F373xx peripheral register boundary addresses(1) (continued) Bus Boundary address Size Peripheral 0x4001 6800 - 0x4001 6BFF 1KB SDADC3 0x4001 6400 - 0x4001 67FF 1KB SDADC2 0x4001 6000 - 0x4001 63FF 1KB SDADC1 0x4001 5C00 - 0x4001 5FFF 1KB TIM19 0x4001 4C00 - 0x4001 5BFF 4KB Reserved 0x4001 4800 - 0x4001 4BFF 1KB TIM17 0x4001 4400 - 0x4001 47FF 1KB TIM16 0x4001 4000 - 0x4001 43FF 1KB TIM15 APB2 0x4001 3C00 - 0x4001 3FFF 1KB Reserved 0x4001 3800 - 0x4001 3BFF 1KB USART1 0x4001 3400 - 0x4001 37FF 1KB Reserved 0x4001 3000 - 0x4001 33FF 1KB SPI1/I2S1 0x4001 2800 - 0x4001 2FFF 1KB Reserved 0x4001 2400 - 0x4001 27FF 1KB ADC 0x4001 0800 - 0x4001 23FF 7KB Reserved 0x4001 0400 - 0x4001 07FF 1KB EXTI 0x4001 0000 - 0x4001 03FF 1KB SYSCFG + COMP - 0x4000 4000 - 0x4000 FFFF 24KB Reserved 0x4000 9C00 – 0x4000 9FFF 1KB TIM18 0x4000 9800 - 0x4000 9BFF 1KB DAC2 0x4000 7C00 - 0x4000 97FF 8KB Reserved 0x4000 7800 - 0x4000 7BFF 1KB CEC 0x4000 7400 - 0x4000 77FF 1KB DAC1 APB1 0x4000 7000 - 0x4000 73FF 1KB PWR 0x4000 6800 - 0x4000 6FFF 2KB Reserved 0x4000 6400 - 0x4000 67FF 1KB CAN 0x4000 6000 - 0x4000 63FF 1KB USB packet SRAM 0x4000 5C00 - 0x4000 5FFF 1 KB USB FS 50/137 DocID022691 Rev 7

STM32F373xx Memory mapping Table 18. STM32F373xx peripheral register boundary addresses(1) (continued) Bus Boundary address Size Peripheral 0x4000 5800 - 0x4000 5BFF 1KB I2C2 0x4000 5400 - 0x4000 57FF 1KB I2C1 0x4000 4C00 - 0x4000 53FF 2KB Reserved 0x4000 4800 - 0x4000 4BFF 1KB USART3 0x4000 4400 - 0x4000 47FF 1KB USART2 0x4000 4000 - 0x4000 43FF 1KB Reserved 0x4000 3C00 - 0x4000 3FFF 1KB SPI3/I2S3 0x4000 3800 - 0x4000 3BFF 1KB SPI2/I2S2 0x4000 3400 - 0x4000 37FF 1KB Reserved 0x4000 3000 - 0x4000 33FF 1KB IWDG 0x4000 2C00 - 0x4000 2FFF 1KB WWDG APB1 0x4000 2800 - 0x4000 2BFF 1KB RTC 0x4000 2400 - 0x4000 27FF 1KB Reserved 0x4000 2000 - 0x4000 23FF 1KB TIM14 0x4000 1C00 - 0x4000 1FFF 1KB TIM13 0x4000 1800 - 0x4000 1BFF 1KB TIM12 0x4000 1400 - 0x4000 17FF 1KB TIM7 0x4000 1000 - 0x4000 13FF 1KB TIM6 0x4000 0C00 - 0x4000 0FFF 1KB TIM5 0x4000 0800 - 0x4000 0BFF 1KB TIM4 0x4000 0400 - 0x4000 07FF 1KB TIM3 0x4000 0000 - 0x4000 03FF 1KB TIM2 1. Cells in gray indicate Reserved memory locations. DocID022691 Rev 7 51/137 51

Electrical characteristics STM32F373xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V . SS 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = V = V = A DD DDA DDSDx 3.3 V. They are given only as design guidelines and are not tested. Typical ADC and SDADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure7. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure8. Figure 7. Pin loading conditions Figure 8. Pin input voltage (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:57)(cid:44)(cid:49) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:19)(cid:57)(cid:20) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:20)(cid:57)(cid:20) 52/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.1.6 Power supply scheme Figure 9. Power supply scheme (cid:57)(cid:37)(cid:36)(cid:55) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:85)(cid:92) (cid:20)(cid:17)(cid:25)(cid:24)(cid:16)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:51)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:3)(cid:86)(cid:3)(cid:90)(cid:3)(cid:3)(cid:3)(cid:76)(cid:3)(cid:87)(cid:3)(cid:70)(cid:75) (cid:11)(cid:47)(cid:54)(cid:40)(cid:15)(cid:53)(cid:55)(cid:38)(cid:15) (cid:58)(cid:68)(cid:78)(cid:72)(cid:88)(cid:83)(cid:3)(cid:79)(cid:82)(cid:74)(cid:76)(cid:70) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:86)(cid:12) (cid:50)(cid:56)(cid:55) (cid:72)(cid:85) (cid:75)(cid:76)(cid:73)(cid:87) (cid:44)(cid:50) (cid:42)(cid:35)(cid:51)(cid:57)(cid:44)(cid:39)(cid:18)(cid:50)(cid:39)(cid:86) (cid:44)(cid:49) (cid:89)(cid:72)(cid:79)(cid:3)(cid:86) (cid:47)(cid:82)(cid:74)(cid:76)(cid:70) (cid:72) (cid:47) (cid:57)(cid:39)(cid:39) (cid:22)(cid:3)(cid:3)(cid:238)(cid:3)(cid:3)(cid:57)(cid:3)(cid:3)(cid:3)(cid:39)(cid:3)(cid:39) (cid:20)(cid:17)(cid:27)(cid:3)(cid:57) (cid:53)(cid:72)(cid:74)(cid:88)(cid:79)(cid:68)(cid:87)(cid:82)(cid:85) (cid:21)(cid:3)(cid:3)(cid:238)(cid:3)(cid:3)(cid:3)(cid:3)(cid:20)(cid:3)(cid:3)(cid:19)(cid:3)(cid:19)(cid:3)(cid:81)(cid:41) (cid:46)(cid:72)(cid:85)(cid:81)(cid:72)(cid:79)(cid:3)(cid:79)(cid:82)(cid:74)(cid:76)(cid:70)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:14)(cid:3)(cid:20)(cid:3)(cid:238)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:23)(cid:3)(cid:3)(cid:17)(cid:3)(cid:26)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:21)(cid:3)(cid:3)(cid:238)(cid:3)(cid:3)(cid:57)(cid:3)(cid:3)(cid:54)(cid:3)(cid:3)(cid:54) (cid:11)(cid:38)(cid:51)(cid:56)(cid:15)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:39)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:9)(cid:3)(cid:48)(cid:72)(cid:80)(cid:82)(cid:85)(cid:76)(cid:72)(cid:86)(cid:12)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:50)(cid:56)(cid:55) (cid:72)(cid:85) (cid:75)(cid:76)(cid:73)(cid:87) (cid:44)(cid:50) (cid:35)(cid:42)(cid:57)(cid:39)(cid:51)(cid:39)(cid:44)(cid:18)(cid:54)(cid:50)(cid:39)(cid:86)(cid:22) (cid:44)(cid:49) (cid:89)(cid:72)(cid:79)(cid:3)(cid:86) (cid:47)(cid:82)(cid:74)(cid:76)(cid:70) (cid:72) (cid:47) (cid:50)(cid:56)(cid:55) (cid:72)(cid:85) (cid:75)(cid:76)(cid:73)(cid:87) (cid:44)(cid:50) (cid:35)(cid:57)(cid:42)(cid:39)(cid:51)(cid:39)(cid:44)(cid:54)(cid:18)(cid:50)(cid:39)(cid:86)(cid:20)(cid:21) (cid:44)(cid:49) (cid:89)(cid:72)(cid:79)(cid:3)(cid:86) (cid:47)(cid:82)(cid:74)(cid:76)(cid:70) (cid:72) (cid:47) (cid:57)(cid:39)(cid:39)(cid:54)(cid:39)(cid:20)(cid:21) (cid:57)(cid:39)(cid:39)(cid:54)(cid:39)(cid:20)(cid:21) (cid:57)(cid:39)(cid:39)(cid:54)(cid:39)(cid:22) (cid:57)(cid:39)(cid:39)(cid:54)(cid:39)(cid:22) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:57)(cid:54)(cid:54)(cid:54)(cid:39) (cid:54)(cid:76)(cid:74)(cid:80)(cid:68) (cid:39)(cid:72)(cid:79)(cid:87)(cid:68) (cid:36)(cid:39)(cid:38)(cid:86) (cid:57)(cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:14)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:57)(cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:14) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:57)(cid:53)(cid:40)(cid:41)(cid:54)(cid:39)(cid:16) (cid:57)(cid:39)(cid:39)(cid:36) (cid:57)(cid:39)(cid:39)(cid:36) (cid:57)(cid:53)(cid:40)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:36)(cid:39)(cid:38)(cid:18) (cid:36)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74)(cid:29)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:14)(cid:3)(cid:20)(cid:3)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3) (cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:39)(cid:36)(cid:38) (cid:53)(cid:38)(cid:86)(cid:17)(cid:15)(cid:17)(cid:3)(cid:17)(cid:51)(cid:47)(cid:47)(cid:15)(cid:3)(cid:38)(cid:50)(cid:48)(cid:51)(cid:15) (cid:14)(cid:3)(cid:20)(cid:3)(cid:151)(cid:3)(cid:3)(cid:41)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:57)(cid:54)(cid:54)(cid:36) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:22)(cid:21)(cid:57)(cid:22) 1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins. DocID022691 Rev 7 53/137 114

Electrical characteristics STM32F373xx Caution: Each power supply pair (V /V , V /V etc..) must be decoupled with filtering DD SS DDA SSA ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 6.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme (cid:41)(cid:36)(cid:36)(cid:63)(cid:54)(cid:34)(cid:33)(cid:52) (cid:54)(cid:34)(cid:33)(cid:52) (cid:41)(cid:36)(cid:36) (cid:54)(cid:36)(cid:36) (cid:41)(cid:36)(cid:36)(cid:33) (cid:54)(cid:36)(cid:36)(cid:33) (cid:41)(cid:36)(cid:36)(cid:51)(cid:36)(cid:17)(cid:18) (cid:54)(cid:36)(cid:36)(cid:51)(cid:36)(cid:17)(cid:18) (cid:41)(cid:36)(cid:36)(cid:51)(cid:36)(cid:19) (cid:54)(cid:36)(cid:36)(cid:51)(cid:36)(cid:19) (cid:45)(cid:51)(cid:17)(cid:25)(cid:18)(cid:19)(cid:19)(cid:54)(cid:17) 54/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table19: Voltage characteristics, Table20: Current characteristics, and Table21: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 19. Voltage characteristics(1) Symbol Ratings Min Max Unit External main supply voltage (including V V , V V –V DDA, DDSDx BAT - 0.3 4.0 DD SS and V ) DD V –V Allowed voltage difference for V > V - 0.4 DD DDA DD DDA V – V Allowed voltage difference for V > V - 0.4 DDSDx DDA DDSDx DDA V – REFSD+ Allowed voltage difference for V > V - 0.4 V REFSD+ DDSD3 DDSD3 V V – V Allowed voltage difference for V > V - 0.4 REF+ DDA REF+ DDA Input voltage on FT and FTf pins V - 0.3 V + 4.0 SS DD Input voltage on TTa pins V - 0.3 4.0 V (2) SS IN Input voltage on TC pins on SDADCx channels inputs(3) V - 0.3 4.0 SS Input voltage on any other pin V - 0.3 4.0 SS |V - V | - 50 mV SSX SS Variations between all the different ground pins |V - V | - 50 mV REFSD- SSx see Section6.3.12: V Electrostatic discharge voltage (human body model) Electrical sensitivity - ESD(HBM) characteristics 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power supply, in the DD DDA SS SSA permitted range. 2. V maximum must always be respected. Refer to Table20: Current characteristics for the maximum allowed injected IN current values. 3. VDDSD12 is the external power supply for PB2, PB10, and PE7 to PE15 I/O pins (I/O ground pin is internally connected to V ). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (I/O ground pin is internally SS connected to V ). SS All main power (V , V , V and V ) and ground (V , V , and V ) pins DD DDSD12 DDSD3 DDA SS SSSD SSA must always be connected to the external power supply, in the permitted range. The following relationship must be respected between V and V : V must power on DDA DD DDA before or at the same time as V in the power up sequence. V must be greater than or DD DDA equal to V . DD The following relationship must be respected between V and V : V must power DDA DDSD12 DDA on before or at the same time as V or V in the power up sequence. V must DDSD12 DDSD3 DDA be greater than or equal to V or V . DDSD12 DDSD3 The following relationship must be respected between V and V : V must DDSD12 DDSD3 DDSD3 power on before or at the same time as V in the power up sequence. DDSD12 After power up (V > Vrefint = 1.2 V) V can be higher or lower than V . DDSD12 DDSD3 DDSD12 DocID022691 Rev 7 55/137 114

Electrical characteristics STM32F373xx The following relationship must be respected between V and V , V : REFSD+ DDSD12 DDSD3 V must be lower than V . REFSD+ DDSD3 Depending on the SDADCx operation mode, there can be more constraints between V , V and V which are described in reference manual RM0313. REFSD+ DDSD12 DDSD3 Table 20. Current characteristics Symbol Ratings Max. Unit Total current into sum of all VDD_xand VDDSDx power lines ΣI 160 VDD (source)(1) Total current out of sum of all VSS_xand VSSSD ground lines ΣI -160 VSS (sink)(1) I Maximum current into each VDD_x or VDDSDx power pin (source)(1) 100 VDD(PIN) I Maximum current out of each VSS_x or VSSSD ground pin (sink)(1) -100 VSS(PIN) Output current sunk by any I/O and control pin 25 I IO(PIN) Output current source by any I/O and control pin -25 mA Total output current sunk by sum of all IOs and control pins(2) 80 ΣI IO(PIN) Total output current sourced by sum of all IOs and control pins(2) -80 Injected current on FT, FTf and B pins(3) -5/+0 I Injected current on TC and RST pin(4) ± 5 INJ(PIN) Injected current on TTa pins(5) ± 5 ΣI Total injected current (sum of all I/O and control pins)(6) ± 25 INJ(PIN) 1. VDDSD12 is the external power supply for the PB2, PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected to V ). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground SS is internally connected to V ). V (VDD_x) is the external power supply for all remaining I/O pins (the I/O pin ground is SS DD internally connected to V ). SS 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by V >V while a negative injection is induced by V < V . I must never be IN DD IN SS INJ(PIN) exceeded. Refer to Table19: Voltage characteristics for the maximum allowed input voltage values. 5. A positive injection is induced by V >V while a negative injection is induced by V < V . I (PIN) must never be IN DDA IN SS INJ exceeded. Refer also to Table19: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note (2) below Table62. 6. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the positive and INJ(PIN) negative injected currents (instantaneous values). Table 21. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range –65 to +150 °C STG T Maximum junction temperature 150 °C J 56/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter Conditions Min Max Unit f Internal AHB clock frequency - 0 72 HCLK f Internal APB1 clock frequency - 0 36 MHz PCLK1 f Internal APB2 clock frequency - 0 72 PCLK2 Must have a potential equal to V Standard operating voltage 2.0 3.6 V DD or lower than V DDA Analog operating voltage 2.4 3.6 (ADC and DAC used) Must have a potential equal to V (1) V DDA Analog operating voltage or higher than VDD 2.0 3.6 (ADC and DAC not used) VDDSD12 operating voltage 2.2 3.6 (SDADC used) Must have a potential equal to V V DDSD12 VDDSD12 operating voltage or lower than VDDA 2.0 3.6 (SDADC not used) VDDSD3 operating voltage 2.2 3.6 (SDADC used) Must have a potential equal to V V DDSD3 VDDSD3 operating voltage or lower than VDDA 2.0 3.6 (SDADC not used) Positive reference voltage (ADC 2.4 3.6 and DAC used) Must have a potential equal to V V REF+ or lower than V Positive reference voltage (ADC DDA 2.0 3.6 and DAC not used) SDADCx positive reference Must have a potential equal to V 1.1 3.6 V REFSD+ voltage or lower than any V DDSDx V Backup operating voltage - 1.65 3.6 V BAT Input voltage on FT and FTf pins(2) - 0.3 5.5 Input voltage on TTa pins - 0.3 V + 0.3 DDA Input voltage on TC pins on - 0.3 V + 0.3 V SDADCx channels inputs(3) - DDSDx V IN Input voltage on BOOT0 pin 0 5.5 V Input voltage on any other pin - 0.3 DD + 0.3 LQFP100 - 434 Power dissipation at TA = 85°C for LQFP64 - 444 P suffix 6 or T = 105°C for suffix mW D A 7(4) LQFP48 - 364 UFBGA100 - 338 DocID022691 Rev 7 57/137 114

Electrical characteristics STM32F373xx Table 22. General operating conditions (continued) Symbol Parameter Conditions Min Max Unit Ambient temperature for 6 suffix Maximum power dissipation –40 85 °C version Low power dissipation(5) –40 105 TA Ambient temperature for 7 suffix Maximum power dissipation –40 105 °C version Low power dissipation(5) –40 125 6 suffix version –40 105 TJ Junction temperature range °C 7 suffix version –40 125 1. When the ADC is used, refer to Table60: ADC characteristics. 2. To sustain a voltage higher than V +0.3 V, the internal pull-up/pull-down resistors must be disabled. DD 3. VDDSD12 is the external power supply for the PB2, PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally connected to VSS). 4. If T is lower, higher P values are allowed as long as T does not exceed T . A D J Jmax 5. In low power dissipation state, T can be extended to this range as long as T does not exceed T . A J Jmax 6.3.2 Operating conditions at power-up / power-down The parameters given in Table23 are derived from tests performed under the ambient temperature condition summarized in Table22. Table 23. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max Unit V rise time rate 0 ∞ DD t - VDD V fall time rate 20 ∞ DD µs/V V rise time rate 0 ∞ DDA t - VDDA V fall time rate 20 ∞ DDA 58/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.3 Embedded reset and power control block characteristics The parameters given in Table24 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table22. DD Table 24. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit Power on/power down Falling edge 1.80(2) 1.88 1.96 V V (1) POR/PDR reset threshold Rising edge 1.84 1.92 2.00 V V (3) PDR hysteresis - - 40 - mV PDRhyst t (3) POR reset temporization - 1.50 2.50 4.50 ms RSTTEMPO 1. The PDR detector monitors VDD, VDDA and VDDSD12 (if kept enabled in the option bytes). The POR detector monitors only V . DD 2. The product behavior is guaranteed by design down to the minimum V value. POR/PDR 3. Guaranteed by design. Table 25. Programmable voltage detector characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit Rising edge 2.10 2.18 2.26 V V PVD threshold 0 PVD0 Falling edge 2.00 2.08 2.16 V Rising edge 2.19 2.28 2.37 V V PVD threshold 1 PVD1 Falling edge 2.09 2.18 2.27 V Rising edge 2.28 2.38 2.48 V V PVD threshold 2 PVD2 Falling edge 2.18 2.28 2.38 V Rising edge 2.38 2.48 2.58 V V PVD threshold 3 PVD3 Falling edge 2.28 2.38 2.48 V Rising edge 2.47 2.58 2.69 V V PVD threshold 4 PVD4 Falling edge 2.37 2.48 2.59 V Rising edge 2.57 2.68 2.79 V V PVD threshold 5 PVD5 Falling edge 2.47 2.58 2.69 V Rising edge 2.66 2.78 2.9 V V PVD threshold 6 PVD6 Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3.00 V V PVD threshold 7 PVD7 Falling edge 2.66 2.78 2.90 V V (2) PVD hysteresis - - 100 - mV PVDhyst PVD current IDD(PVD)(2) - - 0.15 0.26 µA consumption 1. Guaranteed by characterization results. 2. Guaranteed by design. DocID022691 Rev 7 59/137 114

Electrical characteristics STM32F373xx 6.3.4 Embedded reference voltage The parameters given in Table27 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table22. DD Table 26. Embedded internal reference voltage calibration values Calibration value name Description Memory address Raw data acquired at VREFINT_CAL temperature of 30 °C 0x1FFF F7BA - 0x1FFF F7BB V = 3.3V DDA Table 27. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit V Internal reference voltage –40°C < T < +105°C 1.20 1.23 1.25 V REFINT A ADC sampling time when T (1) reading the internal reference - 17.10 - - µs S_vrefint voltage Internal reference voltage V (2) spread over the temperature V = 3 V ±10 mV - - 10 mV REFINT_s DD range T (2) Temperature coefficient - - - 100 ppm/°C Coeff t (2) Startup time - - - 10 µs START 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 60/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at V or V (no load) DD SS • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted to the f frequency (0 wait state from 0 HCLK to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48MHz to 72MHz) • Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled f = f /2 , f = f APB1 AHB APB2 AHB • When f > 8 MHz PLL is ON and PLL inputs is equal to HSI/2 = 4 MHz (if internal HCLK clock is used) or HSE = 8 MHz (if HSE bypass mode is used) The parameters given in Table28 to Table34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table22. Table 2 8 . Typical and maximum current consumption from V supply at V = 3.6 V(1) DD DD All peripherals enabled All peripherals disabled Symbol Parameter Conditions f Max @ T (2) Max @ T (2) Unit HCLK A A Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 72 MHz 63.1 70.7 71.5 73.4 29.2 31.1 31.7 34.2 64 MHz 56.3 63.3 64.1 64.9 26.1 27.8 28.4 30.4 HSE bypass, 48 MHz 42.5 48.5 48.0 50.1 19.9 22.6 21.9 23.1 PLL on 32 MHz 28.8 31.4 32.2 34.3 13.1 16.1 14.9 16.2 24 MHz 21.9 24.4 24.4 25.8 10.1 10.9 11.9 12.4 Supply current in HSE 8 MHz 7.3 8.0 9.3 9.3 3.7 4.1 4.4 5.0 Run mode, bypass, I mA DD code PLL off 1 MHz 1.1 1.5 1.8 2.3 0.8 1.1 1.4 1.9 executing 64 MHz 51.7 57.7 58.0 60.4 25.8 27.6 28.1 30.1 from Flash 48 MHz 38.6 45.9 43.5 46.9 19.8 21.9 21.7 22.8 HSI clock, PLL on 32 MHz 26.4 31.1 29.7 31.9 13.1 15.7 14.8 16.2 24 MHz 20.3 22.6 22.6 23.7 6.9 7.5 8.1 8.8 HSI clock, 8 MHz 7.0 7.6 8.8 8.8 3.7 4.1 4.4 5.0 PLL off DocID022691 Rev 7 61/137 114

Electrical characteristics STM32F373xx Table 28. Typical and maximum current consumption from V supply at V = 3.6 V(1) DD DD All peripherals enabled All peripherals disabled Symbol Parameter Conditions f Max @ T (2) Max @ T (2) Unit HCLK A A Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 63.6 30.0 72 MHz 70.7(3) 75.7(3) 72.3(3) 31.9(3) 32.6(3) 33.8(3) (3) (3) HSE 64 MHz 56.7 62.5 67.1 64.0 26.7 28.6 29.3 30.0 bypass, 48 MHz 42.0 50.5 47.4 50.1 20.2 21.5 22.1 22.7 PLL on 32 MHz 28.3 32.1 31.8 33.7 13.4 14.6 14.8 15.7 Supply 24 MHz 21.1 25.0 24.2 25.9 10.0 11.3 11.2 12.6 current in HSE 8 MHz 6.9 7.4 8.3 8.7 3.4 3.7 4.1 4.8 Run mode, bypass, code PLL off 1 MHz 0.8 1.2 1.5 2.0 0.4 0.6 1.0 1.5 executing from RAM 64 MHz 51.9 59.5 59.4 58.6 26.4 28.1 28.7 29.5 HSI clock, 48 MHz 38.1 44.7 43.8 45.4 20.0 21.3 21.9 22.3 PLL on 32 MHz 25.9 31.2 29.4 30.5 13.2 14.3 14.6 15.5 24 MHz 19.6 22.7 22.6 23.2 6.5 7.0 7.9 8.2 HSI clock, 8 MHz 6.6 7.1 8.0 8.4 3.3 3.7 4.0 4.7 I PLL off mA DD 72 MHz 43.2 46.9 48.7 52.5 6.7 7.2 7.6 8.3 64 MHz 38.5 41.6 43.7 46.6 5.9 6.5 6.8 7.5 HSE bypass, 48 MHz 29.1 31.3 32.5 34.1 4.5 4.9 5.3 5.9 PLL on 32 MHz 19.4 21.1 24.6 23.0 3.0 3.4 3.8 4.4 Supply 24 MHz 14.7 16.1 18.5 17.6 2.4 2.6 3.0 3.6 current in Sleep HSE 8 MHz 4.9 5.3 6.1 6.6 0.8 1.0 1.4 1.9 mode, bypass, code PLL off 1 MHz 0.6 0.9 1.3 1.8 0.1 0.3 0.6 1.2 executing 64 MHz 34.5 37.1 39.6 42.0 5.6 6.1 6.5 7.1 from Flash or RAM HSI clock, 48 MHz 26.1 28.0 29.0 30.7 4.2 4.6 5.0 5.6 PLL on 32 MHz 17.4 19.1 21.1 20.8 2.9 3.2 3.6 4.2 24 MHz 13.3 14.6 16.1 16.0 1.5 1.8 2.2 2.6 HSI clock, 8 MHz 4.5 4.9 5.5 6.1 0.7 0.9 1.3 1.8 PLL off 1. To calculate complete device consumption there must be added consumption from VDDA (Table 29.). 2. Data based on characterization results, not tested in production unless otherwise specified. 3. Data based on characterization results and tested in production with code executing from RAM. 62/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics T able 29. Typical and maximum current consumption from V supply DDA V = 2.4 V V = 3.6 V DDA DDA Conditions Symbol Parameter f Max @ T (2) Max @ T (2) Unit (1) HCLK A A Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 72 MHz 228 261 274 280 249 288 304 311 64 MHz 201 235 247 251 220 257 269 275 HSE bypass, 48 MHz 152 182 190 195 164 196 208 212 PLL on 32 MHz 104 132 137 141 112 141 147 150 Supply current in 24 MHz 81 108 112 111 87 115 119 119 Run or HSE 8 MHz 2 4 4 5 3 5 5 6 Sleep bypass, IDDA mode, PLL off 1 MHz 2 4 5 5 3 5 5 6 µA code executing 64 MHz 270 307 320 326 298 337 353 361 from Flash or RAM HSI clock, 48 MHz 220 254 264 269 243 276 292 297 PLL on 32 MHz 172 203 211 214 191 222 232 235 24 MHz 151 181 185 189 166 194 201 204 HSI clock, 8 MHz 70 85 87 87 81 93 96 98 PLL off 1. Current consumption from the V supply is independent of whether the peripherals are on or off. Furthermore when the DDA PLL is off, I is independent from the frequency. DDA 2. Guaranteed by characterization results. Tab le 30. Typical and maximum V consumption in Stop and Standby modes DD Typ@V (V =V ) Max DD DD DDA Symbol Parameter Conditions Unit T = T = T = 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V A A A 25 °C 85 °C 105 °C Regulators in run mode, all 19.33 19.58 19.68 19.73 19.76 19.84 46.5 480 1019 oscillators Supply OFF current in Regulators in Stop mode low-power I mode, all 7.72 7.88 8.01 8.13 8.25 8.27 31.8 451.4 966.0 µA DD oscillators OFF Supply LSI ON and 0.78 0.95 1.07 1.21 1.32 1.45 - - - current in IWDG ON Standby LSI OFF and mode IWDG OFF 0.61 0.72 0.81 0.90 0.98 1.08 2.7 3.5 5.3 Note: V monitoring is OFF and V monitoring is OFF. DDA DDSD12 To calculate complete device consumption there must be added consumption from V (Table 31.) DDA DocID022691 Rev 7 63/137 114

Electrical characteristics STM32F373xx Tab l e 31. Typical and maximum V consumption in Stop and Standby modes DDA Typ@V (V =V ) Max(1) DD DD DDA Symbol Parameter Conditions Unit T = T = T = 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V A A A 25 °C 85 °C 105 °C Regulator in run mode, all 1.99 2.07 2.19 2.33 2.46 2.64 10.8 11.8 12.4 Supply oscillators OFF current in Regulator in Stop mode low-power 2 1.99 2.07 2.18 2.32 2.47 2.63 10.6 11.5 12.5 I D1 mode, all DDA S D oscillators OFF D V Supply d LSI ON and 2.44 2.53 2.7 2.89 3.09 3.33 - - - µA current in n IWDG ON a Smtoadnedby DDA LIWSID OGF OF FaFnd 1.87 1.94 2.06 2.19 2.35 2.51 4.1 4.5 4.8 V Supply current for IDDAmon V and - 0.95 1.02 1.12 1.2 1.27 1.4 - - - DDA V DDSD12 monitoring 1. Data based on characterization results and tested in production. 2. To obtain data with monitoring OFF is necessary to substract the IDDAmon current. T able 32. Typical and maximum current consumption from V supply(1) BAT Typ @ V Max(2) BAT Symbol Parameter Conditions V V V V V V V Unit = 1.65 = 1.8 = 2.0 = 2.4 = 2.7 = 3.3 = 3.6 2T5A °=C 8T5A °=C 10T5A =°C LSE & RTC ON; "Xtal mode" lower 0.50 0.52 0.55 0.63 0.70 0.87 0.95 1.1 1.6 2.2 Backup driving capability; I domain LSEDRV[1:0] = '00' DD_ µA VBAT supply LSE & RTC ON; current "Xtal mode" higher 0.85 0.90 0.93 1.02 1.10 1.27 1.38 1.6 2.4 3.0 driving capability; LSEDRV[1:0] = '11' 1. Crystal used: Abracon ABS07-120-32.768kHz-T with 6 pF of CL for typical values. 2. Guaranteed by characterization results. 64/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 11. Typical V current consumption (LSE and RTC ON/LSEDRV[1:0]='00') BAT (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:23) (cid:20)(cid:17)(cid:25)(cid:24)(cid:3)(cid:57) (cid:20)(cid:17)(cid:21) (cid:20)(cid:17)(cid:27)(cid:3)(cid:57) (cid:20) (cid:9) (cid:21)(cid:3)(cid:57) (cid:33) (cid:151) (cid:0)(cid:8)(cid:52) (cid:19)(cid:17)(cid:27) (cid:21)(cid:17)(cid:23)(cid:3)(cid:57) (cid:33) (cid:34) (cid:21)(cid:17)(cid:26)(cid:3)(cid:57) (cid:54) (cid:41) (cid:19)(cid:17)(cid:25) (cid:22)(cid:3)(cid:57) (cid:19)(cid:17)(cid:23) (cid:22)(cid:17)(cid:22)(cid:3)(cid:57) (cid:19)(cid:17)(cid:21) (cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:19) (cid:21)(cid:24)(cid:131)(cid:38) (cid:25)(cid:19)(cid:131)(cid:38) (cid:27)(cid:24)(cid:131)(cid:38) (cid:20)(cid:19)(cid:24)(cid:131)(cid:38) (cid:52) (cid:8)(cid:160)(cid:35)(cid:9) (cid:33) (cid:45)(cid:51)(cid:19)(cid:17)(cid:20)(cid:17)(cid:19)(cid:54)(cid:17) Typical current consumption The MCU is placed under the following conditions: • V = V = V = V = 3.3 V DD DDA DDSD12 DDSD3 • All I/O pins are in analog input configuration • The Flash access time is adjusted to f frequency (0 wait states from 0 to 24 MHz, HCLK 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz) • Prefetch is ON • When the peripherals are enabled, f = f , f = f APB1 AHB APB2 AHB • PLL is used for frequencies greater than 8 MHz • AHB prescaler of 2, 4, 8, 16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz, 500 kHz and 125 kHz respectively DocID022691 Rev 7 65/137 114

Electrical characteristics STM32F373xx Table 33. T y pical current consumption in Run mode, code with data processing running from Flash Typ Symbol Parameter Conditions f Unit HCLK Peripherals Peripherals enabled disabled 72 MHz 61.4 28.8 64 MHz 55.4 25.9 Running from HSE crystal clock 8 MHz, 48 MHz 42.3 20.0 code executing 32 MHz 28.7 13.8 from Flash, PLL on 24 MHz 21.9 10.7 Supply current in 16 MHz 14.8 7.4 I Run mode from mA DD V supply 8 MHz 7.8 4.1 DD 4 MHz 4.6 2.6 Running from HSE crystal clock 8 MHz, 2 MHz 2.9 1.8 code executing 1 MHz 2.0 1.3 from Flash, PLL off 500 kHz 1.5 1.1 125 kHz 1.2 1.0 72 MHz 243.3 242.4 64 MHz 214.3 213.3 Running from HSE crystal clock 8 MHz, 48 MHz 159.3 158.3 code executing 32 MHz 107.7 107.3 from Flash, PLL on 24 MHz 82.8 82.6 Supply current in 16 MHz 58.4 58.2 I (1)(2) Run mode from µA DDA V supply 8 MHz 1.2 1.2 DDA 4 MHz 1.2 1.2 Running from HSE crystal clock 8 MHz, 2 MHz 1.2 1.2 code executing 1 MHz 1.2 1.2 from Flash, PLL off 500 kHz 1.2 1.2 125 kHz 1.2 1.2 Supply currents in Run mode from I + SDADC12 V and - - 2.5 1 µA I DDSD12 SDADC3 V (SDADCs DDSD3 are off) 1. VDDA monitoring is off, VDDSD12 monitoring is off. 2. When peripherals are enabled, power consumption of the analog part of peripherals such as ADC, DACs, Comparators, etc. is not included. Refer to those peripherals characteristics in the subsequent sections. 66/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 3 4 . Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol Parameter Conditions f Unit HCLK Peripherals Peripherals enabled disabled 72 MHz 42.8 6.9 64 MHz 38.2 6.2 Running from HSE crystal clock 8 MHz, 48 MHz 28.9 4.8 code executing from Flash or RAM, 32 MHz 19.5 3.4 PLL on 24 MHz 14.7 2.7 Supply current in 16 MHz 10.2 2.0 I Sleep mode from mA DD V supply 8 MHz 5.2 1.2 DD 4 MHz 3.4 1.1 Running from HSE crystal clock 8 MHz, 2 MHz 2.2 0.9 code executing from Flash or RAM, 1 MHz 1.6 0.9 PLL off 500 kHz 1.4 0.8 125 kHz 1.1 0.8 72 MHz 242.9 241.5 64 MHz 213.7 212.7 Running from HSE crystal clock 8 MHz, 48 MHz 158.8 158.0 code executing from Flash or RAM, 32 MHz 107.6 107.3 PLL on 24 MHz 82.7 82.6 Supply current in 16 MHz 58.3 58.2 I (1) Sleep mode from µA DDA V supply 8 MHz 1.2 1.2 DDA 4 MHz 1.2 1.2 Running from HSE crystal clock 8 MHz, 2 MHz 1.2 1.2 code executing from Flash or RAM, 1 MHz 1.2 1.2 PLL off 500 kHz 1.2 1.2 125 kHz 1.2 1.2 1. VDDA monitoring is off, VDDSD12 monitoring is off. DocID022691 Rev 7 67/137 114

Electrical characteristics STM32F373xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table52: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC and SDADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. Under reset conditions all I/Os are configured in input floating mode - so if some inputs do not have a defined voltage level then they can generate additional consumption. This consumption is visible on V supply and also on V supply DD DDSDx because some I/Os are powered from SDADCx supply (all I/Os which have SDADC analog input functionality). I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table36: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I = V × f × C SW DD SW where I is the current sunk by a switching I/O to charge/discharge the capacitive load SW V is the MCU supply voltage DD f is the I/O switching frequency SW C is the total capacitance seen by the I/O pin: C = C + C + C INT EXT S C is the PCB board capacitance including the pad pin. S The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 68/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 35. Switching output I/O current consumption I/O toggling Symbol Parameter Conditions(1) Typ Unit frequency (f ) SW 2 MHz 0.77 4 MHz 0.87 V = 3.3V DD 8 MHz 0.95 C = 0pF ext 18 MHz 1.59 C = C + C + C INT EXT S 36 MHz 2.57 48 MHz 3.11 2 MHz 0.96 4 MHz 1.0 V = 3.3V DD 8 MHz 1.08 C = 10 pF mA ext 18 MHz 2.17 C = C + C + CS INT EXT 36 MHz 3.42 48 MHz 5.50 2 MHz 0.98 4 MHz 1.23 ISW cIo/Ons cuumrrpetinotn CVDD == 232.3 pVF 8 MHz 1.48 ext C = CINT + CEXT+ CS 18 MHz 2.93 36 MHz 6.59 48 MHz 7.03 2 MHz 1.03 4 MHz 1.3 V = 3.3V DD C = 33 pF 8 MHz 1.81 ext C = C + C + C INT EXT S 18 MHz 3.42 36 MHz 8.27 mA 2 MHz 1.09 4 MHz 1.55 V = 3.3V DD C = 47 pF 8 MHz 2.18 ext C = C + C + C INT EXT S 18 MHz 4.38 36 MHz 9.65 1. C = 5 pF (estimated value). S DocID022691 Rev 7 69/137 114

Electrical characteristics STM32F373xx On-chip peripheral current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The given value is calculated by measuring the current consumption – with all peripherals clocked off; – with only one peripheral clocked on. • Ambient operating temperature at 25°C and V = V = 3.3 Volts. DD DDA Table 36. Peripheral current consumption Peripheral Typical consumption(1) Unit AHB peripherals - BusMatrix(2) 6.9 DMA1 18.3 DMA2 4.8 CRC 2.6 GPIOA 12.2 GPIOB 11.9 GPIOC 4.3 GPIOD 12.0 GPIOE 4.4 GPIOF 3.7 TSC 5.7 APB2 peripherals µA/MHz APB2-Bridge(3) 4.2 SYSCFG & COMP 2.8 ADC1 17.7 SPI1 12.3 USART1 22.9 TIM15 15.7 TIM16 12.2 TIM17 12.1 TIM19 18.5 SDAC1 10.8 SDAC2 10.5 SDAC3 10.3 70/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 36. Peripheral current consumption (continued) Peripheral Typical consumption(1) Unit APB1 peripherals APB1-Bridge(3) 6.9 TIM2 47.9 TIM3 36.8 TIM4 36.9 TIM5 45.5 TIM6 8.4 TIM7 8.2 TIM12 21.3 TIM13 14.2 TIM14 14.4 TIM18 10.1 WWDG 4.7 µA/MHz SPI2 24.3 SPI3 25.3 USART2 45.3 USART3 43.1 I2C1 14.0 I2C2 13.9 USB 27.9 CAN 38.1 DAC2 7.7 PWR 5.4 DAC1 14.8 CEC 5.4 1. When peripherals are enabled, power consumption of the analog part of peripherals such as ADC, DACs, Comparators, etc. is not included. Refer to those peripherals characteristics in the subsequent sections. 2. The BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2). 3. The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus. 6.3.6 Wakeup time from low-power mode The wakeup times given in Table37 are measured from the wakeup event trigger to the first instruction executed by the CPU. The clock source used to wake up the device depends from the current operating mode: • Stop or sleep mode: the wakeup event is WFE. • The WKUP1 (PA0) pin is used to wakeup from standby, stop and sleep modes. DocID022691 Rev 7 71/137 114

Electrical characteristics STM32F373xx All timings are derived from tests performed under ambient temperature and V supply DD voltage conditions summarized in Table22. Table 37. Low-power mode wakeup timings Typ @V = V DD DDA Symbol Parameter Conditions Max Unit = 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V Regulator in run mode 4.1 3.9 3.8 3.7 3.6 4.5 Wakeup from Stop tWUSTOP mode Regulator in low 7.9 6.7 6.1 5.7 5.4 8.6 power mode µs t Wakeup from WUSTANDB LSI and IWDG off 62.6 53.7 49.2 45.7 42.7 100 Standby mode Y CPU Wakeup from Sleep t After WFE instruction 6 clock WUSLEEP mode cycles 6.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section6.3.14. However, the recommended clock input waveform is shown in Figure12. Table 38. High-speed external user clock characteristics Symbol Parameter(1) Conditions Min Typ Max Unit CSS is on or 1 User external clock source PLL is used f 8 32 MHz HSE_ext frequency CSS is off, 0 PLL not used V OSC_IN input pin high level voltage - 0.7V - V HSEH DD DD V V OSC_IN input pin low level voltage - V - 0.3V HSEL SS DD t w(HSEH) OSC_IN high or low time - 15 - - t w(HSEL) ns t r(HSE) OSC_IN rise or fall time - - - 20 t f(HSE) 1. Guaranteed by design. 72/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 12. High-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:43)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:43)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:43)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:23)(cid:57)(cid:21) Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section6.3.14. However, the recommended clock input waveform is shown in Figure13. Table 39. Low-speed external user clock characteristics Symbol Parameter(1) Conditions Min Typ Max Unit User External clock source f - - 32.768 1000 kHz LSE_ext frequency OSC32_IN input pin high level V - 0.7V - V LSEH voltage DD DD V OSC32_IN input pin low level V - V - 0.3V LSEL voltage SS DD t w(LSEH) OSC32_IN high or low time - 450 - - t w(LSEL) ns t r(LSE) OSC32_IN rise or fall time - - - 50 t f(LSE) 1. Guaranteed by design. DocID022691 Rev 7 73/137 114

Electrical characteristics STM32F373xx Figure 13. Low-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:47)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:47)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:47)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:24)(cid:57)(cid:21) High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. HSE oscillator characteristics Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit f Oscillator frequency - 4 8 32 MHz OSC_IN R Feedback resistor - - 200 - kΩ F During startup(3) - - 8.5 V = 3.3 V, Rm= 30 Ω, DD - 0.4 - CL= 10 pF@8 MHz V = 3.3 V, Rm= 45 Ω, DD - 0.5 - CL= 10 pF@8 MHz IDD HSE current consumption VDD = 3.3 V, Rm= 30 Ω, - 0.8 - mA CL=5 pF@32 MHz V = 3.3 V, Rm= 30 Ω, DD - 1 - CL= 10 pF@32 MHz V = 3.3 V, Rm= 30 Ω, DD - 1.5 - CL= 20 pF@32 MHz g Oscillator transconductance Startup 10 - - mA/V m t (4) Startup time V is stabilized - 2 - ms SU(HSE) DD 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz SU(HSE) oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 74/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics For C and C , it is recommended to use high-quality external ceramic capacitors in the L1 L2 5pF to 20pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure14). C and C are usually the L1 L2 same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C . PCB and MCU pin capacitance must be included (10pF L1 L2 can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . L1 L2 Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 14. Typical application with an 8 MHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3) (cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:73)(cid:43)(cid:54)(cid:40) (cid:37)(cid:76)(cid:68)(cid:86)(cid:3) (cid:27)(cid:3)(cid:48)(cid:43)(cid:93)(cid:3) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:71)(cid:3) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:53)(cid:41) (cid:74)(cid:68)(cid:76)(cid:81) (cid:53)(cid:40)(cid:59)(cid:55)(cid:11)(cid:20)(cid:12) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:38)(cid:47)(cid:21) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:26)(cid:25)(cid:57)(cid:20) 1. R value depends on the crystal characteristics. EXT DocID022691 Rev 7 75/137 114

Electrical characteristics STM32F373xx Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table41. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 41. LSE oscillator characteristics (f = 32.768 kHz) LSE Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit LSEDRV[1:0]=00 - 0.5 0.9 lower driving capability LSEDRV[1:0]= 10 - - 1 medium low driving capability I LSE current consumption µA DD LSEDRV[1:0] = 01 - - 1.3 medium high driving capability LSEDRV[1:0]=11 - - 1.6 higher driving capability LSEDRV[1:0]=00 5 - - lower driving capability LSEDRV[1:0]= 10 8 - - Oscillator medium low driving capability g µA/V m transconductance LSEDRV[1:0] = 01 15 - - medium high driving capability LSEDRV[1:0]=11 25 - - higher driving capability t (3) Startup time V is stabilized - 2 - s SU(LSE) DD 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. Guaranteed by design. 3. t is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768kHz oscillation is SU(LSE) reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. 76/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 15. Typical application with a 32.768 kHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75) (cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:73)(cid:47)(cid:54)(cid:40) (cid:39)(cid:85)(cid:76)(cid:89)(cid:72) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93) (cid:3)(cid:83)(cid:85)(cid:82)(cid:74)(cid:85)(cid:68)(cid:80)(cid:80)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:68)(cid:80)(cid:83)(cid:79)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:38) (cid:47)(cid:21) (cid:48)(cid:54)(cid:22)(cid:19)(cid:21)(cid:24)(cid:22)(cid:57)(cid:20) Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.8 Internal clock source characteristics The parameters given in Table42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table22. The provided curves are characterization results, not tested in production. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit f Frequency - - 8 - MHz HSI TRIM HSI user trimming step - - - 1(2) % DuCy Duty cycle - 45(2) - 55(2) % (HSI) T = –40 to 105°C –3.8(3) - 4.6(3) % A Accuracy of the HSI T = –10 to 85°C –2.9(3) - 2.9(3) % A ACC oscillator (factory HSI calibrated) TA = 0 to 70°C –2.3(3) - –2.2(3) % T = 25°C –1 - 1 % A HSI oscillator startup t - 1(3) - 2(3) µs su(HSI) time HSI oscillator power I - - 80 100(3) µA DD(HSI) consumption 1. V =3.3V, T = –40 to 105°C unless otherwise specified. DDA A 2. Guaranteed by design. 3. Guaranteed by characterization results. DocID022691 Rev 7 77/137 114

Electrical characteristics STM32F373xx Figure 16. HSI oscillator accuracy characterization results (cid:21)(cid:5) (cid:45)(cid:33)(cid:56) (cid:45)(cid:41)(cid:46) (cid:20)(cid:5) (cid:19)(cid:5) (cid:18)(cid:5) (cid:17)(cid:5) (cid:52)(cid:0)(cid:0)(cid:59)(cid:160)(cid:35)(cid:61) (cid:16)(cid:5) (cid:33) (cid:13)(cid:20)(cid:16) (cid:13)(cid:18)(cid:16) (cid:16) (cid:18)(cid:16) (cid:20)(cid:16) (cid:22)(cid:16) (cid:24)(cid:16) (cid:17)(cid:16)(cid:16) (cid:17)(cid:18)(cid:16) (cid:13)(cid:17)(cid:5) (cid:13)(cid:18)(cid:5) (cid:13)(cid:19)(cid:5) (cid:13)(cid:20)(cid:5) (cid:13)(cid:21)(cid:5) (cid:45)(cid:51)(cid:19)(cid:16)(cid:25)(cid:24)(cid:22)(cid:54)(cid:18) Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics(1) Symbol Parameter Min Typ Max Unit f Frequency 30 40 60 kHz LSI t (2) LSI oscillator startup time - - 85 µs su(LSI) I (2) LSI oscillator power consumption - 0.75 1.2 µA DD(LSI) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design. 6.3.9 PLL characteristics The parameters given in Table44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table22. Table 44. PLL characteristics Value Symbol Parameter Unit Min Typ Max PLL input clock(1) 1(2) - 24(2) MHz f PLL_IN PLL input clock duty cycle 40(2) - 60(2) % f PLL multiplier output clock 16(2) - 72 MHz PLL_OUT t PLL lock time - - 200(2) µs LOCK Jitter Cycle-to-cycle jitter - - 300(2) ps 1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f . PLL_OUT 2. Guaranteed by design. 78/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.10 Memory characteristics Flash memory The characteristics are given at T = –40 to 105°C unless otherwise specified. A Table 45. Flash memory characteristics Symbol Parameter Conditions Min Typ Max(1) Unit t 16-bit programming time T = –40 to +105 °C 40 53.5 60 µs prog A t Page (2 kB) erase time T = –40 to +105 °C 20 - 40 ms ERASE A t Mass erase time T = –40 to +105 °C 20 - 40 ms ME A Write mode - - 10 mA I Supply current DD Erase mode - - 12 mA 1. Guaranteed by design. Table 46. Flash memory endurance and data retention Value Symbol Parameter Conditions Unit Min(1) T = –40 to +85 °C (6 suffix versions) N Endurance A 10 kcycles END T = –40 to +105 °C (7 suffix versions) A 1 kcycle(2) at T = 85 °C 30 A t Data retention 1 kcycle(2) at T = 105 °C 10 Years RET A 10 kcycles(2) at T = 55 °C 20 A 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DocID022691 Rev 7 79/137 114

Electrical characteristics STM32F373xx 6.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and DD V through a 100 pF capacitor, until a functional disturbance occurs. This test is SS compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table47. They are based on the EMS levels and classes defined in application note AN1709. Table 47. EMS characteristics Level/ Symbol Parameter Conditions Class V = 3.3 V, LQFP100, T = +25 °C, Voltage limits to be applied on any I/O pin DD A V f = 72 MHz 3B FESD to induce a functional disturbance HCLK conforms to IEC 61000-4-2 Fast transient voltage burst limits to be V = 3.3 V, LQFP100, T = +25 °C, DD A V applied through 100 pF on V and V f = 72 MHz 4A EFTB DD SS HCLK pins to induce a functional disturbance conforms to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. 80/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 48. EMI characteristics Max vs. [f /f ] Monitored HSE HCLK Symbol Parameter Conditions Unit frequency band 8/72 MHz 0.1 to 30 MHz 9 V - 3.3 V, T - 25°C, DD A LQFP100 package 30 to 130 MHz 26 dBµV S Peak level EMI compliant with IEC 130 MHz to 1 GHz 30 61967-2 SAE EMI Level 4 - 6.3.12 Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 49. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) T = +25 °C, Electrostatic discharge A V conforming to JESD22- 2 2000 ESD(HBM) voltage (human body model) A114 T = +25 °C, A conforming to V Electrostatic discharge ANSI/ESD STM5.3.1, V voltage (charge device II 500 ESD(CDM) LQFP100, LQFP64, model) LQFP48 and UFBGA100 packages 1. Guaranteed by characterization results. DocID022691 Rev 7 81/137 114

Electrical characteristics STM32F373xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 50. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +105 °C conforming to JESD78A II level A A 6.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The test results are given in Table51. 82/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 51. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on BOOT0 pin -0 NA Injected current on PC0 pin -0 +5 Injected current on TC type I/O pins on VDDSD12 power domain: PB2, PE7, PE8, PE9, PE10, PE11, PE12, PE13, -5 +5 PE14, PE15, PB10 with induced leakage current on other pins from this group less than -50 µA Injected current on TC type I/O pins on VDDSD3 power I mA INJ domain: PB14, PB15, PD8, PD9, PD10, PD12, PD13, PD14, -5 +5 PD15 with induced leakage current on other pins from this group less than -50 µA Injected current on TTa type pins: PA4, PA5, PA6 with induced -5 +5 leakage current on adjacent pins less than -10 µA Injected current on any other FT and FTf pins -5 NA Injected current on any other pins -5 +5 Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DocID022691 Rev 7 83/137 114

Electrical characteristics STM32F373xx 6.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table52 are derived from tests performed under the conditions summarized in Table22. All I/Os are CMOS and TTL compliant. Table 52. I/O static characteristics(1) Symbol Parameter Conditions Min Typ Max Unit TC and TTa I/O - - 0.3V +0.07(2) DD Low level input FT and FTf I/O - - 0.475VDD–0.2(2) V IL voltage BOOT0 - - 0.3V –0.3(2) DD All I/Os except BOOT0 pin - - 0.3V DD V TC and TTa I/O 0.445V +0.398(2) - - DD High level input FT and FTf I/O 0.5VDD+0.2(2) - - V IH voltage BOOT0 0.2V +0.95(2) - - DD All I/Os except BOOT0 pin 0.7V - - DD TC and TTa I/O - 200(2) - Schmitt trigger V FT and FTf I/O - 100(2) - mV hys hysteresis BOOT0 - 300(2) - TC, FT and FTf I/O TTa in digital mode - - ±0.1 VSS < VIN < VDD TTa in digital mode Ilkg Icnupruret nlet a(3k)age VDD ≤ VIN≤ VDDA - - 1 µA TTa in analog mode - - ±0.2 V ≤ V ≤ V SS IN DDA FT and FTf I/O (3) - - 10 V ≤ V ≤ 5 V DD IN Weak pull-up RPU equivalent VIN = VSS 25 40 55 resistor(4) kΩ Weak pull-down RPD equivalent VIN = VDD 25 40 55 resistor(4) C I/O pin capacitance - - 5 - pF IO 1. VDDSD12 is the external power supply for the PB2, PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally connected to VSS). For those pins all V supply references in this table are related to their given VDDSDx DD power supply. 2. Guaranteed by design. 3. Leakage could be higher than maximum value, if negative current is injected on adjacent pins. 4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 84/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Note: I/O pins are powered from V voltage except pins which can be used as SDADC inputs: DD - The PB2, PB10 and PE7 to PE15 I/O pins are powered from V . DDSD12 - PB14 to PB15 and PD8 to PD15 I/O pins are powered from V . All I/O pin ground is DDSD3 internally connected to V . SS V mentioned in the Table52 represents power voltage for a given I/O pin (V or DD DD V or V ). DDSD12 DDSD3 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure17 for standard I/Os, and in Figure18 for 5 V tolerant I/Os. The following curves are design simulation results, not tested in production. Figure 17. TC and TTa I/O input characteristics - CMOS port (cid:22) (cid:21)(cid:17)(cid:24) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:49)(cid:3)(cid:11)(cid:57)(cid:12)(cid:21) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:20)(cid:17)(cid:24) (cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:26)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81) (cid:14)(cid:3)(cid:19)(cid:17)(cid:22)(cid:28)(cid:27) (cid:56)(cid:49)(cid:39)(cid:40)(cid:41)(cid:44)(cid:49)(cid:40)(cid:39)(cid:3)(cid:44)(cid:49)(cid:51)(cid:56)(cid:55)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81)(cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:23)(cid:23)(cid:24)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91)(cid:3) (cid:20) (cid:19)(cid:17)(cid:24) (cid:57)(cid:57)(cid:44)(cid:47)(cid:44)(cid:47)(cid:80)(cid:80)(cid:68)(cid:68)(cid:91)(cid:91)(cid:3)(cid:3)(cid:32)(cid:32)(cid:3)(cid:3)(cid:19)(cid:19)(cid:17)(cid:17)(cid:22)(cid:22)(cid:3)(cid:3)(cid:57)(cid:57)(cid:39)(cid:39)(cid:39)(cid:39)(cid:44)(cid:50)(cid:44)(cid:50)(cid:91)(cid:91)(cid:3)(cid:14)(cid:3)(cid:3)(cid:3)(cid:3)(cid:19)(cid:3)(cid:3)(cid:17)(cid:3)(cid:19)(cid:3)(cid:3)(cid:26)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:19) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:19) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22)(cid:17)(cid:19) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57) (cid:3)(cid:11)(cid:57)(cid:12) (cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:19)(cid:57)(cid:23) DocID022691 Rev 7 85/137 114

Electrical characteristics STM32F373xx Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port (cid:22) (cid:21)(cid:17)(cid:24) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:49)(cid:3)(cid:11)(cid:57)(cid:12)(cid:21) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:20)(cid:17)(cid:24) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81)(cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:26)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:56)(cid:49)(cid:39)(cid:40)(cid:41)(cid:44)(cid:49)(cid:40)(cid:39)(cid:3)(cid:44)(cid:49)(cid:51)(cid:56)(cid:55)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:14)(cid:3)(cid:19)(cid:17)(cid:21) (cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:24)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91)(cid:3) (cid:20) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81) (cid:16)(cid:3)(cid:19)(cid:17)(cid:21) (cid:19)(cid:17)(cid:24) (cid:57)(cid:57)(cid:44)(cid:44)(cid:47)(cid:47)(cid:80)(cid:80)(cid:68)(cid:68)(cid:91)(cid:91)(cid:3)(cid:3)(cid:32)(cid:32)(cid:3)(cid:3)(cid:19)(cid:19)(cid:17)(cid:17)(cid:23)(cid:22)(cid:26)(cid:3)(cid:57)(cid:24)(cid:3)(cid:39)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:39)(cid:91)(cid:44)(cid:3)(cid:50)(cid:3)(cid:91)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:19) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:19) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22)(cid:17)(cid:19) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57) (cid:3)(cid:11)(cid:57)(cid:12) (cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:20)(cid:57)(cid:23) Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8mA, and sink or source up to ± 20mA (with a relaxed V V ). OL/ OH In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section6.2: • The sum of the currents sourced by all the I/Os on all VDD_x and VDDSDx, plus the maximum Run consumption of the MCU sourced on V cannot exceed the absolute DD maximum rating SI (see Table20). VDD • The sum of the currents sunk by all the I/Os on all VSS_x and VSSSD, plus the maximum Run consumption of the MCU sunk on V cannot exceed the absolute SS maximum rating SI (see Table20). VSS 86/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table53 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table22. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified). Table 53. Output voltage characteristics(1) Symbol Parameter Conditions Min Max Unit V (2) Output low level voltage for an I/O pin CMOS port(3) - 0.4 OL I = +8 mA V (4) Output high level voltage for an I/O pin IO V –0.4 - OH 2.7 V < V < 3.6V DD DD V (2) Output low level voltage for an I/O pin TTL port(3) - 0.4 OL I = +8 mA V (4) Output high level voltage for an I/O pin IO 2.4 - OH 2.7 V < V < 3.6V DD VOL(2)(5) Output low level voltage for an I/O pin IIO = +20 mA - 1.3 V VOH(4)(5) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6V VDD–1.3 - VOL(2)(5) Output low level voltage for an I/O pin IIO = +6 mA - 0.4 VOH(4)(5) Output high level voltage for an I/O pin 2 V < VDD < 2.7V VDD–0.4 - V (2) Output low level voltage for a FTf I/O pins IIO = +20 mA - 0.4 OLFM+ in FM+ mode 2.7 V < V < 3.6 V DD 1. VDDSD12 is the external power supply for PB2, PB10, and PE7 to PE15 I/O pins (the I/O ground pin is internally connected to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O ground pin is internally connected to VSS). For those pins all V supply references in this DD table are related to their given VDDSDx power supply. 2. The I current sunk by the device must always respect the absolute maximum rating specified in Table20 IO and the sum of I (I/O ports and control pins) must not exceed I . IO VSS 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 4. The I current sourced by the device must always respect the absolute maximum rating specified in IO Table20 and the sum of I (I/O ports and control pins) must not exceed I . IO VDD 5. Guaranteed by design. Note: I/O pins are powered from V voltage except pins which can be used as SDADC inputs: DD - The PB2, PB10 and PE7 to PE15 I/O pins are powered from V . DDSD12 - PB14 to PB15 and PD8 to PD15 I/O pins are powered from V . All I/O pin ground is DDSD3 internally connected to V . SS V mentioned in the Table53 represents power voltage for a given I/O pin (V or DD DD V or V ). DDSD12 DDSD3 DocID022691 Rev 7 87/137 114

Electrical characteristics STM32F373xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure19 and Table54, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table22. DD Table 54. I/O AC characteristics(1) OSPEEDRy Symbol Parameter Conditions Min Max Unit [1:0] value(1) f Maximum frequency(2) C = 50pF, V = 2 V to 3.6V - 2 MHz max(IO)out L DD Output high to low level t - 125(3) x0 f(IO)out fall time C = 50pF, V = 2 V to 3.6V ns L DD Output low to high level t - 125(3) r(IO)out rise time f Maximum frequency(2) C = 50pF, V = 2 V to 3.6V - 10 MHz max(IO)out L DD Output high to low level t - 25(3) 01 f(IO)out fall time C = 50pF, V = 2 V to 3.6V ns L DD Output low to high level t - 25(3) r(IO)out rise time C = 30 pF, V = 2.7 V to 3.6V - 50 MHz L DD f Maximum frequency(2)(3) C = 50 pF, V = 2.7 V to 3.6V - 30 MHz max(IO)out L DD C = 50 pF, V = 2 V to 2.7V - 20 MHz L DD C = 30pF, V = 2.7 V to 3.6V - 5(3) L DD Output high to low level 11 t C = 50pF, V = 2.7 V to 3.6V - 8(3) f(IO)out fall time L DD C = 50pF, V = 2 V to 2.7V - 12(3) L DD ns C = 30pF, V = 2.7 V to 3.6V - 5(3) L DD Output low to high level t C = 50pF, V = 2.7 V to 3.6V - 8(3) r(IO)out rise time L DD C = 50pF, V = 2 V to 2.7V - 12(3) L DD f Maximum frequency(2) - 2 MHz max(IO)out FM+ Output high to low level t - 12 configuration f(IO)out fall time CL = 50 pF, V = 2 V to 3.6 V DD (4) ns Output low to high level t - 34 r(IO)out rise time Pulse width of external - t signals detected by the - 10 - ns EXTIpw EXTI controller 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0313 reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure19. 3. Guaranteed by design. 4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F37xx reference manual RM0313 for a description of FM+ I/O mode configuration 88/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 19. I/O AC characteristics definition (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:28)(cid:19)(cid:8) (cid:40)(cid:59)(cid:55)(cid:40)(cid:53)(cid:49)(cid:36)(cid:47) (cid:87)(cid:85)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:87)(cid:73)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:50)(cid:49)(cid:3)(cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:55) (cid:48)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:76)(cid:86)(cid:3)(cid:68)(cid:70)(cid:75)(cid:76)(cid:72)(cid:89)(cid:72)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:11)(cid:87)(cid:3)(cid:85)(cid:3)(cid:14)(cid:3)(cid:87)(cid:3)(cid:73)(cid:3)(cid:11)(cid:148)(cid:3)(cid:21)(cid:18)(cid:22)(cid:12)(cid:55)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:71)(cid:88)(cid:87)(cid:92)(cid:3)(cid:70)(cid:92)(cid:70)(cid:79)(cid:72)(cid:3)(cid:76)(cid:86)(cid:3)(cid:11)(cid:23)(cid:24)(cid:16)(cid:24)(cid:24)(cid:8)(cid:12) (cid:90)(cid:75)(cid:72)(cid:81)(cid:3)(cid:79)(cid:82)(cid:68)(cid:71)(cid:72)(cid:71)(cid:3)(cid:69)(cid:92)(cid:3)(cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:48)(cid:54)(cid:22)(cid:21)(cid:20)(cid:22)(cid:21)(cid:57)(cid:20) 6.3.15 NRST characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R (see Table52). PU Unless otherwise specified, the parameters given in Table55 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table22. Table 55. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit V (1) NRST Input low level voltage - - - 0.3V + 0.07(1) IL(NRST) DD V V (1) NRST Input high level voltage - 0.445V + 0.398(1) - - IH(NRST) DD NRST Schmitt trigger voltage V (1) - - 200 - mV hys(NRST) hysteresis RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ V (1) NRST Input filtered pulse - - - 100 ns F(NRST) V (1) NRST Input not filtered pulse - 500 - - ns NF(NRST) 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). DocID022691 Rev 7 89/137 114

Electrical characteristics STM32F373xx Figure 20. Recommended NRST pin protection (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:57)(cid:39)(cid:39) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:85)(cid:92)(cid:3)(cid:11)(cid:20)(cid:12) (cid:53)(cid:51)(cid:56) (cid:49)(cid:53)(cid:54)(cid:55)(cid:3)(cid:11)(cid:21)(cid:12) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:20)(cid:3)(cid:151)(cid:41) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:26)(cid:27)(cid:57)(cid:20) 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table55. Otherwise the reset will not be taken into account by the device. 90/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.16 Communications interfaces I2C interface characteristics 2 2 The I C interface meets the requirements of the standard I C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open- drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table56. Refer also to Section6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 56. I2C characteristics(1) Standard Fast mode Fast mode + Symbol Parameter Unit Min Max Min Max Min Max f SCL clock frequency 0 100 0 400 0 1000 KHz SCL t Low period of the SCL clock 4.7 - 1.3 - 0.5 - µs LOW t High Period of the SCL clock 4 - 0.6 - 0.26 - µs HIGH Rise time of both SDA and SCL tr - 1000 - 300 - 120 ns signals Fall time of both SDA and SCL tf - 300 - 300 - 120 ns signals t Data hold time 0 - 0 - 0 - µs HD;DAT t Data valid time - 3.45(2) - 0.9(2) - 0.45(2) µs VD;DAT t Data valid acknowledge time - 3.45(2) - 0.9(2) - 0.45(2) µs VD;ACK t Data setup time 250 - 100 - 50 - ns SU;DAT Hold time (repeated) START t 4.0 - 0.6 - 0.26 - µs HD;STA condition Set-up time for a repeated t START 4.7 - 0.6 - 0.26 - µs SU;STA condition t Set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs SU;STO Bus free time between a t 4.7 - 1.3 - 0.5 - µs BUF STOP and START condition C Capacitive load for each bus line - 400 - 400 - 550 pF b 1. The I2C characteristics are the requirements from the I2C bus specification rev03. They are guaranteed by design when the I2Cx_TIMING register is correctly programmed (refer to reference manual). These characteristics are not tested in production. 2. The maximum t could be 3.45µs, 0.9µs and 0.45µs for standard mode, fast mode and fast mode HD;DAT plus, but must be less than the maximum of t or t by a transition time. VD;DAT VD;ACK DocID022691 Rev 7 91/137 114

Electrical characteristics STM32F373xx Table 57. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit Maximum pulse width of spikes that are t 50(2) 260(3) ns AF suppressed by the analog filter 1. Guaranteed by design. 2. Spikes width below t (min) are filtered. AF 3. Spikes width above t (max) are not filtered. AF Figure 21. I2C bus AC waveforms and measurement circuit (cid:57)(cid:39)(cid:39)(cid:66)(cid:44)(cid:21)(cid:38)(cid:3) (cid:57)(cid:39)(cid:39)(cid:66)(cid:44)(cid:21)(cid:38)(cid:3) (cid:53)(cid:83) (cid:53)(cid:83) (cid:48)(cid:38)(cid:56) (cid:53)(cid:86) (cid:54)(cid:39)(cid:36) (cid:44)(cid:21)(cid:38)(cid:3)(cid:69)(cid:88)(cid:86) (cid:53)(cid:86) (cid:54)(cid:38)(cid:47) (cid:85) (cid:85) (cid:85) (cid:71) (cid:83) (cid:52)(cid:54)(cid:28)(cid:37)(cid:34)(cid:53) (cid:24)(cid:17)(cid:6) (cid:24)(cid:17)(cid:6) (cid:52)(cid:37)(cid:34) (cid:20)(cid:17)(cid:6) (cid:20)(cid:17)(cid:6) (cid:68)(cid:80)(cid:79)(cid:85)(cid:74)(cid:79)(cid:86)(cid:70)(cid:69) (cid:85)(cid:71) (cid:85)(cid:41)(cid:37)(cid:28)(cid:37)(cid:34)(cid:53) (cid:85)(cid:83) (cid:85)(cid:41)(cid:42)(cid:40)(cid:41) (cid:85)(cid:55)(cid:37)(cid:28)(cid:37)(cid:34)(cid:53) (cid:52)(cid:36)(cid:45) (cid:24)(cid:17)(cid:6) (cid:24)(cid:17)(cid:6) (cid:24)(cid:17)(cid:6) (cid:24)(cid:17)(cid:6) (cid:68)(cid:80)(cid:79)(cid:85)(cid:74)(cid:79)(cid:86)(cid:70)(cid:69) (cid:20)(cid:17)(cid:6) (cid:20)(cid:17)(cid:6) (cid:20)(cid:17)(cid:6) (cid:20)(cid:17)(cid:6) (cid:85)(cid:41)(cid:37)(cid:28)(cid:52)(cid:53)(cid:34) (cid:85)(cid:45)(cid:48)(cid:56) (cid:26)(cid:85)(cid:73)(cid:1)(cid:68)(cid:77)(cid:80)(cid:68)(cid:76) (cid:18)(cid:1)(cid:16)(cid:1)(cid:71) (cid:52) (cid:52)(cid:36)(cid:45) (cid:85) (cid:18)(cid:84)(cid:85)(cid:1)(cid:68)(cid:77)(cid:80)(cid:68)(cid:76)(cid:1)(cid:68)(cid:90)(cid:68)(cid:77)(cid:70) (cid:35)(cid:54)(cid:39) (cid:52)(cid:37)(cid:34) (cid:85)(cid:52)(cid:54)(cid:28)(cid:52)(cid:53)(cid:34) (cid:85)(cid:41)(cid:37)(cid:28)(cid:52)(cid:53)(cid:34) (cid:85)(cid:55)(cid:37)(cid:28)(cid:34)(cid:36)(cid:44) (cid:85)(cid:52)(cid:54)(cid:28)(cid:52)(cid:53)(cid:48) (cid:85) (cid:52)(cid:49) (cid:52)(cid:36)(cid:45) (cid:52)(cid:83) (cid:49) (cid:52) (cid:26)(cid:85)(cid:73)(cid:1)(cid:68)(cid:77)(cid:80)(cid:68)(cid:76) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:26)(cid:28)(cid:57)(cid:22) 1. Legend: Rs: Series protection resistors. Rp: Pull-up resistors. V : I2C bus supply. DD_I2C 92/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics SPI/I2S characteristics Unless otherwise specified, the parameters given in Table58 for SPI or in Table59 for I2S are derived from tests performed under ambient temperature, f frequency and V PCLKx DD supply voltage conditions summarized in Table22. Refer to Section6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 58. SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode - 18 SCK SPI clock frequency 1/tc(SCK)(1) Slave mode - 18 MHz t SPI clock rise and fall r(SCK) Capacitive load: C = 30 pF - 8 ns t (1) time f(SCK) SPI slave input clock DuCy(SCK)(1) Slave mode 30 70 % duty cycle t (1) NSS setup time Slave mode 2Tpclk - su(NSS) t (1) NSS hold time Slave mode 4Tpclk - h(NSS) t (1) Master mode, f = 36 MHz, Tpclk/2 Tpclk/2 w(SCKH) SCK high and low time PCLK t (1) presc = 4 - 3 + 3 w(SCKL) t (1) Master mode 5.5 - su(MI) Data input setup time tsu(SI)(1) Slave mode 6.5 - t (1) Master mode 5 - h(MI) Data input hold time ns t (1) Slave mode 5 - h(SI) t (1)(2) Data output access time Slave mode, f = 24 MHz 0 4Tpclk a(SO) PCLK t (1)(3) Data output disable time Slave mode 0 24 dis(SO) t (1) Data output valid time Slave mode (after enable edge) - 39 v(SO) t (1) Data output valid time Master mode (after enable edge) - 3 v(MO) t (1) Slave mode (after enable edge) 15 - h(SO) Data output hold time t (1) Master mode (after enable edge) 4 - h(MO) 1. Guaranteed by characterization results. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID022691 Rev 7 93/137 114

Electrical characteristics STM32F373xx Figure 22. SPI timing diagram - slave mode and CPHA = 0 (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:38)(cid:46)(cid:3)(cid:44)(cid:81)(cid:83) (cid:38)(cid:38)(cid:51)(cid:51)(cid:50)(cid:43)(cid:36)(cid:47)(cid:32)(cid:32)(cid:19)(cid:19) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:57)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:23)(cid:70) Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:81) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:46)(cid:3)(cid:76) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:43)(cid:12) (cid:38) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:47)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:3)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24)(cid:69) 1. Measurement points are done at 0.5V level and with external C = 30 pF DD L . 94/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 24. SPI timing diagram - master mode(1) (cid:43)(cid:76)(cid:74)(cid:75) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:86)(cid:88)(cid:11)(cid:48)(cid:44)(cid:12) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:48)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:89)(cid:11)(cid:48)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:48)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:25)(cid:70) 1. Measurement points are done at 0.5V level and with external C = 30 pF DD L . DocID022691 Rev 7 95/137 114

Electrical characteristics STM32F373xx Table 59. I2S characteristics Symbol Parameter Conditions Min Max Unit I2S slave input clock duty DuCy(SCK)(1) Slave mode 30 70 % cycle Master mode (data: 16 bits, Audio fCK(1) I2S clock frequency frequency = 48kHz) 1.528 1.539 1/t MHz c(CK) Slave mode 0 12.288 t (1) r(CK) I2S clock rise and fall time Capacitive load C =30pF - 8 t L f(CK) t (1) WS valid time Master mode 4 - v(WS) t (1) WS hold time Master mode 4 - h(WS) t (1) WS setup time Slave mode 2 - su(WS) t (1) WS hold time Slave mode - - h(WS) t (1) I2S clock high time 306 - w(CKH) Master fPCLK= 16MHz, audio t (1) I2S clock low time frequency = 48kHz 312 - w(CKL) t (1) Master receiver 6 - su(SD_MR) Data input setup time t (1) Slave receiver 3 - ns su(SD_SR) t (1) Master receiver 1.5 - h(SD_MR) Data input hold time t (1) Slave receiver 1.5 - h(SD_SR) Slave transmitter t (1) Data output valid time - 16 v(SD_ST) (after enable edge) Slave transmitter t (1) Data output hold time 16 - h(SD_ST) (after enable edge) Master transmitter t (1) Data output valid time - 2 v(SD_MT) (after enable edge) Master transmitter t (1) Data output hold time 0 - h(SD_MT) (after enable edge) 1. Guaranteed by characterization results. 96/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Figure 25. I2S slave timing diagram (Philips protocol)(1) (cid:87)(cid:70)(cid:11)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:19) (cid:83) (cid:81) (cid:46)(cid:3)(cid:44) (cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:20) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:43)(cid:12) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:47)(cid:12) (cid:87)(cid:75)(cid:11)(cid:58)(cid:54)(cid:12) (cid:58)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:58)(cid:54)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:55)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:55)(cid:12) (cid:54)(cid:39)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:47)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:47)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:53)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:53)(cid:12) (cid:54)(cid:39)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:27)(cid:20)(cid:69) 1. Measurement points are done at 0.5 V level and with external C = 30 pF. DD L 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 26. I2S master timing diagram (Philips protocol)(1) (cid:84)(cid:70)(cid:8)(cid:35)(cid:43)(cid:9) (cid:84)(cid:82)(cid:8)(cid:35)(cid:43)(cid:9) (cid:84)(cid:67)(cid:8)(cid:35)(cid:43)(cid:9) (cid:85)(cid:84) (cid:35)(cid:48)(cid:47)(cid:44)(cid:0)(cid:29)(cid:0)(cid:16) (cid:80) (cid:85)(cid:84) (cid:79) (cid:84)(cid:87)(cid:8)(cid:35)(cid:43)(cid:40)(cid:9) (cid:43)(cid:0) (cid:35) (cid:35)(cid:48)(cid:47)(cid:44)(cid:0)(cid:29)(cid:0)(cid:17) (cid:84)(cid:86)(cid:8)(cid:55)(cid:51)(cid:9) (cid:84)(cid:87)(cid:8)(cid:35)(cid:43)(cid:44)(cid:9) (cid:84)(cid:72)(cid:8)(cid:55)(cid:51)(cid:9) (cid:55)(cid:51)(cid:0)(cid:79)(cid:85)(cid:84)(cid:80)(cid:85)(cid:84) (cid:84)(cid:86)(cid:8)(cid:51)(cid:36)(cid:63)(cid:45)(cid:52)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:36)(cid:63)(cid:45)(cid:52)(cid:9) (cid:51)(cid:36)(cid:84)(cid:82)(cid:65)(cid:78)(cid:83)(cid:77)(cid:73)(cid:84) (cid:44)(cid:51)(cid:34)(cid:0)(cid:84)(cid:82)(cid:65)(cid:78)(cid:83)(cid:77)(cid:73)(cid:84)(cid:8)(cid:18)(cid:9) (cid:45)(cid:51)(cid:34)(cid:0)(cid:84)(cid:82)(cid:65)(cid:78)(cid:83)(cid:77)(cid:73)(cid:84) (cid:34)(cid:73)(cid:84)(cid:78)(cid:0)(cid:84)(cid:82)(cid:65)(cid:78)(cid:83)(cid:77)(cid:73)(cid:84) (cid:44)(cid:51)(cid:34)(cid:0)(cid:84)(cid:82)(cid:65)(cid:78)(cid:83)(cid:77)(cid:73)(cid:84) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:36)(cid:63)(cid:45)(cid:50)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:36)(cid:63)(cid:45)(cid:50)(cid:9) (cid:51)(cid:36)(cid:82)(cid:69)(cid:67)(cid:69)(cid:73)(cid:86)(cid:69) (cid:44)(cid:51)(cid:34)(cid:0)(cid:82)(cid:69)(cid:67)(cid:69)(cid:73)(cid:86)(cid:69)(cid:8)(cid:18)(cid:9) (cid:45)(cid:51)(cid:34)(cid:0)(cid:82)(cid:69)(cid:67)(cid:69)(cid:73)(cid:86)(cid:69) (cid:34)(cid:73)(cid:84)(cid:78)(cid:0)(cid:82)(cid:69)(cid:67)(cid:69)(cid:73)(cid:86)(cid:69) (cid:44)(cid:51)(cid:34)(cid:0)(cid:82)(cid:69)(cid:67)(cid:69)(cid:73)(cid:86)(cid:69) (cid:65)(cid:73)(cid:17)(cid:20)(cid:24)(cid:24)(cid:20)(cid:66) 1. Measurement points are done at 0.5 V level and with external C = 30 pF. DD L 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID022691 Rev 7 97/137 114

Electrical characteristics STM32F373xx 6.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table60 are preliminary values derived from tests performed under ambient temperature, f frequency and V supply PCLK2 DDA voltage conditions summarized in Table22. Note: It is recommended to perform a calibration after each power-up. Table 60. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V Power supply - 2.4 - 3.6 V DDA V Positive reference voltage - 2.4 - V V REF+ DDA V Negative reference voltage - 0 - - V REF- I (1) Current consumption from V V = V = 3.3 V - 0.9 - mA DDA(ADC) DDA DD DDA I Current on the V input pin - - 160(2) 220(2) µA VREF REF f ADC clock frequency - 0.6 - 14 MHz ADC f (3) Sampling rate - 0.05 - 1 MHz S f = 14 MHz - - 823 kHz f (3) External trigger frequency ADC TRIG - - - 17 1/f ADC 0 (V or V V Conversion voltage range - SSA REF- - V V AIN tied to ground) REF+ See Equation 1 and R (3) Signal source impedance - - 50 kΩ SRC Table61 for details R (3) Sampling switch resistance - - - 1 kΩ ADC Internal sample and hold C (3) - - - 8 pF ADC capacitor f = 14 MHz 5.9 µs t (3) Calibration time ADC CAL - 83 1/f ADC t (3) Injection trigger conversion fADC = 14 MHz - - 0.214 µs lat latency - - - 2(4) 1/f ADC t (3) Regular trigger conversion fADC = 14 MHz - - 0.143 µs latr latency - - - 2(4) 1/f ADC f = 14 MHz 0.107 - 17.1 µs t (3) Sampling time ADC S - 1.5 - 239.5 1/f ADC t (3) Power-up time - - - 1 µs STAB f = 14 MHz 1 - 18 µs ADC Total conversion time (including tCONV(3) sampling time) - 14 to 252 (tS for sampling +12.5 for 1/f successive approximation) ADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I and 60 µA DDA on I is present DD 2. Guaranteed by characterization results. 3. Guaranteed by design. 4. For external triggers, a delay of 1/f must be added to the latency specified in Table60 PCLK2 98/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Equation 1: R max formula SRC T R <---------------------------------S-------------------------------–R SRC f × C × ln(2N+2) ADC ADC ADC The formula above (Equation 1) is used to determine the maximum external signal source impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 61. R max for f = 14 MHz(1) SRC ADC T (cycles) t (µs) R max (kΩ) s S SRC 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 50 239.5 17.1 50 1. Guaranteed by design. Table 62. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) Unit ET Total unadjusted error ±1.3 ±3 EO Offset error f = 14 MHz, R < 10 kΩ, ±1 ±2 ADC SRC EG Gain error V = 3 V to 3.6 V ±0.5 ±1.5 LSB DDA T = 25 °C ED Differential linearity error A ±0.7 ±1 EL Integral linearity error ±0.8 ±1.5 ET Total unadjusted error ±3.3 ±4 EO Offset error f = 14 MHz, R < 10 kΩ, ±1.9 ±2.8 ADC SRC EG Gain error V = 2.7 V to 3.6 V ±2.8 ±3 LSB DDA T = -40 to 105 °C ED Differential linearity error A ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 ET Total unadjusted error ±3.3 ±4 EO Offset error f = 14 MHz, R < 10 kΩ, ±1.9 ±2.8 ADC SRC EG Gain error V = 2.4 V to 3.6 V ±2.8 ±3 LSB DDA T = 25 °C ED Differential linearity error A ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 1. ADC DC accuracy values are measured after internal calibration. DocID022691 Rev 7 99/137 114

Electrical characteristics STM32F373xx 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for I and ΣI in Section6.3.14 does not INJ(PIN) INJ(PIN) affect the ADC accuracy. 3. Better performance may be achieved in restricted V , frequency and temperature ranges. DDA 4. Guaranteed by characterization results. Figure 27. ADC accuracy characteristics (cid:57)(cid:54)(cid:54)(cid:36) (cid:40)(cid:42) (cid:11)(cid:20)(cid:12)(cid:3)(cid:40)(cid:91)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:82)(cid:73)(cid:3)(cid:68)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:24) (cid:11)(cid:21)(cid:12)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:23) (cid:11)(cid:22)(cid:12)(cid:3)(cid:40)(cid:81)(cid:71)(cid:3)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72) (cid:23)(cid:19)(cid:28)(cid:22) (cid:40)(cid:55)(cid:3)(cid:32)(cid:3)(cid:55)(cid:82)(cid:87)(cid:68)(cid:79)(cid:3)(cid:56)(cid:81)(cid:68)(cid:77)(cid:88)(cid:86)(cid:87)(cid:72)(cid:71)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:11)(cid:21)(cid:12) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72)(cid:86)(cid:17) (cid:40)(cid:55) (cid:11)(cid:22)(cid:12) (cid:40)(cid:50)(cid:3)(cid:32)(cid:3)(cid:50)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:26) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:76)(cid:85)(cid:86)(cid:87) (cid:11)(cid:20)(cid:12) (cid:25) (cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:40)(cid:42)(cid:3)(cid:32)(cid:3)(cid:42)(cid:68)(cid:76)(cid:81)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3) (cid:24) (cid:40)(cid:50) (cid:40)(cid:47) (cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:23) (cid:40)(cid:39)(cid:3)(cid:32)(cid:3)(cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3) (cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:86)(cid:87)(cid:72)(cid:83)(cid:86)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:86)(cid:17) (cid:22) (cid:40)(cid:39) (cid:40)(cid:47)(cid:3)(cid:32)(cid:3)(cid:44)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:21) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:81)(cid:92)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:72)(cid:81)(cid:71)(cid:3)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:3) (cid:20) (cid:20)(cid:3)(cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:39)(cid:40)(cid:36)(cid:47) (cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:17) (cid:19) (cid:57)(cid:39)(cid:39)(cid:36) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:23)(cid:19)(cid:28)(cid:22)(cid:23)(cid:19)(cid:28)(cid:23) (cid:23)(cid:19)(cid:28)(cid:24) (cid:23)(cid:19)(cid:28)(cid:25) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:27)(cid:19)(cid:57)(cid:21) Figure 28. Typical connection diagram using the ADC (cid:57)(cid:39)(cid:39) (cid:54)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:75)(cid:82)(cid:79)(cid:71)(cid:3)(cid:36)(cid:39)(cid:38) (cid:57)(cid:55) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:25)(cid:57) (cid:50)(cid:51)(cid:50)(cid:35)(cid:8)(cid:17)(cid:9) (cid:36)(cid:44)(cid:49)(cid:91) (cid:53)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:38)(cid:83)(cid:68)(cid:85)(cid:68)(cid:86)(cid:76)(cid:87)(cid:76)(cid:70) (cid:57)(cid:55) (cid:44)(cid:47)(cid:147)(cid:20)(cid:151)(cid:36) (cid:55)(cid:51)(cid:50)(cid:35) (cid:19)(cid:17)(cid:25)(cid:57) (cid:38)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:45)(cid:51)(cid:19)(cid:18)(cid:17)(cid:22)(cid:19)(cid:54)(cid:17) 1. Refer to Table60 for the values of R , R and C . SRC ADC ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC General PCB design guidelines Power supply decoupling should be performed as shown in Figure9. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 100/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.18 DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit V Analog supply voltage - 2.4 - 3.6 V DDA V Reference supply voltage V must always be below V 2.4 - 3.6 V REF+ REF+ DDA V Ground - 0 - 0 V SSA DAC Connected to V 5 - - SSA R (1) Resistive load output kΩ LOAD buffer ON Connected to VDDA 25 - - R (1) Output Impedance DAC output buffer OFF - - 15 kΩ O Maximum capacitive load at DAC_OUT C (1) Capacitive load - - 50 pF LOAD pin (when the buffer is ON). It gives the maximum output excursion DAC_OUT Lower DAC_OUT voltage of the DAC. 0.2 - - V min(1) with buffer ON It corresponds to 12-bit input code (0x0E0) to (0xF1C) at V = 3.6V REF+ DAC_OUT Higher DAC_OUT and (0x155) and (0xEAB) at V = REF+ - - V – 0.2 V max(1) voltage with buffer ON 2.4V DDA DAC_OUT Lower DAC_OUT voltage - 0.5 - mV min(1) with buffer OFF It gives the maximum output excursion DAC_OUT Higher DAC_OUT of the DAC. - - V – 1LSB V max(1) voltage with buffer OFF REF+ DAC DC current With no load, worst code (0xF1C) at I (3) consumption in quiescent V = 3.6V in terms of DC - - 220 µA DDVREF+ REF+ mode (Standby mode) consumption on the inputs With no load, middle code (0x800) on - - 380 µA DAC DC current the inputs IDDA(3) consumption in quiescent With no load, worst code (0xF1C) at mode(2) V = 3.6V in terms of DC - - 480 µA REF+ consumption on the inputs Given for the DAC in 10-bit Differential non linearity configuration - - ±0.5 LSB DNL(3) Difference between two consecutive code-1LSB) Given for the DAC in 12-bit - - ±2 LSB configuration Integral non linearity Given for the DAC in 10-bit - - ±1 LSB (difference between configuration measured value at Code i INL(3) and the value at Code i on a line drawn between Given for the DAC in 12-bit - - ±4 LSB Code 0 and last Code configuration 1023) DocID022691 Rev 7 101/137 114

Electrical characteristics STM32F373xx Table 63. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - - ±10 mV Offset error (difference between Given for the DAC in 10-bit at VREF+ = - - ±3 LSB Offset(3) measured value at Code 3.6V (0x800) and the ideal Given for the DAC in 12-bit at V = value = V /2) REF+ - - ±12 LSB REF+ 3.6V Gain Given for the DAC in 12bit Gain error - - ±0.5 % error(3) configuration Settling time (full scale: for a 10-bit input code transition between the t (3) lowest and the highest C ≤ 50 pF, R ≥ 5 kΩ - 3 4 µs SETTLING LOAD LOAD input codes when DAC_OUT reaches final value ±1LSB Max frequency for a correct DAC_OUT Update change when small C ≤ 50 pF, R ≥ 5 kΩ - - 1 MS/s rate(3) LOAD LOAD variation in the input code (from code i to i+1LSB) Wakeup time from off C ≤ 50 pF, R ≥ 5 kΩ state (Setting the ENx bit LOAD LOAD tWAKEUP(3) in the DAC Control input code between lowest and highest - 6.5 10 µs possible ones. register) Power supply rejection PSRR+ (1) ratio (to V ) (static DC No R , C = 50 pF - -67 -40 dB DDA LOAD LOAD measurement 1. Guaranteed by design. 2. Quiescent mode refers to the state of the DAC keeping a steady value on the output, so no dynamic consumption is involved. 3. Guaranteed by characterization. Figure 29. 12-bit buffered /non-buffered DAC (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:18)(cid:81)(cid:82)(cid:81)(cid:16)(cid:69)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:3)(cid:39)(cid:36)(cid:38) (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:11)(cid:20)(cid:12) (cid:53)(cid:47)(cid:50)(cid:36)(cid:39) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:39)(cid:36)(cid:38)(cid:91)(cid:66)(cid:50)(cid:56)(cid:55) (cid:71)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79)(cid:3)(cid:87)(cid:82)(cid:3) (cid:68)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:38)(cid:47)(cid:50)(cid:36)(cid:39) (cid:68)(cid:76)(cid:20)(cid:26)(cid:20)(cid:24)(cid:26)(cid:68) 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 102/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.19 Comparator characteristics Table 64. Comparator characteristics Symbol Parameter Conditions Min Typ Max(1) Unit V Analog supply voltage - 2 - 3.6 V DDA Comparator V - 0 - V V IN input voltage range DDA V scaler V REFINT - - 1.2 - V BG input voltage V scaler V REFINT - - ±5 ±10 mV SC offset voltage First V scaler activation after device REFINT 1000(2) t Scaler startup time power on - - ms S_SC from power down Next activations 0.2 Startup time to reach propagation delay t Comparator startup time - - 60 µs START specification Ultra-low power mode - 2 4.5 Low power mode - 0.7 1.5 µs Propagation delay for 200 mV step with 100 mV Medium power mode - 0.3 0.6 overdrive V ≥ 2.7 V - 50 100 DDA High speed mode ns V < 2.7 V - 100 240 DDA t D Ultra-low power mode - 2 7 Low power mode - 0.7 2.1 µs Propagation delay for full range step with 100 mV Medium power mode - 0.3 1.2 overdrive V ≥ 2.7 V - 90 180 DDA High speed mode ns V < 2.7 V - 110 300 DDA V Comparator offset error - - ±4 ±10 mV offset Offset error temperature dV /dT - - 18 - µV/°C offset coefficient Ultra-low power mode - 1.2 1.5 Low power mode - 3 5 COMP current I µA DD(COMP) consumption Medium power mode - 10 15 High speed mode - 75 100 DocID022691 Rev 7 103/137 114

Electrical characteristics STM32F373xx Table 64. Comparator characteristics (continued) Symbol Parameter Conditions Min Typ Max(1) Unit No hysteresis - - 0 - (COMPxHYST[1:0]=00) High speed mode 3 13 Low hysteresis 8 (COMPxHYST[1:0]=01) All other power 5 10 modes V Comparator hysteresis High speed mode 7 26 mV hys Medium hysteresis 15 (COMPxHYST[1:0]=10) All other power 9 19 modes High speed mode 18 49 High hysteresis 31 (COMPxHYST[1:0]=11) All other power 19 40 modes 1. Guaranteed by design. 2. For more details and conditions see Figure30: Maximum VREFINT scaler startup time from power down Figure 30. Maximum V scaler startup time from power down REFINT (cid:7)(cid:23)(cid:4)(cid:24)(cid:2)(cid:25)(cid:2)(cid:24) (cid:2)(cid:26)(cid:2)(cid:7)(cid:23)(cid:6)(cid:24) (cid:2)(cid:3)(cid:4)(cid:4)(cid:4) (cid:11)(cid:11)(cid:12) (cid:7)(cid:23)(cid:6)(cid:24)(cid:2)(cid:25)(cid:2)(cid:24) (cid:2)(cid:26)(cid:2)(cid:27)(cid:23)(cid:4)(cid:24) (cid:11)(cid:11)(cid:12) (cid:27)(cid:23)(cid:4)(cid:24)(cid:2)(cid:25)(cid:2)(cid:24) (cid:2)(cid:25)(cid:2)(cid:27)(cid:23)(cid:8)(cid:24) (cid:11)(cid:11)(cid:12) (cid:14) (cid:2)(cid:3)(cid:4)(cid:4) (cid:13) (cid:12) (cid:11) (cid:2)(cid:9)(cid:10) (cid:8) (cid:7) (cid:4)(cid:5)(cid:6) (cid:2) (cid:2)(cid:3) (cid:2)(cid:3)(cid:4) (cid:10) (cid:2)(cid:3) (cid:5)(cid:6)(cid:4) (cid:5)(cid:7)(cid:4) (cid:2)(cid:4) (cid:2)(cid:7)(cid:4) (cid:2)(cid:6)(cid:4) (cid:2)(cid:8)(cid:4) (cid:2)(cid:9)(cid:4) (cid:2)(cid:3)(cid:4)(cid:4) (cid:15)(cid:16)(cid:12)(cid:17)(cid:16)(cid:18)(cid:19)(cid:10)(cid:20)(cid:18)(cid:16)(cid:2)(cid:11)(cid:21)(cid:22)(cid:14) 104/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.20 Temperature sensor characteristics Table 65. Temperature sensor calibration values Calibration value name Description Memory address TS ADC raw data acquired at TS_CAL1 temperature of 30°C±5°C, 0x1FFF F7B8 - 0x1FFF F7B9 V = 3.3V DDA TS ADC raw data acquired at TS_CAL2 temperature of 110°C±5°C 0x1FFF F7C2 - 0x1FFF F7C3 V = 3.3V DDA Table 66. TS characteristics Symbol Parameter Min Typ Max Unit T V linearity with temperature - ±1 ±2 °C L SENSE Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C V Voltage at 25 °C 1.34 1.43 1.52 V 25 t (1) Startup time 4 - 10 µs START ADC sampling time when reading the T (2)(1) 17.1 - - µs S_temp temperature 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.21 V monitoring characteristics BAT Table 67. V monitoring characteristics BAT Symbol Parameter Min Typ Max Unit R Resistor bridge for V - 50 - KΩ BAT Q Ratio on V measurement - 2 - - BAT Er(1) Error on Q -1 - +1 % ADC sampling time when reading the V T (2) BAT 5 - - µs S_vbat 1mV accuracy 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.22 Timer characteristics The parameters given in Table68 are guaranteed by design. Refer to Section6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). DocID022691 Rev 7 105/137 114

Electrical characteristics STM32F373xx Table 68. TIMx(1) (2)characteristics Symbol Parameter Conditions Min Max Unit - 1 - t TIMxCLK t Timer resolution time res(TIM) f = 72 MHz 13.9 - ns TIMxCLK Timer external clock 0 fTIMxCLK/2 MHz f EXT frequency on CH1 to CH4 f = 72 MHz 0 24 MHz TIMxCLK TIMx (except - 16 Res Timer resolution TIM2) bit TIM TIM2 - 32 - 1 65536 t TIMxCLK t 16-bit counter clock period COUNTER f = 72 MHz 0.0139 910 µs TIMxCLK tMAX_COUN Maximum possible count - - 65536 × 65536 tTIMxCLK T with 32-bit counter fTIMxCLK = 72 MHz - 59.65 s 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14, TIM15, TIM16 , TIM17, TIM18 and TIM19 timers. 2. Guaranteed by characterization results. Table 69. IWDG min/max timeout period at 40 kHz (LSI)(1)(2) Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]= Prescaler divider PR[2:0] bits 0x000 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. 2. Guaranteed by characterization results. Table 70. WWDG min-max timeout value @72 MHz (PCLK) Prescaler WDGTB Min timeout value Max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 106/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics 6.3.23 USB characteristics Table 71. USB startup time Symbol Parameter Max Unit t (1) USB transceiver startup time 1 µs STARTUP 1. Guaranteed by design. Table 72. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit Input levels V USB operating voltage(2) - 3.0(3) 3.6 V DD Differential input sensitivity (for V (4) I(USB_DP, USB_DM) 0.2 - DI USB compliance) V V (4) Differential common mode range Includes V range 0.8 2.5 CM DI V (4) Single ended receiver threshold - 1.3 2.0 SE Output levels V Static output level low R of 1.5kΩ to 3.6 V(5) - 0.3 OL L V V Static output level high R of 15kΩ to V (5) 2.8 3.6 OH L SS 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F3xxx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V voltage range. DD 4. Guaranteed by design. 5. RL is the load connected on the USB drivers DocID022691 Rev 7 107/137 114

Electrical characteristics STM32F373xx Figure 31. USB timings: definition of data signal rise and fall time (cid:38)(cid:85)(cid:82)(cid:86)(cid:86)(cid:82)(cid:89)(cid:72)(cid:85) (cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:86) (cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:86) (cid:57) (cid:38)(cid:53)(cid:54) (cid:57) (cid:54)(cid:54) (cid:87)(cid:73) (cid:87)(cid:85) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:26) Table 73. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit Driver characteristics t Rise time(2) C = 50 pF 4 - 20 ns r L t Fall time(2) C = 50 pF 4 - 20 ns f L t Rise/ fall time matching t/t 90 - 110 % rfm r f V Output signal crossover voltage - 1.3 - 2.0 V CRS Output driver driving high and Z 28 40 44 Ω Impedance(3) DRV low 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is already included in the embedded driver. 6.3.24 CAN (controller area network) interface Refer to Section6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 6.3.25 SDADC characteristics Table 74. SDADC characteristics (1) Symbol Parameter Conditions Min Typ Max Unit Note Power Slow mode (fADC = 1.5MHz) 2.2 - VDDA - V V DDSDx supply Normal mode (f = 6MHz) 2.4 - V - ADC DDA SDADC Slow mode (f = 1.5MHz) 0.5 1.5 1.65 - ADC f clock MHz ADC frequency Normal mode (fADC = 6MHz) 0.5 6 6.3 - Positive V - 1.1 - V V - REFSD+ ref. voltage DDSDx 108/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max Unit Note Negative V - - V - V - REFSD- ref. voltage SSA Normal mode (f = 6MHz) - 800 1200 - ADC Supply Slow mode (f = 1.5MHz) - - 600 - ADC current I Standby - - 200 µA - DDSDx (V = DDSDx 3.3 V) Power down - - 2.5 - SD_ADC off - - 1 - V Single ended mode (zero reference) V - REFSD+ Common REFSD- /gain Voltage on input V V V AINP or AIN voltage Single ended offset mode V - REFSD+/ REFSD- (gain*2) AINN pin range Differential mode V - V SSA DDSDx Differential Differential voltage -V V / V input Differential mode only REFSD+/ - REFSD+ - between DIFF (gain*2) (gain*2) voltage AINP and AINN Slow mode (f = 1.5MHz) - 4.166 - f /360 ADC ADC Slow mode one channel only - 12.5 - f /120 (f = 1.5MHz) ADC ADC fS Sraatempling N(form a=l 6m ModHez m) ultiplexed channel - 16.66 - kHz fADC/360 ADC Normal mode one channel only, FAST= 1 - 50 - f /120 ADC (f = 6MHz) ADC Conversio t - - 1/fs - s - CONV n time One channel, gain = 0.5, - 540 - see f = 1.5MHz Analog ADC reference Rain input One channel, gain = 0.5, f = 6 kΩ manual for ADC - 135 - impedance MHz detailed description One channel, gain = 8, f = 6 MHz - 47 - ADC Calibration t f = 6MHz, one offset calibration - 5120 - µs 30720/f CALIB time ADC ADC 600/f , ADC Stabilizatio 75/f if t From power down f = 6 MHz - 100 - µs ADC STAB n time ADC SLOWCK =1 Wakeup fADC = 6 MHz - 50 - 300/fADC tSTANDBY fsrtoamnd by f = 1.5MHz - 50 - µs 7S5L/OfAWDCC iKf ADC time =1 DocID022691 Rev 7 109/137 114

Electrical characteristics STM32F373xx Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max Unit Note f = V ADC REFSD+ - - 110 1.5MHz = 3.3 1 e ain = fADC = V= R1E.2FSD+ - - 110 od g 6MHz V m REFSD+ - - 100 al = 3.3 nti V e REFSD+ - - 70 EO Offset Differ gain = 8 f6ADMCH =z VDDSDx =V= R13E..23FSD+ - - 100 uV after offset error f = = 3.3 V calibration ADC REFSD+ - - 90 1.5MHz = 3.3 V = 1 = R1E.2FSD+ - - 2100 n ode gai V= R3E.3FSD+ - - 2000 m d - de 8 VREFSD+ - - 1500 en = = 1.2 e n Singl gai V= R3E.3FSD+ - - 1800 Offset drift D with Differential or single ended mode, voffsettem - 10 15 uV/K - temperatur gain=1, V = 3.3V p DDSDx e negative gain error = All gains, differential mode, single EG Gain error -2.4 -2.7 -3.1 % data result ended mode are greater than ideal Gain drift with gain = 1, differential mode, single ppm EGT - 0 - - temperatur ended mode /K e 110/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max Unit Note V 1 REFSD+ - - 16 de n = = 1.2 mo gai VREFSD+ - - 14 al = 3.3 nti V Differe n = 8 = R1E.2FSD+ - - 26 Integral gai V= R3E.3FSD+ - - 14 EL linearity V = 3.3 LSB - DDSDx error(2) 1 VREFSD+ - - 31 ode n = = 1.2 d m gai V= R3E.3FSD+ - - 23 e d gle en = 8 V= R1E.2FSD+ - - 80 n n Si gai VREFSD+ - - 35 = 3.3 V 1 REFSD+ - - 2.4 de n = = 1.2 mo gai VREFSD+ - - 1.8 al = 3.3 nti V Differe n = 8 = R1E.2FSD+ - - 3.6 Differential gai V= R3E.3FSD+ - - 2.9 ED linearity V = 3.3 LSB - DDSDx error 1 VREFSD+ - - 3.2 ode n = = 1.2 d m gai V= R3E.3FSD+ - - 2.8 e d gle en = 8 V= R1E.2FSD+ - - 4.1 n n Si gai VREFSD+ - - 3.3 = 3.3 DocID022691 Rev 7 111/137 114

Electrical characteristics STM32F373xx Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max Unit Note f = V ADC REFSD+ 84 85 - 1.5MHz = 3.3(3) 1 e ain = fADC = V= R1E.2F(S4D)+ 86 88 - od g 6MHz V m REFSD+ 88 92 - al = 3.3 nti V e REFSD+ 76 78 - Differ n = 8 f6ADMCH =z =V= R13E..23F(S4D)+ 82 86 - ai g Signal to f = V V SNR(5) ADC DDSDx REFSD+ 76 80 - dB - noise ratio 1.5MHz = 3.3 = 3.3(3) f = V ADC REFSD+ 80 84 - 1.5MHz = 3.3 1 mode ain = fADC = V= R1E.2F(S4D)+ 77 81 - ded g 6MHz VREFSD+ 85 90 - n = 3.3 e e Singl = 8 fADC = V= R1E.2F(S4D)+ 66 71 - gain 6MHz VREFSD+ 74 78 - = 3.3 112/137 DocID022691 Rev 7

STM32F373xx Electrical characteristics Table 74. SDADC characteristics (continued)(1) Symbol Parameter Conditions Min Typ Max Unit Note f = V ADC REFSD+ 76 77 - 1.5MHz = 3.3(3) 1 = V e gain fADC = 6 = R1E.2F(S4D)+ 75 76 - od MHz V m REFSD+ 76 77 - al = 3.3 nti V e REFSD+ 70 74 - Differ =8 fMADHCz = 6 =V 1.2(4) n REFSD+ 79 85 - Signal to gai = 3.3 ENOB = noise and f = V V SINAD(5) ADC DDSDx REFSD+ 75 81 - dB SINAD/ distortion 1.5 MHz = 3.3 = 3.3(3) 6.02 -0.292 ratio f = V ADC REFSD+ 72 73 - 1.5MHz = 3.3 1 e = V ded mod gain f6ADMCH =z =V RR1EE.2FF(SS4DD)++ 6782 7713 -- n = 3.3 e e Singl gain =8 f6ADMCH =z V=V RR1EE.2FF(S 4=D) + 6607 6742 -- 3.3 f = V ADC REFSD+ - -77 -76 1.5MHz = 3.3(3) 1 = V e gain fADC = = R1E.2F(S4D)+ - -77 -76 od 6MHz V m REFSD+ - -77 -76 al = 3.3 nti V e REFSD+ - -85 -70 Differ =8 f6ADMCH =z =V 1.2(4) THD(5) Thoatraml onic gain VDDSDx = R3E.3FSD+ - -93 -80 dB - distortion fADC = = 3.3 VREFSD+ - -93 -83 1.5 MHz = 3.3(3) V REFSD+ - -72 -68 e =1 f = = 1.2(4) d mod gain 6ADMCH z V= R3E.3FSD+ - -74 -72 e d Single en gain =8 f6ADMCH =z V=V RR1EE.2FF(SS4DD)++ -- --6765 --6710 = 3.3 DocID022691 Rev 7 113/137 114

Electrical characteristics STM32F373xx 1. Guaranteed by characterization results. 2. Integral linearity error can be improved by software calibration of SDADC transfer curve (2-nd order polynomial calibration). 3. For f lower than 5 MHz, there will be a performance degradation of around 2 dB due to flicker noise increase. ADC 4. If the reference value is lower than 2.4 V, there will be a performance degradation proportional to the reference supply drop, according to this formula: 20*log10(V /2.4) dB REF 5. SNR, THD, SINAD parameters are valid for frequency bandwidth 20Hz - 1kHz. Input signal frequency is 300Hz (for f =6MHz) and 100Hz (for f =1.5MHz). ADC ADC Table 75. VREFSD+ pin characteristics(1) Symbol Parameter Conditions Min Typ Max Unit Note See Section6.3.4: Buffered embedded Embedded - 1.2 - V reference voltage (1.2V) reference voltage on V Internal reference page60 REFINT voltage Embedded reference voltage amplified by - 1.8 - V - factor 1.5 Reference voltage C (2) V = V 1000 - 10000 nF - VREFSD+ filtering capacitor REFSD+ REFINT Normal mode R Reference voltage (fADC = 6MHz) - 238 - kΩ Sreefeer RenMc0e3 m1a3n ual for VREFSD+ input impedance Slow mode detailed description - 952 - (f = 1.5MHz) ADC 1. Guaranteed by characterization results. 2. If internal reference voltage is selected then this capacitor is charged through internal resistance - typ. 300 ohm. If internal reference source is selected through the reference voltage selection bits (REFV<>”00” in SDADC_CR1 register), the application must first configure REFV bits and then wait for capacitor charging. Recommended waiting time is 3 ms if 1 µF capacitor is used. 114/137 DocID022691 Rev 7

STM32F373xx Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA100 package information Figure 32. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package outline (cid:61) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:36)(cid:23) (cid:36)(cid:22) (cid:36)(cid:21) (cid:36)(cid:20) (cid:36) (cid:40)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:59) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:40) (cid:72) (cid:41) (cid:36) (cid:41) (cid:39)(cid:20) (cid:39) (cid:72) (cid:60) (cid:48) (cid:20)(cid:21) (cid:20) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:69)(cid:3)(cid:11)(cid:20)(cid:19)(cid:19)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:12) (cid:55)(cid:50)(cid:51)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:72)(cid:72)(cid:72)(cid:48) (cid:61) (cid:60) (cid:59) (cid:145)(cid:73)(cid:73)(cid:73) (cid:48) (cid:61) (cid:36)(cid:19)(cid:38)(cid:21)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:23) 1. Drawing is not to scale. T able 76. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches(1) Symbol Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 DocID022691 Rev 7 115/137 130

Package information STM32F373xx Table 76. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches(1) Symbol Min. Typ. Max. Min. Typ. Max. D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 33. UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package recommended footprint (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:36)(cid:19)(cid:38)(cid:21)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:20) Table 77. UFBGA100 recommended PCB design rules (0.5mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280mm 0.370mm typ. (depends on the soldermask Dsm registration tolerance) Stencil opening 0.280mm Stencil thickness Between 0.100mm and 0.125mm 116/137 DocID022691 Rev 7

STM32F373xx Package information Device Marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball 1 identifier location. Figure 34. UFBGA100 marking example (package top view) (cid:87)(cid:396)(cid:381)(cid:282)(cid:437)(cid:272)(cid:410)(cid:3)(cid:349)(cid:282)(cid:286)(cid:374)(cid:410)(cid:349)(cid:296)(cid:349)(cid:272)(cid:258)(cid:410)(cid:349)(cid:381)(cid:374)(cid:894)(cid:1005)(cid:895) (cid:1007)(cid:1006)(cid:38)(cid:1007)(cid:1011)(cid:1007) (cid:115)(cid:1012)(cid:44)(cid:1010) (cid:24)(cid:258)(cid:410)(cid:286)(cid:3)(cid:272)(cid:381)(cid:282)(cid:286)(cid:3)(cid:1089)(cid:3)(cid:455)(cid:286)(cid:258)(cid:396)(cid:3)(cid:1085)(cid:3)(cid:449)(cid:286)(cid:286)(cid:364) (cid:122) (cid:116)(cid:116) (cid:17)(cid:258)(cid:367)(cid:367)(cid:3)(cid:1005)(cid:3)(cid:349)(cid:282)(cid:286)(cid:374)(cid:410)(cid:349)(cid:296)(cid:349)(cid:272)(cid:258)(cid:410)(cid:349)(cid:381)(cid:374) (cid:4)(cid:282)(cid:282)(cid:349)(cid:410)(cid:349)(cid:381)(cid:374)(cid:258)(cid:367)(cid:3)(cid:349)(cid:374)(cid:296)(cid:381)(cid:396)(cid:373)(cid:258)(cid:410)(cid:349)(cid:381)(cid:374) (cid:17) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:28)(cid:23)(cid:26)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID022691 Rev 7 117/137 130

Package information STM32F373xx 7.2 LQFP100 package information Figure 35. LQFP100 - 100-pin, 14 x 14mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:33) (cid:18) (cid:17) (cid:33) (cid:33) (cid:67) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:44) (cid:33)(cid:17) (cid:43) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:23)(cid:21) (cid:21)(cid:17) (cid:21)(cid:16) (cid:23)(cid:22) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:17) (cid:18)(cid:21) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:69) (cid:17)(cid:44)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:21) 1. Drawing is not to scale. 118/137 DocID022691 Rev 7

STM32F373xx Package information Table 78. LQPF100 - 100-pin, 14 x 14mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022691 Rev 7 119/137 130

Package information STM32F373xx Figure 36. LQFP100 - 100-pin, 14 x 14mm low-profile quad flat recommended footprint (cid:23)(cid:21) (cid:21)(cid:17) (cid:23)(cid:22) (cid:21)(cid:16) (cid:16)(cid:14)(cid:21) (cid:16)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:17)(cid:20)(cid:14)(cid:19) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:17)(cid:14)(cid:18) (cid:17) (cid:18)(cid:21) (cid:17)(cid:18)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:22)(cid:67) 1. Dimensions are expressed in millimeters. Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 37. LQFP100 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:38)(cid:1007)(cid:1011)(cid:1007) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:115)(cid:1012)(cid:100)(cid:1010)(cid:3)(cid:3) (cid:17) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:122) (cid:116)(cid:116) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:28)(cid:23)(cid:27)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 120/137 DocID022691 Rev 7

STM32F373xx Package information 7.3 LQFP64 package information Figure 38. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:70) (cid:36) (cid:70)(cid:70)(cid:70) (cid:38) (cid:20) (cid:39) (cid:36) (cid:46) (cid:39)(cid:20) (cid:47) (cid:39)(cid:22) (cid:47)(cid:20) (cid:23)(cid:27) (cid:22)(cid:22) (cid:22)(cid:21) (cid:23)(cid:28) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20) (cid:20)(cid:25) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:72) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:24)(cid:58)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. DocID022691 Rev 7 121/137 130

Package information STM32F373xx Table 79. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 122/137 DocID022691 Rev 7

STM32F373xx Package information Figure 39. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package recommended footprint (cid:20)(cid:24) (cid:19)(cid:19) (cid:16)(cid:14)(cid:19) (cid:20)(cid:25) (cid:16)(cid:14)(cid:21) (cid:19)(cid:18) (cid:17)(cid:18)(cid:14)(cid:23) (cid:17)(cid:16)(cid:14)(cid:19) (cid:17)(cid:16)(cid:14)(cid:19) (cid:22)(cid:20) (cid:17)(cid:23) (cid:17)(cid:14)(cid:18) (cid:17) (cid:17)(cid:22) (cid:23)(cid:14)(cid:24) (cid:17)(cid:18)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:25)(cid:67) 1. Dimensions are expressed in millimeters. Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 40. LQFP64 marking example (package top view) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:17) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:38)(cid:1007)(cid:1011)(cid:1007) (cid:90)(cid:17)(cid:100)(cid:1010) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:122) (cid:116)(cid:116) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:28)(cid:23)(cid:25)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID022691 Rev 7 123/137 130

Package information STM32F373xx 7.4 LQFP48 package information Figure 41. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33)(cid:33) (cid:17) (cid:33) (cid:67) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:43) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:20)(cid:24) (cid:17)(cid:19) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:17)(cid:18) (cid:69) (cid:21)(cid:34)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:18) 1. Drawing is not to scale. 124/137 DocID022691 Rev 7

STM32F373xx Package information Table 80. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022691 Rev 7 125/137 130

Package information STM32F373xx Figure 42. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package recommended footprint (cid:16)(cid:14)(cid:21)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:16)(cid:14)(cid:18)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:24) (cid:17)(cid:19) (cid:17) (cid:17)(cid:18) (cid:17)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:17)(cid:17)(cid:68) 1. Dimensions are expressed in millimeters. Device marking for LQFP48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 43. LQFP48 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:38) (cid:1007)(cid:1011)(cid:1007)(cid:18)(cid:17)(cid:100)(cid:1010)(cid:3)(cid:3) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:122) (cid:116)(cid:116) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:36)(cid:71)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:1005) (cid:48)(cid:54)(cid:89)(cid:22)(cid:26)(cid:28)(cid:23)(cid:24)(cid:57)(cid:20) 1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. Only if ST has authorized in writing the customer qualification Engineering Samples can be used for reliability qualification trials. 126/137 DocID022691 Rev 7

STM32F373xx Package information 7.5 Thermal characteristics The maximum chip junction temperature (T max) must never exceed the values given in J Table22: General operating conditions. The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated J using the following equation: T max = T max + (P max x Q ) J A D JA Where: • T max is the maximum ambient temperature in °C, A • Q is the package junction-to-ambient thermal resistance, in °C/W, JA • P max is the sum of P max and P max (P max = P max + P max), D INT I/O D INT I/O • P max is the product of I andV , expressed in Watts. This is the maximum chip INT DD DD internal power. P max represents the maximum power dissipation on output pins where: I/O PI/O max = S (VOL × IOL) + S((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 81. Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction-ambient 45 LQFP64 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient 55 LQFP48 - 7 × 7 mm Θ °C/W JA Thermal resistance junction-ambient 46 LQFP100 - 14 × 14 mm / 0.5 mm pitch Thermal resistance junction-ambient 59 UFBGA100 - 7 x 7 mm 7.5.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org DocID022691 Rev 7 127/137 130

Package information STM32F373xx 7.5.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F373xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature T = 82 °C (measured according to JESD51-2), Amax I = 50 mA, V = 3.5 V, maximum 3 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V and maximum 2 I/Os used at the same time in output OL OL at low level with I = 20 mA, V = 1.3 V OL OL P = 50 mA × 3.5 V= 175 mW INTmax P = 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW IOmax This gives: P = 175 mW and P = 61.6 mW: INTmax IOmax P =175 61.6 = 236.6 mW Dmax + Thus: P = 236.6 mW Dmax Using the values obtained in Table81 T is calculated as follows: Jmax – For LQFP64, 45°C/W T = 82 °C + (45°C/W × 236.6 mW) = 82 °C + 10.65 °C = 92.65 °C Jmax This is within the range of the suffix 6 version parts (–40 < T < 105 °C). J In this case, parts must be ordered at least with the temperature range suffix 6 (see Section8: Part numbering). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T remains within the J specified range. Assuming the following application conditions: Maximum ambient temperature T = 115 °C (measured according to JESD51-2), Amax I = 20 mA, V = 3.5 V, maximum 9 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V OL OL P =20 mA × 3.5 V= 70 mW INTmax P = 9 × 8 mA × 0.4 V = 28.8 mW IOmax This gives: P = 70 mW and P = 28.8 mW: INTmax IOmax P = 70+28.8 = 98.8 mW Dmax Thus: P = 98.8 mW Dmax 128/137 DocID022691 Rev 7

STM32F373xx Package information Using the values obtained in Table81 T is calculated as follows: Jmax – For LQFP100, 46°C/W T = 115 °C + (46°C/W × 98.8 mW) = 115 °C + 4.54 °C = 119.5 °C Jmax This is within the range of the suffix 7 version parts (–40 < T < 125 °C). J In this case, parts must be ordered at least with the temperature range suffix 7 (see Section8: Part numbering). Figure 44. LQFP64 P max vs. T D A (cid:26)(cid:19)(cid:19) (cid:25)(cid:19)(cid:19) (cid:24)(cid:19)(cid:19) (cid:12) (cid:58) (cid:80) (cid:23)(cid:19)(cid:19) (cid:54)(cid:88)(cid:73)(cid:73)(cid:76)(cid:91)(cid:3)(cid:25) (cid:11) (cid:3)(cid:39) (cid:22)(cid:19)(cid:19) (cid:51) (cid:54)(cid:88)(cid:73)(cid:73)(cid:76)(cid:91)(cid:3)(cid:26) (cid:21)(cid:19)(cid:19) (cid:20)(cid:19)(cid:19) (cid:19) (cid:25)(cid:24) (cid:26)(cid:24) (cid:27)(cid:24) (cid:28)(cid:24) (cid:20)(cid:19)(cid:24) (cid:20)(cid:20)(cid:24) (cid:20)(cid:21)(cid:24) (cid:20)(cid:22)(cid:24) (cid:55) (cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:23)(cid:22)(cid:57)(cid:20) DocID022691 Rev 7 129/137 130

Part numbering STM32F373xx 8 Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 82. Ordering information scheme Example: STM32 F 373 R 8 T 6 x Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 373 = STM32F373xx Pin count C = 48 pins R = 64 pins V = 100 pins Code size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package T = LQFP H = BGA Temperature range 6 = Industrial temperature range, –40 to 85 °C 7 = Industrial temperature range, –40 to 105 °C Options xxx = programmed parts TR = tape and reel 130/137 DocID022691 Rev 7

STM32F373xx Revision history 9 Revision history Table 83. Document revision history Date Revision Changes 18-Jun-2012 1 Initial release. Added ‘F’ to all ‘Cortex-M4’ occurrences Modified the shapes of Figure2: STM32F373xx LQFP48 pinout to Figure4: STM32F373xx LQFP100 pinout Added two rows ‘VREFSD+ - VDDSD3’ and ‘VREF+ - VDDA’ in Table19: Voltage characteristics Removed PB0 in footnote of Table19: Voltage characteristics and in Section6.3.14: I/O port characteristics Added a paragraph after ‘...power up sequence’ in Section6.2: Absolute maximum ratings and after ‘...in output mode’ in I/O system current consumption Corrected SDAC_VREF+ in Figure9: Power supply scheme Modified Table20: Current characteristics Added BGA100 in Table22: General operating conditions Added values in Table27: Embedded internal reference voltage Filled values in Table28: Typical and maximum current consumption from VDD supply at VDD = 3.6 V Filled values in Table29: Typical and maximum current consumption from VDDA supply Filled values in Table30: Typical and maximum VDD consumption in Stop and Standby modes 07-Sep-2012 2 Removed table: “Typical and maximum VDDA consumption in Stop modes” Filled values in Table31: Typical and maximum VDDA consumption in Stop and Standby modes Added VBAT values in Table32: Typical and maximum current consumption from VBAT supply Added typ values in Table33: Typical current consumption in Run mode, code with data processing running from Flash and Table34: Typical current consumption in Sleep mode, code running from Flash or RAM Added max value in Table41: LSE oscillator characteristics (fLSE = 32.768 kHz) Modified min and max values in Table42: HSI oscillator characteristics Added values in Table37: Low-power mode wakeup timings Added Class values in Table47: EMS characteristics Modified values in Table48: EMI characteristics Added values in Table49: ESD absolute maximum ratings Added class value in Table50: Electrical sensitivities Modified values and descriptions in Table51: I/O current injection susceptibility DocID022691 Rev 7 131/137 136

Revision history STM32F373xx Table 83. Document revision history (continued) Date Revision Changes Filled values in Table70: WWDG min-max timeout value @72 MHz (PCLK) Filled values in Table58: SPI characteristics Filled values in Table59: I2S characteristics Replaced Table60: ADC characteristics Added values in Table74: SDADC characteristics Modified footnote in Table75: VREFSD+ pin characteristics Replaced ‘AIN’ with ‘SRC’ in Table61: RSRC max for fADC = 14 MHz and Figure28: Typical connection diagram using the ADC Reordered chapters and Cover page features. Added subsection to GPIOS in Table2: Device overview Aligned SRAM with USB in Figure1: Block diagram Added “Do not reconfigure...” sentence in Section3.9: General-purpose input/outputs (GPIOs) Added Table7: STM32F373xx I2C implementation Added Table8: STM32F373xx USART implementation Merged SPI and I2S into one section Reshaped Figure5: STM32F373xx UFBGA100 ballout and removed ADC10 Added notes column, modified I/O structure values and pin, function names, removed TIM1_TX & TIM1_RX in Table11: 2 07-Sep-2012 STM32F373xx pin definitions (cont’d) Added the note “do not reconfigure...” after Table11: STM32F373xx pin definitions Modified “x_CK” occurrences to “I2Sx_CK” in Table12: Alternate functions for port PA to Table17: Alternate functions for port PF Added two GP I/Os in Figure9: Power supply scheme Added Caution after Figure9: Power supply scheme Added Max values in Table23: Operating conditions at power-up / power-down Modified (1) footnote in Table24: Embedded reset and power control block characteristics Added row to Table27: Embedded internal reference voltage Added the note “ It is recommended...” under Table51: I/O current injection susceptibility Modified Table51: I/O current injection susceptibility Modified temperature and current values in Section7.5.2: Selecting the product temperature range Added crystal EPSON-TOYOCOM bullet under Typical current consumption Modified Figure9: Power supply scheme Removed Boot 0 section Modified Table73: USB: Full-speed electrical characteristics 132/137 DocID022691 Rev 7

STM32F373xx Revision history Table 83. Document revision history (continued) Date Revision Changes Updated Table2: Device overview, capacitive sensing channels peripheral added. Updated Table3: Capacitive sensing GPIOs available on STM32F373xx devices Updated Section3.19: Inter-integrated circuit interface (I2C) Updated the function names in Table11: STM32F373 pin definitions Updated Table20: Current characteristics Updated Table22: General operating conditions Updated Table30: Typical and maximum VDD consumption in Stop and Standby modes Updated Table32: Typical and maximum current consumption from VBAT supply Added Figure11: Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0]='00') Updated Table33: Typical current consumption in Run mode, code with data processing running from Flash and Table34: Typical current consumption in Sleep mode, code running from Flash or RAM Added Table35: Switching output I/O current consumption Added Table36: Peripheral current consumption, Figure16: HSI oscillator accuracy characterization results Updated Section6.3.6: Wakeup time from low-power mode Updated Table37: Low-power mode wakeup timings 21-Dec-2012 3 Updated Table47: EMS characteristics Updated Table51: I/O current injection susceptibility Updated Table52: I/O static characteristics Updated , Figure18: TC and TTa I/O input characteristics - TTL port, Figure18: Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port and Figure20: Five volt tolerant (FT and FTf) I/O input characteristics - TTL port Updated Table53: Output voltage characteristics Updated Table54: I/O AC characteristics Updated Table55: NRST pin characteristics Updated Table63: DAC characteristics Updated Table74: SDADC characteristics Updated Figure32: LQFP100 –14 x 14 mm 100-pin low- profile quad flat package outline, Figure35: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Figure38: LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline Updated Table72: LQPF100 – 14 x 14 mm low-profile quad flat package mechanical data, Table73: LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data and Table74: LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data Added Figure16: HSI oscillator accuracy characterization results DocID022691 Rev 7 133/137 136

Revision history STM32F373xx Table 83. Document revision history (continued) Date Revision Changes Replaced “Cortex-M4F” with “Cortex-M4” throughout the document. Removed part number STM32F372xx. Added “1.25 DMIPS/MHz (Dhrystone 2.1)” in Features. Updated Introduction. Added reference to the STMTouch touch sensing firmware library in Section3.16: Touch sensing controller (TSC). Added “All I2S interfaces can operate in half-duplex mode only.” in Section3.21: Serial peripheral interface (SPI)/Inter- integrated sound interfaces (I2S). Added row “I2S full-duplex mode” to Table9: STM32F373xx SPI/I2S implementation. Modified introduction of I2C interface characteristics. Added alternate function RTC_REFIN and removed additional function RTC_REF_CLK_IN to pins PA1 and PB15. Replaced alternate function JNTRST with NJTRST for pin PB4. In Table12: Alternate functions for port PA: replaced alternate function JTMS-SWDIO with SWDIO-JTMS for pin PA13, and JTCK-SWCLK with SWCLK-JTCK for pin PA14. 19-Sep-2013 4 Added rows V andV to Table22: General REF+ REFSD+ operating conditions. Replaced "f = f " with "f = f " for “When the APB1 AHB/2 APB1 AHB peripherals are enabled...” in Typical current consumption. Added COMP in Table36: Peripheral current consumption Added conditions for f in Table38: High-speed external HSE_ext user clock characteristics. Added Min and Max values for ACC in Table42: HSI HISI oscillator characteristics. Replaced reference "JESD22-C101" with "ANSI/ESD STM5.3.1" in Table49: ESD absolute maximum ratings. Removed pins PB0 and PB1 in description of I in Table51: INJ I/O current injection susceptibility. Updated Table56: I2C characteristics. Replaced all occurrences of “gain/2” with “gain*2” in Table74: SDADC characteristics. Corrected typo in Figure19: I/O AC characteristics definition. Replaced Figure21: I2C bus AC waveforms and measurement circuit.. Added I and footnote 1 in Table60: ADC DDA(ADC) characteristics 134/137 DocID022691 Rev 7

STM32F373xx Revision history Table 83. Document revision history (continued) Date Revision Changes Renamed part number STM32F37x to STM32F373xx Added note1 in Table28: Typical and maximum current consumption from VDD supply at VDD = 3.6 V Updated Chapter3.14: Digital-to-analog converter (DAC) Updated, added note 2 and 3 in Table57: I2C analog filter 18-Mar-2014 5 characteristics Renamed t symbol with t SP AF. Added note for EG Symbol in Table74: SDADC characteristics Added all packages top view Updated Section7 Updated Section3.13 Updated Section3.7.1, Section3.7.4 Updated Table11: STM32F373xx pin definitions, Table19: Voltage characteristics, Table49: ESD absolute maximum ratings, Table74: SDADC characteristics, Table76: UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package mechanical data, and Table78: LQPF100 - 100-pin, 14 x 14mm low-profile quad flat package mechanical data Updated Figure2: STM32F373xx LQFP48 pinout, Figure9: Power supply scheme, Figure32: UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package outline, Figure34: UFBGA100 marking example (package top view), Figure36: LQFP100 - 100-pin, 14 x 14mm low-profile quad flat recommended footprint, Figure37: LQFP100 21-Jul-2015 6 marking example (package top view), Figure38: LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package outline, Figure39: LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package recommended footprint, Figure40: LQFP64 marking example (package top view), Figure42: LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package recommended footprint, Figure43: LQFP48 marking example (package top view). Added Table32: Typical and maximum current consumption from VBAT supply, Table49: ESD absolute maximum ratings, Table64: Comparator characteristics, Table77: UFBGA100 recommended PCB design rules (0.5mm pitch BGA). Added Figure11: Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0]='00'), Figure30: Maximum VREFINT scaler startup time from power down, Figure33: UFBGA100 - 100-pin, 7 x 7mm, 0.50mm pitch, ultra fine pitch ball grid array package recommended footprint. DocID022691 Rev 7 135/137 136

Revision history STM32F373xx Table 83. Document revision history (continued) Date Revision Changes Updated: – Table3: Capacitive sensing GPIOs available on STM32F373xx devices – Table19: Voltage characteristics – Table27: Embedded internal reference voltage – Table41: LSE oscillator characteristics (fLSE = 32.768 kHz) – Table49: ESD absolute maximum ratings – Table60: ADC characteristics – Table63: DAC characteristics – Table65: Temperature sensor calibration values 08-Jun-2016 7 – Table74: SDADC characteristics – Table81: Package thermal characteristics – Figure17: TC and TTa I/O input characteristics - CMOS port – Figure18: Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port Removed: – Figure18: TC and TTa I/O input characteristics - TTL port – Figure20: Five volt tolerant (FT and FTf) I/O input characteristics - TTL port 136/137 DocID022691 Rev 7

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