图片仅供参考

详细数据请看参考数据手册

Datasheet下载
  • 型号: STM32F103ZDT6
  • 制造商: STMicroelectronics
  • 库位|库存: xxxx|xxxx
  • 要求:
数量阶梯 香港交货 国内含税
+xxxx $xxxx ¥xxxx

查看当月历史价格

查看今年历史价格

STM32F103ZDT6产品简介:

ICGOO电子元器件商城为您提供STM32F103ZDT6由STMicroelectronics设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 STM32F103ZDT6价格参考。STMicroelectronicsSTM32F103ZDT6封装/规格:嵌入式 - 微控制器, ARM® Cortex®-M3 微控制器 IC STM32F1 32-位 72MHz 384KB(384K x 8) 闪存 144-LQFP(20x20)。您可以下载STM32F103ZDT6参考资料、Datasheet数据手册功能说明书,资料中有STM32F103ZDT6 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
A/D位大小

12 bit

产品目录

集成电路 (IC)半导体

描述

MCU ARM 32BIT 384K FLASH 144LQFPARM微控制器 - MCU 32BIT Cortex M3 H/D 262 to 512 USB/CAN

EEPROM容量

-

产品分类

嵌入式 - 微控制器

I/O数

112

品牌

STMicroelectronics

产品手册

点击此处下载产品Datasheet

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

嵌入式处理器和控制器,微控制器 - MCU,ARM微控制器 - MCU,STMicroelectronics STM32F103ZDT6STM32 F1

数据手册

点击此处下载产品Datasheet

产品型号

STM32F103ZDT6

RAM容量

64K x 8

产品培训模块

http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=30015http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=30339

产品种类

ARM微控制器 - MCU

供应商器件封装

144-LQFP(20x20)

其它名称

497-11544
STM32F103ZDT6-ND

其它有关文件

http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1031/LN1565/PF206934?referrer=70071840

包装

托盘

可用A/D通道

16

可编程输入/输出端数量

112

商标

STMicroelectronics

商标名

STM32

处理器系列

ARM Cortex-M

外设

DMA,电机控制 PWM,PDR,POR,PVD,PWM,温度传感器,WDT

安装风格

SMD/SMT

定时器数量

8 Timer

封装

Tray

封装/外壳

144-LQFP

封装/箱体

LQFP-144

工作温度

-40°C ~ 85°C

工作电源电压

2 V to 3.6 V

工厂包装数量

60

振荡器类型

内部

接口类型

CAN, I2C, SPI, USART

数据RAM大小

64 kB

数据Ram类型

SRAM

数据总线宽度

32 bit

数据转换器

A/D 21x12b; D/A 2x12b

最大工作温度

+ 85 C

最大时钟频率

72 MHz

最小工作温度

- 40 C

标准包装

60

核心

ARM Cortex M3

核心处理器

ARM® Cortex®-M3

核心尺寸

32-位

片上ADC

Yes

片上DAC

With DAC

特色产品

http://www.digikey.com/product-highlights/cn/zh/stmicroelectronics-stm32/1369

电压-电源(Vcc/Vdd)

2 V ~ 3.6 V

程序存储器大小

384 kB

程序存储器类型

闪存

程序存储容量

384KB(384K x 8)

系列

STM32F1

输入/输出端数量

112 I/O

连接性

CAN, I²C, IrDA, LIN, SPI, UART/USART, USB

速度

72MHz

配用

/product-detail/zh/FS2009USB(ARM)/483-1023-ND/3479597/product-detail/zh/STEVAL-ISQ008V1/497-11038-ND/2524216/product-detail/zh/STM3210E-SK%2FHIT/497-10030-ND/2137268/product-detail/zh/KSDKSTM32-PL/KSDKSTM32-PL-ND/2021937/product-detail/zh/STM3210E-SK%2FKEIL/497-8512-ND/2000403/product-detail/zh/STM3210E-PRIMER/497-8511-ND/2000402/product-detail/zh/STM3210E-SK%2FIAR/497-8505-ND/1994837/product-detail/zh/STM3210E-EVAL/497-6438-ND/1852088/product-detail/zh/STM3210B-PFSTICK/497-6289-ND/1754421/product-detail/zh/STM3210B-SK%2FRAIS/497-6053-ND/1646328/product-detail/zh/STM3210B-SK%2FKEIL/497-6052-ND/1646327/product-detail/zh/STM3210B-SK%2FHIT/497-6050-ND/1646325/product-detail/zh/STM3210B-PRIMER/497-6049-ND/1646324/product-detail/zh/STM3210B-EVAL/497-6048-ND/1646323/product-detail/zh/STM32103B-D%2FRAIS/497-6047-ND/1646322

长度

20 mm

推荐商品

型号:MK12DX128VMC5

品牌:NXP USA Inc.

产品名称:集成电路(IC)

获取报价

型号:PIC18F13K22-E/SS

品牌:Microchip Technology

产品名称:集成电路(IC)

获取报价

型号:LPC1113FHN33/303,5

品牌:NXP USA Inc.

产品名称:集成电路(IC)

获取报价

型号:MSP430FE427IPM

品牌:Texas Instruments

产品名称:集成电路(IC)

获取报价

型号:ATTINY861-20MU

品牌:Microchip Technology

产品名称:集成电路(IC)

获取报价

型号:PIC24FJ128DA110-I/BG

品牌:Microchip Technology

产品名称:集成电路(IC)

获取报价

型号:C8051F381-GM

品牌:Silicon Labs

产品名称:集成电路(IC)

获取报价

型号:PIC18F66J50-I/PT

品牌:Microchip Technology

产品名称:集成电路(IC)

获取报价

样品试用

万种样品免费试用

去申请
STM32F103ZDT6 相关产品

P87C58X2FA,512

品牌:NXP USA Inc.

价格:

LM3S1H11-IQC80-A2T

品牌:Texas Instruments

价格:

MC68HC908JB16DW

品牌:NXP USA Inc.

价格:

S9S12GA240F0MLL

品牌:NXP USA Inc.

价格:

DSPIC33EP256MC206-I/MR

品牌:Microchip Technology

价格:

Z8F0213SH005EG2156

品牌:Zilog

价格:

PIC16LF1947-I/PT

品牌:Microchip Technology

价格:

DSPIC33EP128GP502-E/SS

品牌:Microchip Technology

价格:

PDF Datasheet 数据手册内容提取

STM32F103xC, STM32F103xD, STM32F103xE ® High-density performance line Arm -based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces − Datasheet production data Features • Core: Arm® 32-bit Cortex®-M3 CPU WLCSP64 – 72 MHz maximum frequency, 1.25DMIPS/MHz LQFP64 10 × 10 mm, (Dhrystone 2.1) performance at 0 wait state LQFP100 14 × 14 mm, LFBGA100 10 × 10 mm memory access LQFP144 20 × 20 mm LFBGA144 10 × 10 mm – Single-cycle multiplication and hardware • Up to 11 timers division • Memories – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature – 256 to 512 Kbytes of Flash memory (incremental) encoder input – up to 64 Kbytes of SRAM – 2 × 16-bit motor control PWM timers with dead- – Flexible static memory controller with 4 Chip time generation and emergency stop Select. Supports Compact Flash, SRAM, – 2 × watchdog timers (Independent and Window) PSRAM, NOR and NAND memories – SysTick timer: a 24-bit downcounter – LCD parallel interface, 8080/6800 modes – 2 × 16-bit basic timers to drive the DAC • Clock, reset and supply management • Up to 13 communication interfaces – 2.0 to 3.6V application supply and I/Os – Up to 2 × I2C interfaces (SMBus/PMBus) – POR, PDR, and programmable voltage detector – Up to 5 USARTs (ISO 7816 interface, LIN, IrDA (PVD) capability, modem control) – 4-to-16 MHz crystal oscillator – Up to 3 SPIs (18 Mbit/s), 2 with I2S interface – Internal 8 MHz factory-trimmed RC multiplexed – Internal 40 kHz RC with calibration – CAN interface (2.0B Active) – 32 kHz oscillator for RTC with calibration – USB 2.0 full speed interface • Low power – SDIO interface – Sleep, Stop and Standby modes • CRC calculation unit, 96-bit unique ID – V supply for RTC and backup registers BAT • ECOPACK® packages • 3 × 12-bit, 1 µs A/D converters (up to 21 channels) Table 1.Device summary – Conversion range: 0 to 3.6 V Reference Part number – Triple-sample and hold capability – Temperature sensor STM32F103RC STM32F103VC STM32F103xC • 2 × 12-bit D/A converters STM32F103ZC • DMA: 12-channel DMA controller STM32F103RD STM32F103VD STM32F103xD – Supported peripherals: timers, ADCs, DAC, STM32F103ZD SDIO, I2Ss, SPIs, I2Cs and USARTs STM32F103RE STM32F103ZE • Debug mode STM32F103xE STM32F103VE – Serial wire debug (SWD) & JTAG interfaces – Cortex®-M3 Embedded Trace Macrocell™ • Up to 112 fast I/O ports – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5V-tolerant July 2018 DS5792 Rev 13 1/143 www.st.com

Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 15 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 45 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DS5792 Rev 13 3/143 4

Contents STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2 LFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 133 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. High-density timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. High-density STM32F103xC/D/E pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 13. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 14. Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 15. Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 49 Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 50 Table 18. Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22. Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 24. LSE oscillator characteristics (f = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LSE Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 28. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 29. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 30. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 67 Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 68 Table 33. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 34. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 36. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 37. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 81 Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 85 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 42. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 43. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DS5792 Rev 13 5/143 6

List of tables STM32F103xC, STM32F103xD, STM32F103xE Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 48. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 51. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 52. SCL frequency (f = 36 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PCLK1 DD_I2C Table 53. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 54. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 55. SD / MMC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 56. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 57. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 58. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 59. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 60. R max for f = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 AIN ADC Table 61. ADC accuracy - limited test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 64. TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 66. LFBGA144 recommended PCB design rules (0.8mm pitch BGA). . . . . . . . . . . . . . . . . . 115 Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 68. LFBGA100 recommended PCB design rules (0.8mm pitch BGA). . . . . . . . . . . . . . . . . . 118 Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 70. WLCSP64 recommended PCB design rules (0.5mm pitch) . . . . . . . . . . . . . . . . . . . . . . 121 Table 71. LQFP144 - 144-pin, 20 x 20mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 129 Table 74. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 75. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. STM32F103xC/D/E BGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 4. STM32F103xC/D/E performance line BGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 5. STM32F103xC/D/E performance line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6. STM32F103xC/D/E performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 7. STM32F103xC/D/E performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 11. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 48 Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)- code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 48 Figure 16. Typical current consumption on V with RTC on vs. temperature BAT at different V values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 BAT Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DD Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DD Figure 19. Typical current consumption in Standby mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DD Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 23. Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 66 Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 67 Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 32. PC Card/CompactFlash controller waveforms for common memory read access. . . . . . . 77 Figure 33. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 78 Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 80 Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access. . . . . . . . . . . . . 81 Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DS5792 Rev 13 7/143 8

List of figures STM32F103xC, STM32F103xD, STM32F103xE Figure 40. NAND controller waveforms for common memory read access. . . . . . . . . . . . . . . . . . . . . 84 Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 85 Figure 42. Standard I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 43. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 44. 5V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 45. 5V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 48. I2C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 51. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 52. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 53. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 55. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 56. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 57. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 58. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 59. Power supply and reference decoupling (V not connected to V ). . . . . . . . . . . . . 109 REF+ DDA Figure 60. Power supply and reference decoupling (V connected to V ). . . . . . . . . . . . . . . . 110 REF+ DDA Figure 61. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 64. LFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprintoutline. . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 67. LFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049mm, 0.5mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 70. LQFP144 - 144-pin, 20 x 20mm low-profile quad flat package outline . . . . . . . . . . . . . . 122 Figure 71. LQFP144 - 144-pin,20 x 20mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 72. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . 126 Figure 74. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 75. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 129 Figure 77. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat recommended footprint . . . . . . . . . . 130 Figure 78. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 79. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 D A 8/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xC/D/E family, please refer to Section2.2: Full compatibility throughout the family. The high-density STM32F103xC/D/E datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS5792 Rev 13 9/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16- bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xC/D/E high-density performance line family operates in the –40 to +105°C temperature range, from a 2.0 to 3.6V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F103xC/D/E high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC. 10/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description 2.1 Device overview The STM32F103xC/D/E high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure1 shows the general block diagram of the device family. Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Peripherals STM32F103Rx STM32F103Vx STM32F103Zx Flash memory in Kbytes 256 384 512 256 384 512 256 384 512 SRAM in Kbytes 48 64 48 64 48 64 FSMC No Yes(1) Yes General-purpose 4 Timers Advanced-control 2 Basic 2 SPI(I2S)(2) 3(2) I2C 2 USART 5 Comm USB 1 CAN 1 SDIO 1 GPIOs 51 80 112 12-bit ADC 3 3 3 Number of channels 16 16 21 12-bit DAC 2 Number of channels 2 CPU frequency 72 MHz Operating voltage 2.0 to 3.6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table10) Operating temperatures Junction temperature: –40 to + 125 °C (see Table10) Package LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144 1. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. DS5792 Rev 13 11/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram (cid:52)(cid:50)(cid:33)(cid:35)(cid:37)(cid:35)(cid:44)(cid:43) (cid:52)(cid:50)(cid:33)(cid:35)(cid:37)(cid:36)(cid:59)(cid:16)(cid:26)(cid:19)(cid:61) (cid:52)(cid:48)(cid:41)(cid:53) (cid:32)(cid:54)(cid:36)(cid:36) (cid:65)(cid:83)(cid:0)(cid:33)(cid:51) (cid:52)(cid:82)(cid:65)(cid:67)(cid:69)(cid:15)(cid:84)(cid:82)(cid:73)(cid:71) (cid:52)(cid:82)(cid:65)(cid:67)(cid:69) (cid:42)(cid:42)(cid:52)(cid:52)(cid:35)(cid:45)(cid:43)(cid:51)(cid:15)(cid:46)(cid:15)(cid:51)(cid:51)(cid:42)(cid:55)(cid:55)(cid:52)(cid:65)(cid:42)(cid:42)(cid:52)(cid:83)(cid:50)(cid:35)(cid:36)(cid:52)(cid:0)(cid:36)(cid:51)(cid:33)(cid:44)(cid:41)(cid:36)(cid:47)(cid:47)(cid:43)(cid:52)(cid:38)(cid:41) (cid:51)(cid:35)(cid:55)(cid:38)(cid:79)(cid:15)(cid:77)(cid:82)(cid:42)(cid:84)(cid:52)(cid:69)(cid:65)(cid:33)(cid:88)(cid:88)(cid:13)(cid:39)(cid:26)(cid:0)(cid:45)(cid:20)(cid:24)(cid:19)(cid:15)(cid:0)(cid:23)(cid:35)(cid:18)(cid:48)(cid:0)(cid:45)(cid:53)(cid:40)(cid:90) (cid:36)(cid:66)(cid:48)(cid:85)(cid:66)(cid:83)(cid:85)(cid:83)(cid:41)(cid:66)(cid:85)(cid:83) (cid:67)(cid:79)(cid:78)(cid:84)(cid:82)(cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:79)(cid:66)(cid:76)(cid:79)(cid:76)(cid:76)(cid:69)(cid:73)(cid:78)(cid:84)(cid:69)(cid:82)(cid:70)(cid:65)(cid:67)(cid:69)(cid:82) (cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:22)(cid:0)(cid:20)(cid:21)(cid:0)(cid:17)(cid:66)(cid:18)(cid:73)(cid:84)(cid:0)(cid:43)(cid:66)(cid:89)(cid:84)(cid:69)(cid:83) (cid:54)(cid:36)(cid:36) (cid:51)(cid:83)(cid:54)(cid:19)(cid:85)(cid:32)(cid:85)(cid:14)(cid:79)(cid:80)(cid:19)(cid:80)(cid:76)(cid:54)(cid:69)(cid:0)(cid:80)(cid:84)(cid:54)(cid:48)(cid:14)(cid:82)(cid:36)(cid:0)(cid:76)(cid:0)(cid:86)(cid:79)(cid:89)(cid:82)(cid:84)(cid:36)(cid:69)(cid:79)(cid:73)(cid:87)(cid:83)(cid:71)(cid:0)(cid:33)(cid:17)(cid:73)(cid:69)(cid:79)(cid:14)(cid:14)(cid:82)(cid:24)(cid:78)(cid:0)(cid:54) (cid:46)(cid:54)(cid:51)(cid:50)(cid:51)(cid:51)(cid:52) (cid:46)(cid:54)(cid:41)(cid:35) (cid:51)(cid:89)(cid:83)(cid:84)(cid:69)(cid:77) (cid:34)(cid:85)(cid:83)(cid:45)(cid:65)(cid:84)(cid:82)(cid:73)(cid:88)(cid:0) (cid:51)(cid:22)(cid:50)(cid:20)(cid:0)(cid:33)(cid:43)(cid:45)(cid:34)(cid:0) (cid:50)(cid:32)(cid:35)(cid:0)(cid:54)(cid:24)(cid:36)(cid:0)(cid:45)(cid:36)(cid:33)(cid:40)(cid:90) (cid:50)(cid:48)(cid:69)(cid:47)(cid:83)(cid:41)(cid:78)(cid:69)(cid:50)(cid:84)(cid:84) (cid:48)(cid:47)(cid:50)(cid:48)(cid:0)(cid:54)(cid:15)(cid:48)(cid:0)(cid:36)(cid:36)(cid:50) (cid:54)(cid:54)(cid:36)(cid:51)(cid:51)(cid:36)(cid:33)(cid:33) (cid:36)(cid:33)(cid:59)(cid:59)(cid:18)(cid:17)(cid:21)(cid:21)(cid:26)(cid:26)(cid:16)(cid:16)(cid:61)(cid:61) (cid:23)(cid:39)(cid:0)(cid:48)(cid:67)(cid:72)(cid:0)(cid:36)(cid:65)(cid:45)(cid:78)(cid:78)(cid:33)(cid:69)(cid:17)(cid:76)(cid:83) (cid:50)(cid:35)(cid:48)(cid:0)(cid:20)(cid:44)(cid:16)(cid:44)(cid:0)(cid:75)(cid:40)(cid:90) (cid:56)(cid:32)(cid:52)(cid:33)(cid:54)(cid:44)(cid:36)(cid:0)(cid:47)(cid:36)(cid:51)(cid:35) (cid:47)(cid:47)(cid:51)(cid:51)(cid:35)(cid:35)(cid:63)(cid:63)(cid:41)(cid:47)(cid:46)(cid:53)(cid:52) (cid:46)(cid:35)(cid:47)(cid:44)(cid:43)(cid:37) (cid:39)(cid:48)(cid:0)(cid:36)(cid:45)(cid:33)(cid:18) (cid:45)(cid:40)(cid:90) (cid:20)(cid:13)(cid:17)(cid:22)(cid:0)(cid:45)(cid:40)(cid:90) (cid:46)(cid:46)(cid:46)(cid:34)(cid:37)(cid:44)(cid:55)(cid:46)(cid:59)(cid:59)(cid:17)(cid:20)(cid:33)(cid:55)(cid:26)(cid:26)(cid:41)(cid:16)(cid:17)(cid:52)(cid:37)(cid:61)(cid:61) (cid:21)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:38)(cid:78)(cid:51)(cid:69)(cid:45)(cid:76)(cid:83)(cid:35)(cid:0) (cid:65)(cid:88)(cid:0)(cid:29)(cid:0)(cid:20)(cid:24)(cid:15)(cid:23)(cid:18)(cid:0) (cid:50)(cid:35)(cid:67)(cid:79)(cid:69)(cid:76)(cid:79)(cid:78)(cid:83)(cid:67)(cid:84)(cid:69)(cid:82)(cid:75)(cid:79)(cid:84)(cid:0)(cid:76)(cid:6) (cid:48)(cid:48)(cid:40)(cid:38)(cid:35)(cid:35)(cid:35)(cid:35)(cid:44)(cid:44)(cid:44)(cid:44)(cid:43)(cid:43)(cid:43)(cid:43)(cid:17)(cid:18) (cid:0)(cid:51)(cid:73)(cid:78)(cid:41)(cid:84)(cid:55)(cid:65)(cid:84)(cid:69)(cid:78)(cid:82)(cid:32)(cid:36)(cid:70)(cid:68)(cid:65)(cid:66)(cid:39)(cid:67)(cid:54)(cid:89)(cid:69)(cid:34)(cid:33)(cid:52) (cid:54)(cid:34)(cid:33)(cid:52)(cid:29)(cid:17)(cid:14)(cid:24)(cid:0)(cid:54)(cid:0)(cid:84)(cid:79)(cid:0)(cid:19)(cid:14)(cid:22)(cid:0)(cid:54) (cid:46)(cid:44)(cid:0)(cid:8)(cid:79)(cid:82)(cid:0)(cid:46)(cid:65)(cid:33)(cid:83)(cid:36)(cid:0)(cid:33)(cid:54)(cid:38)(cid:9) (cid:34)(cid:26)(cid:0)(cid:38)(cid:77) (cid:56)(cid:52)(cid:33)(cid:44)(cid:0)(cid:19)(cid:18)(cid:75)(cid:40)(cid:90) (cid:47)(cid:47)(cid:51)(cid:51)(cid:35)(cid:35)(cid:19)(cid:19)(cid:18)(cid:18)(cid:63)(cid:63)(cid:41)(cid:47)(cid:46)(cid:53)(cid:52) (cid:36)(cid:59)(cid:23)(cid:26)(cid:16)(cid:61) (cid:51)(cid:36)(cid:41)(cid:47) (cid:33)(cid:40) (cid:33)(cid:50)(cid:55)(cid:52)(cid:53)(cid:35) (cid:34)(cid:65)(cid:82)(cid:69)(cid:67)(cid:75)(cid:71)(cid:85)(cid:80) (cid:52)(cid:33)(cid:33)(cid:44)(cid:45)(cid:33)(cid:50)(cid:48)(cid:45)(cid:37)(cid:50)(cid:15)(cid:51)(cid:13)(cid:50)(cid:37)(cid:35)(cid:52)(cid:35)(cid:47)(cid:15)(cid:46)(cid:36)(cid:0)(cid:47)(cid:53)(cid:52) (cid:35)(cid:45)(cid:36) (cid:34)(cid:65)(cid:67)(cid:75)(cid:85)(cid:80)(cid:0)(cid:73)(cid:78)(cid:84)(cid:69)(cid:82)(cid:70)(cid:65)(cid:67)(cid:69) (cid:35)(cid:43)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:33)(cid:40)(cid:34)(cid:18) (cid:33)(cid:40)(cid:34)(cid:18) (cid:33)(cid:48)(cid:34)(cid:18) (cid:33)(cid:48)(cid:34)(cid:17) (cid:52)(cid:41)(cid:45)(cid:18) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83)(cid:12)(cid:0)(cid:37)(cid:52)(cid:50)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:17)(cid:17)(cid:18)(cid:33)(cid:38) (cid:37)(cid:55)(cid:56)(cid:43)(cid:52)(cid:53)(cid:14)(cid:41)(cid:52)(cid:48) (cid:52)(cid:41)(cid:45)(cid:19) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83)(cid:12)(cid:0)(cid:37)(cid:52)(cid:50)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:48)(cid:33)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:39)(cid:48)(cid:41)(cid:47)(cid:0)(cid:80)(cid:79)(cid:82)(cid:84)(cid:0)(cid:33) (cid:45)(cid:40)(cid:90) (cid:52)(cid:41)(cid:45)(cid:20) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83)(cid:12)(cid:0)(cid:37)(cid:52)(cid:50)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:22)(cid:0) (cid:48)(cid:34)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:39)(cid:48)(cid:41)(cid:47)(cid:0)(cid:80)(cid:79)(cid:82)(cid:84)(cid:0)(cid:34) (cid:20)(cid:15)(cid:19) (cid:52)(cid:41)(cid:45)(cid:21) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:18) (cid:48)(cid:35)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:39)(cid:48)(cid:41)(cid:47)(cid:0)(cid:80)(cid:79)(cid:82)(cid:84)(cid:0)(cid:35) (cid:0)(cid:29)(cid:0)(cid:65)(cid:88) (cid:53)(cid:51)(cid:33)(cid:50)(cid:52)(cid:18) (cid:50)(cid:35)(cid:56)(cid:43)(cid:12)(cid:0)(cid:0)(cid:65)(cid:52)(cid:83)(cid:56)(cid:0)(cid:12)(cid:33)(cid:0)(cid:35)(cid:38)(cid:52)(cid:51)(cid:12)(cid:0)(cid:50)(cid:52)(cid:51)(cid:12) (cid:48)(cid:48)(cid:36)(cid:37)(cid:59)(cid:59)(cid:17)(cid:17)(cid:21)(cid:21)(cid:26)(cid:26)(cid:16)(cid:16)(cid:61)(cid:61) (cid:39)(cid:39)(cid:48)(cid:48)(cid:41)(cid:41)(cid:47)(cid:47)(cid:0)(cid:0)(cid:80)(cid:80)(cid:79)(cid:79)(cid:82)(cid:82)(cid:84)(cid:84)(cid:0)(cid:0)(cid:36)(cid:37) (cid:20)(cid:24)(cid:15)(cid:23)(cid:18)(cid:0)(cid:45)(cid:40)(cid:90) (cid:33)(cid:48)(cid:34)(cid:17)(cid:26)(cid:0)(cid:38)(cid:77) (cid:53)(cid:53)(cid:51)(cid:33)(cid:33)(cid:50)(cid:50)(cid:52)(cid:52)(cid:20)(cid:19) (cid:50)(cid:35)(cid:50)(cid:56)(cid:43)(cid:56)(cid:12)(cid:0)(cid:0)(cid:12)(cid:65)(cid:52)(cid:52)(cid:83)(cid:56)(cid:56)(cid:0)(cid:0)(cid:12)(cid:33)(cid:0)(cid:65)(cid:35)(cid:38)(cid:83)(cid:0)(cid:52)(cid:33)(cid:51)(cid:38)(cid:12)(cid:0)(cid:50)(cid:52)(cid:51)(cid:12) (cid:29)(cid:0) (cid:48)(cid:38)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:39)(cid:48)(cid:41)(cid:47)(cid:0)(cid:80)(cid:79)(cid:82)(cid:84)(cid:0)(cid:38) (cid:65)(cid:88)(cid:0) (cid:53)(cid:33)(cid:50)(cid:52)(cid:21) (cid:50)(cid:56)(cid:12)(cid:52)(cid:56)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:77) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:48)(cid:83)(cid:39)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:39)(cid:48)(cid:41)(cid:47)(cid:0)(cid:80)(cid:79)(cid:82)(cid:84)(cid:0)(cid:39) (cid:34)(cid:18)(cid:26)(cid:0)(cid:38) (cid:18)(cid:88)(cid:8)(cid:51)(cid:24)(cid:48)(cid:88)(cid:73)(cid:17)(cid:41)(cid:84)(cid:18)(cid:9)(cid:22)(cid:0)(cid:15)(cid:66)(cid:0)(cid:41)(cid:18)(cid:51)(cid:18) (cid:45)(cid:51)(cid:35)(cid:47)(cid:43)(cid:51)(cid:15)(cid:41)(cid:35)(cid:15)(cid:51)(cid:43)(cid:36)(cid:12)(cid:0)(cid:12)(cid:45)(cid:0)(cid:45)(cid:35)(cid:41)(cid:43)(cid:51)(cid:12)(cid:47)(cid:0)(cid:46)(cid:51)(cid:0)(cid:51)(cid:15)(cid:55)(cid:51)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:19)(cid:34)(cid:0)(cid:43)(cid:67)(cid:79)(cid:41)(cid:46)(cid:77)(cid:12)(cid:0)(cid:80)(cid:37)(cid:76)(cid:14)(cid:52)(cid:0)(cid:67)(cid:50)(cid:72)(cid:0)(cid:65)(cid:65)(cid:78)(cid:83)(cid:78)(cid:0)(cid:33)(cid:69)(cid:38)(cid:76)(cid:83) (cid:52)(cid:41)(cid:45)(cid:17) (cid:33)(cid:48) (cid:18)(cid:88)(cid:8)(cid:51)(cid:24)(cid:48)(cid:88)(cid:73)(cid:17)(cid:84)(cid:41)(cid:9)(cid:19)(cid:22)(cid:0)(cid:66)(cid:15)(cid:0)(cid:41)(cid:18)(cid:51)(cid:19) (cid:45)(cid:51)(cid:35)(cid:47)(cid:43)(cid:51)(cid:15)(cid:41)(cid:35)(cid:15)(cid:51)(cid:43)(cid:36)(cid:12)(cid:0)(cid:12)(cid:45)(cid:0)(cid:45)(cid:35)(cid:41)(cid:43)(cid:51)(cid:12)(cid:47)(cid:0)(cid:46)(cid:51)(cid:0)(cid:51)(cid:15)(cid:55)(cid:51)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:20)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83) (cid:19)(cid:0)(cid:67)(cid:79)(cid:77)(cid:80)(cid:76)(cid:14)(cid:0)(cid:67)(cid:72)(cid:65)(cid:78)(cid:78)(cid:69)(cid:76)(cid:83) (cid:52)(cid:41)(cid:45)(cid:24) (cid:41)(cid:18)(cid:35)(cid:17) (cid:51)(cid:35)(cid:44)(cid:12)(cid:0)(cid:51)(cid:36)(cid:33)(cid:12)(cid:0)(cid:51)(cid:45)(cid:34)(cid:33)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:34)(cid:43)(cid:41)(cid:46)(cid:12)(cid:0)(cid:37)(cid:52)(cid:50)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:45)(cid:47)(cid:51)(cid:41)(cid:12)(cid:0)(cid:45)(cid:41)(cid:51)(cid:47)(cid:12) (cid:51)(cid:48)(cid:41)(cid:17) (cid:51)(cid:50)(cid:33)(cid:45)(cid:0)(cid:21)(cid:17)(cid:18)(cid:0)(cid:34) (cid:41)(cid:18)(cid:35)(cid:18) (cid:51)(cid:35)(cid:44)(cid:12)(cid:0)(cid:51)(cid:36)(cid:33)(cid:12)(cid:0)(cid:51)(cid:45)(cid:34)(cid:33)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:51)(cid:35)(cid:43)(cid:12)(cid:0)(cid:46)(cid:51)(cid:51)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:50)(cid:56)(cid:12)(cid:0)(cid:52)(cid:56)(cid:12)(cid:0)(cid:35)(cid:52)(cid:51)(cid:12) (cid:53)(cid:51)(cid:33)(cid:50)(cid:52)(cid:17) (cid:55)(cid:55)(cid:36)(cid:39) (cid:66)(cid:88)(cid:35)(cid:33)(cid:46)(cid:0)(cid:68)(cid:69)(cid:86)(cid:73)(cid:67)(cid:69) (cid:50)(cid:52)(cid:51)(cid:12)(cid:0)(cid:35)(cid:43)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:53)(cid:51)(cid:34)(cid:63)(cid:36)(cid:48)(cid:15)(cid:35)(cid:33)(cid:46)(cid:63)(cid:52)(cid:56) (cid:53)(cid:51)(cid:34)(cid:0)(cid:18)(cid:14)(cid:16)(cid:0)(cid:38)(cid:51) (cid:53)(cid:51)(cid:34)(cid:63)(cid:36)(cid:45)(cid:15)(cid:35)(cid:33)(cid:46)(cid:63)(cid:50)(cid:56) (cid:52)(cid:69)(cid:77)(cid:80)(cid:14)(cid:0)(cid:83)(cid:69)(cid:78)(cid:83)(cid:79)(cid:82) (cid:68)(cid:69)(cid:86)(cid:73)(cid:67)(cid:69) (cid:24)(cid:0)(cid:33)(cid:36)(cid:35)(cid:17)(cid:18)(cid:19)(cid:63)(cid:41)(cid:46)(cid:83) (cid:52)(cid:41)(cid:45)(cid:22) (cid:41)(cid:41)(cid:38)(cid:38) (cid:17)(cid:18)(cid:66)(cid:73)(cid:84)(cid:0)(cid:36)(cid:33)(cid:35)(cid:17) (cid:36)(cid:33)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52)(cid:17)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:67)(cid:79)(cid:77)(cid:77)(cid:79)(cid:78)(cid:0)(cid:84)(cid:79)(cid:0)(cid:84)(cid:72)(cid:69)(cid:0)(cid:19)(cid:0)(cid:33)(cid:36)(cid:35)(cid:83) (cid:17)(cid:18)(cid:13)(cid:66)(cid:73)(cid:84)(cid:0)(cid:33)(cid:36)(cid:35)(cid:17) (cid:41)(cid:38) (cid:41)(cid:38) (cid:24)(cid:0)(cid:33)(cid:36)(cid:35)(cid:17)(cid:18)(cid:63)(cid:41)(cid:46)(cid:83)(cid:0)(cid:67)(cid:79)(cid:77)(cid:77)(cid:79)(cid:78) (cid:52)(cid:41)(cid:45)(cid:23) (cid:17)(cid:18)(cid:66)(cid:73)(cid:84)(cid:0)(cid:36)(cid:33)(cid:35)(cid:18) (cid:36)(cid:33)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52)(cid:18)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:84)(cid:79)(cid:0)(cid:33)(cid:36)(cid:35)(cid:17)(cid:0)(cid:6)(cid:0)(cid:33)(cid:36)(cid:35)(cid:18) (cid:17)(cid:18)(cid:13)(cid:66)(cid:73)(cid:84)(cid:0)(cid:33)(cid:36)(cid:35)(cid:18) (cid:41)(cid:38) (cid:21)(cid:0)(cid:33)(cid:36)(cid:35)(cid:19)(cid:63)(cid:41)(cid:46)(cid:83)(cid:0)(cid:79)(cid:78)(cid:0)(cid:33)(cid:36)(cid:35)(cid:19) (cid:17)(cid:18)(cid:13)(cid:66)(cid:73)(cid:84)(cid:0)(cid:33)(cid:36)(cid:35)(cid:19) (cid:41)(cid:38) (cid:32)(cid:54)(cid:36)(cid:36)(cid:33) (cid:54) (cid:54)(cid:50)(cid:37)(cid:38)(cid:110) (cid:32)(cid:0)(cid:54)(cid:36)(cid:36)(cid:33) (cid:50)(cid:37)(cid:38)(cid:11) (cid:65)(cid:73)(cid:17)(cid:20)(cid:22)(cid:22)(cid:22)(cid:71) 1. T = –40 °C to +85 °C (suffix 6, see Table75) or –40 °C to +105 °C (suffix 7, see Table75), junction A temperature up to 105°C or 125 °C, respectively. 2. AF = alternate function on I/O port pin.9 12/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description Figure 2. Clock tree (cid:41)(cid:47)(cid:44)(cid:55)(cid:41)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:83)(cid:85)(cid:82)(cid:74)(cid:85)(cid:68)(cid:80)(cid:80)(cid:76)(cid:81)(cid:74)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72) (cid:56)(cid:54)(cid:37) (cid:23)(cid:27)(cid:3)(cid:48)(cid:43)(cid:93) (cid:56)(cid:54)(cid:37)(cid:38)(cid:47)(cid:46) (cid:51)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85) (cid:87)(cid:82)(cid:3)(cid:56)(cid:54)(cid:37)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72) (cid:18)(cid:20)(cid:15)(cid:3)(cid:20)(cid:17)(cid:24) (cid:44)(cid:21)(cid:54)(cid:22)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:44)(cid:21)(cid:54)(cid:22) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72) (cid:44)(cid:21)(cid:54)(cid:21)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:44)(cid:21)(cid:54)(cid:21) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:54)(cid:39)(cid:44)(cid:50)(cid:38)(cid:47)(cid:46) (cid:27)(cid:3)(cid:48)(cid:43)(cid:93) (cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:87)(cid:82)(cid:3)(cid:54)(cid:39)(cid:44)(cid:50) (cid:43)(cid:54)(cid:44)(cid:3)(cid:53)(cid:38) (cid:43)(cid:54)(cid:44) (cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72) (cid:41)(cid:54)(cid:48)(cid:38)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:41)(cid:54)(cid:48)(cid:38) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:18)(cid:21) (cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72) (cid:43)(cid:38)(cid:47)(cid:46) (cid:26)(cid:21)(cid:3)(cid:48)(cid:43)(cid:93)(cid:3)(cid:80)(cid:68)(cid:91) (cid:87)(cid:82)(cid:3)(cid:36)(cid:43)(cid:37)(cid:3)(cid:69)(cid:88)(cid:86)(cid:15)(cid:3)(cid:70)(cid:82)(cid:85)(cid:72)(cid:15)(cid:3) (cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:39)(cid:48)(cid:36) (cid:40)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:23)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:12) (cid:18)(cid:27) (cid:87)(cid:82)(cid:3)(cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91)(cid:3)(cid:54)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:87)(cid:76)(cid:80)(cid:72)(cid:85) (cid:51)(cid:47)(cid:47)(cid:54)(cid:53)(cid:38) (cid:54)(cid:58) (cid:51)(cid:47)(cid:47)(cid:48)(cid:56)(cid:47) (cid:41)(cid:38)(cid:47)(cid:46)(cid:3)(cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91) (cid:43)(cid:54)(cid:44) (cid:73)(cid:85)(cid:72)(cid:72)(cid:3)(cid:85)(cid:88)(cid:81)(cid:81)(cid:76)(cid:81)(cid:74)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:17)(cid:17)(cid:17)(cid:15)(cid:3)(cid:91)(cid:20)(cid:25) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46) (cid:36)(cid:43)(cid:37) (cid:36)(cid:51)(cid:37)(cid:20) (cid:22)(cid:25)(cid:3)(cid:48)(cid:43)(cid:93)(cid:3)(cid:80)(cid:68)(cid:91) (cid:51)(cid:38)(cid:47)(cid:46)(cid:20) (cid:91)(cid:21)(cid:15)(cid:3)(cid:91)(cid:22)(cid:15)(cid:3)(cid:91)(cid:23)(cid:3) (cid:51)(cid:47)(cid:47)(cid:38)(cid:47)(cid:46) (cid:26)(cid:21)(cid:3)(cid:48)(cid:43)(cid:93) (cid:51)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85) (cid:51)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85) (cid:87)(cid:82)(cid:3)(cid:36)(cid:51)(cid:37)(cid:20) (cid:51)(cid:47)(cid:47) (cid:3)(cid:80)(cid:68)(cid:91) (cid:18)(cid:20)(cid:15)(cid:3)(cid:21)(cid:17)(cid:17)(cid:24)(cid:20)(cid:21) (cid:18)(cid:20)(cid:15)(cid:3)(cid:21)(cid:15)(cid:3)(cid:23)(cid:15)(cid:3)(cid:27)(cid:15)(cid:3)(cid:20)(cid:25) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:43)(cid:54)(cid:40) (cid:40)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:21)(cid:19)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:12) (cid:55)(cid:44)(cid:48)(cid:21)(cid:15)(cid:22)(cid:15)(cid:23)(cid:15)(cid:24)(cid:15)(cid:25)(cid:15)(cid:26) (cid:44)(cid:73)(cid:3)(cid:11)(cid:36)(cid:51)(cid:37)(cid:20)(cid:3)(cid:83)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85)(cid:3)(cid:32)(cid:20)(cid:12)(cid:3)(cid:91)(cid:20) (cid:87)(cid:82)(cid:3)(cid:55)(cid:44)(cid:48)(cid:21)(cid:15)(cid:22)(cid:15)(cid:23)(cid:15)(cid:24)(cid:15)(cid:25)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:26) (cid:38)(cid:54)(cid:54) (cid:72)(cid:79)(cid:86)(cid:72)(cid:3)(cid:91)(cid:21) (cid:55)(cid:44)(cid:48)(cid:59)(cid:38)(cid:47)(cid:46) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3) (cid:40)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:25)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:12) (cid:51)(cid:47)(cid:47)(cid:59)(cid:55)(cid:51)(cid:53)(cid:40) (cid:36)(cid:51)(cid:37)(cid:21) (cid:26)(cid:21)(cid:3)(cid:48)(cid:43)(cid:93)(cid:3)(cid:80)(cid:68)(cid:91) (cid:51)(cid:38)(cid:47)(cid:46)(cid:21) (cid:51)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:18)(cid:20)(cid:15)(cid:3)(cid:21)(cid:15)(cid:3)(cid:23)(cid:15)(cid:3)(cid:27)(cid:15)(cid:3)(cid:20)(cid:25) (cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86)(cid:3)(cid:87)(cid:82)(cid:3)(cid:36)(cid:51)(cid:37)(cid:21) (cid:23)(cid:16)(cid:20)(cid:25)(cid:3)(cid:48)(cid:43)(cid:93) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3) (cid:43)(cid:54)(cid:40)(cid:3)(cid:50)(cid:54)(cid:38) (cid:40)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:20)(cid:24)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:12) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49)(cid:3) (cid:18)(cid:21) (cid:55)(cid:44)(cid:48)(cid:20)(cid:3)(cid:9)(cid:3)(cid:27)(cid:3)(cid:87)(cid:76)(cid:80)(cid:72)(cid:85)(cid:86) (cid:87)(cid:82)(cid:3)(cid:55)(cid:44)(cid:48)(cid:20)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:55)(cid:44)(cid:48)(cid:27)(cid:3) (cid:44)(cid:73)(cid:3)(cid:11)(cid:36)(cid:51)(cid:37)(cid:21)(cid:3)(cid:83)(cid:85)(cid:72)(cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:85)(cid:3)(cid:32)(cid:20)(cid:12)(cid:3)(cid:91)(cid:20) (cid:72)(cid:79)(cid:86)(cid:72)(cid:3)(cid:91)(cid:21) (cid:55)(cid:44)(cid:48)(cid:91)(cid:38)(cid:47)(cid:46) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3) (cid:18)(cid:20)(cid:21)(cid:27) (cid:40)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:11)(cid:21)(cid:3)(cid:69)(cid:76)(cid:87)(cid:12) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:47)(cid:54)(cid:40)(cid:3)(cid:50)(cid:54)(cid:38) (cid:47)(cid:54)(cid:40) (cid:87)(cid:82)(cid:3)(cid:53)(cid:55)(cid:38) (cid:51)(cid:85)(cid:72)(cid:36)(cid:86)(cid:39)(cid:70)(cid:38)(cid:68)(cid:79)(cid:72)(cid:85) (cid:36)(cid:39)(cid:38)(cid:38)(cid:47)(cid:46) (cid:87)(cid:82)(cid:3)(cid:36)(cid:39)(cid:38)(cid:20)(cid:15)(cid:3)(cid:21)(cid:3)(cid:82)(cid:85)(cid:3)(cid:22) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93) (cid:53)(cid:55)(cid:38)(cid:38)(cid:47)(cid:46) (cid:18)(cid:21)(cid:15)(cid:3)(cid:23)(cid:15)(cid:3)(cid:25)(cid:15)(cid:3)(cid:27) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:53)(cid:55)(cid:38)(cid:54)(cid:40)(cid:47)(cid:62)(cid:20)(cid:29)(cid:19)(cid:64)(cid:3) (cid:18)(cid:21) (cid:43)(cid:38)(cid:47)(cid:46)(cid:18)(cid:21) (cid:55)(cid:82)(cid:3)(cid:54)(cid:39)(cid:44)(cid:50)(cid:3)(cid:36)(cid:43)(cid:37)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:47)(cid:54)(cid:44)(cid:3)(cid:53)(cid:38) (cid:47)(cid:54)(cid:44) (cid:87)(cid:82)(cid:3)(cid:44)(cid:81)(cid:71)(cid:72)(cid:83)(cid:72)(cid:81)(cid:71)(cid:72)(cid:81)(cid:87)(cid:3)(cid:58)(cid:68)(cid:87)(cid:70)(cid:75)(cid:71)(cid:82)(cid:74)(cid:3)(cid:11)(cid:44)(cid:58)(cid:39)(cid:42)(cid:12) (cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72) (cid:23)(cid:19)(cid:3)(cid:78)(cid:43)(cid:93) (cid:44)(cid:58)(cid:39)(cid:42)(cid:38)(cid:47)(cid:46) (cid:48)(cid:68)(cid:76)(cid:81) (cid:18)(cid:21) (cid:51)(cid:47)(cid:47)(cid:38)(cid:47)(cid:46) (cid:47)(cid:72)(cid:74)(cid:72)(cid:81)(cid:71)(cid:29) (cid:38)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:50)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87) (cid:43)(cid:54)(cid:40)(cid:3)(cid:32)(cid:3)(cid:43)(cid:76)(cid:74)(cid:75)(cid:3)(cid:54)(cid:83)(cid:72)(cid:72)(cid:71)(cid:3)(cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:74)(cid:81)(cid:68)(cid:79) (cid:48)(cid:38)(cid:50)(cid:3) (cid:43)(cid:54)(cid:44) (cid:43)(cid:54)(cid:44)(cid:3)(cid:32)(cid:3)(cid:43)(cid:76)(cid:74)(cid:75)(cid:3)(cid:54)(cid:83)(cid:72)(cid:72)(cid:71)(cid:3)(cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:74)(cid:81)(cid:68)(cid:79) (cid:43)(cid:54)(cid:40) (cid:47)(cid:54)(cid:44)(cid:3)(cid:32)(cid:3)(cid:47)(cid:82)(cid:90)(cid:3)(cid:54)(cid:83)(cid:72)(cid:72)(cid:71)(cid:3)(cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:74)(cid:81)(cid:68)(cid:79) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46) (cid:47)(cid:54)(cid:40)(cid:3)(cid:32)(cid:3)(cid:47)(cid:82)(cid:90)(cid:3)(cid:54)(cid:83)(cid:72)(cid:72)(cid:71)(cid:3)(cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:74)(cid:81)(cid:68)(cid:79) (cid:48)(cid:38)(cid:50)(cid:3) (cid:68)(cid:76)(cid:20)(cid:23)(cid:26)(cid:24)(cid:21)(cid:69) 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. DS5792 Rev 13 13/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE 2.2 Full compatibility throughout the family The STM32F103xC/D/E is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low-density and high-density devices are an extension of the STM32F103x8/B medium- density devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC while remaining fully compatible with the other members of the family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Medium-density devices High-density devices 32 KB 128 KB 256 KB Pinout 16 KB Flash 64 KB Flash 384 KB Flash 512 KB Flash Flash(1) Flash Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 RAM 64 KB RAM 64 KB RAM 144 5 × USARTs 4 × 16-bit timers, 2 × basic timers 100 3 × USARTs 3 × SPIs, 2 × I2Ss, 2 × I2Cs 3 × 16-bit timers USB, CAN, 2 × PWM timers 64 2 × USARTs 2 × SPIs, 2 × I2Cs, USB, 3 × ADCs, 2 × DACs, 1 × SDIO 2 × 16-bit timers CAN, 1 × PWM timer FSMC (100- and 144-pin packages(2)) 1 × SPI, 1 × I2C, USB, CAN, 2 × ADCs 48 1 × PWM timer 2 × ADCs 36 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. 2. Ports F and G are not available in devices delivered in 100-pin packages. 14/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM The Arm Cortex®-M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The Arm Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. With its embedded Arm core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all Arm tools and software. Figure1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory Up to 512 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 Embedded SRAM Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: • The three FSMC interrupt lines are ORed in order to be connected to the NVIC • Write FIFO • Code execution from external memory except for NAND Flash and PC Card • The targeted frequency, f , is HCLK/2, so external access is at 36 MHz when HCLK CLK is at 72MHz and external access is at 24 MHz when HCLK is at 48 MHz DS5792 Rev 13 15/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost- effective graphic applications using LCD modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.3.7 Nested vectored interrupt controller (NVIC) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure2 for details on the clock tree. 16/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: • Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1. 2.3.11 Power supply schemes • V = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. DD Provided externally through V pins. DD • V , V = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset SSA DDA blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). V and V must be connected to V and V , respectively. DDA SSA DD SS • V = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup BAT registers (through power switch) when V is not present. DD For more details on how to connect power pins, refer to Figure12: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V is below a specified threshold, V , without the need for an DD POR/PDR external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the V /V power supply and compares it to the V threshold. An interrupt can be DD DDA PVD generated when V /V drops below the V threshold and/or when V /V is DD DDA PVD DD DDA higher than the V threshold. The interrupt service routine can then generate a warning PVD message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table12: Embedded reset and power control block characteristics for the values of V and V . POR/PDR PVD 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop modes. • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. DS5792 Rev 13 17/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.14 Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on V supply when present or through the V pin. The backup registers are forty-two 16-bit DD BAT registers used to store 84 bytes of user application data when V power is not present. DD They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a 18/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F103xC/D/E performance line devices include up to two advanced- control timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. High-density timer feature comparison Counter Counter Prescaler DMA request Capture/compare Complementary Timer resolution type factor generation channels outputs Up, Any integer TIM1, 16-bit down, between 1 Yes 4 Yes TIM8 up/down and 65536 TIM2, Up, Any integer TIM3, 16-bit down, between 1 Yes 4 No TIM4, up/down and 65536 TIM5 Any integer TIM6, 16-bit Up between 1 Yes 0 No TIM7 and 65536 DS5792 Rev 13 19/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) • One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one- pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from 20/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source 2.3.18 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48kHz are supported. When either or both of the I2S interfaces is/are configured in master DS5792 Rev 13 21/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1. 2.3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 2.3.24 Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 2.3.25 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current- capable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.26 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold • Single shunt 22/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.27 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference V REF+ Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. DS5792 Rev 13 23/143 135

Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.28 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V < 3.6 V. The temperature sensor is internally DDA connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.29 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.30 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 24/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 3 Pinouts and pin descriptions Figure 3. STM32F103xC/D/E BGA144 ballout 1 2 3 4 5 6 7 8 9 10 11 12 A TAMPPCE1R3--RTC PE3 PE2 PE1 PE0 JTPRBS4T JPTBD3O PD6 PD7 PJATD15I JPTAC1K4 JPTAM1S3 B PC14- PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 OSC32_IN PC15- C OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 NC PA11 D OSC_IN VSS_5 VDD_5 PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E OSC_OUT PF3 PF4 PF5 VSS_3 VSS_11 VSS_10 PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD_4 VDD_3 VDD_11 VDD_10 VDD_8 VDD_2 VDD_9 PC8 PC7 G PF10 PF9 PF8 VSS_4 VDD_6 VDD_7 VDD_1 VSS_8 VSS_2 VSS_9 PG8 PC6 H PC0 PC1 PC2 PC3 VSS_6 VSS_7 VSS_1 PE11 PD11 PG7 PG6 PG5 PB2/ J VSSA PA0-WKUP PA4 PC4 BOOT1 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF– PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 AI14798b 1. The above figure shows the package top view. DS5792 Rev 13 25/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 4. STM32F103xC/D/E performance line BGA100 ballout 1 2 3 4 5 6 7 8 9 10 PC14- PC13- A OSC32_IN TAMPER- PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 RTC PC15- B OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 (cid:1)VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI14601c 1. The above figure shows the package top view. 26/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Figure 5. STM32F103xC/D/E performance line LQFP144 pinout (cid:36)(cid:36)(cid:63)(cid:19)(cid:51)(cid:51)(cid:63)(cid:19)(cid:37)(cid:17)(cid:37)(cid:16)(cid:34)(cid:25)(cid:34)(cid:24)(cid:47)(cid:47)(cid:52)(cid:16)(cid:34)(cid:23)(cid:34)(cid:22)(cid:34)(cid:21)(cid:34)(cid:20)(cid:34)(cid:19)(cid:39)(cid:17)(cid:21) (cid:36)(cid:36)(cid:63)(cid:17)(cid:17)(cid:51)(cid:51)(cid:63)(cid:17)(cid:17)(cid:39)(cid:17)(cid:20)(cid:39)(cid:17)(cid:19)(cid:39)(cid:17)(cid:18)(cid:39)(cid:17)(cid:17)(cid:39)(cid:17)(cid:16)(cid:39)(cid:25)(cid:36)(cid:23)(cid:36)(cid:22) (cid:36)(cid:36)(cid:63)(cid:17)(cid:16)(cid:51)(cid:51)(cid:63)(cid:17)(cid:16)(cid:36)(cid:21)(cid:36)(cid:20)(cid:36)(cid:19)(cid:36)(cid:18)(cid:36)(cid:17)(cid:36)(cid:16)(cid:35)(cid:17)(cid:18)(cid:35)(cid:17)(cid:17)(cid:35)(cid:17)(cid:16)(cid:33)(cid:17)(cid:21)(cid:33)(cid:17)(cid:20) (cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:34)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48) (cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25)(cid:24)(cid:23)(cid:22)(cid:21)(cid:20)(cid:19)(cid:18)(cid:17)(cid:16)(cid:25) (cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:18)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:16) (cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17) (cid:48)(cid:37)(cid:18) (cid:17) (cid:17)(cid:16)(cid:24) (cid:54) (cid:36)(cid:36)(cid:63)(cid:18) (cid:48)(cid:37)(cid:19) (cid:18) (cid:17)(cid:16)(cid:23) (cid:54) (cid:51)(cid:51)(cid:63)(cid:18) (cid:48)(cid:37)(cid:20) (cid:19) (cid:17)(cid:16)(cid:22) (cid:46)(cid:35) (cid:48)(cid:37)(cid:21) (cid:20) (cid:17)(cid:16)(cid:21) (cid:48)(cid:33)(cid:17)(cid:19) (cid:48)(cid:37)(cid:22) (cid:21) (cid:17)(cid:16)(cid:20) (cid:48)(cid:33)(cid:17)(cid:18) (cid:54)(cid:34)(cid:33)(cid:52) (cid:22) (cid:17)(cid:16)(cid:19) (cid:48)(cid:33)(cid:17)(cid:17) (cid:48)(cid:35)(cid:17)(cid:19)(cid:13)(cid:52)(cid:33)(cid:45)(cid:48)(cid:37)(cid:50)(cid:13)(cid:50)(cid:52)(cid:35) (cid:23) (cid:17)(cid:16)(cid:18) (cid:48)(cid:33)(cid:17)(cid:16) (cid:48)(cid:35)(cid:17)(cid:20)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:41)(cid:46) (cid:24) (cid:17)(cid:16)(cid:17) (cid:48)(cid:33)(cid:25) (cid:48)(cid:35)(cid:17)(cid:21)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:47)(cid:53)(cid:52) (cid:25) (cid:17)(cid:16)(cid:16) (cid:48)(cid:33)(cid:24) (cid:48)(cid:38)(cid:16) (cid:17)(cid:16) (cid:25)(cid:25) (cid:48)(cid:35)(cid:25) (cid:48)(cid:38)(cid:17) (cid:17)(cid:17) (cid:25)(cid:24) (cid:48)(cid:35)(cid:24) (cid:48)(cid:38)(cid:18) (cid:17)(cid:18) (cid:25)(cid:23) (cid:48)(cid:35)(cid:23) (cid:48)(cid:38)(cid:19) (cid:17)(cid:19) (cid:25)(cid:22) (cid:48)(cid:35)(cid:22) (cid:48)(cid:38)(cid:20) (cid:17)(cid:20) (cid:25)(cid:21) (cid:54) (cid:36)(cid:36)(cid:63)(cid:25) (cid:48)(cid:38)(cid:21) (cid:17)(cid:21) (cid:25)(cid:20) (cid:54) (cid:51)(cid:51)(cid:63)(cid:25) (cid:54)(cid:51)(cid:51)(cid:63)(cid:21) (cid:17)(cid:22) (cid:44)(cid:49)(cid:38)(cid:48)(cid:17)(cid:20)(cid:20) (cid:25)(cid:19) (cid:48)(cid:39)(cid:24) (cid:54)(cid:36)(cid:36)(cid:63)(cid:21) (cid:17)(cid:23) (cid:25)(cid:18) (cid:48)(cid:39)(cid:23) (cid:48)(cid:38)(cid:22) (cid:17)(cid:24) (cid:25)(cid:17) (cid:48)(cid:39)(cid:22) (cid:48)(cid:38)(cid:23) (cid:17)(cid:25) (cid:25)(cid:16) (cid:48)(cid:39)(cid:21) (cid:48)(cid:38)(cid:24) (cid:18)(cid:16) (cid:24)(cid:25) (cid:48)(cid:39)(cid:20) (cid:48)(cid:38)(cid:25) (cid:18)(cid:17) (cid:24)(cid:24) (cid:48)(cid:39)(cid:19) (cid:48)(cid:38)(cid:17)(cid:16) (cid:18)(cid:18) (cid:24)(cid:23) (cid:48)(cid:39)(cid:18) (cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46) (cid:18)(cid:19) (cid:24)(cid:22) (cid:48)(cid:36)(cid:17)(cid:21) (cid:47)(cid:51)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52) (cid:18)(cid:20) (cid:24)(cid:21) (cid:48)(cid:36)(cid:17)(cid:20) (cid:46)(cid:50)(cid:51)(cid:52) (cid:18)(cid:21) (cid:24)(cid:20) (cid:54) (cid:36)(cid:36)(cid:63)(cid:24) (cid:48)(cid:35)(cid:16) (cid:18)(cid:22) (cid:24)(cid:19) (cid:54) (cid:51)(cid:51)(cid:63)(cid:24) (cid:48)(cid:35)(cid:17) (cid:18)(cid:23) (cid:24)(cid:18) (cid:48)(cid:36)(cid:17)(cid:19) (cid:48)(cid:35)(cid:18) (cid:18)(cid:24) (cid:24)(cid:17) (cid:48)(cid:36)(cid:17)(cid:18) (cid:48)(cid:35)(cid:19) (cid:18)(cid:25) (cid:24)(cid:16) (cid:48)(cid:36)(cid:17)(cid:17) (cid:54)(cid:51)(cid:51)(cid:33) (cid:19)(cid:16) (cid:23)(cid:25) (cid:48)(cid:36)(cid:17)(cid:16) (cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:19)(cid:17) (cid:23)(cid:24) (cid:48)(cid:36)(cid:25) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:19)(cid:18) (cid:23)(cid:23) (cid:48)(cid:36)(cid:24) (cid:54)(cid:36)(cid:36)(cid:33) (cid:19)(cid:19) (cid:23)(cid:22) (cid:48)(cid:34)(cid:17)(cid:21) (cid:48)(cid:33)(cid:16)(cid:13)(cid:55)(cid:43)(cid:53)(cid:48) (cid:19)(cid:20) (cid:23)(cid:21) (cid:48)(cid:34)(cid:17)(cid:20) (cid:48)(cid:33)(cid:17) (cid:19)(cid:21) (cid:23)(cid:20) (cid:48)(cid:34)(cid:17)(cid:19) (cid:48)(cid:33)(cid:18) (cid:19)(cid:22) (cid:23)(cid:19) (cid:48)(cid:34)(cid:17)(cid:18) (cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18) (cid:19)(cid:19)(cid:19)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:21)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:22)(cid:23)(cid:23)(cid:23) (cid:19) (cid:20)(cid:21)(cid:22)(cid:23)(cid:20)(cid:21)(cid:16)(cid:17)(cid:18)(cid:17)(cid:18) (cid:19)(cid:20)(cid:21)(cid:16)(cid:17)(cid:23)(cid:24)(cid:25) (cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:16)(cid:17) (cid:48)(cid:33) (cid:51)(cid:51)(cid:63)(cid:20)(cid:36)(cid:36)(cid:63)(cid:20)(cid:48)(cid:33)(cid:48)(cid:33)(cid:48)(cid:33)(cid:48)(cid:33)(cid:48)(cid:35)(cid:48)(cid:35)(cid:48)(cid:34)(cid:48)(cid:34)(cid:48)(cid:34)(cid:48)(cid:38)(cid:17)(cid:48)(cid:38)(cid:17) (cid:51)(cid:51)(cid:63)(cid:22)(cid:36)(cid:36)(cid:63)(cid:22)(cid:48)(cid:38)(cid:17)(cid:48)(cid:38)(cid:17)(cid:48)(cid:38)(cid:17)(cid:48)(cid:39)(cid:48)(cid:39)(cid:48)(cid:37)(cid:48)(cid:37)(cid:48)(cid:37) (cid:51)(cid:51)(cid:63)(cid:23)(cid:36)(cid:36)(cid:63)(cid:23)(cid:48)(cid:37)(cid:17)(cid:48)(cid:37)(cid:17)(cid:48)(cid:37)(cid:17)(cid:48)(cid:37)(cid:17)(cid:48)(cid:37)(cid:17)(cid:48)(cid:37)(cid:17)(cid:48)(cid:34)(cid:17)(cid:48)(cid:34)(cid:17) (cid:51)(cid:51)(cid:63)(cid:17)(cid:36)(cid:36)(cid:63)(cid:17) (cid:54)(cid:54) (cid:54)(cid:54) (cid:54)(cid:54) (cid:54)(cid:54) (cid:65)(cid:73)(cid:17)(cid:20)(cid:22)(cid:22)(cid:23) 1. The above figure shows the package top view. DS5792 Rev 13 27/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 6. STM32F103xC/D/E performance line LQFP100 pinout (cid:36)(cid:36)(cid:63)(cid:19)(cid:0)(cid:0)(cid:51)(cid:51)(cid:63)(cid:19)(cid:0)(cid:0)(cid:37)(cid:17)(cid:0)(cid:0)(cid:37)(cid:16)(cid:0)(cid:0)(cid:34)(cid:25)(cid:0)(cid:0)(cid:34)(cid:24)(cid:0)(cid:0)(cid:47)(cid:47)(cid:52)(cid:16)(cid:0)(cid:0)(cid:34)(cid:23)(cid:0)(cid:0)(cid:34)(cid:22)(cid:0)(cid:0)(cid:34)(cid:21)(cid:0)(cid:0)(cid:34)(cid:20)(cid:0)(cid:0)(cid:34)(cid:19)(cid:0)(cid:0)(cid:36)(cid:23)(cid:0)(cid:0)(cid:36)(cid:22)(cid:0)(cid:0)(cid:36)(cid:21)(cid:0)(cid:0)(cid:36)(cid:20)(cid:0)(cid:0)(cid:36)(cid:19)(cid:0)(cid:0)(cid:36)(cid:18)(cid:0)(cid:0)(cid:36)(cid:17)(cid:0)(cid:0)(cid:36)(cid:16)(cid:0)(cid:0)(cid:35)(cid:17)(cid:18)(cid:0)(cid:0)(cid:35)(cid:17)(cid:17)(cid:0)(cid:0)(cid:35)(cid:17)(cid:16)(cid:0)(cid:0)(cid:33)(cid:17)(cid:21)(cid:0)(cid:0)(cid:33)(cid:17)(cid:20)(cid:0) (cid:54)(cid:54)(cid:48)(cid:48)(cid:48)(cid:48)(cid:34)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48) (cid:17)(cid:16)(cid:16)(cid:25)(cid:25)(cid:25)(cid:24)(cid:25)(cid:23)(cid:25)(cid:22)(cid:25)(cid:21)(cid:25)(cid:20)(cid:25)(cid:19)(cid:25)(cid:18)(cid:25)(cid:17)(cid:25)(cid:16)(cid:24)(cid:25)(cid:24)(cid:24)(cid:24)(cid:23)(cid:24)(cid:22)(cid:24)(cid:21)(cid:24)(cid:20)(cid:24)(cid:19)(cid:24)(cid:18)(cid:24)(cid:17)(cid:24)(cid:16)(cid:23)(cid:25)(cid:23)(cid:24)(cid:23)(cid:23)(cid:23)(cid:22) (cid:48)(cid:37)(cid:18) (cid:17) (cid:23)(cid:21) (cid:54)(cid:36)(cid:36)(cid:63)(cid:18)(cid:0) (cid:48)(cid:37)(cid:19) (cid:18) (cid:23)(cid:20) (cid:54)(cid:51)(cid:51)(cid:63)(cid:18)(cid:0)(cid:0) (cid:48)(cid:37)(cid:20) (cid:19) (cid:23)(cid:19) (cid:46)(cid:35)(cid:0)(cid:0) (cid:48)(cid:37)(cid:21) (cid:20) (cid:23)(cid:18) (cid:48)(cid:33)(cid:0)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:37)(cid:22) (cid:21) (cid:23)(cid:17) (cid:48)(cid:33)(cid:0)(cid:17)(cid:18)(cid:0)(cid:0) (cid:54)(cid:34)(cid:33)(cid:52) (cid:22) (cid:23)(cid:16) (cid:48)(cid:33)(cid:0)(cid:17)(cid:17)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17)(cid:19)(cid:13)(cid:52)(cid:33)(cid:45)(cid:48)(cid:37)(cid:50)(cid:13)(cid:50)(cid:52)(cid:35) (cid:23) (cid:22)(cid:25) (cid:48)(cid:33)(cid:0)(cid:17)(cid:16)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17)(cid:20)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:41)(cid:46) (cid:24) (cid:22)(cid:24) (cid:48)(cid:33)(cid:0)(cid:25)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17)(cid:21)(cid:13)(cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:47)(cid:53)(cid:52) (cid:25) (cid:22)(cid:23) (cid:48)(cid:33)(cid:0)(cid:24)(cid:0)(cid:0) (cid:54)(cid:51)(cid:51)(cid:63)(cid:21) (cid:17)(cid:16) (cid:22)(cid:22) (cid:48)(cid:35)(cid:25)(cid:0)(cid:0) (cid:54)(cid:36)(cid:36)(cid:63)(cid:21) (cid:17)(cid:17) (cid:22)(cid:21) (cid:48)(cid:35)(cid:24)(cid:0)(cid:0) (cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46) (cid:17)(cid:18) (cid:22)(cid:20) (cid:48)(cid:35)(cid:23)(cid:0)(cid:0) (cid:47)(cid:51)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52) (cid:17)(cid:19) (cid:44)(cid:49)(cid:38)(cid:48)(cid:17)(cid:16)(cid:16) (cid:22)(cid:19) (cid:48)(cid:35)(cid:22)(cid:0)(cid:0) (cid:46)(cid:50)(cid:51)(cid:52) (cid:17)(cid:20) (cid:22)(cid:18) (cid:48)(cid:36)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:35)(cid:16) (cid:17)(cid:21) (cid:22)(cid:17) (cid:48)(cid:36)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:35)(cid:17) (cid:17)(cid:22) (cid:22)(cid:16) (cid:48)(cid:36)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:35)(cid:18) (cid:17)(cid:23) (cid:21)(cid:25) (cid:48)(cid:36)(cid:17)(cid:18)(cid:0)(cid:0) (cid:48)(cid:35)(cid:19) (cid:17)(cid:24) (cid:21)(cid:24) (cid:48)(cid:36)(cid:17)(cid:17)(cid:0)(cid:0) (cid:54)(cid:51)(cid:51)(cid:33) (cid:17)(cid:25) (cid:21)(cid:23) (cid:48)(cid:36)(cid:17)(cid:16)(cid:0)(cid:0) (cid:54)(cid:50)(cid:37)(cid:38)(cid:13) (cid:18)(cid:16) (cid:21)(cid:22) (cid:48)(cid:36)(cid:25)(cid:0)(cid:0) (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:18)(cid:17) (cid:21)(cid:21) (cid:48)(cid:36)(cid:24)(cid:0)(cid:0) (cid:54)(cid:36)(cid:36)(cid:33) (cid:18)(cid:18) (cid:21)(cid:20) (cid:48)(cid:34)(cid:17)(cid:21)(cid:0)(cid:0) (cid:48)(cid:33)(cid:16)(cid:13)(cid:55)(cid:43)(cid:53)(cid:48) (cid:18)(cid:19) (cid:21)(cid:19) (cid:48)(cid:34)(cid:17)(cid:20)(cid:0)(cid:0) (cid:48)(cid:33)(cid:17) (cid:18)(cid:20) (cid:21)(cid:18) (cid:48)(cid:34)(cid:17)(cid:19)(cid:0)(cid:0) (cid:48)(cid:33)(cid:18) (cid:18)(cid:21) (cid:21)(cid:17) (cid:48)(cid:34)(cid:17)(cid:18)(cid:0)(cid:0) (cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:16) (cid:18)(cid:18)(cid:18)(cid:18)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:20)(cid:21) (cid:19)(cid:20)(cid:20)(cid:20)(cid:21)(cid:22)(cid:23)(cid:20)(cid:21)(cid:16)(cid:17)(cid:18)(cid:23)(cid:24)(cid:25)(cid:16)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:16)(cid:17)(cid:17)(cid:17) (cid:33)(cid:63)(cid:63)(cid:33)(cid:33)(cid:33)(cid:33)(cid:35)(cid:35)(cid:34)(cid:34)(cid:34)(cid:37)(cid:37)(cid:37)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:17)(cid:63)(cid:63) (cid:48)(cid:51)(cid:36)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:37)(cid:34)(cid:34)(cid:51)(cid:36) (cid:51)(cid:36) (cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:48)(cid:51)(cid:36) (cid:54)(cid:54) (cid:54)(cid:54) (cid:65)(cid:73)(cid:17)(cid:20)(cid:19)(cid:25)(cid:17) 1. The above figure shows the package top view. 28/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Figure 7. STM32F103xC/D/E performance line LQFP64 pinout (cid:1004)(cid:3)(cid:3)(cid:3)(cid:3) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1007)(cid:115)(cid:94)(cid:94)(cid:890)(cid:1007) (cid:87)(cid:17)(cid:1013)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:17)(cid:1012)(cid:3)(cid:3)(cid:3)(cid:3)(cid:17)(cid:75)(cid:75)(cid:100)(cid:87)(cid:17)(cid:1011)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:17)(cid:1010)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:17)(cid:1009)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:17)(cid:1008)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:17)(cid:1007)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:24)(cid:1006)(cid:3)(cid:3)(cid:3)(cid:3)(cid:87)(cid:18)(cid:1005)(cid:1006)(cid:87)(cid:18)(cid:1005)(cid:1005)(cid:87)(cid:18)(cid:1005)(cid:1004)(cid:87)(cid:4)(cid:1005)(cid:1009)(cid:87)(cid:4)(cid:1005)(cid:1008) (cid:1010)(cid:1008)(cid:1010)(cid:1007)(cid:1010)(cid:1006)(cid:1010)(cid:1005)(cid:1010)(cid:1004)(cid:1009)(cid:1013)(cid:1009)(cid:1012)(cid:1009)(cid:1011)(cid:1009)(cid:1010)(cid:1009)(cid:1009)(cid:1009)(cid:1008)(cid:1009)(cid:1007)(cid:1009)(cid:1006)(cid:1009)(cid:1005)(cid:1009)(cid:1004)(cid:1008)(cid:1013) (cid:115)(cid:17)(cid:4)(cid:100) (cid:1005) (cid:1008)(cid:1012) (cid:115)(cid:24)(cid:24)(cid:890)(cid:1006) (cid:87)(cid:18)(cid:1005)(cid:1007)(cid:882)(cid:100)(cid:4)(cid:68)(cid:87)(cid:28)(cid:90)(cid:882)(cid:90)(cid:100)(cid:18) (cid:1006) (cid:1008)(cid:1011) (cid:115)(cid:94)(cid:94)(cid:890)(cid:1006) (cid:87)(cid:18)(cid:1005)(cid:1008)(cid:882)(cid:75)(cid:94)(cid:18) (cid:1007)(cid:1006)(cid:890)(cid:47)(cid:69) (cid:1007) (cid:1008)(cid:1010) (cid:87)(cid:4)(cid:1005)(cid:1007) (cid:87)(cid:18)(cid:1005)(cid:1009)(cid:882)(cid:75)(cid:94)(cid:18) (cid:1007)(cid:1006)(cid:890)(cid:75)(cid:104)(cid:100) (cid:1008) (cid:1008)(cid:1009) (cid:87)(cid:4)(cid:1005)(cid:1006) (cid:87)(cid:24)(cid:1004)(cid:882)(cid:75)(cid:94)(cid:18)(cid:890)(cid:47)(cid:69) (cid:1009) (cid:1008)(cid:1008) (cid:87)(cid:4)(cid:1005)(cid:1005) (cid:87)(cid:24)(cid:1005)(cid:882)(cid:75)(cid:94)(cid:18)(cid:890)(cid:75)(cid:104)(cid:100) (cid:1010)(cid:3)(cid:3) (cid:1008)(cid:1007) (cid:87)(cid:4)(cid:1005)(cid:1004) (cid:69)(cid:90)(cid:94)(cid:100) (cid:1011)(cid:3)(cid:3) (cid:1008)(cid:1006) (cid:87)(cid:4)(cid:1013) (cid:87)(cid:18)(cid:1004) (cid:1012)(cid:3)(cid:3) (cid:1008)(cid:1005) (cid:87)(cid:4)(cid:1012) (cid:87)(cid:18)(cid:1005) (cid:1013)(cid:3)(cid:3) (cid:62)(cid:89)(cid:38)(cid:87)(cid:1010)(cid:1008) (cid:1008)(cid:1004) (cid:87)(cid:18)(cid:1013) (cid:87)(cid:18)(cid:1006) (cid:1005)(cid:1004) (cid:1007)(cid:1013) (cid:87)(cid:18)(cid:1012) (cid:87)(cid:18)(cid:1007) (cid:1005)(cid:1005) (cid:1007)(cid:1012) (cid:87)(cid:18)(cid:1011) (cid:115)(cid:94)(cid:94)(cid:4) (cid:1005)(cid:1006) (cid:1007)(cid:1011) (cid:87)(cid:18)(cid:1010) (cid:115)(cid:24)(cid:24)(cid:4) (cid:1005)(cid:1007) (cid:1007)(cid:1010) (cid:87)(cid:17)(cid:1005)(cid:1009) (cid:87)(cid:4)(cid:1004)(cid:882)(cid:116)(cid:60)(cid:104)(cid:87) (cid:1005)(cid:1008) (cid:1007)(cid:1009) (cid:87)(cid:17)(cid:1005)(cid:1008) (cid:87)(cid:4)(cid:1005) (cid:1005)(cid:1009) (cid:1007)(cid:1008) (cid:87)(cid:17)(cid:1005)(cid:1007) (cid:87)(cid:4)(cid:1006) (cid:1005)(cid:1010) (cid:1007)(cid:1007) (cid:87)(cid:17)(cid:1005)(cid:1006) (cid:1005)(cid:1011)(cid:1005)(cid:1012)(cid:1005)(cid:1013)(cid:1006)(cid:1004)(cid:1006)(cid:1005)(cid:1006)(cid:1006)(cid:1006)(cid:1007)(cid:1006)(cid:1008)(cid:1006)(cid:1009)(cid:1006)(cid:1010)(cid:1006)(cid:1011)(cid:1006)(cid:1012)(cid:1006)(cid:1013)(cid:1007)(cid:1004)(cid:1007)(cid:1005)(cid:1007)(cid:1006) (cid:87)(cid:4)(cid:1007)(cid:115)(cid:94)(cid:94)(cid:890)(cid:1008)(cid:115)(cid:24)(cid:24)(cid:890)(cid:1008)(cid:87)(cid:4)(cid:1008)(cid:87)(cid:4)(cid:1009)(cid:87)(cid:4)(cid:1010)(cid:87)(cid:4)(cid:1011)(cid:87)(cid:18)(cid:1008)(cid:87)(cid:18)(cid:1009)(cid:87)(cid:17)(cid:1004)(cid:87)(cid:17)(cid:1005)(cid:87)(cid:17)(cid:1006)(cid:87)(cid:17)(cid:1005)(cid:1004)(cid:87)(cid:17)(cid:1005)(cid:1005)(cid:115)(cid:94)(cid:94)(cid:890)(cid:1005)(cid:115)(cid:24)(cid:24)(cid:890)(cid:1005) (cid:68)(cid:76)(cid:20)(cid:23)(cid:22)(cid:28)(cid:21) 1. The above figure shows the package top view. DS5792 Rev 13 29/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side 8 7 6 5 4 3 2 1 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BVYSPSA_2SS/ C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 D OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9 E PC0 VSSA PA1 PA5 PA8 PC8 PC7 PC6 F PC1 VREF+ PWAK0U-P VSS_4 PB1 PB11 PB14 PB15 G VDDA PA3 VDD_4 PA6 PA7 PB10 PB12 PB13 H PA2 PA4 PC4 PC5 PB0 PB2 VSS_1 VDD_1 ai15460b 30/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions Pins Alternate functions(4) 2) GA144 GA100 CSP64 FP64 FP100 FP144 Pin name (1)Type (O Level (fauftneMcrta irioenns (e3t)) Default Remap FB FB WL LQ LQ LQ I / L L A3 A3 - - 1 1 PE2 I/O FT PE2 TRACECK/ FSMC_A23 - A2 B3 - - 2 2 PE3 I/O FT PE3 TRACED0/FSMC_A19 - B2 C3 - - 3 3 PE4 I/O FT PE4 TRACED1/FSMC_A20 - B3 D3 - - 4 4 PE5 I/O FT PE5 TRACED2/FSMC_A21 - B4 E3 - - 5 5 PE6 I/O FT PE6 TRACED3/FSMC_A22 - C2 B2 C6 1 6 6 V S - V - - BAT BAT PC13-TAMPER- A1 A2 C8 2 7 7 I/O - PC13(6) TAMPER-RTC - RTC(5) PC14- B1 A1 B8 3 8 8 I/O - PC14(6) OSC32_IN - OSC32_IN(5) PC15- C1 B1 B7 4 9 9 I/O - PC15(6) OSC32_OUT - OSC32_OUT(5) C3 - - - - 10 PF0 I/O FT PF0 FSMC_A0 - C4 - - - - 11 PF1 I/O FT PF1 FSMC_A1 - D4 - - - - 12 PF2 I/O FT PF2 FSMC_A2 - E2 - - - - 13 PF3 I/O FT PF3 FSMC_A3 - E3 - - - - 14 PF4 I/O FT PF4 FSMC_A4 - E4 - - - - 15 PF5 I/O FT PF5 FSMC_A5 - D2 C2 - - 10 16 V S - V - - SS_5 SS_5 D3 D2 - - 11 17 V S - V - - DD_5 DD_5 F3 - - - - 18 PF6 I/O - PF6 ADC3_IN4/FSMC_NIORD - F2 - - - - 19 PF7 I/O - PF7 ADC3_IN5/FSMC_NREG - G3 - - - - 20 PF8 I/O - PF8 ADC3_IN6/FSMC_NIOWR - G2 - - - - 21 PF9 I/O - PF9 ADC3_IN7/FSMC_CD - G1 - - - - 22 PF10 I/O - PF10 ADC3_IN8/FSMC_INTR - D1 C1 D8 5 12 23 OSC_IN I - OSC_IN - - E1 D1 D7 6 13 24 OSC_OUT O - OSC_OUT - - F1 E1 C7 7 14 25 NRST I/O - NRST - - H1 F1 E8 8 15 26 PC0 I/O - PC0 ADC123_IN10 - H2 F2 F8 9 16 27 PC1 I/O - PC1 ADC123_IN11 - H3 E2 D6 10 17 28 PC2 I/O - PC2 ADC123_IN12 - DS5792 Rev 13 31/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Pins Alternate functions(4) 2) FBGA144 FBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name (1)Type (I / O Level (fauftneMcrta irioenns (e3t)) Default Remap L L H4 F3 - 11 18 29 PC3(7) I/O - PC3 ADC123_IN13 - J1 G1 E7 12 19 30 V S - V - - SSA SSA K1 H1 - - 20 31 V S - V - - REF- REF- F7 L1 J1 - 21 32 V S - V - - (8) REF+ REF+ M1 K1 G8 13 22 33 V S - V - - DDA DDA WKUP/USART2_CTS(9) ADC123_IN0 J2 G2 F6 14 23 34 PA0-WKUP I/O - PA0 - TIM2_CH1_ETR TIM5_CH1/TIM8_ETR USART2_RTS(9) K2 H2 E6 15 24 35 PA1 I/O - PA1 ADC123_IN1/ - TIM5_CH2/TIM2_CH2(9) USART2_TX(9)/TIM5_CH3 L2 J2 H8 16 25 36 PA2 I/O - PA2 ADC123_IN2/ - TIM2_CH3 (9) USART2_RX(9)/TIM5_CH4 M2 K2 G7 17 26 37 PA3 I/O - PA3 - ADC123_IN3/TIM2_CH4(9) G4 E4 F5 18 27 38 V S - V - - SS_4 SS_4 F4 F4 G6 19 28 39 V S - V - - DD_4 DD_4 SPI1_NSS(9)/ J3 G3 H7 20 29 40 PA4 I/O - PA4 USART2_CK(9) - DAC_OUT1/ADC12_IN4 SPI1_SCK(9) K3 H3 E5 21 30 41 PA5 I/O - PA5 - DAC_OUT2 ADC12_IN5 SPI1_MISO(9) L3 J3 G5 22 31 42 PA6 I/O - PA6 TIM8_BKIN/ADC12_IN6 TIM1_BKIN TIM3_CH1(9) SPI1_MOSI(9)/ M3 K3 G4 23 32 43 PA7 I/O - PA7 TIM8_CH1N/ADC12_IN7 TIM1_CH1N TIM3_CH2(9) J4 G4 H6 24 33 44 PC4 I/O - PC4 ADC12_IN14 - K4 H4 H5 25 34 45 PC5 I/O - PC5 ADC12_IN15 - ADC12_IN8/TIM3_CH3 L4 J4 H4 26 35 46 PB0 I/O - PB0 TIM1_CH2N TIM8_CH2N ADC12_IN9/TIM3_CH4(9) M4 K4 F4 27 36 47 PB1 I/O - PB1 TIM1_CH3N TIM8_CH3N 32/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions (continued) Pins Alternate functions(4) 2) FBGA144 FBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name (1)Type (I / O Level (fauftneMcrta irioenns (e3t)) Default Remap L L J5 G5 H3 28 37 48 PB2 I/O FT PB2/BOOT1 - - M5 - - - - 49 PF11 I/O FT PF11 FSMC_NIOS16 - L5 - - - - 50 PF12 I/O FT PF12 FSMC_A6 - H5 - - - - 51 V S - V - - SS_6 SS_6 G5 - - - - 52 V S - V - - DD_6 DD_6 K5 - - - - 53 PF13 I/O FT PF13 FSMC_A7 - M6 - - - - 54 PF14 I/O FT PF14 FSMC_A8 - L6 - - - - 55 PF15 I/O FT PF15 FSMC_A9 - K6 - - - - 56 PG0 I/O FT PG0 FSMC_A10 - J6 - - - - 57 PG1 I/O FT PG1 FSMC_A11 - M7 H5 - - 38 58 PE7 I/O FT PE7 FSMC_D4 TIM1_ETR L7 J5 - - 39 59 PE8 I/O FT PE8 FSMC_D5 TIM1_CH1N K7 K5 - - 40 60 PE9 I/O FT PE9 FSMC_D6 TIM1_CH1 H6 - - - - 61 V S - V - - SS_7 SS_7 G6 - - - - 62 V S - V - - DD_7 DD_7 J7 G6 - - 41 63 PE10 I/O FT PE10 FSMC_D7 TIM1_CH2N H8 H6 - - 42 64 PE11 I/O FT PE11 FSMC_D8 TIM1_CH2 J8 J6 - - 43 65 PE12 I/O FT PE12 FSMC_D9 TIM1_CH3N K8 K6 - - 44 66 PE13 I/O FT PE13 FSMC_D10 TIM1_CH3 L8 G7 - - 45 67 PE14 I/O FT PE14 FSMC_D11 TIM1_CH4 M8 H7 - - 46 68 PE15 I/O FT PE15 FSMC_D12 TIM1_BKIN M9 J7 G3 29 47 69 PB10 I/O FT PB10 I2C2_SCL/USART3_TX(9) TIM2_CH3 M10 K7 F3 30 48 70 PB11 I/O FT PB11 I2C2_SDA/USART3_RX(9) TIM2_CH4 H7 E7 H2 31 49 71 V S - V - - SS_1 SS_1 G7 F7 H1 32 50 72 V S - V - - DD_1 DD_1 SPI2_NSS/I2S2_WS/ I2C2_SMBA/ M11 K8 G2 33 51 73 PB12 I/O FT PB12 - USART3_CK(9)/ TIM1_BKIN(9) SPI2_SCK/I2S2_CK M12 J8 G1 34 52 74 PB13 I/O FT PB13 USART3_CTS(9)/ - TIM1_CH1N DS5792 Rev 13 33/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Pins Alternate functions(4) 2) FBGA144 FBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name (1)Type (I / O Level (fauftneMcrta irioenns (e3t)) Default Remap L L SPI2_MISO/TIM1_CH2N L11 H8 F2 35 53 75 PB14 I/O FT PB14 - USART3_RTS(9)/ SPI2_MOSI/I2S2_SD L12 G8 F1 36 54 76 PB15 I/O FT PB15 - TIM1_CH3N(9)/ L9 K9 - - 55 77 PD8 I/O FT PD8 FSMC_D13 USART3_TX K9 J9 - - 56 78 PD9 I/O FT PD9 FSMC_D14 USART3_RX J9 H9 - - 57 79 PD10 I/O FT PD10 FSMC_D15 USART3_CK H9 G9 - - 58 80 PD11 I/O FT PD11 FSMC_A16 USART3_CTS TIM4_CH1 / L10 K10 - - 59 81 PD12 I/O FT PD12 FSMC_A17 USART3_RTS K10 J10 - - 60 82 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 G8 - - - - 83 V S - V - - SS_8 SS_8 F8 - - - - 84 V S - V - - DD_8 DD_8 K11 H10 - - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 K12 G10 - - 62 86 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 J12 - - - - 87 PG2 I/O FT PG2 FSMC_A12 - J11 - - - - 88 PG3 I/O FT PG3 FSMC_A13 - J10 - - - - 89 PG4 I/O FT PG4 FSMC_A14 - H12 - - - - 90 PG5 I/O FT PG5 FSMC_A15 - H11 - - - - 91 PG6 I/O FT PG6 FSMC_INT2 - H10 - - - - 92 PG7 I/O FT PG7 FSMC_INT3 - G11 - - - - 93 PG8 I/O FT PG8 - - G10 - - - - 94 V S - V - - SS_9 SS_9 F10 - - - - 95 V S - V - - DD_9 DD_9 I2S2_MCK/ G12 F10 E1 37 63 96 PC6 I/O FT PC6 TIM3_CH1 TIM8_CH1/SDIO_D6 I2S3_MCK/ F12 E10 E2 38 64 97 PC7 I/O FT PC7 TIM3_CH2 TIM8_CH2/SDIO_D7 F11 F9 E3 39 65 98 PC8 I/O FT PC8 TIM8_CH3/SDIO_D0 TIM3_CH3 E11 E9 D1 40 66 99 PC9 I/O FT PC9 TIM8_CH4/SDIO_D1 TIM3_CH4 USART1_CK/ E12 D9 E4 41 67 100 PA8 I/O FT PA8 - TIM1_CH1(9)/MCO 34/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions (continued) Pins Alternate functions(4) 2) FBGA144 FBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name (1)Type (I / O Level (fauftneMcrta irioenns (e3t)) Default Remap L L USART1_TX(9)/ D12 C9 D2 42 68 101 PA9 I/O FT PA9 - TIM1_CH2(9) USART1_RX(9)/ D11 D10 D3 43 69 102 PA10 I/O FT PA10 - TIM1_CH3(9) USART1_CTS/USBDM C12 C10 C1 44 70 103 PA11 I/O FT PA11 - CAN_RX(9)/TIM1_CH4(9) USART1_RTS/USBDP/ B12 B10 C2 45 71 104 PA12 I/O FT PA12 - CAN_TX(9)/TIM1_ETR(9) A12 A10 D4 46 72 105 PA13 I/O FT JTMS-SWDIO - PA13 C11 F8 - - 73 106 Not connected - G9 E6 B1 47 74 107 V S - V - - SS_2 SS_2 F9 F6 A1 48 75 108 V S - V - - DD_2 DD_2 A11 A9 B2 49 76 109 PA14 I/O FT JTCK-SWCLK - PA14 TIM2_CH1_ET SPI3_NSS/ A10 A8 C3 50 77 110 PA15 I/O FT JTDI R PA15 / I2S3_WS SPI1_NSS B11 B9 A2 51 78 111 PC10 I/O FT PC10 UART4_TX/SDIO_D2 USART3_TX B10 B8 B3 52 79 112 PC11 I/O FT PC11 UART4_RX/SDIO_D3 USART3_RX C10 C8 C4 53 80 113 PC12 I/O FT PC12 UART5_TX/SDIO_CK USART3_CK E10 D8 D8 5 81 114 PD0 I/O FT OSC_IN(10) FSMC_D2(11) CAN_RX D10 E8 D7 6 82 115 PD1 I/O FT OSC_OUT(10) FSMC_D3(11) CAN_TX TIM3_ETR/UART5_RX E9 B7 A3 54 83 116 PD2 I/O FT PD2 - SDIO_CMD D9 C7 - - 84 117 PD3 I/O FT PD3 FSMC_CLK USART2_CTS C9 D7 - - 85 118 PD4 I/O FT PD4 FSMC_NOE USART2_RTS B9 B6 - - 86 119 PD5 I/O FT PD5 FSMC_NWE USART2_TX E7 - - - - 120 V S - V - - SS_10 SS_10 F7 - - - - 121 V S - V - - DD_10 DD_10 A8 C6 - - 87 122 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX A9 D6 - - 88 123 PD7 I/O FT PD7 FSMC_NE1/FSMC_NCE2 USART2_CK E8 - - - - 124 PG9 I/O FT PG9 FSMC_NE2/FSMC_NCE3 - FSMC_NCE4_1/ D8 - - - - 125 PG10 I/O FT PG10 - FSMC_NE3 DS5792 Rev 13 35/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Pins Alternate functions(4) 2) FBGA144 FBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name (1)Type (I / O Level (fauftneMcrta irioenns (e3t)) Default Remap L L C8 - - - - 126 PG11 I/O FT PG11 FSMC_NCE4_2 - B8 - - - - 127 PG12 I/O FT PG12 FSMC_NE4 - D7 - - - - 128 PG13 I/O FT PG13 FSMC_A24 - C7 - - - - 129 PG14 I/O FT PG14 FSMC_A25 - E6 - - - - 130 V S - V - - SS_11 SS_11 F6 - - - - 131 V S - V - - DD_11 DD_11 B7 - - - - 132 PG15 I/O FT PG15 - - PB3/TRACES WO A7 A7 A4 55 89 133 PB3 I/O FT JTDO SPI3_SCK / I2S3_CK/ TIM2_CH2 / SPI1_SCK PB4 / A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO TIM3_CH1 SPI1_MISO I2C1_SMBA/ SPI3_MOSI TIM3_CH2 / B6 C5 A5 57 91 135 PB5 I/O - PB5 I2S3_SD SPI1_MOSI C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(9)/ TIM4_CH1(9) USART1_TX I2C1_SDA(9) / FSMC_NADV D6 A5 C5 59 93 137 PB7 I/O FT PB7 USART1_RX / TIM4_CH2(9) D5 D5 A6 60 94 138 BOOT0 I - BOOT0 - - I2C1_SCL/ C5 B4 D5 61 95 139 PB8 I/O FT PB8 TIM4_CH3(9)/SDIO_D4 CAN_RX I2C1_SDA / B5 A4 B6 62 96 140 PB9 I/O FT PB9 TIM4_CH4(9)/SDIO_D5 CAN_TX A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 - A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1 - E5 E5 A7 63 99 143 V S - V - - SS_3 SS_3 10 F5 F5 A8 64 144 V S - V - - 0 DD_3 DD_3 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 36/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. In the WCLSP64 package, the PC3 I/O pin is not bonded and it must be configured by software to output mode (Push-pull) and writing 0 to the data register in order to avoid an extra consumption during low-power modes. 8. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V functionality is provided instead. REF+ 9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 10. For the WCLSP64/LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 11. For devices delivered in LQFP64 packages, the FSMC function is not available. DS5792 Rev 13 37/143 135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 6. FSMC pin definition FSMC LQFP100 Pins NOR/PSRAM/ BGA100(1) CF CF/IDE NOR/PSRAM Mux NAND 16 bit SRAM PE2 - - A23 A23 - Yes PE3 - - A19 A19 - Yes PE4 - - A20 A20 - Yes PE5 - - A21 A21 - Yes PE6 - - A22 A22 - Yes PF0 A0 A0 A0 - - - PF1 A1 A1 A1 - - - PF2 A2 A2 A2 - - - PF3 A3 - A3 - - - PF4 A4 - A4 - - - PF5 A5 - A5 - - - PF6 NIORD NIORD - - - - PF7 NREG NREG - - - - PF8 NIOWR NIOWR - - - - PF9 CD CD - - - - PF10 INTR INTR - - - - PF11 NIOS16 NIOS16 - - - - PF12 A6 - A6 - - - PF13 A7 - A7 - - - PF14 A8 - A8 - - - PF15 A9 - A9 - - - PG0 A10 - A10 - - - PG1 - - A11 - - - PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes 38/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 6. FSMC pin definition (continued) FSMC LQFP100 Pins NOR/PSRAM/ BGA100(1) CF CF/IDE NOR/PSRAM Mux NAND 16 bit SRAM PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 - - A16 A16 CLE Yes PD12 - - A17 A17 ALE Yes PD13 - - A18 A18 - Yes PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 - - A12 - - - PG3 - - A13 - - - PG4 - - A14 - - - PG5 - - A15 - - - PG6 - - - - INT2 - PG7 - - - - INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes PD3 - - CLK CLK - Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 - - NE1 NE1 NCE2 Yes PG9 - - NE2 NE2 NCE3 - PG10 NCE4_1 NCE4_1 NE3 NE3 - - PG11 NCE4_2 NCE4_2 - - - - PG12 - - NE4 NE4 - - PG13 - - A24 A24 - - PG14 - - A25 A25 - - PB7 - - NADV NADV - Yes PE0 - - NBL0 NBL0 - Yes PE1 - - NBL1 NBL1 - Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. DS5792 Rev 13 39/143 135

Memory mapping STM32F103xC, STM32F103xD, STM32F103xE 4 Memory mapping The memory map is shown in Figure9. Figure 9. Memory map Reserved 0xA000 1000 - 0xBFFF FFFF FSMC register 0xA000 0000 - 0xA000 0FFF FSMC bank4 PCCARD 0x9000 0000 - 0x9FFF FFFF FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF Reserved 0x4002 4400 - 0x5FFF FFFF CRC 0x4002 3000 - 0x4002 33FF Reserved 0x4002 2400 - 0x4002 2FFF Flash interface 0x4002 2000 - 0x4002 23FF Reserved 0x4002 1400 - 0x4002 1FFF RCC 0x4002 1000 - 0x4002 13FF Reserved 0x4002 0400 - 0x4002 0FFF DMA2 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF Reserved 0x4001 8400 - 0x4001 FFFF SDIO 0x4001 8000 - 0x4001 83FF Reserved 0x4001 400 - 0x4001 7FFF ADC3 0x4001 3C00 - 0x4001 3FFF USART1 0x4001 3800 - 0x4001 3BFF TIM8 0x4001 3400 - 0x4001 37FF 0xFFFF FFFF 512-Mbyte TSIPMI11 00xx44000011 230C0000 -- 00xx44000011 323FFFFF block 7 ADC2 0x4001 2800 - 0x4001 2BFF Cortex-M3's ADC1 0x4001 2400 - 0x4001 27FF internal Port G 0x4001 2000 - 0x4001 23FF 0xE000 0000 peripherals Port F 0x4001 1C00 - 0x4001 1FFF 0xDFFF FFFF Port E 0x4001 1800 - 0x4001 1BFF 512-Mbyte Port D 0x4001 1400 - 0x4001 17FF block 6 Port C 0x4001 1000 - 0x4001 13FF Not used Port B 0x4001 0C00 - 0x4001 0FFF Port A 0x4001 0800 - 0x4001 0BFF 00xxBCF0F0F0 F0F0F0F0 AEFXITOI 00xx44000011 00040000 -- 00xx44000011 0037FFFF 512-Mbyte Reserved 0x4000 7800 - 0x4000 FFFF block 5 DAC 0x4000 7400 - 0x4000 77FF FSMC register PWR 0x4000 7000 - 0x4000 73FF 0xA000 0000 BKP 0x4000 6C00 - 0x4000 6FFF 0x9FFF FFFF Reserved 0x4000 6800 - 0x4000 6BFF 512-Mbyte BxCAN 0x4000 6400 - 0x4000 67FF block 4 Shared USB/CAN SRAM 512 0x4000 6000 - 0x4000 63FF FSMC bank 3 USB breytgeissters 0x4000 5C00 - 0x4000 5FFF & bank4 I2C2 0x4000 5800 - 0x4000 5BFF 00xx78F0F0F0 F0F0F0F0 I2C1 0x4000 5400 - 0x4000 57FF 512-Mbyte UART5 0x4000 5000 - 0x4000 53FF block 3 UART4 0x4000 4C00 - 0x4000 4FFF FSMC bank1 USART3 0x4000 4800 - 0x4000 4BFF 0x6000 0000 & bank2 USART2 0x4000 4400 - 0x4000 47FF 0x5FFF FFFF Reserved 0x4000 4000 - 0x4000 43FF 512-Mbyte SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF block 2 SPI2/I2S2 0x4000 3800 - 0x4000 3BFF Peripherals Reserved 0x4000 3400 - 0x4000 37FF 0x4000 0000 IWDG 0x4000 3000 - 0x4000 33FF 0x3FFF FFFF WWDG 0x4000 2C00 - 0x4000 2FFF 512-Mbyte RTC 0x4000 2800 - 0x4000 2BFF block 1 Reserved 0x4000 1800 - 0x4000 27FF SRAM TIM7 0x4000 1400 - 0x4000 17FF 0x2000 0000 TIM6 0x4000 1000 - 0x4000 13FF 0x1FFF FFFF TIM5 0x4000 0C00 - 0x4000 0FFF 512-Mbyte TIM4 0x4000 0800 - 0x4000 0BFF block 0 TIM3 0x4000 0400 - 0x4000 07FF Code TIM2 0x4000 0000 - 0x4000 03FF 0x0000 0000 0x3FFF FFFF Reserved 0x2001 0000 SRAM (64 KB aliased 0x2000 FFFF by bit-banding) 0x2000 0000 Option Bytes 0x1FFF F800 - 0x1FFF F80F System memory 0x1FFF F000- 0x1FFF F7FF Reserved 0x1FFF EFFF 0x0808 0000 Flash 00xx00880007 0F0F0F0F Reserved 0x07FF FFFF 0x0008 0000 Aliased to Flash or system 0x0007 FFFF memory depending on BOOT pins 0x0000 0000 ai14753d 40/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V . SS 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the A DD 2V≤V ≤3.6V voltage range). They are given only as design guidelines and are not DD tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure11. Figure 10. Pin loading conditions Figure 11. Pin input voltage (cid:45)(cid:35)(cid:53)(cid:0)(cid:80)(cid:73)(cid:78) (cid:45)(cid:35)(cid:53)(cid:0)(cid:80)(cid:73)(cid:78) (cid:35)(cid:0)(cid:29)(cid:0)(cid:21)(cid:16)(cid:0)(cid:80)(cid:38) (cid:54)(cid:41)(cid:46) (cid:45)(cid:51)(cid:17)(cid:25)(cid:16)(cid:17)(cid:17)(cid:54)(cid:18) (cid:45)(cid:51)(cid:17)(cid:25)(cid:16)(cid:17)(cid:16)(cid:54)(cid:18) DS5792 Rev 13 41/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.1.6 Power supply scheme Figure 12. Power supply scheme (cid:115)(cid:17)(cid:4)(cid:100) (cid:17)(cid:258)(cid:272)(cid:364)(cid:437)(cid:393)(cid:3)(cid:272)(cid:349)(cid:396)(cid:272)(cid:437)(cid:349)(cid:410)(cid:396)(cid:455) (cid:1005)(cid:856)(cid:1012)(cid:882)(cid:1007)(cid:856)(cid:1010)(cid:115) (cid:87)(cid:381)(cid:449)(cid:286)(cid:396)(cid:3)(cid:3)(cid:400)(cid:449)(cid:349)(cid:410)(cid:272)(cid:346) (cid:894)(cid:75)(cid:94)(cid:18)(cid:1007)(cid:1006)(cid:60)(cid:853)(cid:90)(cid:100)(cid:18)(cid:853) (cid:116)(cid:258)(cid:364)(cid:286)(cid:882)(cid:437)(cid:393)(cid:3)(cid:367)(cid:381)(cid:336)(cid:349)(cid:272) (cid:17)(cid:258)(cid:272)(cid:364)(cid:437)(cid:393)(cid:3)(cid:396)(cid:286)(cid:336)(cid:349)(cid:400)(cid:410)(cid:286)(cid:396)(cid:400)(cid:895) (cid:75)(cid:104)(cid:100) (cid:286)(cid:396) (cid:39)(cid:87) (cid:47)(cid:876)(cid:75)(cid:400) (cid:47)(cid:69) (cid:448)(cid:286)(cid:367)(cid:3)(cid:400)(cid:346)(cid:349)(cid:296)(cid:410) (cid:62)(cid:381)(cid:47)(cid:75)(cid:336)(cid:349)(cid:272) (cid:60)(cid:286)(cid:396)(cid:374)(cid:286)(cid:367)(cid:3)(cid:367)(cid:381)(cid:336)(cid:349)(cid:272)(cid:3)(cid:3) (cid:286) (cid:62) (cid:894)(cid:18)(cid:87)(cid:104)(cid:853)(cid:3)(cid:3) (cid:24)(cid:349)(cid:336)(cid:349)(cid:410)(cid:258)(cid:367)(cid:3)(cid:3) (cid:115)(cid:24)(cid:24) (cid:920)(cid:3)(cid:68)(cid:286)(cid:373)(cid:381)(cid:396)(cid:349)(cid:286)(cid:400)(cid:895)(cid:3)(cid:3) (cid:115)(cid:24)(cid:24)(cid:1005)(cid:876)(cid:1006)(cid:876)(cid:856)(cid:856)(cid:856)(cid:876)(cid:1005)(cid:1005) (cid:90)(cid:286)(cid:336)(cid:437)(cid:367)(cid:258)(cid:410)(cid:381)(cid:396) (cid:1005)(cid:1005)(cid:3)(cid:3)(cid:1087)(cid:1005)(cid:1004)(cid:1004)(cid:3)(cid:374)(cid:38) (cid:1085)(cid:3)(cid:1005)(cid:3)(cid:3)(cid:1087)(cid:1008)(cid:856)(cid:1011)(cid:3)(cid:3)(cid:1106)(cid:38) (cid:115)(cid:94)(cid:94)(cid:1005)(cid:876)(cid:1006)(cid:876)(cid:856)(cid:856)(cid:856)(cid:876)(cid:1005)(cid:1005) (cid:115)(cid:24)(cid:24) (cid:115)(cid:24)(cid:24)(cid:4) (cid:115)(cid:90)(cid:28)(cid:38) (cid:115)(cid:90)(cid:28)(cid:38)(cid:1085) (cid:1005)(cid:1004)(cid:3)(cid:374)(cid:38) (cid:4)(cid:24)(cid:18)(cid:876) (cid:4)(cid:374)(cid:258)(cid:367)(cid:381)(cid:336)(cid:855)(cid:3)(cid:3) (cid:1005)(cid:1004)(cid:3)(cid:374)(cid:38) (cid:1085)(cid:3)(cid:1005)(cid:3)(cid:3)(cid:1106)(cid:38) (cid:115)(cid:90)(cid:28)(cid:38)(cid:882) (cid:24)(cid:4)(cid:18) (cid:90)(cid:18)(cid:400)(cid:853)(cid:3)(cid:87)(cid:62)(cid:62)(cid:853) (cid:1085)(cid:3)(cid:1005)(cid:3)(cid:3)(cid:1106)(cid:38) (cid:856)(cid:856)(cid:856) (cid:115)(cid:94)(cid:94)(cid:4) (cid:258)(cid:349)(cid:1005)(cid:1009)(cid:1008)(cid:1004)(cid:1005) Caution: In Figure12, the 4.7 µF capacitor must be connected to V . DD3 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme (cid:44)(cid:39)(cid:39)(cid:66)(cid:57)(cid:37)(cid:36)(cid:55) (cid:57)(cid:37)(cid:36)(cid:55) (cid:44)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39)(cid:36) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:21)(cid:25) 42/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table7: Voltage characteristics, Table8: Current characteristics, and Table9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Voltage characteristics Symbol Ratings Min Max Unit External main supply voltage (including V V –V DDA –0.3 4.0 DD SS and V )(1) DD V Input voltage on five volt tolerant pin V − 0.3 V + 4.0 V (2) SS DD IN Input voltage on any other pin V − 0.3 4.0 SS |ΔV | Variations between different V power pins - 50 DDx DD mV Variations between all the different ground |V − V | - 50 SSX SS pins(3) see Section5.3.12: Electrostatic discharge voltage (human body V Absolute maximum ratings - ESD(HBM) model) (electrical sensitivity) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power DD DDA SS SSA supply, in the permitted range. 2. V maximum must always be respected. Refer to Table8: Current characteristics for the maximum IN allowed injected current values. 3. Include V pin. REF- Table 8. Current characteristics Symbol Ratings Max. Unit I Total current into V /V power lines (source)(1) 150 VDD DD DDA I Total current out of V ground lines (sink)(1) 150 VSS SS Output current sunk by any I/O and control pin 25 I IO Output current source by any I/Os and control pin − 25 mA Injected current on five volt tolerant pins(3) -5/+0 I (2) INJ(PIN) Injected current on any other pin(4) ± 5 ΣI Total injected current (sum of all I/O and control pins)(5) ± 25 INJ(PIN) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power DD DDA SS SSA supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note 3 below Table62 on page108. 3. Positive injection is not possible on these I/Os. A negative injection is induced by V <V . I must IN SS INJ(PIN) never be exceeded. Refer to Table7: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by V >V while a negative injection is induced by V <V . I must IN DD IN SS INJ(PIN) never be exceeded. Refer to Table7: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the INJ(PIN) positive and negative injected currents (instantaneous values). DS5792 Rev 13 43/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 9. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range –65 to +150 °C STG T Maximum junction temperature 150 °C J 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol Parameter Conditions Min Max Unit f Internal AHB clock frequency - 0 72 HCLK f Internal APB1 clock frequency - 0 36 MHz PCLK1 f Internal APB2 clock frequency - 0 72 PCLK2 V Standard operating voltage - 2 3.6 V DD Analog operating voltage 2 3.6 (ADC not used) Must be the same potential V (1) V DDA Analog operating voltage as VDD(2) 2.4 3.6 (ADC used) V Backup operating voltage - 1.8 3.6 V BAT LQFP144 - 666 LQFP100 - 434 Power dissipation at TA = LQFP64 - 444 P 85°C for suffix 6 or T = mW D A 105°C for suffix 7(3) LFBGA100 - 500 LFBGA144 - 500 WLCSP64 - 400 Ambient temperature for 6 Maximum power dissipation -40 85 °C suffix version Low-power dissipation(4) -40 105 TA Ambient temperature for 7 Maximum power dissipation -40 105 °C suffix version Low-power dissipation(4) -40 125 6 suffix version -40 105 TJ Junction temperature range °C 7 suffix version -40 125 1. When the ADC is used, refer to Table59: ADC characteristics. 2. It is recommended to power V and V from the same source. A maximum difference of 300mV DD DDA between V and V can be tolerated during power-up and operation. DD DDA 3. If T is lower, higher P values are allowed as long as T does not exceed T max (see Table6.7: Thermal A D J J characteristics on page132). 4. In low-power dissipation state, T can be extended to this range as long as T does not exceed T max (see A J J Table6.7: Thermal characteristics on page132). 44/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.2 Operating conditions at power-up / power-down The parameters given in Table11 are derived from tests performed under the ambient temperature condition summarized in Table10. Table 11. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max Unit V rise time rate 0 ∞ DD t - µs/V VDD V fall time rate 20 ∞ DD 5.3.3 Embedded reset and power control block characteristics The parameters given in Table12 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table10. DD Table 12. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 PLS[2:0]=000 (falling edge) 2 2.08 2.16 PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V V PVD detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 PLS[2:0]=111 (rising edge) 2.76 2.88 3 PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V (2) PVD hysteresis - - 100 - mV PVDhyst Power on/power down Falling edge 1.8(1) 1.88 1.96 V V POR/PDR reset threshold Rising edge 1.84 1.92 2.0 V (2) PDR hysteresis - - 40 - mV PDRhyst T (2) Reset temporization - 1 2.5 4.5 ms RSTTEMPO 1. The product behavior is guaranteed by design down to the minimum V value. POR/PDR 2. Guaranteed by design. DS5792 Rev 13 45/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.4 Embedded reference voltage The parameters given in Table13 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table10. DD Table 13. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit –40 °C < T < +105 °C 1.16 1.20 1.26 A V Internal reference voltage V REFINT –40 °C < T < +85 °C 1.16 1.20 1.24 A ADC sampling time when T (1) reading the internal reference - - 5.1 17.1(2) µs S_vrefint voltage Internal reference voltage V (2) spread over the temperature V = 3 V ±10 mV - - 10 mV RERINT DD range T (2) Temperature coefficient - - - 100 ppm/°C Coeff 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at V or V (no load) DD SS • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted to the f frequency (0 wait state from 0 HCLK to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) • Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled f = f /2, f = f PCLK1 HCLK PCLK2 HCLK The parameters given in Table14, Table15 and Table16 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table10. DD 46/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions f Unit HCLK T = 85°C T = 105°C A A 72 MHz 69 70 48 MHz 50 50.5 External clock(2), all 36 MHz 39 39.5 peripherals enabled 24 MHz 27 28 16 MHz 20 20.5 Supply current in 8 MHz 11 11.5 I mA DD Run mode 72 MHz 37 37.5 48 MHz 28 28.5 External clock(2), all 36 MHz 22 22.5 peripherals disabled 24 MHz 16.5 17 16 MHz 12.5 13 8 MHz 8 8 1. Guaranteed by characterization results. 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK CIATOable 15. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions f Unit HCLK T = 85°C T = 105°C A A 72 MHz 66 67 48 MHz 43.5 45.5 External clock(2), all 36 MHz 33 35 peripherals enabled 24 MHz 23 24.5 16 MHz 16 18 Supply current 8 MHz 9 10.5 I mA DD in Run mode 72 MHz 33 33.5 48 MHz 23 23.5 External clock(2), all 36 MHz 18 18.5 peripherals disabled 24 MHz 13 13.5 16 MHz 10 10.5 8 MHz 6 6.5 1. Guaranteed by characterization results at V max, f max. DD HCLK 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK DS5792 Rev 13 47/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled (cid:23)(cid:16) (cid:22)(cid:16) (cid:21)(cid:16) (cid:33)(cid:9) (cid:77) (cid:77)(cid:80)(cid:84)(cid:73)(cid:79)(cid:78)(cid:0)(cid:8) (cid:20)(cid:16) (cid:23)(cid:20)(cid:19)(cid:18)(cid:24)(cid:22)(cid:45)(cid:45)(cid:45)(cid:40)(cid:40)(cid:40)(cid:90)(cid:90)(cid:90) (cid:35)(cid:79)(cid:78)(cid:83)(cid:85) (cid:19)(cid:16) (cid:18)(cid:17)(cid:20)(cid:22)(cid:45)(cid:45)(cid:40)(cid:40)(cid:90)(cid:90) (cid:18)(cid:16) (cid:24)(cid:45)(cid:40)(cid:90) (cid:17)(cid:16) (cid:16) (cid:13)(cid:20)(cid:21) (cid:18)(cid:21) (cid:23)(cid:16) (cid:24)(cid:21) (cid:17)(cid:16)(cid:21) (cid:52)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:22)(cid:25) Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)- code with data processing running from RAM, peripherals disabled (cid:20)(cid:16) (cid:19)(cid:21) (cid:19)(cid:16) (cid:23)(cid:18)(cid:45)(cid:40)(cid:90) (cid:33)(cid:9) (cid:18)(cid:21) (cid:20)(cid:24)(cid:45)(cid:40)(cid:90) (cid:77) (cid:78)(cid:0)(cid:8) (cid:19)(cid:22)(cid:45)(cid:40)(cid:90) (cid:79) (cid:80)(cid:84)(cid:73) (cid:18)(cid:16) (cid:18)(cid:20)(cid:45)(cid:40)(cid:90) (cid:77) (cid:85) (cid:17)(cid:22)(cid:45)(cid:40)(cid:90) (cid:78)(cid:83) (cid:35)(cid:79) (cid:17)(cid:21) (cid:24)(cid:45)(cid:40)(cid:90) (cid:17)(cid:16) (cid:21) (cid:16) (cid:13)(cid:20)(cid:21) (cid:18)(cid:21) (cid:23)(cid:16) (cid:24)(cid:21) (cid:17)(cid:16)(cid:21) (cid:52)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:18)(cid:16) 48/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics T able 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions f Unit HCLK T = 85°C T = 105°C A A 72 MHz 45 46 48 MHz 31 32 External clock(2), all 36 MHz 24 25 peripherals enabled 24 MHz 17 17.5 16 MHz 12.5 13 Supply current 8 MHz 8 8 I mA DD in Sleep mode 72 MHz 8.5 9 48 MHz 7 7.5 External clock(2), all 36 MHz 6 6.5 peripherals disabled 24 MHz 5 5.5 16 MHz 4.5 5 8 MHz 4 4 1. Guaranteed by characterization results at V max, f max with peripherals enabled. DD HCLK 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK DS5792 Rev 13 49/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 17. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Max Symbol Parameter Conditions Unit V /V V /V V /V T = T = DD BAT DD BAT DD BAT A A = 2.0V = 2.4V = 3.3V 85°C 105°C Regulator in run mode, low- speed and high-speed internal RC oscillators and high-speed - 34.5 35 379 1130 oscillator OFF (no independent Supply watchdog) current in Stop mode Regulator in low-power mode, low-speed and high-speed internal RC oscillators and high- - 24.5 25 365 1110 speed oscillator OFF (no I independent watchdog) DD Low-speed internal RC oscillator and independent watchdog ON - 3 3.8 - - µA Supply Low-speed internal RC oscillator - 2.8 3.6 - - current in ON, independent watchdog OFF Standby Low-speed internal RC oscillator mode and independent watchdog OFF, - 1.9 2.1 5(2) 6.5(2) low-speed oscillator and RTC OFF Backup domain Low-speed oscillator and RTC I 1.05 1.1 1.4 2(2) 2.3(2) DD_VBAT supply ON current 1. Typical values are measured at T = 25 °C. A 2. Guaranteed by characterization results. 50/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 16. Typical current consumption on V with RTC on vs. temperature BAT at different V values BAT (cid:21)(cid:17)(cid:24) (cid:21) (cid:36)(cid:12) (cid:151) (cid:20)(cid:17)(cid:27)(cid:3)(cid:57) (cid:82)(cid:81)(cid:3)(cid:11) (cid:20)(cid:17)(cid:24) (cid:21)(cid:3)(cid:57) (cid:80)(cid:83)(cid:87)(cid:76) (cid:21)(cid:17)(cid:23)(cid:3)(cid:57) (cid:88) (cid:86) (cid:22)(cid:17)(cid:22)(cid:3)(cid:57) (cid:81) (cid:20) (cid:82) (cid:38) (cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:19)(cid:17)(cid:24) (cid:19) (cid:177)(cid:23)(cid:24) (cid:21)(cid:24) (cid:27)(cid:24) (cid:20)(cid:19)(cid:24) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:68)(cid:76)(cid:20)(cid:26)(cid:22)(cid:22)(cid:26) Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V values DD (cid:22)(cid:16)(cid:16) (cid:22)(cid:16)(cid:16) (cid:21)(cid:16)(cid:16) (cid:21)(cid:16)(cid:16) (cid:20)(cid:16)(cid:16) (cid:33)(cid:9) (cid:541) (cid:20)(cid:16)(cid:16) (cid:80)(cid:84)(cid:73)(cid:79)(cid:78)(cid:0)(cid:8) (cid:19)(cid:16)(cid:79)(cid:78)(cid:0)(cid:8)(cid:541)(cid:33)(cid:9)(cid:16) (cid:18)(cid:14)(cid:20)(cid:54) (cid:18)(cid:18)(cid:14)(cid:14)(cid:20)(cid:23)(cid:54)(cid:54) (cid:77) (cid:80)(cid:84)(cid:73) (cid:19)(cid:16)(cid:16) (cid:18)(cid:14)(cid:23)(cid:54) (cid:85) (cid:77) (cid:19)(cid:14)(cid:16)(cid:54) (cid:78)(cid:83) (cid:83)(cid:85) (cid:19)(cid:14)(cid:16)(cid:54) (cid:79) (cid:78) (cid:35) (cid:18)(cid:16)(cid:35)(cid:79)(cid:16) (cid:18)(cid:16)(cid:16) (cid:19)(cid:14)(cid:19)(cid:54) (cid:19)(cid:14)(cid:19)(cid:54) (cid:19)(cid:14)(cid:22)(cid:54) (cid:19)(cid:14)(cid:22)(cid:54) (cid:17)(cid:16)(cid:16) (cid:17)(cid:16)(cid:16) (cid:16) (cid:16) (cid:13)(cid:20)(cid:21)(cid:35) (cid:18)(cid:21)(cid:35) (cid:24)(cid:21)(cid:35) (cid:17)(cid:16)(cid:21)(cid:35) (cid:13)(cid:20)(cid:21)(cid:35) (cid:18)(cid:21)(cid:52)(cid:35)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:24)(cid:21)(cid:35) (cid:17)(cid:16)(cid:21)(cid:35) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:18)(cid:17) (cid:52)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:18)(cid:17) DS5792 Rev 13 51/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V values DD (cid:22)(cid:16)(cid:16) (cid:21)(cid:16)(cid:16) (cid:20)(cid:16)(cid:16) (cid:33)(cid:9) (cid:541) (cid:8) (cid:79)(cid:78) (cid:18)(cid:14)(cid:20)(cid:54) (cid:77)(cid:80)(cid:84)(cid:73) (cid:19)(cid:16)(cid:16) (cid:18)(cid:14)(cid:23)(cid:54) (cid:85) (cid:83) (cid:19)(cid:14)(cid:16)(cid:54) (cid:78) (cid:79) (cid:35) (cid:19)(cid:14)(cid:19)(cid:54) (cid:18)(cid:16)(cid:16) (cid:19)(cid:14)(cid:22)(cid:54) (cid:17)(cid:16)(cid:16) (cid:16) (cid:13)(cid:20)(cid:21)(cid:35) (cid:18)(cid:21)(cid:35) (cid:24)(cid:21)(cid:35) (cid:17)(cid:16)(cid:21)(cid:35) (cid:52)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:18)(cid:18) Figure 19. Typical current consumption in Standby mode versus temperature at different V values DD (cid:20)(cid:14)(cid:21) (cid:20) (cid:19)(cid:14)(cid:21) (cid:33)(cid:9) (cid:19) (cid:541) (cid:79)(cid:78)(cid:0)(cid:8) (cid:18)(cid:14)(cid:21) (cid:18)(cid:14)(cid:20)(cid:54) (cid:80)(cid:84)(cid:73) (cid:18)(cid:14)(cid:23)(cid:54) (cid:77) (cid:85) (cid:18) (cid:19)(cid:14)(cid:16)(cid:54) (cid:83) (cid:78) (cid:35)(cid:79) (cid:17)(cid:14)(cid:21) (cid:19)(cid:14)(cid:19)(cid:54) (cid:19)(cid:14)(cid:22)(cid:54) (cid:17) (cid:16)(cid:14)(cid:21) (cid:16) (cid:13)(cid:20)(cid:21)(cid:35) (cid:18)(cid:21)(cid:35) (cid:23)(cid:16)(cid:35) (cid:24)(cid:21)(cid:35) (cid:52)(cid:69)(cid:77)(cid:80)(cid:69)(cid:82)(cid:65)(cid:84)(cid:85)(cid:82)(cid:69)(cid:0)(cid:8)(cid:160)(cid:35)(cid:9) (cid:65)(cid:73)(cid:17)(cid:24)(cid:21)(cid:18)(cid:19) 52/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at V or V (no load). DD SS • All peripherals are disabled except if it is explicitly mentioned. • The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1 HCLK wait state from 24 to 48 MHZ and 2 wait states above). • Ambient temperature and V supply voltage conditions summarized in Table10. DD • Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled f = f /4, f 2 = f /2, f = f /4 PCLK1 HCLK PCLK HCLK ADCCLK PCLK2 Table 18. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions f Unit HCLK All peripherals All peripherals enabled(2) disabled 72 MHz 51 30.5 48 MHz 34.6 20.7 36 MHz 26.6 16.2 24 MHz 18.5 11.4 16 MHz 12.8 8.2 External clock(3) 8 MHz 7.2 5 mA 4 MHz 4.2 3.1 2 MHz 2.7 2.1 1 MHz 2 1.7 500 kHz 1.6 1.4 Supply 125 kHz 1.3 1.2 I current in DD Run mode 64 MHz 45 27 48 MHz 34 20.1 36 MHz 26 15.6 24 MHz 17.9 10.8 Running on high speed internal RC 16 MHz 12.2 7.6 (HSI), AHB 8 MHz 6.6 4.4 mA prescaler used to reduce the 4 MHz 3.6 2.5 frequency 2 MHz 2.1 1.5 1 MHz 1.4 1.1 500 kHz 1 0.8 125 kHz 0.7 0.6 1. Typical values are measures at T = 25 °C, V = 3.3 V. A DD DS5792 Rev 13 53/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions f Unit HCLK All peripherals All peripherals enabled(2) disabled 72 MHz 29.5 6.4 48 MHz 20 4.6 36 MHz 15.1 3.6 24 MHz 10.4 2.6 16 MHz 7.2 2 External clock(3) 8 MHz 3.9 1.3 4 MHz 2.6 1.2 2 MHz 1.85 1.15 1 MHz 1.5 1.1 500 kHz 1.3 1.05 Supply 125 kHz 1.2 1.05 I current in mA DD Sleep mode 64 MHz 25.6 5.1 48 MHz 19.4 4 36 MHz 14.5 3 24 MHz 9.8 2 Running on high 16 MHz 6.6 1.4 speed internal RC (HSI), AHB prescaler 8 MHz 3.3 0.7 used to reduce the 4 MHz 2 0.6 frequency 2 MHz 1.25 0.55 1 MHz 0.9 0.5 500 kHz 0.7 0.45 125 kHz 0.6 0.45 1. Typical values are measures at T = 25 °C, V = 3.3 V. A DD 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK 54/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table20. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at V or V (no load) DD SS • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on • ambient operating temperature and V supply voltage conditions summarized in DD Table7 Table 20. Peripheral current consumption Current Peripheral Unit consumption DMA1 20,42 DMA2 19,03 FSMC 52,36 AHB (up to 72MHz) μA/MHz CRC 2,36 SDIO 33,33 BusMatrix(1) 9,72 DS5792 Rev 13 55/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 20. Peripheral current consumption (continued) Current Peripheral Unit consumption APB1-Bridge 7,78 TIM2 33,06 TIM3 31,94 TIM4 31,67 TIM5 31,94 TIM6 8,06 TIM7 8,06 SPI2/I2S2(2) 8,33 SPI3/I2S3(2) 8,33 USART2 12,22 USART3 12,22 APB1 (up to 36MHz) μA/MHz UART4 12,22 UART5 12,22 I2C1 10,28 I2C2 10,00 USB 18,06 CAN1 18,33 DAC(3) 8,06 WWDG 3,89 PWR 1,11 BKP 1,11 IWDG 5,28 56/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 20. Peripheral current consumption (continued) Current Peripheral Unit consumption APB2-Bridge 4,17 GPIOA 8,47 GPIOB 8,47 GPIOC 6,53 GPIOD 8,47 GPIOE 6,53 GPIOF 6,53 APB2 (up to 72MHz) GPIOG 6,11 μA/MHz SPI1 4,72 USART1 12,50 TIM1 22,92 TIM8 22,92 ADC1(4) 17,32 ADC2(4) 15,18 ADC3(4) 14,82 1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1 or DMA2). 2. When the I2S is enabled, a current consumption equal to 0.02mA must be added. 3. When DAC_OU1 or DAC_OUT2 is enabled, a current consumption equal to 0.36mA must be added. 4. Specific conditions for measuring ADC current consumption: f = 56 MHz, f = f /2, f = HCLK APB1 HCLK APB2 f , f = f /4. When ADON bit in the ADCx_CR2 register is set to 1, a current consumption of HCLK ADCCLK APB2 analog part equal to 0.54 mA must be added for each ADC. DS5792 Rev 13 57/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table10. Table 21. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source f 1 8 25 MHz HSE_ext frequency(1) V OSC_IN input pin high level voltage 0.7V - V HSEH DD DD V V OSC_IN input pin low level voltage V - 0.3V HSEL - SS DD t w(HSE) OSC_IN high or low time(1) 5 - - t w(HSE) ns t r(HSE) OSC_IN rise or fall time(1) - - 20 t f(HSE) C OSC_IN input capacitance(1) - - 5 - pF in(HSE) DuCy Duty cycle - 45 - 55 % (HSE) I OSC_IN Input leakage current V ≤V ≤V - - ±1 µA L SS IN DD 1. Guaranteed by design. Low-speed external user clock generated from an external source The characteristics given in Table22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table10. Table 22. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit User External clock source f - 32.768 1000 kHz LSE_ext frequency(1) OSC32_IN input pin high level V 0.7V - V LSEH voltage DD DD V OSC32_IN input pin low level V - V - 0.3V LSEL voltage SS DD t w(LSE) OSC32_IN high or low time(1) 450 - - t w(LSE) ns t r(LSE) OSC32_IN rise or fall time(1) - - 50 t f(LSE) C OSC32_IN input capacitance(1) - - 5 - pF in(LSE) DuCy Duty cycle - 30 - 70 % (LSE) I OSC32_IN Input leakage current V ≤V ≤V - - ±1 µA L SS IN DD 1. Guaranteed by design. 58/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 20. High-speed external clock source AC timing diagram (cid:54)(cid:40)(cid:51)(cid:37)(cid:40) (cid:25)(cid:16)(cid:5) (cid:17)(cid:16)(cid:5) (cid:54)(cid:40)(cid:51)(cid:37)(cid:44) (cid:84)(cid:82)(cid:8)(cid:40)(cid:51)(cid:37)(cid:9) (cid:84)(cid:70)(cid:8)(cid:40)(cid:51)(cid:37)(cid:9) (cid:84)(cid:55)(cid:8)(cid:40)(cid:51)(cid:37)(cid:9) (cid:84)(cid:55)(cid:8)(cid:40)(cid:51)(cid:37)(cid:9) (cid:84) (cid:52)(cid:40)(cid:51)(cid:37) (cid:37)(cid:88)(cid:84)(cid:69)(cid:82)(cid:78)(cid:65)(cid:76) (cid:70)(cid:40)(cid:51)(cid:37)(cid:63)(cid:69)(cid:88)(cid:84) (cid:41)(cid:44) (cid:67)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:83)(cid:79)(cid:85)(cid:82)(cid:67)(cid:69) (cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46) (cid:51)(cid:52)(cid:45)(cid:19)(cid:18)(cid:38) (cid:65)(cid:73)(cid:17)(cid:23)(cid:21)(cid:18)(cid:24) Figure 21. Low-speed external clock source AC timing diagram (cid:57)(cid:47)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:47)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:58)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:58)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87) (cid:55)(cid:47)(cid:54)(cid:40) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:73)(cid:47)(cid:54)(cid:40)(cid:66)(cid:72)(cid:91)(cid:87) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:44)(cid:47) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:86)(cid:82)(cid:88)(cid:85)(cid:70)(cid:72) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:68)(cid:76)(cid:20)(cid:26)(cid:24)(cid:21)(cid:28) DS5792 Rev 13 59/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit f Oscillator frequency - 4 8 16 MHz OSC_IN R Feedback resistor - - 200 - kΩ F Recommended load capacitance C versus equivalent serial R = 30 Ω - 30 - pF S resistance of the crystal (R )(3) S V = 3.3 V, V =V i HSE driving current DD IN SS - - 1 mA 2 with 30 pF load g Oscillator transconductance Startup 25 - - mA/V m t (4) Startup time V is stabilized - 2 - ms SU(HSE) DD 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz SU(HSE) oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C and C , it is recommended to use high-quality external ceramic capacitors in the L1 L2 5pF to 25pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure22). C and C are usually the L1 L2 same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C . PCB and MCU pin capacitance must be included (10pF L1 L2 can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . Refer to the application note AN2867 “Oscillator design guide for ST L1 L2 microcontrollers” available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75) (cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:73)(cid:43)(cid:54)(cid:40) (cid:37)(cid:76)(cid:68)(cid:86)(cid:3) (cid:27)(cid:3)(cid:48)(cid:43)(cid:93) (cid:53)(cid:41) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:71) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:74)(cid:68)(cid:76)(cid:81) (cid:38)(cid:47)(cid:21) (cid:53)(cid:40)(cid:59)(cid:55)(cid:11)(cid:20)(cid:12)(cid:3) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:68)(cid:76)(cid:20)(cid:26)(cid:24)(cid:22)(cid:19) 1. R value depends on the crystal characteristics. EXT 60/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 24. LSE oscillator characteristics (f = 32.768 kHz)(1)(2) LSE Symbol Parameter Conditions Min Typ Max Unit R Feedback resistor - - 5 - MΩ F Recommended load capacitance C(2) versus equivalent serial R = 30 kΩ - - 15 pF S resistance of the crystal (R ) S I LSE driving current V = 3.3 V, V = V - - 1.4 µA 2 DD IN SS g Oscillator transconductance - 5 - - µA/V m T = 50 °C - 1.5 - A T = 25 °C - 2.5 - A T = 10 °C - 4 - A t (3) Startup time VDD is TA = 0 °C - 6 - s SU(LSE) stabilized T = -10 °C - 10 - A T = -20 °C - 17 - A T = -30 °C - 32 - A T = -40 °C - 60 - A 1. Guaranteed by characterization results. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. t is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768kHz oscillation is SU(LSE) reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB layout and humidity. Note: For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to L1 L2 15pF range selected to match the requirements of the crystal or resonator (see Figure23). C and C are usually the same size. The crystal manufacturer typically specifies a load L1 L2, capacitance which is the series combination of C and C . L1 L2 Load capacitance C has the following formula: C = C x C / (C + C ) + C where L L L1 L2 L1 L2 stray C is the pin capacitance and board or trace PCB-related capacitance. Typically, it is stray between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended L1 L2 to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load L capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of C = 6 pF, and C = 2 pF, L stray then C = C = 8 pF. L1 L2 DS5792 Rev 13 61/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 23. Typical application with a 32.768 kHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75) (cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38)(cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:73)(cid:47)(cid:54)(cid:40) (cid:37)(cid:76)(cid:68)(cid:86)(cid:3) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93) (cid:53)(cid:41) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:71) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:74)(cid:68)(cid:76)(cid:81) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:38)(cid:47)(cid:21) (cid:68)(cid:76)(cid:20)(cid:26)(cid:24)(cid:22)(cid:20) 5.3.7 Internal clock source characteristics The parameters given in Table25 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table10. DD High-speed internal (HSI) RC oscillator Table 25. HSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit f Frequency - - 8 - MHz HSI DuCy Duty cycle - 45 - 55 % (HSI) User-trimmed with the RCC_CR - - 1(3) % register(2) T = –40 to 105°C –2 - 2.5 % Accuracy of the HSI A ACC HSI oscillator Factory- TA = –10 to 85°C –1.5 - 2.2 % calibrated(4) T = 0 to 70°C –1.3 - 2 % A T = 25°C –1.1 - 1.8 % A HSI oscillator t (4) - 1 - 2 µs su(HSI) startup time HSI oscillator power I (4) - - 80 100 µA DD(HSI) consumption 1. V = 3.3V, T = –40 to 105°C unless otherwise specified. DD A 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design. 4. Guaranteed by characterization results. 62/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol Parameter Min Typ Max Unit f (2) Frequency 30 40 60 kHz LSI t (3) LSI oscillator startup time - - 85 µs su(LSI) I (3) LSI oscillator power consumption - 0.65 1.2 µA DD(LSI) 1. V = 3 V, T = –40 to 105 °C unless otherwise specified. DD A 2. Guaranteed by characterization results. 3. Guaranteed by design. Wakeup time from low-power mode The wakeup times given in Table27 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and V supply DD voltage conditions summarized in Table10. Table 27. Low-power mode wakeup timings Symbol Parameter Typ Unit t (1) Wakeup from Sleep mode 1.8 µs WUSLEEP Wakeup from Stop mode (regulator in run mode) 3.6 t (1) µs WUSTOP Wakeup from Stop mode (regulator in low-power mode) 5.4 t (1) Wakeup from Standby mode 50 µs WUSTDBY 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. DS5792 Rev 13 63/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.8 PLL characteristics The parameters given in Table28 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table10. DD Table 28. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.0 25 MHz f PLL_IN PLL input clock duty cycle 40 - 60 % f PLL multiplier output clock 16 - 72 MHz PLL_OUT t PLL lock time - - 200 µs LOCK Jitter Cycle-to-cycle jitter - - 300 ps 1. Guaranteed by characterization results. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f . PLL_OUT 5.3.9 Memory characteristics Flash memory The characteristics are given at T = –40 to 105°C unless otherwise specified. A Table 29. Flash memory characteristics Symbol Parameter Conditions Min Typ Max(1) Unit t 16-bit programming time T = –40 to +105 °C 40 52.5 70 µs prog A t Page (2 KB) erase time T = –40 to +105 °C 20 - 40 ms ERASE A t Mass erase time T = –40 to +105 °C 20 - 40 ms ME A Read mode f = 72 MHz with 2 wait - - 28 mA HCLK states, V = 3.3 V DD Write mode - - 7 mA IDD Supply current fHCLK = 72 MHz, VDD = 3.3 V Erase mode - - 5 mA f = 72 MHz, V = 3.3 V HCLK DD Power-down mode / Halt, - - 50 µA V = 3.0 to 3.6 V DD V Programming voltage - 2 - 3.6 V prog 1. Guaranteed by design. 64/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 30. Flash memory endurance and data retention Value Symbol Parameter Conditions Unit Min(1) T = -40 to +85 °C (6 suffix versions) N Endurance A 10 kcycles END T = -40 to +105 °C (7 suffix versions) A 1 kcycle(2) at T = 85 °C 30 A t Data retention 1 kcycle(2) at T = 105 °C 10 Years RET A 10 kcycles(2) at T = 55 °C 20 A 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS5792 Rev 13 65/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.10 FSMC characteristics Asynchronous waveforms and timings Figure24 through Figure27 represent asynchronous waveforms and Table31 through Table34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 0 • AddressHoldTime = 1 • DataSetupTime = 1 Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms (cid:87) (cid:90)(cid:11)(cid:49)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:40) (cid:87)(cid:89)(cid:11)(cid:49)(cid:50)(cid:40)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:40)(cid:66)(cid:49)(cid:50)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:89)(cid:11)(cid:36)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:36)(cid:66)(cid:49)(cid:50)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:21)(cid:24)(cid:29)(cid:19)(cid:64) (cid:36)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:87) (cid:89)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87) (cid:75)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:50)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:37)(cid:47)(cid:62)(cid:20)(cid:29)(cid:19)(cid:64) (cid:87)(cid:75)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87) (cid:86)(cid:88)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:39)(cid:68)(cid:87)(cid:68) (cid:87) (cid:89)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87) (cid:90)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57)(cid:11)(cid:20)(cid:12) (cid:48)(cid:54)(cid:20)(cid:27)(cid:24)(cid:27)(cid:25)(cid:57)(cid:21) 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. 66/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min Max Unit t FSMC_NE low time 5t – 1.5 5t + 2 ns w(NE) HCLK HCLK t FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns v(NOE_NE) t FSMC_NOE low time 5t – 1.5 5t + 1.5 ns w(NOE) HCLK HCLK t FSMC_NOE high to FSMC_NE high hold time –1.5 - ns h(NE_NOE) t FSMC_NEx low to FSMC_A valid - 0 ns v(A_NE) t Address hold time after FSMC_NOE high 0.1 - ns h(A_NOE) t FSMC_NEx low to FSMC_BL valid - 0 ns v(BL_NE) t FSMC_BL hold time after FSMC_NOE high 0 - ns h(BL_NOE) t Data to FSMC_NEx high setup time 2t + 25 - ns su(Data_NE) HCLK t Data to FSMC_NOEx high setup time 2t + 25 - ns su(Data_NOE) HCLK t Data hold time after FSMC_NOE high 0 - ns h(Data_NOE) t Data hold time after FSMC_NEx high 0 - ns h(Data_NE) t FSMC_NEx low to FSMC_NADV low - 5 ns v(NADV_NE) t FSMC_NADV low time - t + 1.5 ns w(NADV) HCLK 1. C = 15 pF. L Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms (cid:87)(cid:90)(cid:11)(cid:49)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:40)(cid:91) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:40)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:89)(cid:11)(cid:36)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:36)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:21)(cid:24)(cid:29)(cid:19)(cid:64) (cid:36)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:87)(cid:89)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:37)(cid:47)(cid:62)(cid:20)(cid:29)(cid:19)(cid:64) (cid:49)(cid:37)(cid:47) (cid:87)(cid:89)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:39)(cid:68)(cid:87)(cid:68) (cid:87)(cid:89)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57)(cid:11)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:28)(cid:19) 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. DS5792 Rev 13 67/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit t FSMC_NE low time 3t – 1 3t + 2 ns w(NE) HCLK HCLK t FSMC_NEx low to FSMC_NWE low t – 0.5 t + 1.5 ns v(NWE_NE) HCLK HCLK t FSMC_NWE low time t – 0.5 t + 1.5 ns w(NWE) HCLK HCLK t FSMC_NWE high to FSMC_NE high hold time t - ns h(NE_NWE) HCLK t FSMC_NEx low to FSMC_A valid - 7.5 ns v(A_NE) t Address hold time after FSMC_NWE high t - ns h(A_NWE) HCLK t FSMC_NEx low to FSMC_BL valid - 0 ns v(BL_NE) t FSMC_BL hold time after FSMC_NWE high t – 0.5 - ns h(BL_NWE) HCLK t FSMC_NEx low to Data valid - t + 7 ns v(Data_NE) HCLK t Data hold time after FSMC_NWE high t - ns h(Data_NWE) HCLK t FSMC_NEx low to FSMC_NADV low - 5.5 ns v(NADV_NE) t FSMC_NADV low time - t + 1.5 ns w(NADV) HCLK 1. C = 15 pF. L 2. Guaranteed by characterization results. Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms (cid:84)(cid:87)(cid:8)(cid:46)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:37) (cid:84)(cid:86)(cid:8)(cid:46)(cid:47)(cid:37)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:72)(cid:8)(cid:46)(cid:37)(cid:63)(cid:46)(cid:47)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:47)(cid:37) (cid:84)(cid:87)(cid:8)(cid:46)(cid:47)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:37) (cid:84)(cid:86)(cid:8)(cid:33)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:72)(cid:8)(cid:33)(cid:63)(cid:46)(cid:47)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:59)(cid:18)(cid:21)(cid:26)(cid:17)(cid:22)(cid:61) (cid:33)(cid:68)(cid:68)(cid:82)(cid:69)(cid:83)(cid:83) (cid:84)(cid:86)(cid:8)(cid:34)(cid:44)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:72)(cid:8)(cid:34)(cid:44)(cid:63)(cid:46)(cid:47)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:34)(cid:44)(cid:59)(cid:17)(cid:26)(cid:16)(cid:61) (cid:46)(cid:34)(cid:44) (cid:84)(cid:72)(cid:8)(cid:36)(cid:65)(cid:84)(cid:65)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:36)(cid:65)(cid:84)(cid:65)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:86)(cid:8)(cid:33)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:36)(cid:65)(cid:84)(cid:65)(cid:63)(cid:46)(cid:47)(cid:37)(cid:9) (cid:84)(cid:72)(cid:8)(cid:36)(cid:65)(cid:84)(cid:65)(cid:63)(cid:46)(cid:47)(cid:37)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:33)(cid:68)(cid:68)(cid:82)(cid:69)(cid:83)(cid:83) (cid:36)(cid:65)(cid:84)(cid:65) (cid:84)(cid:86)(cid:8)(cid:46)(cid:33)(cid:36)(cid:54)(cid:63)(cid:46)(cid:37)(cid:9) (cid:84)(cid:72)(cid:8)(cid:33)(cid:36)(cid:63)(cid:46)(cid:33)(cid:36)(cid:54)(cid:9) (cid:84)(cid:87)(cid:8)(cid:46)(cid:33)(cid:36)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:33)(cid:36)(cid:54) (cid:65)(cid:73)(cid:17)(cid:20)(cid:24)(cid:25)(cid:18)(cid:66) 68/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit t FSMC_NE low time 7t – 2 7t + 2 ns w(NE) HCLK HCLK t FSMC_NEx low to FSMC_NOE low 3t – 0.5 3t + 1.5 ns v(NOE_NE) HCLK HCLK t FSMC_NOE low time 4t – 1 4t + 2 ns w(NOE) HCLK HCLK t FSMC_NOE high to FSMC_NE high hold time –1 - ns h(NE_NOE) t FSMC_NEx low to FSMC_A valid - 0 ns v(A_NE) t FSMC_NEx low to FSMC_NADV low 3 5 ns v(NADV_NE) t FSMC_NADV low time t –1.5 t + 1.5 ns w(NADV) HCLK HCLK FSMC_AD (address) valid hold time after t t - ns h(AD_NADV) FSMC_NADV high HCLK t Address hold time after FSMC_NOE high t -2 - ns h(A_NOE) HCLK t FSMC_BL hold time after FSMC_NOE high 0 - ns h(BL_NOE) t FSMC_NEx low to FSMC_BL valid - 0 ns v(BL_NE) t Data to FSMC_NEx high setup time 2t + 24 - ns su(Data_NE) HCLK t Data to FSMC_NOE high setup time 2t + 25 - ns su(Data_NOE) HCLK t Data hold time after FSMC_NEx high 0 - ns h(Data_NE) t Data hold time after FSMC_NOE high 0 - ns h(Data_NOE) 1. C = 15 pF. L 2. Guaranteed by characterization results. DS5792 Rev 13 69/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms (cid:87)(cid:90)(cid:11)(cid:49)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:40)(cid:91) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:40)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:89)(cid:11)(cid:36)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:36)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:21)(cid:24)(cid:29)(cid:20)(cid:25)(cid:64) (cid:36)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:87)(cid:89)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:37)(cid:47)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:37)(cid:47)(cid:62)(cid:20)(cid:29)(cid:19)(cid:64) (cid:49)(cid:37)(cid:47) (cid:87)(cid:89)(cid:11)(cid:36)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:89)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57)(cid:12) (cid:87)(cid:75)(cid:11)(cid:39)(cid:68)(cid:87)(cid:68)(cid:66)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:36)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:39)(cid:68)(cid:87)(cid:68) (cid:87)(cid:89)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:66)(cid:49)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:36)(cid:39)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:36)(cid:39)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:20)(cid:37) Table 34. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit t FSMC_NE low time 5t – 1 5t + 2 ns w(NE) HCLK HCLK t FSMC_NEx low to FSMC_NWE low 2t 2t + 1 ns v(NWE_NE) HCLK HCLK t FSMC_NWE low time 2t – 1 2t + 2 ns w(NWE) HCLK HCLK t FSMC_NWE high to FSMC_NE high hold time t – 1 - ns h(NE_NWE) HCLK t FSMC_NEx low to FSMC_A valid - 7 ns v(A_NE) t FSMC_NEx low to FSMC_NADV low 3 5 ns v(NADV_NE) t FSMC_NADV low time t – 1 t + 1 ns w(NADV) HCLK HCLK FSMC_AD (address) valid hold time after t t – 3 - ns h(AD_NADV) FSMC_NADV high HCLK t Address hold time after FSMC_NWE high 4t - ns h(A_NWE) HCLK t FSMC_NEx low to FSMC_BL valid - 1.6 ns v(BL_NE) t FSMC_BL hold time after FSMC_NWE high t – 1.5 - ns h(BL_NWE) HCLK t FSMC_NADV high to Data valid - t + 1.5 ns v(Data_NADV) HCLK t Data hold time after FSMC_NWE high t – 5 - ns h(Data_NWE) HCLK 1. C = 15 pF. L 2. BGuaranteed by characterization results. 70/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Synchronous waveforms and timings Figure28 through Figure31 represent synchronous waveforms and Table36 through Table38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 28. Synchronous multiplexed NOR/PSRAM read timings (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:34)(cid:53)(cid:51)(cid:52)(cid:53)(cid:50)(cid:46)(cid:0)(cid:29)(cid:0)(cid:16) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:35)(cid:44)(cid:43) (cid:36)(cid:65)(cid:84)(cid:65)(cid:0)(cid:76)(cid:65)(cid:84)(cid:69)(cid:78)(cid:67)(cid:89)(cid:0)(cid:29)(cid:0)(cid:16) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:37)(cid:88) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:33)(cid:36)(cid:54) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:41)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:59)(cid:18)(cid:21)(cid:26)(cid:17)(cid:22)(cid:61) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:47)(cid:37)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:47)(cid:37)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:47)(cid:37) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:36)(cid:41)(cid:54)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:33)(cid:36)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:36)(cid:54)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:33)(cid:36)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:33)(cid:36)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:33)(cid:36)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:33)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:36)(cid:17) (cid:36)(cid:18) (cid:36)(cid:19) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52) (cid:8)(cid:55)(cid:33)(cid:41)(cid:52)(cid:35)(cid:38)(cid:39)(cid:0)(cid:29)(cid:0)(cid:17)(cid:66)(cid:12)(cid:0)(cid:55)(cid:33)(cid:41)(cid:52)(cid:48)(cid:47)(cid:44)(cid:0)(cid:11)(cid:0)(cid:16)(cid:66)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52) (cid:8)(cid:55)(cid:33)(cid:41)(cid:52)(cid:35)(cid:38)(cid:39)(cid:0)(cid:29)(cid:0)(cid:16)(cid:66)(cid:12)(cid:0)(cid:55)(cid:33)(cid:41)(cid:52)(cid:48)(cid:47)(cid:44)(cid:0)(cid:11)(cid:0)(cid:16)(cid:66)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:24)(cid:25)(cid:19)(cid:73) DS5792 Rev 13 71/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit t FSMC_CLK period 27.7 - ns w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low - 4 ns d(CLKL-NADVL) t FSMC_CLK low to FSMC_NADV high 5 - ns d(CLKL-NADVH) t FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns d(CLKL-AV) t FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns d(CLKL-AIV) t FSMC_CLK low to FSMC_NOE low - 1 ns d(CLKL-NOEL) t FSMC_CLK low to FSMC_NOE high 1.5 - ns d(CLKL-NOEH) t FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns d(CLKL-ADV) t FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns d(CLKL-ADIV) FSMC_A/D[15:0] valid data before FSMC_CLK t 6 - ns su(ADV-CLKH) high t FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns h(CLKH-ADV) t FSMC_NWAIT valid before FSMC_CLK high 8 - ns su(NWAITV-CLKH) t FSMC_NWAIT valid after FSMC_CLK high 2 - ns h(CLKH-NWAITV) 1. C = 15 pF. L 2. Guaranteed by characterization results. 72/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 29. Synchronous multiplexed PSRAM write timings (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:34)(cid:53)(cid:51)(cid:52)(cid:53)(cid:50)(cid:46)(cid:0)(cid:29)(cid:0)(cid:16) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:35)(cid:44)(cid:43) (cid:36)(cid:65)(cid:84)(cid:65)(cid:0)(cid:76)(cid:65)(cid:84)(cid:69)(cid:78)(cid:67)(cid:89)(cid:0)(cid:29)(cid:0)(cid:16) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:37)(cid:88) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:33)(cid:36)(cid:54) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:41)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:59)(cid:18)(cid:21)(cid:26)(cid:17)(cid:22)(cid:61) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:55)(cid:37)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:55)(cid:37)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:37) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:36)(cid:41)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:36)(cid:65)(cid:84)(cid:65)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:36)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:36)(cid:65)(cid:84)(cid:65)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:33)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:36)(cid:17) (cid:36)(cid:18) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52) (cid:8)(cid:55)(cid:33)(cid:41)(cid:52)(cid:35)(cid:38)(cid:39)(cid:0)(cid:29)(cid:0)(cid:16)(cid:66)(cid:12)(cid:0)(cid:55)(cid:33)(cid:41)(cid:52)(cid:48)(cid:47)(cid:44)(cid:0)(cid:11)(cid:0)(cid:16)(cid:66)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:34)(cid:44)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:34)(cid:44) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:25)(cid:18)(cid:71) DS5792 Rev 13 73/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 36. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit t FSMC_CLK period 27.7 - ns w(CLK) t FSMC_CLK low to FSMC_Nex low (x = 0...2) - 2 ns d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low - 4 ns d(CLKL-NADVL) t FSMC_CLK low to FSMC_NADV high 5 - ns d(CLKL-NADVH) t FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns d(CLKL-AV) t FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns d(CLKL-AIV) t FSMC_CLK low to FSMC_NWE low - 1 ns d(CLKL-NWEL) t FSMC_CLK low to FSMC_NWE high 1 - ns d(CLKL-NWEH) t FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns d(CLKL-ADV) t FSMC_CLK low to FSMC_AD[15:0] invalid 3 - ns d(CLKL-ADIV) t FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns d(CLKL-Data) t FSMC_CLK low to FSMC_NBL high 1 - ns d(CLKL-NBLH) t FSMC_NWAIT valid before FSMC_CLK high 7 - ns su(NWAITV-CLKH) t FSMC_NWAIT valid after FSMC_CLK high 2 - ns h(CLKH-NWAITV) 1. C = 15 pF. L 2. Guaranteed by characterization results. 74/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:84)(cid:87)(cid:8)(cid:35)(cid:44)(cid:43)(cid:9) (cid:34)(cid:53)(cid:51)(cid:52)(cid:53)(cid:50)(cid:46)(cid:0)(cid:29)(cid:0)(cid:16) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:35)(cid:44)(cid:43) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:37)(cid:88)(cid:40)(cid:9) (cid:36)(cid:65)(cid:84)(cid:65)(cid:0)(cid:76)(cid:65)(cid:84)(cid:69)(cid:78)(cid:67)(cid:89)(cid:0)(cid:29)(cid:0)(cid:16) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:37)(cid:88) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:33)(cid:36)(cid:54)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:33)(cid:36)(cid:54) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:54)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:33)(cid:41)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:33)(cid:59)(cid:18)(cid:21)(cid:26)(cid:16)(cid:61) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:47)(cid:37)(cid:44)(cid:9) (cid:84)(cid:68)(cid:8)(cid:35)(cid:44)(cid:43)(cid:44)(cid:13)(cid:46)(cid:47)(cid:37)(cid:40)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:47)(cid:37) (cid:84)(cid:83)(cid:85)(cid:8)(cid:36)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:36)(cid:54)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:36)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:36)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:36)(cid:59)(cid:17)(cid:21)(cid:26)(cid:16)(cid:61) (cid:36)(cid:17) (cid:36)(cid:18) (cid:36)(cid:19) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52) (cid:8)(cid:55)(cid:33)(cid:41)(cid:52)(cid:35)(cid:38)(cid:39)(cid:0)(cid:29)(cid:0)(cid:17)(cid:66)(cid:12)(cid:0)(cid:55)(cid:33)(cid:41)(cid:52)(cid:48)(cid:47)(cid:44)(cid:0)(cid:11)(cid:0)(cid:16)(cid:66)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:38)(cid:51)(cid:45)(cid:35)(cid:63)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52) (cid:8)(cid:55)(cid:33)(cid:41)(cid:52)(cid:35)(cid:38)(cid:39)(cid:0)(cid:29)(cid:0)(cid:16)(cid:66)(cid:12)(cid:0)(cid:55)(cid:33)(cid:41)(cid:52)(cid:48)(cid:47)(cid:44)(cid:0)(cid:11)(cid:0)(cid:16)(cid:66)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:13)(cid:35)(cid:44)(cid:43)(cid:40)(cid:9) (cid:84)(cid:72)(cid:8)(cid:35)(cid:44)(cid:43)(cid:40)(cid:13)(cid:46)(cid:55)(cid:33)(cid:41)(cid:52)(cid:54)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:24)(cid:25)(cid:20)(cid:72) Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit t FSMC_CLK period 27.7 - ns w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low - 4 ns d(CLKL-NADVL) t FSMC_CLK low to FSMC_NADV high 5 - ns d(CLKL-NADVH) t FSMC_CLK low to FSMC_Ax valid (x = 0...25) - 0 ns d(CLKL-AV) t FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 4 - ns d(CLKL-AIV) t FSMC_CLK low to FSMC_NOE low - 1.5 ns d(CLKL-NOEL) t FSMC_CLK low to FSMC_NOE high 1.5 - ns d(CLKL-NOEH) FSMC_D[15:0] valid data before FSMC_CLK t 6.5 - ns su(DV-CLKH) high t FSMC_D[15:0] valid data after FSMC_CLK high 7 - ns h(CLKH-DV) t FSMC_NWAIT valid before FSMC_SMCLK high 7 - ns su(NWAITV-CLKH) t FSMC_NWAIT valid after FSMC_CLK high 2 - ns h(CLKH-NWAITV) 1. C = 15 pF. L 2. Guaranteed by characterization results. DS5792 Rev 13 75/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 31. Synchronous non-multiplexed PSRAM write timings (cid:87)(cid:90)(cid:11)(cid:38)(cid:47)(cid:46)(cid:12) (cid:87)(cid:90)(cid:11)(cid:38)(cid:47)(cid:46)(cid:12) (cid:37)(cid:56)(cid:54)(cid:55)(cid:56)(cid:53)(cid:49)(cid:3)(cid:32)(cid:3)(cid:19) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:38)(cid:47)(cid:46) (cid:39)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:68)(cid:87)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:32)(cid:3)(cid:19) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:49)(cid:40)(cid:91)(cid:47)(cid:12) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:49)(cid:40)(cid:91)(cid:43)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:40)(cid:91) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:49)(cid:36)(cid:39)(cid:57)(cid:47)(cid:12) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:49)(cid:36)(cid:39)(cid:57)(cid:43)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:36)(cid:39)(cid:57) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:36)(cid:57)(cid:12) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:36)(cid:44)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:21)(cid:24)(cid:29)(cid:20)(cid:25)(cid:64) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:49)(cid:50)(cid:40)(cid:47)(cid:12) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:49)(cid:50)(cid:40)(cid:43)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:36)(cid:39)(cid:44)(cid:57)(cid:12) (cid:87)(cid:75)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:36)(cid:39)(cid:57)(cid:12) (cid:87)(cid:71)(cid:11)(cid:38)(cid:47)(cid:46)(cid:47)(cid:16)(cid:36)(cid:39)(cid:57)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:36)(cid:39)(cid:57)(cid:16)(cid:38)(cid:47)(cid:46)(cid:43)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:36)(cid:39)(cid:57)(cid:16)(cid:38)(cid:47)(cid:46)(cid:43)(cid:12) (cid:87)(cid:75)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:36)(cid:39)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:36)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:39)(cid:20) (cid:39)(cid:21) (cid:87)(cid:86)(cid:88)(cid:11)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:16)(cid:38)(cid:47)(cid:46)(cid:43)(cid:12) (cid:87)(cid:75)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55) (cid:11)(cid:58)(cid:36)(cid:44)(cid:55)(cid:38)(cid:41)(cid:42)(cid:3)(cid:32)(cid:3)(cid:20)(cid:69)(cid:15)(cid:3)(cid:58)(cid:36)(cid:44)(cid:55)(cid:51)(cid:50)(cid:47)(cid:3)(cid:14)(cid:3)(cid:19)(cid:69)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:16)(cid:38)(cid:47)(cid:46)(cid:43)(cid:12) (cid:87)(cid:75)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55) (cid:11)(cid:58)(cid:36)(cid:44)(cid:55)(cid:38)(cid:41)(cid:42)(cid:3)(cid:32)(cid:3)(cid:19)(cid:69)(cid:15)(cid:3)(cid:58)(cid:36)(cid:44)(cid:55)(cid:51)(cid:50)(cid:47)(cid:3)(cid:14)(cid:3)(cid:19)(cid:69)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:16)(cid:38)(cid:47)(cid:46)(cid:43)(cid:12) (cid:87)(cid:75)(cid:11)(cid:38)(cid:47)(cid:46)(cid:43)(cid:16)(cid:49)(cid:58)(cid:36)(cid:44)(cid:55)(cid:57)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:22)(cid:75) Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit t FSMC_CLK period 27.7 - ns w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) - 2 ns d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low - 4 ns d(CLKL-NADVL) t FSMC_CLK low to FSMC_NADV high 5 - ns d(CLKL-NADVH) t FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns d(CLKL-AV) t FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns d(CLKL-AIV) t FSMC_CLK low to FSMC_NWE low - 1 ns d(CLKL-NWEL) t FSMC_CLK low to FSMC_NWE high 1 - ns d(CLKL-NWEH) t FSMC_D[15:0] valid data after FSMC_CLK low - 6 ns d(CLKL-Data) t FSMC_CLK low to FSMC_NBL high 1 - ns d(CLKL-NBLH) t FSMC_NWAIT valid before FSMC_CLK high 7 - ns su(NWAITV-CLKH) t FSMC_NWAIT valid after FSMC_CLK high 2 - ns h(CLKH-NWAITV) 1. C = 15 pF. L 2. Guaranteed by characterization results. 76/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure32 through Figure37 represent synchronous waveforms and Table39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; Figure 32. PC Card/CompactFlash controller waveforms for common memory read access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21)(cid:11)(cid:20)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:91)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:91)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:87)(cid:87)(cid:71)(cid:71)(cid:11)(cid:11)(cid:49)(cid:49)(cid:53)(cid:44)(cid:50)(cid:40)(cid:53)(cid:42)(cid:39)(cid:16)(cid:49)(cid:16)(cid:49)(cid:38)(cid:38)(cid:40)(cid:40)(cid:91)(cid:91)(cid:12)(cid:12) (cid:87)(cid:87)(cid:87)(cid:75)(cid:75)(cid:75)(cid:11)(cid:11)(cid:11)(cid:49)(cid:49)(cid:49)(cid:38)(cid:38)(cid:38)(cid:40)(cid:40)(cid:40)(cid:91)(cid:91)(cid:91)(cid:16)(cid:16)(cid:16)(cid:49)(cid:49)(cid:49)(cid:44)(cid:53)(cid:44)(cid:50)(cid:50)(cid:40)(cid:58)(cid:53)(cid:42)(cid:39)(cid:53)(cid:12)(cid:12)(cid:3)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:71)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:50)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:24)(cid:69) 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. DS5792 Rev 13 77/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 33. PC Card/CompactFlash controller waveforms for common memory write access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21) (cid:43)(cid:76)(cid:74)(cid:75) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:87)(cid:87)(cid:71)(cid:71)(cid:11)(cid:11)(cid:49)(cid:49)(cid:53)(cid:44)(cid:50)(cid:40)(cid:53)(cid:42)(cid:39)(cid:16)(cid:49)(cid:16)(cid:49)(cid:38)(cid:38)(cid:40)(cid:40)(cid:23)(cid:23)(cid:66)(cid:66)(cid:20)(cid:20)(cid:12)(cid:12) (cid:87)(cid:87)(cid:87)(cid:75)(cid:75)(cid:75)(cid:11)(cid:11)(cid:11)(cid:49)(cid:49)(cid:49)(cid:38)(cid:38)(cid:38)(cid:40)(cid:40)(cid:40)(cid:23)(cid:23)(cid:23)(cid:66)(cid:66)(cid:66)(cid:20)(cid:20)(cid:20)(cid:16)(cid:16)(cid:16)(cid:49)(cid:49)(cid:49)(cid:53)(cid:44)(cid:44)(cid:50)(cid:50)(cid:40)(cid:53)(cid:58)(cid:42)(cid:39)(cid:53)(cid:12)(cid:12)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:87)(cid:71)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:71)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:48)(cid:40)(cid:48)(cid:91)(cid:43)(cid:44)(cid:61)(cid:3)(cid:32)(cid:20) (cid:87)(cid:71)(cid:11)(cid:39)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:25)(cid:69) 78/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21) (cid:43)(cid:76)(cid:74)(cid:75) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:87)(cid:71)(cid:11)(cid:49)(cid:53)(cid:40)(cid:42)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:53)(cid:40)(cid:42)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:71)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:71)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64)(cid:11)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:26)(cid:69) 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DS5792 Rev 13 79/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21) (cid:43)(cid:76)(cid:74)(cid:75) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:87)(cid:71)(cid:11)(cid:49)(cid:53)(cid:40)(cid:42)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:53)(cid:40)(cid:42)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:87)(cid:71)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:58)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:71)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:26)(cid:29)(cid:19)(cid:64)(cid:11)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:27)(cid:69) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:91)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:87)(cid:71)(cid:11)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39)(cid:16)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:16)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39)(cid:12) (cid:87)(cid:71)(cid:11)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:27)(cid:28)(cid:28)(cid:37) 80/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:21) (cid:87)(cid:89)(cid:11)(cid:49)(cid:38)(cid:40)(cid:91)(cid:16)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:36)(cid:44)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:62)(cid:20)(cid:19)(cid:29)(cid:19)(cid:64) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:53)(cid:40)(cid:42) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:53)(cid:39) (cid:87)(cid:71)(cid:11)(cid:49)(cid:38)(cid:40)(cid:23)(cid:66)(cid:20)(cid:16)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53) (cid:36)(cid:55)(cid:55)(cid:91)(cid:43)(cid:44)(cid:61)(cid:3)(cid:32)(cid:20) (cid:87)(cid:75)(cid:11)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53)(cid:16)(cid:39)(cid:12) (cid:87)(cid:89)(cid:11)(cid:49)(cid:44)(cid:50)(cid:58)(cid:53)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:19)(cid:19)(cid:70) Ta b le 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) Symbol Parameter Min Max Unit FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = t v(NCEx-A) 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay - 0 ns t v(NCE4_1-A) valid (y = 0...10) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = t h(NCEx-AI) 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax 2.5 - ns t h(NCE4_1-AI) invalid (x = 0...10) t FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 d(NREG-NCEx) - 5 ns t low to FSMC_NREG valid d(NREG-NCE4_1) t FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 h(NCEx-NREG) t + 3 - ns t high to FSMC_NREG invalid HCLK h(NCE4_1-NREG) t FSMC_NCE4_1 low to FSMC_NOE low - 5t + 2 ns d(NCE4_1-NOE) HCLK t FSMC_NOE low width 8t –1.5 8t + 1 ns w(NOE) HCLK HCLK t FSMC_NOE high to FSMC_NCE4_1 high 5t + 2 - ns d(NOE-NCE4_1 HCLK t FSMC_D[15:0] valid data before FSMC_NOE high 25 - ns su(D-NOE) t FSMC_D[15:0] valid data after FSMC_NOE high 15 - ns h(NOE-D) t FSMC_NWE low width 8t – 1 8t + 2 ns w(NWE) HCLK HCLK t FSMC_NWE high to FSMC_NCE4_1 high 5t + 2 - ns d(NWE-NCE4_1) HCLK t FSMC_NCE4_1 low to FSMC_NWE low - 5t + 1.5 ns d(NCE4_1-NWE) HCLK t FSMC_NWE low to FSMC_D[15:0] valid - 0 ns v(NWE-D) t FSMC_NWE high to FSMC_D[15:0] invalid 11t - ns h(NWE-D) HCLK t FSMC_D[15:0] valid before FSMC_NWE high 13t - ns d(D-NWE) HCLK DS5792 Rev 13 81/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Symbol Parameter Min Max Unit t FSMC_NIOWR low width 8t + 3 - ns w(NIOWR) HCLK t FSMC_NIOWR low to FSMC_D[15:0] valid - 5t +1 ns v(NIOWR-D) HCLK t FSMC_NIOWR high to FSMC_D[15:0] invalid 11t - ns h(NIOWR-D) HCLK t FSMC_NCE4_1 low to FSMC_NIOWR valid - 5t +3ns ns d(NCE4_1-NIOWR) HCLK t FSMC_NCEx high to FSMC_NIOWR invalid h(NCEx-NIOWR) 5t – 5 - ns t FSMC_NCE4_1 high to FSMC_NIOWR invalid HCLK h(NCE4_1-NIOWR) t FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 d(NIORD-NCEx) - 5t + 2.5 ns t low to FSMC_NIORD valid HCLK d(NIORD-NCE4_1) t FSMC_NCEx high to FSMC_NIORD invalid h(NCEx-NIORD) 5t – 5 - ns t FSMC_NCE4_1 high to FSMC_NIORD invalid HCLK h(NCE4_1-NIORD) t FSMC_D[15:0] valid before FSMC_NIORD high 4.5 - ns su(D-NIORD) t FSMC_D[15:0] valid after FSMC_NIORD high 9 - ns d(NIORD-D) t FSMC_NIORD low width 8t + 2 - ns w(NIORD) HCLK 1. C = 15 pF. L 2. Guaranteed by characterization results. 82/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics NAND controller waveforms and timings Figure38 through Figure41 represent synchronous waveforms and Table39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; Figure 38. NAND controller waveforms for read access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:91) (cid:47)(cid:82)(cid:90) (cid:36)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:26)(cid:12) (cid:38)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:25)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:71)(cid:11)(cid:36)(cid:47)(cid:40)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:36)(cid:47)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40)(cid:3)(cid:11)(cid:49)(cid:53)(cid:40)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:19)(cid:20)(cid:69) DS5792 Rev 13 83/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 39. NAND controller waveforms for write access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:91) (cid:36)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:26)(cid:12) (cid:38)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:25)(cid:12) (cid:87)(cid:71)(cid:11)(cid:36)(cid:47)(cid:40)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:36)(cid:47)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40)(cid:3)(cid:11)(cid:49)(cid:53)(cid:40)(cid:12) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:18)(cid:67) Figure 40. NAND controller waveforms for common memory read access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:91) (cid:47)(cid:82)(cid:90) (cid:36)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:26)(cid:12) (cid:38)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:25)(cid:12) (cid:87)(cid:71)(cid:11)(cid:36)(cid:47)(cid:40)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:36)(cid:47)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:87)(cid:90)(cid:11)(cid:49)(cid:50)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:86)(cid:88)(cid:11)(cid:39)(cid:16)(cid:49)(cid:50)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:50)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:20)(cid:21)(cid:69) 84/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 41. NAND controller waveforms for common memory write access (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:38)(cid:40)(cid:91) (cid:47)(cid:82)(cid:90) (cid:36)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:26)(cid:12) (cid:38)(cid:47)(cid:40)(cid:3)(cid:11)(cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:36)(cid:20)(cid:25)(cid:12) (cid:87)(cid:71)(cid:11)(cid:36)(cid:47)(cid:40)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:36)(cid:47)(cid:40)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:58)(cid:40) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:49)(cid:50)(cid:40) (cid:87)(cid:71)(cid:11)(cid:39)(cid:16)(cid:49)(cid:58)(cid:40)(cid:12) (cid:87)(cid:89)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:58)(cid:40)(cid:16)(cid:39)(cid:12) (cid:41)(cid:54)(cid:48)(cid:38)(cid:66)(cid:39)(cid:62)(cid:20)(cid:24)(cid:29)(cid:19)(cid:64) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:20)(cid:22)(cid:69) Table 40. Switching characteristics for NAND Flash read and write cycles(1) Symbol Parameter Min Max Unit t (2) FSMC_D[15:0] valid before FSMC_NWE high 5t + 12 - ns d(D-NWE) HCLK t (2) FSMC_NWE low width 4t 4t ns w(NOE) HCLK-1.5 HCLK+1.5 FSMC_D[15:0] valid data before t (2) FSMC_NOE ns su(D-NOE) 25 - high t (2) FSMC_D[15:0] valid data after FSMC_NOE high 7 - - h(NOE-D) t (2) FSMC_NWE low width 4t 4t ns w(NWE) HCLK-1 HCLK+1 t (2) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns v(NWE-D) t (2) FSMC_NWE high to FSMC_D[15:0] invalid 2t + 4 - ns h(NWE-D) HCLK t (3) FSMC_ALE valid before FSMC_NWE low - 3t + 1.5 ns d(ALE-NWE) HCLK t (3) FSMC_NWE high to FSMC_ALE invalid 3t + 4.5 - ns h(NWE-ALE) HCLK t (3) FSMC_ALE valid before FSMC_NOE low - 3t + 2 ns d(ALE-NOE) HCLK t (3) FSMC_NWE high to FSMC_ALE invalid 3t + 4.5 - ns h(NOE-ALE) HCLK 1. C = 15 pF. L 2. Guaranteed by characterization results. 3. Guaranteed by design. DS5792 Rev 13 85/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and DD V through a 100 pF capacitor, until a functional disturbance occurs. This test is SS compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Level/ Symbol Parameter Conditions Class V = 3.3 V, LQFP144, T = +25 °C, Voltage limits to be applied on any I/O pin to DD A V f = 72 MHz 2B FESD induce a functional disturbance HCLK conforms to IEC 61000-4-2 V = 3.3 V, LQFP144, T = +25 Fast transient voltage burst limits to be DD A °C, V applied through 100 pF on V and V 4A EFTB DD SS f = 72 MHz pins to induce a functional disturbance HCLK conforms to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. 86/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Max vs. [f /f ] Monitored HSE HCLK Symbol Parameter Conditions Unit frequency band 8/48 MHz 8/72 MHz 0.1 to 30 MHz 8 12 V = 3.3 V, T = 25°C, DD A LQFP144 package 30 to 130 MHz 31 21 dBµV S Peak level EMI compliant with IEC 130 MHz to 1GHz 28 33 61967-2 SAE EMI Level 4 4 - 5.3.12 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 43. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) Electrostatic discharge voltage T = +25 °C, conforming to V A 2 2000 ESD(HBM) (human body model) JESD22-A114 V Electrostatic discharge voltage T = +25 °C, conforming to V A III 500 ESD(CDM) (charge device model) JESD22-C101 1. Guaranteed by characterization results. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. DS5792 Rev 13 87/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 44. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +105 °C conforming to JESD78A II level A A 5.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table45 Table 45. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on OSC_IN32, -0 +0 OSC_OUT32, PA4, PA5, PC13 I mA INJ Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 88/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table46 are derived from tests performed under the conditions summarized in Table10. All I/Os are CMOS and TTL compliant. Table 46. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit Standard IO input low –0.3 - 0.28*(V -2 V)+0.8 V V level voltage DD V - IL IO FT(1) input low level –0.3 - 0.32*(V -2 V)+0.75 V V voltage DD Standard IO input high 0.41*(V -2 V)+1.3 - DD - V +0.3 V level voltage V DD V IH IO FT(1) input high level VDD > 2 V 5.5 0.42*(V -2 V)+1 V - V voltage V ≤ 2 V DD 5.2 DD Standard IO Schmitt trigger voltage 200 - - mV V hysteresis(2) - hys IO FT Schmitt trigger 5% V (3) - - mV voltage hysteresis(2) DD V ≤V ≤V SS IN DD - - ±1 Standard I/Os I Input leakage current (4) µA lkg VIN= 5 V, - - 3 I/O FT Weak pull-up equivalent R V = V 30 40 50 kΩ PU resistor(5) IN SS Weak pull-down R V = V 30 40 50 kΩ PD equivalent resistor(5) IN DD C I/O pin capacitance - - 5 - pF IO 1. FT = Five-volt tolerant. In order to sustain a voltage higher than V +0.3 the internal pull-up/pull-down resistors must be DD disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure42 and Figure43 for standard I/Os, and in Figure44 and Figure45 for 5V tolerant I/Os. DS5792 Rev 13 89/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42. Standard I/O input characteristics - CMOS port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:22)(cid:21)(cid:54)(cid:18)(cid:17)(cid:15)(cid:36)(cid:22)(cid:14)(cid:21)(cid:26)(cid:36)(cid:25)(cid:0) (cid:54)(cid:18)(cid:41)(cid:15)(cid:40)(cid:24)(cid:18)(cid:29)(cid:16)(cid:14)(cid:20)(cid:17)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:18)(cid:17)(cid:15)(cid:24)(cid:14)(cid:18)(cid:19) (cid:18)(cid:15)(cid:26)(cid:23) (cid:41)(cid:78)(cid:80)(cid:85)(cid:84)(cid:0)(cid:82)(cid:65)(cid:78)(cid:71)(cid:69)(cid:0) (cid:55)(cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:17)(cid:14)(cid:19) (cid:18)(cid:17) (cid:18)(cid:15)(cid:17)(cid:25) (cid:18)(cid:15)(cid:17)(cid:25) (cid:18)(cid:15)(cid:19)(cid:22) (cid:78)(cid:79)(cid:84)(cid:0)(cid:71)(cid:85)(cid:65)(cid:82)(cid:65)(cid:78)(cid:84)(cid:69)(cid:69)(cid:68) (cid:55)(cid:41)(cid:44)(cid:77)(cid:65)(cid:88)(cid:16)(cid:16)(cid:14)(cid:14)(cid:24)(cid:23) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:21)(cid:54)(cid:36)(cid:36) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:18)(cid:24)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:16)(cid:14)(cid:24) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:23) (cid:19) (cid:19)(cid:14)(cid:19) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:23)(cid:66) Figure 43. Standard I/O input characteristics - TTL port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:55) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0) (cid:54)(cid:41)(cid:40)(cid:29)(cid:18)(cid:54) (cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:18)(cid:14)(cid:16) (cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:20)(cid:17)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:17)(cid:14)(cid:19) (cid:17)(cid:14)(cid:25)(cid:22) (cid:78)(cid:79)(cid:41)(cid:78)(cid:84)(cid:0)(cid:80)(cid:71)(cid:85)(cid:85)(cid:84)(cid:65)(cid:0)(cid:82)(cid:82)(cid:65)(cid:65)(cid:78)(cid:78)(cid:71)(cid:84)(cid:69)(cid:69)(cid:69)(cid:0)(cid:68) (cid:17)(cid:14)(cid:19) (cid:17)(cid:14)(cid:18)(cid:21) (cid:55) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:18)(cid:24)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:16)(cid:14)(cid:24) (cid:41)(cid:44)(cid:77)(cid:65)(cid:88) (cid:16)(cid:14)(cid:24) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:24)(cid:54) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:17)(cid:22) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:24) Figure 44. 5V tolerant I/O input characteristics - CMOS port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:22)(cid:21)(cid:54)(cid:36)(cid:36) (cid:17)(cid:14)(cid:20)(cid:18) (cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:20)(cid:18)(cid:8)(cid:54)(cid:36)(cid:17)(cid:17)(cid:36)(cid:14)(cid:14)(cid:21)(cid:17)(cid:13)(cid:18)(cid:21)(cid:22)(cid:9)(cid:11)(cid:17) (cid:17)(cid:17)(cid:14)(cid:22)(cid:23) (cid:41)(cid:78)(cid:80)(cid:85)(cid:84)(cid:0)(cid:82)(cid:65)(cid:78)(cid:71)(cid:69)(cid:0) (cid:17)(cid:14)(cid:19) (cid:17)(cid:14)(cid:18)(cid:25)(cid:21) (cid:17)(cid:14)(cid:16)(cid:23) (cid:78)(cid:79)(cid:84)(cid:0)(cid:71)(cid:85)(cid:65)(cid:82)(cid:65)(cid:78)(cid:84)(cid:69)(cid:69)(cid:68) (cid:17) (cid:16)(cid:14)(cid:25)(cid:23)(cid:21) (cid:16)(cid:14)(cid:23) (cid:16)(cid:14)(cid:23)(cid:21) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:21)(cid:54)(cid:36)(cid:36) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:18)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:16)(cid:14)(cid:23)(cid:21) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:23) (cid:19) (cid:19)(cid:14)(cid:19) (cid:19)(cid:14)(cid:22) (cid:54)(cid:36)(cid:36) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:25)(cid:66) 90/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 45. 5V tolerant I/O input characteristics - TTL port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:18)(cid:54) (cid:18)(cid:14)(cid:16) (cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:20)(cid:18)(cid:10)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:17) (cid:17)(cid:14)(cid:22)(cid:23) (cid:41)(cid:78)(cid:80)(cid:85)(cid:84)(cid:0)(cid:82)(cid:65)(cid:78)(cid:71)(cid:69) (cid:17) (cid:78)(cid:79)(cid:84)(cid:0)(cid:71)(cid:85)(cid:65)(cid:82)(cid:65)(cid:78)(cid:84)(cid:69)(cid:69)(cid:68)(cid:0) (cid:55) (cid:55)(cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:18)(cid:10)(cid:8)(cid:54)(cid:36)(cid:36)(cid:13)(cid:18)(cid:9)(cid:11)(cid:16)(cid:14)(cid:23)(cid:21) (cid:41)(cid:44)(cid:77)(cid:65)(cid:88) (cid:16)(cid:14)(cid:24) (cid:16)(cid:14)(cid:23)(cid:21) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:24)(cid:54)(cid:0) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:17)(cid:22) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:24)(cid:16) Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V V ) except PC13, PC14 and PC15 which can OL/ OH sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section5.2: • The sum of the currents sourced by all the I/Os on V plus the maximum Run DD, consumption of the MCU sourced on V cannot exceed the absolute maximum rating DD, I (see Table8). VDD • The sum of the currents sunk by all the I/Os on V plus the maximum Run SS consumption of the MCU sunk on V cannot exceed the absolute maximum rating SS I (see Table8). VSS Output voltage levels Unless otherwise specified, the parameters given in Table47 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Parameter Conditions Min Max Unit Output low level voltage for an I/O pin VOL(1) when 8 pins are sunk at same time TTL port(3) - 0.4 I = +8 mA V IO VOH(2) Owhuetpnu 8t hpiignhs laervee ls vooulrtcaegde afot rs aanm Ie/O ti mpien 2.7 V < VDD < 3.6V VDD–0.4 - Output low level voltage for an I/O pin VOL (1) when 8 pins are sunk at same time CMOS port(3) - 0.4 I =+ 8mA V IO VOH (2) Owhuetpnu 8t hpiignhs laervee ls vooulrtcaegde afot rs aanm Ie/O ti mpien 2.7 V < VDD < 3.6V 2.4 - DS5792 Rev 13 91/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 47. Output voltage characteristics (continued) Symbol Parameter Conditions Min Max Unit Output low level voltage for an I/O pin V (1)(4) - 1.3 OL when 8 pins are sunk at same time I = +20 mA IO V V (2)(4) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6V V –1.3 - OH when 8 pins are sourced at same time DD Output low level voltage for an I/O pin V (1)(4) - 0.4 OL when 8 pins are sunk at same time I = +6 mA IO V V (2)(4) Output high level voltage for an I/O pin 2 V < VDD < 2.7 V V –0.4 - OH when 8 pins are sourced at same time DD 1. The I current sunk by the device must always respect the absolute maximum rating specified in Table8 IO and the sum of I (I/O ports and control pins) must not exceed I . IO VSS 2. The I current sourced by the device must always respect the absolute maximum rating specified in IO Table8 and the sum of I (I/O ports and control pins) must not exceed I . IO VDD 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 4. Guaranteed by characterization results. 92/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure46 and Table48, respectively. Unless otherwise specified, the parameters given in Table48 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table10. Table 48. I/O AC characteristics(1) MODEx[1:0] Symbol Parameter Conditions Min Max Unit bit value(1) f Maximum frequency(2) C = 50pF, V = 2 V to 3.6V - 2 MHz max(IO)out L DD Output high to low level t - 125(3) 10 f(IO)out fall time C = 50pF, V = 2 V to 3.6V ns L DD Output low to high level t - 125(3) r(IO)out rise time f Maximum frequency(2) C = 50pF, V = 2 V to 3.6V - 10 MHz max(IO)out L DD Output high to low level t - 25(3) 01 f(IO)out fall time C = 50pF, V = 2 V to 3.6V ns L DD Output low to high level t - 25(3) r(IO)out rise time C = 30 pF, V = 2.7 V to 3.6V - 50 MHz L DD F Maximum frequency(2) C = 50 pF, V = 2.7 V to 3.6V - 30 MHz max(IO)out L DD C = 50 pF, V = 2 V to 2.7V - 20 MHz L DD C = 30pF, V = 2.7 V to 3.6V - 5(3) L DD Output high to low level 11 t C = 50pF, V = 2.7 V to 3.6V - 8(3) f(IO)out fall time L DD C = 50pF, V = 2 V to 2.7V - 12(3) L DD ns C = 30pF, V = 2.7 V to 3.6V - 5(3) L DD Output low to high level t C = 50pF, V = 2.7 V to 3.6V - 8(3) r(IO)out rise time L DD C = 50pF, V = 2 V to 2.7V - 12(3) L DD Pulse width of external - t signals detected by the - 10 - ns EXTIpw EXTI controller 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure46. 3. Guaranteed by design. DS5792 Rev 13 93/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 46. I/O AC characteristics definition (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:28)(cid:19)(cid:8) (cid:40)(cid:59)(cid:55)(cid:40)(cid:53)(cid:49)(cid:36)(cid:47) (cid:87)(cid:85)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:87)(cid:73)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:50)(cid:49)(cid:3)(cid:38)(cid:47) (cid:55) (cid:48)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:76)(cid:86)(cid:3)(cid:68)(cid:70)(cid:75)(cid:76)(cid:72)(cid:89)(cid:72)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:11)(cid:87) (cid:14)(cid:3)(cid:87)(cid:12)(cid:3)(cid:148)(cid:3)(cid:11)(cid:21)(cid:18)(cid:22)(cid:12)(cid:55)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:71)(cid:88)(cid:87)(cid:92)(cid:3)(cid:70)(cid:92)(cid:70)(cid:79)(cid:72)(cid:3)(cid:76)(cid:86)(cid:3)(cid:11)(cid:23)(cid:24)(cid:16)(cid:24)(cid:24)(cid:8)(cid:12)(cid:3) (cid:85)(cid:3) (cid:73) (cid:90)(cid:75)(cid:72)(cid:81)(cid:3)(cid:79)(cid:82)(cid:68)(cid:71)(cid:72)(cid:71)(cid:3)(cid:69)(cid:92)(cid:3)(cid:38)(cid:47)(cid:3)(cid:86)(cid:83)(cid:72)(cid:70)(cid:76)(cid:73)(cid:76)(cid:72)(cid:71)(cid:3)(cid:76)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:87)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:179)(cid:3)(cid:44)(cid:18)(cid:50)(cid:3)(cid:36)(cid:38)(cid:3)(cid:70)(cid:75)(cid:68)(cid:85)(cid:68)(cid:70)(cid:87)(cid:72)(cid:85)(cid:76)(cid:86)(cid:87)(cid:76)(cid:70)(cid:86)(cid:180)(cid:17)(cid:3) (cid:3) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:20)(cid:71) 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R (see Table46). PU Unless otherwise specified, the parameters given in Table49 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table10. Table 49. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit V (1) NRST Input low level voltage - –0.5 - 0.8 IL(NRST) V V (1) NRST Input high level voltage - 2 - V +0.5 IH(NRST) DD NRST Schmitt trigger voltage V - - 200 - mV hys(NRST) hysteresis R Weak pull-up equivalent resistor(2) V = V 30 40 50 kΩ PU IN SS V (1) NRST Input filtered pulse - - - 100 ns F(NRST) V (1) NRST Input not filtered pulse - 300 - - ns NF(NRST) 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 94/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 47. Recommended NRST pin protection (cid:57)(cid:39)(cid:39) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:11)(cid:20)(cid:12) (cid:49)(cid:53)(cid:54)(cid:55)(cid:11)(cid:21)(cid:12) (cid:53)(cid:51)(cid:56) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:53)(cid:72)(cid:86)(cid:72)(cid:87) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:20)(cid:3)(cid:151)(cid:41) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:21)(cid:70) 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table49. Otherwise the reset will not be taken into account by the device. 5.3.16 TIM timer characteristics The parameters given in Table50 are guaranteed by design. Refer to Section5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx(1) characteristics Symbol Parameter Conditions Min Max Unit - 1 - t TIMxCLK t Timer resolution time res(TIM) f = 72 MHz 13.9 - ns TIMxCLK Timer external clock - 0 fTIMxCLK/2 MHz f EXT frequency on CH1 to CH4 f = 72 MHz 0 36 MHz TIMxCLK Res Timer resolution - - 16 bit TIM 16-bit counter clock - 1 65536 t TIMxCLK t period when internal clock COUNTER is selected fTIMxCLK = 72 MHz 0.0139 910 µs - - 65536 × 65536 t TIMxCLK t Maximum possible count MAX_COUNT f = 72 MHz - 59.6 s TIMxCLK 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. DS5792 Rev 13 95/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.17 Communications interfaces I2C interface characteristics The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table51. Refer also to Section5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 51. I2C characteristics Standard mode Fast mode I2C(1)(2) I2C(1)(2) Symbol Parameter Unit Min Max Min Max t SCL clock low time 4.7 - 1.3 - w(SCLL) µs t SCL clock high time 4.0 - 0.6 - w(SCLH) t SDA setup time 250 - 100 - su(SDA) t SDA data hold time - 3450(3) - 900(3) h(SDA) tr(SDA) SDA and SCL rise time - 1000 - 300 ns t r(SCL) t f(SDA) SDA and SCL fall time - 300 - 300 t f(SCL) t Start condition hold time 4.0 - 0.6 - h(STA) µs Repeated Start condition t 4.7 - 0.6 - su(STA) setup time t Stop condition setup time 4.0 - 0.6 - μs su(STO) Stop to Start condition time t 4.7 - 1.3 - μs w(STO:STA) (bus free) Capacitive load for each bus C - 400 - 400 pF b line Pulse width of the spikes that are suppressed by the t 0 50(4) 0 50(4) μs SP analog filter for standard and fast mode 1. Guaranteed by design. 2. f must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to aPcChLieK1ve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region on the falling edge of SCL. 4. The minimum width of the spikes filtered by the analog filter is above t (max). SP 96/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 48. I2C bus AC waveforms and measurement circuit (cid:57)(cid:39)(cid:39)(cid:66)(cid:44)(cid:21)(cid:38) (cid:57)(cid:39)(cid:39)(cid:66)(cid:44)(cid:21)(cid:38) (cid:53)(cid:51) (cid:53)(cid:51) (cid:53)(cid:54) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21) (cid:54)(cid:39)(cid:36) (cid:44)(cid:240)(cid:38)(cid:3)(cid:69)(cid:88)(cid:86) (cid:53)(cid:54) (cid:54)(cid:38)(cid:47) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3)(cid:53)(cid:40)(cid:51)(cid:40)(cid:36)(cid:55)(cid:40)(cid:39) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:55)(cid:36)(cid:12) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55) (cid:54)(cid:39)(cid:36) (cid:87)(cid:73)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:54)(cid:55)(cid:50)(cid:51) (cid:87)(cid:90)(cid:11)(cid:54)(cid:55)(cid:50)(cid:29)(cid:54)(cid:55)(cid:36)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:55)(cid:36)(cid:12) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:47)(cid:47)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:36)(cid:12) (cid:54)(cid:38)(cid:47) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:47)(cid:43)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:47)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:47)(cid:12) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:55)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:26)(cid:28)(cid:71) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs: Series protection resistors. 3. Rp: Pull-up resistors. 4. VDD_I2C : I2C bus supply Table 52. SCL frequency (f = 36 MHz.,V = 3.3 V)(1)(2) PCLK1 DD_I2C I2C_CCR value f (kHz) SCL R = 4.7 kΩ P 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. R = External pull-up resistance, f = I2C speed. P SCL 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. DS5792 Rev 13 97/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S - SPI characteristics Unless otherwise specified, the parameters given in Table53 for SPI or in Table54 for I2S are derived from tests performed under ambient temperature, f frequency and V PCLKx DD supply voltage conditions summarized in Table10. Refer to Section5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53. SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode - 18 SCK SPI clock frequency 1/tc(SCK) Slave mode - 18 MHz t SPI clock rise and fall r(SCK) Capacitive load: C = 30 pF - 8 ns t time f(SCK) SPI slave input clock DuCy(SCK) Slave mode 30 70 % duty cycle t (1) NSS setup time Slave mode 4t - su(NSS) PCLK t (1) NSS hold time Slave mode 2t - h(NSS) PCLK t (1) Master mode, f = 36 MHz, w(SCKH) SCK high and low time PCLK 50 60 t (1) presc = 4 w(SCKL) t (1) Master mode 5 - su(MI) Data input setup time tsu(SI)(1) Slave mode 5 - t (1) Master mode 5 - h(MI) Data input hold time ns t (1) Slave mode 4 - h(SI) t (1)(2) Data output access time Slave mode, f = 20 MHz 0 3t a(SO) PCLK PCLK t (1)(3) Data output disable time Slave mode 2 10 dis(SO) t (1) Data output valid time Slave mode (after enable edge) - 25 v(SO) t (1) Data output valid time Master mode (after enable edge) - 5 v(MO) t (1) Slave mode (after enable edge) 15 - h(SO) Data output hold time t (1) Master mode (after enable edge) 2 - h(MO) 1. Guaranteed by characterization results. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 98/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 49. SPI timing diagram - slave mode and CPHA = 0 Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:81) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:46)(cid:3)(cid:76) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:43)(cid:12) (cid:38) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:87)(cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:47)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:3)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24)(cid:69) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. DS5792 Rev 13 99/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 51. SPI timing diagram - master mode(1) (cid:43)(cid:76)(cid:74)(cid:75) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:86)(cid:88)(cid:11)(cid:48)(cid:44)(cid:12) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:48)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:89)(cid:11)(cid:48)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:48)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:25)(cid:70) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. 100/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 54. I2S characteristics Symbol Parameter Conditions Min Max Unit DuCy(SCK) I2S slave input clock duty cycle Slave mode 30 70 % Master mode (data: 16 bits, fCK I2S clock frequency Audio frequency = 48kHz) 1.522 1.525 1/t MHz c(CK) Slave mode 0 6.5 t r(CK) I2S clock rise and fall time Capacitive load C =50pF - 8 t L f(CK) t (1) WS valid time Master mode 3 - v(WS) I2S2 2 - t (1) WS hold time Master mode h(WS) I2S3 0 - t (1) WS setup time Slave mode 4 - su(WS) t (1) WS hold time Slave mode 0 - h(WS) tw(CKH) (1) CK high and low time Master fPCLK= 16MHz, audio 312.5 - t (1) frequency = 48kHz 345 - w(CKL) I2S2 2 - t (1) Data input setup time Master receiver su(SD_MR) I2S3 6.5 - ns t (1) Data input setup time Slave receiver 1.5 - su(SD_SR) t (1)(2) Master receiver 0 - h(SD_MR) Data input hold time t (1)(2) Slave receiver 0.5 - h(SD_SR) Slave transmitter (after enable t (1)(2) Data output valid time - 18 v(SD_ST) edge) Slave transmitter (after enable t (1) Data output hold time 11 - h(SD_ST) edge) Master transmitter (after enable t (1)(2) Data output valid time - 3 v(SD_MT) edge) Master transmitter (after enable t (1) Data output hold time 0 - h(SD_MT) edge) 1. Guaranteed by design and/or characterization results. 2. Depends on f . For example, if f =8 MHz, then T = 1/f =125 ns. PCLK PCLK PCLK PLCLK DS5792 Rev 13 101/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 52. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × V and 0.7 × V DD DD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 53. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 102/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table55 are derived from tests performed under ambient temperature, f frequency and V supply voltage conditions PCLKx DD summarized in Table10. Refer to Section5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 54. SDIO high-speed mode Figure 55. SD default mode (cid:35)(cid:43) (cid:84)(cid:47)(cid:54)(cid:36) (cid:84)(cid:47)(cid:40)(cid:36) (cid:36)(cid:12)(cid:0)(cid:35)(cid:45)(cid:36) (cid:8)(cid:79)(cid:85)(cid:84)(cid:80)(cid:85)(cid:84)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:24)(cid:24)(cid:24) Table 55. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit Clock frequency in data transfer f C ≤ 30 pF 0 48 MHz PP mode L tW(CKL) Clock low time, f = 16MHz C ≤ 30 pF 32 - PP L tW(CKH) Clock high time, f = 16MHz C ≤ 30 pF 30 - PP L ns t Clock rise time C ≤ 30 pF - 4 r L t Clock fall time C ≤ 30 pF - 5 f L DS5792 Rev 13 103/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 55. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit CMD, D inputs (referenced to CK) t Input setup time C ≤ 30 pF 2 - ISU L ns t Input hold time C ≤ 30 pF 0 - IH L CMD, D outputs (referenced to CK) in MMC and SD HS mode t Output valid time C ≤ 30 pF - 6 OV L ns t Output hold time C ≤ 30 pF 0 - OH L CMD, D outputs (referenced to CK) in SD default mode(1) t Output valid default time C ≤ 30 pF - 7 OVD L ns t Output hold default time C ≤ 30 pF 0.5 - OHD L 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 56. USB startup time Symbol Parameter Max Unit t (1) USB transceiver startup time 1 µs STARTUP 1. Guaranteed by design. 104/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 57. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit Input levels V USB operating voltage(2) - 3.0(3) 3.6 V DD V (4) Differential input sensitivity I(USB_DP, USB_DM) 0.2 - DI V (4) Differential common mode range Includes V range 0.8 2.5 V CM DI V (4) Single ended receiver threshold - 1.3 2.0 SE Output levels V Static output level low R of 1.5kΩ to 3.6 V(5) - 0.3 OL L V V Static output level high R of 15kΩ to V (5) 2.8 3.6 OH L SS 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xC/D/E USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V voltage range. DD 4. Guaranteed by characterization results. 5. RL is the load connected on the USB drivers Figure 56. USB timings: definition of data signal rise and fall time (cid:38)(cid:85)(cid:82)(cid:86)(cid:86)(cid:3)(cid:82)(cid:89)(cid:72)(cid:85) (cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:86) (cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:86) (cid:57)(cid:38)(cid:53)(cid:54) (cid:57)(cid:54)(cid:54) (cid:87)(cid:73) (cid:87)(cid:85) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:26)(cid:69) Table 58. USB: full-speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit t Rise time(2) C = 50 pF 4 20 ns r L t Fall Time(2) C = 50 pF 4 20 ns f L t Rise/ fall time matching t/t 90 110 % rfm r f V Output signal crossover voltage - 1.3 2.0 V CRS 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). DS5792 Rev 13 105/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.18 CAN (controller area network) interface Refer to Section5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table59 are preliminary values derived from tests performed under ambient temperature, f frequency and V supply PCLK2 DDA voltage conditions summarized in Table10. Note: It is recommended to perform a calibration after each power-up. Table 59. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V Power supply - 2.4 - 3.6 V DDA V Positive reference voltage - 2.4 - V V REF+ DDA V Negative reference voltage - 0 V REF- Current on the V input I REF - - 160(1) 220 µA VREF pin f ADC clock frequency - 0.6 - 14 MHz ADC f (2) Sampling rate - 0.05 - 1 MHz S f = 14 MHz - - 823 kHz f (2) External trigger frequency ADC TRIG - - - 17 1/f ADC 0 (V or V V Conversion voltage range(3) - SSA REF- - V V AIN tied to ground) REF+ See Equation 1 and R (2) External input impedance - - 50 κΩ AIN Table60 for details R (2) Sampling switch resistance - - - 1 κΩ ADC Internal sample and hold C (2) - - - 8 pF ADC capacitor f = 14 MHz 5.9 µs t (2) Calibration time ADC CAL - 83 1/f ADC t (2) Injection trigger conversion fADC = 14 MHz - - 0.214 µs lat latency - - - 3(4) 1/f ADC t (2) Regular trigger conversion fADC = 14 MHz - - 0.143 µs latr latency - - - 2(4) 1/f ADC f = 14 MHz 0.107 - 17.1 µs t (2) Sampling time ADC S - 1.5 - 239.5 1/f ADC t (2) Power-up time - 0 0 1 µs STAB f = 14 MHz 1 - 18 µs ADC Total conversion time tCONV(2) (including sampling time) - 14 to 252 (tS for sampling +12.5 for 1/f successive approximation) ADC 106/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 1. Guaranteed by characterization results. 2. Guaranteed by design. 3. V can be internally connected to V and V can be internally connected to V , depending on the package. REF+ DDA REF- SSA Refer to Section3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/f must be added to the latency specified in Table59. PCLK2 Equation 1: R max formula AIN T R <---------------------------------S-------------------------------–R AIN f × C × ln(2N+2) ADC ADC ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 60. R max for f = 14 MHz(1) AIN ADC T (cycles) t (µs) R max (kΩ) s S AIN 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design. Table 61. ADC accuracy - limited test conditions(1)(2) Symbol Parameter Test conditions Typ Max(3) Unit ET Total unadjusted error f = 56 MHz, ±1.3 ±2 PCLK2 f = 14 MHz, R < 10 kΩ, EO Offset error ADC AIN ±1 ±1.5 V = 3 V to 3.6 V DDA EG Gain error T = 25 °C ±0.5 ±1.5 LSB A ED Differential linearity error Measurements made after ±0.7 ±1 ADC calibration EL Integral linearity error V = V ±0.8 ±1.5 REF+ DDA 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I and ΣI in Section5.3.14 does not INJ(PIN) INJ(PIN) affect the ADC accuracy. 3. Guaranteed by characterization results. DS5792 Rev 13 107/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 62. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions Typ Max(4) Unit ET Total unadjusted error ±2 ±5 f = 56 MHz, PCLK2 EO Offset error f = 14 MHz, R < 10 kΩ, ±1.5 ±2.5 ADC AIN EG Gain error V = 2.4 V to 3.6 V ±1.5 ±3 LSB DDA Measurements made after ED Differential linearity error ±1 ±2 ADC calibration EL Integral linearity error ±1.5 ±3 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted V , frequency, V and temperature ranges. DD REF 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I and ΣI in Section5.3.14 does not INJ(PIN) INJ(PIN) affect the ADC accuracy. 4. Guaranteed by characterization results. Figure 57. ADC accuracy characteristics (cid:54)(cid:50)(cid:37)(cid:38)(cid:11) (cid:54)(cid:36)(cid:36)(cid:33) (cid:59)(cid:17)(cid:44)(cid:51)(cid:34) (cid:41)(cid:36)(cid:37)(cid:33)(cid:44)(cid:0)(cid:29)(cid:0) (cid:8)(cid:79)(cid:82)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:68)(cid:69)(cid:80)(cid:69)(cid:78)(cid:68)(cid:73)(cid:78)(cid:71)(cid:0)(cid:79)(cid:78)(cid:0)(cid:80)(cid:65)(cid:67)(cid:75)(cid:65)(cid:71)(cid:69)(cid:9)(cid:61) (cid:20)(cid:16)(cid:25)(cid:22) (cid:20)(cid:16)(cid:25)(cid:22) (cid:37)(cid:39) (cid:20)(cid:16)(cid:25)(cid:21) (cid:20)(cid:16)(cid:25)(cid:20) (cid:20)(cid:16)(cid:25)(cid:19) (cid:8)(cid:18)(cid:9) (cid:37)(cid:52) (cid:8)(cid:19)(cid:9) (cid:23) (cid:8)(cid:17)(cid:9) (cid:22) (cid:21) (cid:37)(cid:47) (cid:37)(cid:44) (cid:20) (cid:19) (cid:37)(cid:36) (cid:18) (cid:17) (cid:17)(cid:44)(cid:51)(cid:34)(cid:41)(cid:36)(cid:37)(cid:33)(cid:44) (cid:16) (cid:17) (cid:18) (cid:19) (cid:20)(cid:21)(cid:22) (cid:23) (cid:20)(cid:16)(cid:25)(cid:19) (cid:20)(cid:16)(cid:25)(cid:20) (cid:20)(cid:16)(cid:25)(cid:21) (cid:20)(cid:16)(cid:25)(cid:22) (cid:54)(cid:51)(cid:51)(cid:33) (cid:54)(cid:36)(cid:36)(cid:33) (cid:65)(cid:73)(cid:17)(cid:20)(cid:19)(cid:25)(cid:21)(cid:67) 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 108/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 58. Typical connection diagram using the ADC (cid:57)(cid:39)(cid:39) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:54)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:75)(cid:82)(cid:79)(cid:71)(cid:3)(cid:36)(cid:39)(cid:38)(cid:3) (cid:57)(cid:55) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:25)(cid:3)(cid:57) (cid:53)(cid:36)(cid:44)(cid:49)(cid:11)(cid:20)(cid:12) (cid:36)(cid:44)(cid:49)(cid:91) (cid:53)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:57)(cid:55) (cid:57)(cid:36)(cid:44)(cid:49) (cid:38)(cid:83)(cid:68)(cid:85)(cid:68)(cid:86)(cid:76)(cid:87)(cid:76)(cid:70) (cid:19)(cid:17)(cid:25)(cid:3)(cid:57) (cid:38)(cid:36)(cid:39)(cid:38)(cid:11)(cid:20)(cid:12) (cid:44)(cid:47)(cid:147)(cid:20)(cid:3)(cid:151)(cid:36) (cid:68)(cid:76)(cid:20)(cid:26)(cid:24)(cid:22)(cid:23) 1. Refer to Table59 for the values of R , R and C . AIN ADC ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC General PCB design guidelines Power supply decoupling should be performed as shown in Figure59 or Figure60, depending on whether V is connected to V or not. The 10 nF capacitors should be REF+ DDA ceramic (good quality). They should be placed them as close as possible to the chip. Figure 59. Power supply and reference decoupling (V not connected to V ) REF+ DDA (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:22)(cid:91)(cid:91) (cid:57) (cid:53)(cid:40)(cid:41)(cid:14) (cid:11)(cid:86)(cid:72)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:72)(cid:3)(cid:20)(cid:12) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57) (cid:39)(cid:39)(cid:36) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57) (cid:18)(cid:57) (cid:54)(cid:54)(cid:36) (cid:53)(cid:40)(cid:41)(cid:177) (cid:11)(cid:86)(cid:72)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:72)(cid:3)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:22)(cid:27)(cid:27)(cid:69) 1. V and V inputs are available only on 100-pin packages. REF+ REF– DS5792 Rev 13 109/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60. Power supply and reference decoupling (V connected to V ) REF+ DDA (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:22)(cid:91)(cid:91) (cid:57) (cid:18)(cid:57) (cid:53)(cid:40)(cid:41)(cid:14) (cid:39)(cid:39)(cid:36) (cid:11)(cid:54)(cid:72)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:72)(cid:3)(cid:20)(cid:12) (cid:20)(cid:3)(cid:151)(cid:41)(cid:3)(cid:18)(cid:18)(cid:3)(cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57) (cid:18)(cid:57) (cid:53)(cid:40)(cid:41)(cid:177) (cid:54)(cid:54)(cid:36) (cid:11)(cid:54)(cid:72)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:72)(cid:3)(cid:20)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:22)(cid:27)(cid:28) 1. V and V inputs are available only on 100-pin packages. REF+ REF– 110/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.20 DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Min Typ Max Unit Comments V Analog supply voltage 2.4 - 3.6 V - DDA V Reference supply voltage 2.4 - 3.6 V V must always be below V REF+ REF+ DDA V Ground 0 - 0 V - SSA Resistive load with buffer R (1) 5 - - kΩ - LOAD ON When the buffer is OFF, the Impedance output with Minimum resistive load between R (2) - - 15 kΩ O buffer OFF DAC_OUT and V to have a 1% SS accuracy is 1.5MΩ Maximum capacitive load at C (1) Capacitive load - - 50 pF DAC_OUT pin (when the buffer is LOAD ON). It gives the maximum output DAC_OUT Lower DAC_OUT voltage 0.2 - - V excursion of the DAC. min(1) with buffer ON It corresponds to 12-bit input code (0x0E0) to (0xF1C) at V = 3.6V REF+ DAC_OUT Higher DAC_OUT voltage and (0x155) and (0xEAB) at V - - V – 0.2 V REF+ max(1) with buffer ON DDA = 2.4V DAC_OUT Lower DAC_OUT voltage - 0.5 - mV min(1) with buffer OFF It gives the maximum output DAC_OUT Higher DAC_OUT voltage V – excursion of the DAC. - - REF+ V max(1) with buffer OFF 1LSB DAC DC current With no load, worst code (0xF1C) at I consumption in quiescent - - 220 µA V = 3.6V in terms of DC DDVREF+ REF+ mode (Standby mode) consumption on the inputs With no load, middle code (0x800) - - 380 µA DAC DC current on the inputs IDDA consumption in quiescent With no load, worst code (0xF1C) at mode(3) - - 480 µA V = 3.6V in terms of DC REF+ consumption on the inputs Given for the DAC in 10-bit Differential non linearity - - ±0.5 LSB configuration DNL(4) Difference between two consecutive code-1LSB) Given for the DAC in 12-bit - - ±2 LSB configuration Integral non linearity Given for the DAC in 10-bit - - ±1 LSB (difference between configuration measured value at Code i INL(3) and the value at Code i on a Given for the DAC in 12-bit line drawn between Code 0 - - ±4 LSB configuration and last Code 1023) DS5792 Rev 13 111/143 135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 63. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments - - ±10 mV - Offset error (difference between - - ±3 LSB Given for the DAC in 10-bit at VREF+ Offset(3) measured value at Code = 3.6V (0x800) and the ideal value Given for the DAC in 12-bit at V = V /2) - - ±12 LSB REF+ REF+ = 3.6V Gain Given for the DAC in 12bit Gain error - - ±0.5 % error(3) configuration Settling time (full scale: for a 10-bit input code transition between the t (3) - 3 4 µs C ≤ 50 pF, R ≥ 5 kΩ SETTLING lowest and the highest input LOAD LOAD codes when DAC_OUT reaches final value ±1LSB Max frequency for a correct DAC_OUT change when Update MS/ small variation in the input - - 1 C ≤ 50 pF, R ≥ 5 kΩ rate(3) s LOAD LOAD code (from code i to i+1LSB) Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP(3) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and DAC Control register) highest possible ones. Power supply rejection ratio PSRR+ (1) (to V ) (static DC - –67 –40 dB No R , C = 50 pF DDA LOAD LOAD measurement 1. Guaranteed by design. 2. Guaranteed by characterization. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 61. 12-bit buffered /non-buffered DAC (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:18)(cid:49)(cid:82)(cid:81)(cid:16)(cid:69)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:3)(cid:39)(cid:36)(cid:38) (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:11)(cid:20)(cid:12) (cid:53)(cid:47) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87)(cid:3) (cid:39)(cid:36)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55)(cid:91) (cid:71)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79)(cid:3)(cid:87)(cid:82)(cid:3) (cid:68)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74)(cid:3) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85)(cid:3) (cid:38) (cid:47) (cid:65)(cid:73)(cid:17)(cid:23)(cid:17)(cid:21)(cid:23)(cid:54)(cid:19) 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 112/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.21 Temperature sensor characteristics Table 64. TS characteristics Symbol Parameter Min Typ Max Unit T V linearity with temperature - ±1 ±2 °C L SENSE Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V Voltage at 25 °C 1.34 1.43 1.52 V 25 t (1) Startup time 4 - 10 µs START ADC sampling time when reading the T (2)(1) - - 17.1 µs S_temp temperature 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. DS5792 Rev 13 113/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LFBGA144 package information Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package outline (cid:38) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:71)(cid:71)(cid:71) (cid:38) (cid:36)(cid:23) (cid:36)(cid:22) (cid:36)(cid:21) (cid:36)(cid:20) (cid:36) (cid:39)(cid:20) (cid:36)(cid:20)(cid:3)(cid:37)(cid:36)(cid:47)(cid:47) (cid:37) (cid:36)(cid:20)(cid:3)(cid:37)(cid:36)(cid:47)(cid:47) (cid:3)(cid:51)(cid:36)(cid:39)(cid:3)(cid:38)(cid:50)(cid:53)(cid:49)(cid:40)(cid:53) (cid:39) (cid:72) (cid:41) (cid:3)(cid:51)(cid:36)(cid:39)(cid:3)(cid:38)(cid:50)(cid:53)(cid:49)(cid:40)(cid:53) (cid:36) (cid:41) (cid:40)(cid:20) (cid:40) (cid:72) (cid:36) (cid:48) (cid:20)(cid:21) (cid:20) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:69)(cid:3)(cid:11)(cid:20)(cid:23)(cid:23)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:12) (cid:55)(cid:50)(cid:51)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:72)(cid:72)(cid:72)(cid:48) (cid:38) (cid:36) (cid:37) (cid:145)(cid:73)(cid:73)(cid:73) (cid:48) (cid:38) (cid:47)(cid:41)(cid:37)(cid:42)(cid:36)(cid:20)(cid:23)(cid:23)(cid:66)(cid:59)(cid:22)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:21) 1. Drawing is not to scale. Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8mm pitch, package mechanical data millimeters inches(1) Symbol Min Typ Max Typ Min Max A(2) - - 1.700 - - 0.0669 A1 0.250 0.300 0.350 0.098 0.0118 0.0138 A2 0.810 0.910 1.010 0.0319 0.0358 0.0398 A3 0.225 0.26 0.295 0.0089 0.0102 0.0116 A4 0.585 0.650 0.715 0.0230 0.0256 0.0281 114/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8mm pitch, package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Typ Min Max b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 D1 - 8.800 - - 0.3465 - E 9.900 10.000 10.100 0.3898 0.3937 0.3976 E1 - 8.800 - - 0.3465 - e - 0.800 - - 0.0315 - F - 0.600 - - 0.0236 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. STATSChipPAC package dimensions. Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprint (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:47)(cid:41)(cid:37)(cid:42)(cid:36)(cid:20)(cid:23)(cid:23)(cid:66)(cid:59)(cid:22)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:20) Table 66. LFBGA144 recommended PCB design rules (0.8mm pitch BGA) Dimension Recommended values Pitch 0.8mm Dpad 0.400mm DS5792 Rev 13 115/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Table 66. LFBGA144 recommended PCB design rules (0.8mm pitch BGA) (continued) Dimension Recommended values UBM 0.350 mm 0.470mm typ. (depends on the solder mask Dsm registration tolerance) Stencil opening 0.400mm Stencil thickness Between 0.100mm to 0.125mm Pad trace width 0.120mm Ball Diameter 0.400mm Device marking for LFBGA144 package The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 64. LFBGA144 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:22) (cid:61)(cid:38)(cid:43)(cid:25) (cid:22) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:37)(cid:68)(cid:79)(cid:79)(cid:3) (cid:36)(cid:20)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:60) (cid:58)(cid:58) (cid:48)(cid:54)(cid:89)(cid:22)(cid:28)(cid:23)(cid:19)(cid:24)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity 116/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information 6.2 LFBGA100 package information Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline (cid:61) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:36)(cid:23) (cid:36)(cid:21) (cid:36)(cid:20) (cid:36) (cid:40)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:59) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:40) (cid:72) (cid:41) (cid:36) (cid:41) (cid:39)(cid:20) (cid:39) (cid:72) (cid:60) (cid:46) (cid:20)(cid:19) (cid:20) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:69)(cid:3)(cid:11)(cid:20)(cid:19)(cid:19)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:12) (cid:55)(cid:50)(cid:51)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:72)(cid:72)(cid:72)(cid:48) (cid:61) (cid:60) (cid:59) (cid:145)(cid:73)(cid:73)(cid:73) (cid:48) (cid:61) (cid:43)(cid:19)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:21) 1. Drawing is not to scale. Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.700 - - 0.0669 A1 0.270 - - 0.0106 - - A2 - 0.300 - - 0.0118 - A4 - - 0.800 - - 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 7.200 - - 0.2835 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 1.400 - - 0.0551 - ddd - - 0.120 - - 0.0047 DS5792 Rev 13 117/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprintoutline (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:43)(cid:19)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:20) Table 68. LFBGA100 recommended PCB design rules (0.8mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.500mm 0.570mm typ. (depends on the soldermask Dsm registration tolerance) Stencil opening 0.500mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120mm 118/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LFBGA100 package The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 67. LFBGA100 marking example (package top view) (cid:59) (cid:36)(cid:71)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:3) (cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:22) (cid:57)(cid:27)(cid:43)(cid:25)(cid:3)(cid:3) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:37)(cid:68)(cid:79)(cid:79)(cid:3)(cid:36)(cid:3) (cid:76)(cid:81)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:28)(cid:23)(cid:19)(cid:27)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 119/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE 6.3 WLCSP64 package information Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline (cid:72)(cid:20) (cid:69)(cid:69)(cid:69) (cid:61) (cid:41) (cid:42) (cid:36) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:72)(cid:21) (cid:72) (cid:43) (cid:42) (cid:27) (cid:20) (cid:36) (cid:72) (cid:41) (cid:36)(cid:21) (cid:37)(cid:88)(cid:80)(cid:83)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:54)(cid:76)(cid:71)(cid:72)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:39) (cid:59) (cid:60) (cid:37)(cid:88)(cid:80)(cid:83) (cid:36)(cid:20) (cid:72)(cid:72)(cid:72) (cid:61) (cid:40) (cid:69) (cid:36)(cid:20)(cid:50)(cid:85)(cid:76)(cid:72)(cid:81)(cid:87)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:61) (cid:70)(cid:70)(cid:70) (cid:59) (cid:60) (cid:61) (cid:85)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:68)(cid:68)(cid:68) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:11)(cid:23)(cid:91)(cid:12) (cid:11)(cid:85)(cid:82)(cid:87)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:28)(cid:19)(cid:131)(cid:12) (cid:58)(cid:68)(cid:73)(cid:72)(cid:85)(cid:3)(cid:69)(cid:68)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:38)(cid:53)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:21) 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the ball. Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.535 0.585 0.635 0.0211 0.0230 0.0250 A1 0.205 0.230 0.255 0.0081 0.0091 0.0100 A2 0.330 0.355 0.380 0.0130 0.0140 0.0150 120/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max b(2) 0.290 0.320 0.350 0.0114 0.0126 0.0138 e - 0.500 - - 0.0197 - e1 - 3.500 - - 0.1378 - F - 0.447 - - 0.0176 - G - 0.483 - - 0.0190 - D 4.446 4.466 4.486 0.1750 0.1758 0.1766 E 4.375 4.395 4.415 0.1722 0.1730 0.1738 H - 0.250 - - 0.0098 - L - 0.200 - - 0.0079 - eee - 0.05 - - 0.0020 - aaa - 0.10 - - 0.0039 - Number of balls 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum ball diameter parallel to primary datum Z. Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049mm, 0.5mm pitch wafer level chip scale package recommended footprint (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:58)(cid:47)(cid:38)(cid:54)(cid:51)(cid:25)(cid:23)(cid:66)(cid:38)(cid:53)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:20) Table 70. WLCSP64 recommended PCB design rules (0.5mm pitch) Dimension Recommended values Pitch 0.5 Dpad 250µm Dsm 300µm Stencil Opening 320µm DS5792 Rev 13 121/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Table 70. WLCSP64 recommended PCB design rules (0.5mm pitch) (continued) Dimension Recommended values Stencil Thickness Between 100µm to 125µm Pad trace width 100µm Ball Diameter 320µm 6.4 LQFP144 package information Figure 70. LQFP144 - 144-pin, 20 x 20mm low-profile quad flat package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:36)(cid:20) (cid:70) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:70)(cid:70)(cid:70) (cid:38) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:36) (cid:39) (cid:47) (cid:46) (cid:39)(cid:20) (cid:47)(cid:20) (cid:39)(cid:22) (cid:20)(cid:19)(cid:27) (cid:26)(cid:22) (cid:20)(cid:19)(cid:28) (cid:26)(cid:21) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:22)(cid:26) (cid:20)(cid:23)(cid:23) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:20) (cid:22)(cid:25) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:72) (cid:20)(cid:36)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:23) 1. Drawing is not to scale. 122/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Table 71. LQFP144 - 144-pin, 20 x 20mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS5792 Rev 13 123/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Figure 71. LQFP144 - 144-pin,20 x 20mm low-profile quad flat package recommended footprint (cid:20)(cid:17)(cid:22)(cid:24) (cid:20)(cid:19)(cid:27) (cid:26)(cid:22) (cid:20)(cid:19)(cid:28) (cid:19)(cid:17)(cid:22)(cid:24) (cid:26)(cid:21) (cid:19)(cid:17)(cid:24) (cid:20)(cid:28)(cid:17)(cid:28) (cid:20)(cid:26)(cid:17)(cid:27)(cid:24) (cid:21)(cid:21)(cid:17)(cid:25) (cid:20)(cid:23)(cid:23) (cid:22)(cid:26) (cid:20) (cid:22)(cid:25) (cid:20)(cid:28)(cid:17)(cid:28) (cid:21)(cid:21)(cid:17)(cid:25) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:19)(cid:24)(cid:72) 1. Dimensions are expressed in millimeters. 124/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP144 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 72. LQFP144 marking example (package top view) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:3)(cid:74)(cid:68)(cid:87)(cid:72)(cid:3)(cid:80)(cid:68)(cid:85)(cid:78) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:59) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:22)(cid:61)(cid:40)(cid:55)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:24)(cid:25)(cid:22)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 125/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE 6.5 LQFP100 package information Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:33) (cid:18) (cid:17) (cid:33) (cid:33) (cid:67) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:44) (cid:33)(cid:17) (cid:43) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:23)(cid:21) (cid:21)(cid:17) (cid:21)(cid:16) (cid:23)(cid:22) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:17) (cid:18)(cid:21) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:69) (cid:17)(cid:44)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:21) 1. Drawing is not to scale. Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 126/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 74. LQFP100 recommended footprint (cid:23)(cid:21) (cid:21)(cid:17) (cid:23)(cid:22) (cid:21)(cid:16) (cid:16)(cid:14)(cid:21) (cid:16)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:17)(cid:20)(cid:14)(cid:19) (cid:17)(cid:16)(cid:16) (cid:18)(cid:22) (cid:17)(cid:14)(cid:18) (cid:17) (cid:18)(cid:21) (cid:17)(cid:18)(cid:14)(cid:19) (cid:17)(cid:22)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:22)(cid:67) 1. Dimensions are in millimeters. DS5792 Rev 13 127/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Device marking for LQFP100 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 75. LQFP100 marking example (package top view) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:3)(cid:74)(cid:68)(cid:87)(cid:72)(cid:3) (cid:80)(cid:68)(cid:85)(cid:78) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:38)(cid:1005)(cid:1004)(cid:1007) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:115)(cid:1012)(cid:100)(cid:1010)(cid:3)(cid:3) (cid:121) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:122) (cid:116)(cid:116) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:24)(cid:25)(cid:21)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity 128/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information 6.6 LQFP64 package information Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:70) (cid:36) (cid:70)(cid:70)(cid:70) (cid:38) (cid:20) (cid:39) (cid:36) (cid:46) (cid:39)(cid:20) (cid:47) (cid:39)(cid:22) (cid:47)(cid:20) (cid:23)(cid:27) (cid:22)(cid:22) (cid:22)(cid:21) (cid:23)(cid:28) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20) (cid:20)(cid:25) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:72) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:24)(cid:58)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not in scale. Table 7 3. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS5792 Rev 13 129/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 77. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat recommended footprint (cid:20)(cid:24) (cid:19)(cid:19) (cid:16)(cid:14)(cid:19) (cid:20)(cid:25) (cid:16)(cid:14)(cid:21) (cid:19)(cid:18) (cid:17)(cid:18)(cid:14)(cid:23) (cid:17)(cid:16)(cid:14)(cid:19) (cid:17)(cid:16)(cid:14)(cid:19) (cid:22)(cid:20) (cid:17)(cid:23) (cid:17)(cid:14)(cid:18) (cid:17) (cid:17)(cid:22) (cid:23)(cid:14)(cid:24) (cid:17)(cid:18)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:25)(cid:67) 1. Dimensions are in millimeters. 130/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP64 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 78. LQFP64 marking example (package top view) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:4) (cid:94)(cid:100)(cid:68)(cid:1007)(cid:1006)(cid:38)(cid:1005)(cid:1004)(cid:1007) (cid:90)(cid:28)(cid:100)(cid:1010) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:122) (cid:116)(cid:116) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:24)(cid:25)(cid:23)(cid:57)(cid:20) 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 131/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE 6.7 Thermal characteristics The maximum chip junction temperature (T max) must never exceed the values given in J Table10: General operating conditions on page44. The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated J using the following equation: T max = T max + (P max x Θ ) J A D JA Where: • T max is the maximum ambient temperature in °C, A • Θ is the package junction-to-ambient thermal resistance, in °C/W, JA • P max is the sum of P max and P max (P max = P max + P max), D INT I/O D INT I/O • P max is the product of I andV , expressed in Watts. This is the maximum chip INT DD DD internal power. P max represents the maximum power dissipation on output pins where: I/O PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 74. Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction-ambient 40 LFBGA144 - 10 × 10 mm / 0.8 mm pitch Thermal resistance junction-ambient 30 LQFP144 - 20 × 20 mm / 0.5 mm pitch Thermal resistance junction-ambient 40 LFBGA100 - 10 × 10 mm / 0.8 mm pitch Θ °C/W JA Thermal resistance junction-ambient 46 LQFP100 - 14 × 14 mm / 0.5 mm pitch Thermal resistance junction-ambient 45 LQFP64 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient 50 WLCSP64 6.7.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 132/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information 6.7.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table75: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xC, STM32F103xD and STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature T = 82 °C (measured according to JESD51-2), Amax I = 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output OL OL at low level with I = 20 mA, V = 1.3 V OL OL P 50 mA × 3.5 V= 175 mW INTmax = P × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW IOmax = 20 This gives: P = 175 mW and P = 272 mW: INTmax IOmax P 175 272 = 447 mW Dmax = + Thus: P = 447 mW Dmax Using the values obtained in Table74 T is calculated as follows: Jmax – For LQFP100, 46 °C/W T = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C Jmax This is within the range of the suffix 6 version parts (–40 < T < 105 °C). J In this case, parts must be ordered at least with the temperature range suffix 6 (see Table75: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T remains within the J specified range. Assuming the following application conditions: Maximum ambient temperature T = 115 °C (measured according to JESD51-2), Amax I = 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V OL OL P 20 mA × 3.5 V= 70 mW INTmax = P × 8 mA × 0.4 V = 64 mW IOmax = 20 This gives: P = 70 mW and P = 64 mW: INTmax IOmax P 70 64 = 134 mW Dmax = + Thus: P = 134 mW Dmax DS5792 Rev 13 133/143 135

Package information STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table74 T is calculated as follows: Jmax – For LQFP100, 46 °C/W T = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix 7 version parts (–40 < T < 125 °C). J In this case, parts must be ordered at least with the temperature range suffix 7 (see Table75: Ordering information scheme). Figure 79. LQFP100 P max vs. T D A 700 600 500 ) W Suffix 6 400 m ( Suffix 7 300 D P 200 100 0 65 75 85 95 105 115 125 135 T (°C) A 134/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Ordering information 7 Ordering information Table 75. Ordering information scheme Example: STM32 F 103 R C T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS5792 Rev 13 135/143 135

Revision history STM32F103xC, STM32F103xD, STM32F103xE 8 Revision history Table 76.Document revision history Date Revision Changes 07-Apr-2008 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section1: Introduction and Section2.2: Full compatibility throughout the family modified. Small text changes. Note2 added in Table2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page11. LQPF100/BGA100 column added to Table6: FSMC pin definition on page38. Values and Figures added to Maximum current consumption on page62 (see Table18, Table19, Table20 and Table21 and see Figure14, Figure15, Figure17, Figure18 and Figure19). Values added to Typical current consumption on page73 (see 22-May-2008 2 Table22, Table23 and Table24). Table19: Typical current consumption in Standby mode removed. Note4 and Note1 added to Table65: USB DC electrical characteristics and Table66: USB: full-speed electrical characteristics on page129, respectively. V added to Table65: USB DC electrical characteristics on USB page129. Figure68: Recommended footprint(1) on page143 corrected. Equation 1 corrected. Figure73: LQFP100 PD max vs. TA on page149 modified. Tolerance values corrected in Table74: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8mm pitch, package data on page139. 136/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date Revision Changes Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page22 modified. Number of complementary channels corrected in Figure1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram. Power supply supervisor on page23 modified and V added to DDA Table14: General operating conditions on page59. Table notes revised in Section5: Electrical characteristics. Capacitance modified in Figure12: Power supply scheme on page57. Table60: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated. Table61: SPI characteristics modified, t modified in Figure49: h(NSS) SPI timing diagram - slave mode and CPHA = 0 on page123. Minimum SDA and SCL fall time value for Fast mode removed from 21-Jul-2008 3 Table59: I2C characteristics on page120, note 1 modified. I values and some I values with regulator in run mode added DD_VBAT DD to Table21: Typical and maximum current consumptions in Stop and Standby modes on page68. Table34: Flash memory endurance and data retention on page87 updated. t modified in Table61: SPI characteristics on page122. su(NSS) EO corrected in Table70: ADC accuracy on page132. Figure58: Typical connection diagram using the ADC on page133 and note below corrected. Typical T value removed from Table72: TS characteristics on S_temp page137. Section6.1: Package mechanical data on page138 updated. Small text changes. DS5792 Rev 13 137/143 142

Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date Revision Changes Timers specified on page 1 (motor control capability mentioned). Section2.2: Full compatibility throughout the family updated. Table6: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page27 updated. Figure1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram modified. Note10 added, main function after reset and Note5 on page44 updated in Table8: High-density STM32F103xx pin definitions. Note2 modified below Table11: Voltage characteristics on page58, |DV | min and |DV | min removed. 12-Dec-2008 4 DDx DDx Note2 and P values for LQFP144 and LFBGA144 packages added to D Table14: General operating conditions on page59. Measurement conditions specified in Section5.3.5: Supply current characteristics on page62. Max values at T = 85 °C and T = 105 °C updated in Table21: Typical A A and maximum current consumptions in Stop and Standby modes on page68. Section5.3.10: FSMC characteristics on page87 updated. Data added to Table50: EMI characteristics on page111. I added to Table67: ADC characteristics on page130. VREF Table81: Package thermal characteristics on page146 updated. Small text changes. 138/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date Revision Changes I/O information clarified on page 1. Figure4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1. In Table5: High-density STM32F103xx pin definitions: – I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated – PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column PG14 pin description modified in Table6: FSMC pin definition. Figure9: Memory map on page54 modified. Note modified in Table18: Maximum current consumption in Run mode, code with data processing running from Flash and Table20: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure17, Figure18 and Figure19 show typical curves (titles changed). Table25: High-speed external user clock characteristics and Table26: Low-speed external user clock characteristics modified. ACC max HSI values modified in Table29: HSI oscillator characteristics. FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure24: Asynchronous non- multiplexed SRAM/PSRAM/NOR read waveforms and Figure25: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. 30-Mar-2009 5 t values modified in Table35: Asynchronous non-multiplexed w(NADV) SRAM/PSRAM/NOR read timingsand Table39: Asynchronous multiplexed PSRAM/NOR write timings. t modified in h(Data_NWE) Table36: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings In Table41: Synchronous multiplexed PSRAM write timings and Table43: Synchronous non-multiplexed PSRAM write timings: – t renamed as t v(Data-CLK) d(CLKL-Data) – t min value removed and max value added d(CLKL-Data) – t / t removed h(CLKL-DV) h(CLKL-ADV) Figure28: Synchronous multiplexed NOR/PSRAM read timings, Figure29: Synchronous multiplexed PSRAM write timings and Figure31: Synchronous non-multiplexed PSRAM write timings modified. Figure52: I2S slave timing diagram (Philips protocol)(1) and Figure53: I2S master timing diagram (Philips protocol)(1) modified. WLCSP64 package added (see Figure8: STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side, Table8: High-density STM32F103xx pin definitions, Figure65: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and Table76: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data). Small text changes. DS5792 Rev 13 139/143 142

Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date Revision Changes Figure1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note5 updated and Note4 added in Table5: High-density STM32F103xC/D/E pin definitions. V and T added to Table13: Embedded internal reference RERINT Coeff voltage. Table16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified. f min modified in Table21: High-speed external user clock HSE_ext characteristics. C and C replaced by C in Table23: HSE 4-16 MHz oscillator L1 L2 characteristics and Table24: LSE oscillator characteristics (f = LSE 32.768 kHz), notes modified and moved below the tables. Note1 modified below Figure29: Synchronous multiplexed PSRAM write timings. Table25: HSI oscillator characteristics modified. Conditions removed from Table27: Low-power mode wakeup timings. Jitter added to Table28: PLL characteristics. Figure47: Recommended NRST pin protection modified. In Table31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read 21-Jul-2009 6 timings: th(BL_NOE) and th(A_NOE) modified. In Table32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: t and t modified. h(A_NWE) h(Data_NWE) In Table33: Asynchronous multiplexed PSRAM/NOR read timings: t and t modified. h(AD_NADV) h(A_NOE) In Table34: Asynchronous multiplexed PSRAM/NOR write timings: t modified. h(A_NWE) In Table35: Synchronous multiplexed NOR/PSRAM read timings: t modified. h(CLKH-NWAITV) In Table40: Switching characteristics for NAND Flash read and write cycles: t modified. h(NOE-D) Table53: SPI characteristics modified. Values added to Table54: I2S characteristics and Table55: SD / MMC characteristics. C and R parameters modified in Table59: ADC characteristics. ADC AIN R max values modified in Table60: R max for f = 14 MHz. AIN AIN ADC Table71: DAC characteristics modified. Figure61: 12-bit buffered /non- buffered DAC added. Figure63: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and Table75: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated. Number of DACs corrected in Table3: STM32F103xx family. I updated in Table17: Typical and maximum current DD_VBAT consumptions in Stop and Standby modes. Figure16: Typical current consumption on V with RTC on vs. 24-Sep-2009 7 BAT temperature at different V values added. BAT IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC61967-2 in Section5.3.11: EMC characteristics on page86. Table63: DAC characteristics modified. Small text changes. 140/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date Revision Changes Updated package choice for 103Rx in Table2 Updated footnotes below Table7: Voltage characteristics on page43 and Table8: Current characteristics on page43 Updated tw min in Table21: High-speed external user clock characteristics on page58 Updated startup time in Table24: LSE oscillator characteristics (f = LSE 32.768 kHz) on page61 Updated note 2 in Table51: I2C characteristics on page96 Updated Figure48: I2C bus AC waveforms and measurement circuit Updated Figure47: Recommended NRST pin protection Updated Section5.3.14: I/O port characteristics Updated Table35: Synchronous multiplexed NOR/PSRAM read 19-Apr-2011 8 timings on page72 Updated FSMC Figure26 thru Figure31 Updated Figure 41.: NAND controller waveforms for common memory write access and Figure 48.: I2C bus AC waveforms and measurement circuit Added Section5.3.13: I/O current injection characteristics Updated Figure67 and added Table69: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data on page120 LQFP64 package mechanical data updated: see Figure 73.: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table73: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data on page129. Added Note7 in Table5: High-density STM32F103xC/D/E pin definitions on page31. Updated Note10 in Table5: High-density STM32F103xC/D/E pin definitions on page31. 30-Sept-2014 9 Modified Note2 in Table62: ADC accuracy on page108 Modified Note3 in Table62: ADC accuracy on page108 Modified notes in Table51: I2C characteristics on page96 Updated Figure51: SPI timing diagram - master mode(1) on page100 Updated Figure 66.: BGA pad footprint, Figure70: LQFP144 - 144-pin, 20 x 20mm low-profile quad flat package outline, Figure 73.: LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline, Figure 74.: LQFP100 recommended footprint, Figure 76.: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline, Figure 77.: LQFP64 - 64- pin, 10 x 10mm low-profile quad flat recommended footprint 23-Feb-2015 10 Added Figure 72.: LQFP144 marking example (package top view), Figure 75.: LQFP100 marking example (package top view), Figure 78.: LQFP64 marking example (package top view) Updated Table72: LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data, Table73: LQFP64 – 10 x 10 mm 64 pin low- profile quad flat package mechanical data DS5792 Rev 13 141/143 142

Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date Revision Changes Replaced USBDP and USBDM by USB_DP and USB_DM in the whole document. Updated: – Introduction – Reference standard in Table43: ESD absolute maximum ratings. – Updated I description in Table63: DAC characteristics. DDA – Section: I2C interface characteristics – Figure62: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package outline – Updated sentence before Figure78: LQFP64 marking example (package top view). – Figure65: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and sentence before Figure75: LQFP100 marking example (package top view) – Figure68: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline – Figure48: I2C bus AC waveforms and measurement circuit on 31-08-2015 11 page97 – Section6.1: LFBGA144 package information and Section6.2: LFBGA100 package information. – Table20: Peripheral current consumption Added: – Figure63: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprint – Figure64: LFBGA144 marking example (package top view) – Figure66: LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10mm, 0.8mm pitch, package recommended footprintoutline – Figure69: WLCSP64 - 64-ball, 4.4757 x 4.4049mm, 0.5mm pitch wafer level chip scale package recommended footprint – Table66: LFBGA144 recommended PCB design rules (0.8mm pitch BGA) – Table68: LFBGA100 recommended PCB design rules (0.8mm pitch BGA) – Table70: WLCSP64 recommended PCB design rules (0.5mm pitch). Updated: – Table59: ADC characteristics – Table65: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8mm pitch, package mechanical data 26-Nov-2015 12 – Table66: LFBGA144 recommended PCB design rules (0.8mm pitch BGA) Added: – Note3 on Table7: Voltage characteristics Updated: – Table2: STM32F103xC, STM32F103xD and STM32F103xE features 10-Jul-2018 13 and peripheral counts – Section7: Ordering information 142/143 DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS5792 Rev 13 143/143 143

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: STM32F103RCT6 STM32F103RDT6 STM32F103VCT6 STM32F103VDT6 STM32F103ZCT6 STM32F103ZDT6 STM32F103ZEH6 STM32F103RET6 STM32F103VEH6 STM32F103VET6 STM32F103ZET6 STM32F103RCT6TR STM32F103RCT7 STM32F103RDT6TR STM32F103VDH6TR STM32F103ZET6TR STM32F103VDT7 STM32F103VET7TR STM32F103RET6TR STM32F103RET7 STM32F103VCH6 STM32F103VDH6 STM32F103VEH7 STM32F103VET7 STM32F103ZCH6 STM32F103ZDH6 STM32F103ZEH7 STM32F103ZET7 STM32F103RCY6TR STM32F103RDY6TR STM32F103REY6TR STM32F103VCT6TR STM32F103VET6TR STM32F103ZEH6TR STM32F103ZCT7 STM32F103VDT6TR STM32F103RCY6CTR STM32F103ZCT6TR STM32F103VEH6TR STM32F103ZDH6TR STM32F103ZEH7TR STM32F103ZCT7TR