STM32F102x4 STM32F102x6 ® Low-density USB access line, ARM -based 32-bit MCU with 16/32 KB Flash, USB FS, 5 timers, ADC & 5 com. interfaces Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access LQFP64 LQFP48 10 × 10 mm 7 × 7 mm – Single-cycle multiplication and hardware division • Memories • Up to 5 timers – 16 or 32 Kbytes of Flash memory – Two 16-bit timers, each with up to 4 – 4 or 6 Kbytes of SRAM IC/OC/PWM or pulse counter • Clock, reset and supply management – 2 watchdog timers (Independent and Window) – 2.0 to 3.6 V application supply and I/Os – SysTick timer: 24-bit downcounter – POR, PDR and programmable voltage detector (PVD) • Up to 5 communication interfaces – 4-to-16 MHz crystal oscillator – One I2C interface (SMBus/PMBus) – Internal 8 MHz factory-trimmed RC – Two USARTs (ISO 7816 interface, LIN, – Internal 40 kHz RC IrDA capability, modem control) – One SPI (12 Mbit/s) – PLL for CPU clock – 32 kHz oscillator for RTC with calibration – One USB 2.0 full speed interface • Low power • CRC calculation unit, 96-bit unique ID – Sleep, Stop and Standby modes • ECOPACK® packages – V supply for RTC and backup registers BAT Table 1. Device summary • Debug mode – Serial wire debug (SWD) and JTAG Reference Part number interfaces STM32F102x4 STM32F102C4, STM32F102R4 • DMA STM32F102x6 STM32F102C6, STM32F102R6 – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs • 1 × 12-bit, 1.2 µs A/D converter (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor • Up to 51 fast I/O ports – 37/51 I/Os all mappable on 16 external interrupt vectors and almost all 5V-tolerant May 2015 DocID15057 Rev 5 1/78 This is information on a product in full production. www.st.com

Contents STM32F102x4, STM32F102x6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 28 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 29 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 47 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Contents 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.1 Evaluating the maximum junction temperature for an application . . . . . 74 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DocID15057 Rev 5 3/78 3

List of tables STM32F102x4, STM32F102x6 List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. STM32F102xx USB access line family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Low-density STM32F102xx pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 33 Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 33 Table 16. Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 37 Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 22. LSE oscillator characteristics (f = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LSE Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 26. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 28. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 31. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 33. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 36. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 39. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 40. SCL frequency (f = 36 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PCLK1 DD_I2C Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 42. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 43. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 44. USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 List of tables Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 46. R max for f = 12 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 AIN ADC Table 47. ADC accuracy - limited test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 48. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 49. TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 50. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 51. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 52. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 53. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DocID15057 Rev 5 5/78 5

List of figures STM32F102x4, STM32F102x6 List of figures Figure 1. STM32F102T8 medium-density USB access line block diagram. . . . . . . . . . . . . . . . . . . . 10 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 19 Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 19 Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 32 Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 32 Figure 12. Typical current consumption on V with RTC on versus temperature at different BAT V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 BAT Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V = 3.3V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at V = 3.3V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD Figure 15. Typical current consumption in Standby mode versus temperature at V = 3.3V and DD 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 19. Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 20. Standard I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 21. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 22. 5V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 23. 5V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 26. I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 27. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 28. SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 29. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 30. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 31. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 33. Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 34. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 67 Figure 35. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 36. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 37. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 70 Figure 38. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 39. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 40. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 D A 6/78 DocID15057 Rev 5

Introduction STM32F102x4, STM32F102x6 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of STM32F102x4 and STM32F102x6 low-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family. please refer to Section2.2: Full compatibility throughout the family. The medium-density STM32F102xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference Manual, available from the ARM® website. 7/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description 2 Description The STM32F102xx medium-density USB access line incorporates the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory of 16 or 32 Kbytes and SRAM of 4 or 6 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (one I2C, one SPI, one USB and two USARTs), one 12-bit ADC and two general-purpose 16-bit timers. The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6V power supply. A comprehensive set of power-saving mode allows the design of low- power applications. The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm and LQFP64 10×10mm packages. The STM32F102xx medium-density USB access line microcontrollers are suitable for a wide range of applications. • Application control and user interface • Medical and handheld equipment • PC peripherals, gaming and GPS platforms • Industrial applications: PLC, inverters, printers, and scanners • Alarm systems, Video intercom, and HVAC Figure1 shows the general block diagram of the device family. DocID15057 Rev 5 8/78 66

Description STM32F102x4, STM32F102x6 2.1 Device overview Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features and peripheral counts Peripheral STM32F102Cx STM32F102Rx Flash - Kbytes 16 32 16 32 SRAM - Kbytes 4 6 4 6 Timers General-purpose 2 2 2 2 SPI 1 1 1 1 Communication I2C 1 1 1 1 interfaces USART 2 2 2 2 USB 1 1 1 1 12-bit synchronized ADC 1 1 number of channels 10 channels 16 channels GPIOs 37 51 CPU frequency 48 MHz Operating voltage 2.0 to 3.6 V Ambient temperature: –40 to +85 °C (see Table8) Operating temperatures Junction temperature: –40 to +105 °C (see Table8) Packages LQFP48 LQFP64 9/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description Figure 1. STM32F102T8 medium-density USB access line block diagram TRACECLK TRACED[0:3] TPIU as ASJNTJRTSDTI SW/JTAG TSrWacDe/trig pbus CooTnnrttaroclele r VOPLOTW. REREG. VDD = 2 to 3.6 V JJTTCMKS/S/SWWCDLIOK Cortex M3 CPU Ibus oblce Flash 32 KB 3.3 V to 1.8 V VSS a aJsT DAOF Fmax: 48 MHz Dbus FlashInterf 64 bit @VDD NVIC NVIC System Matrix S6 RKABM @VDD s u B PCLK1 OSC_IN GP DMA PCLK2 PLL & XTAL OSC OSC_OUT CLOCK 4-16 MHz 7 channels HCLK MANAGT FCLK z H M RC 8 MHz 8 IWDG NRST SU@SPUEVPRDPVDLIASYI ON HB:F=4max @RCV D4D0 AkHz @VBAT Sinttaenrdfabcye VBAT A VDDA POR / PDR Rst OSC32_IN VSSA XTAL 32 kHz OSC32_OUT PVD Int AHB2 AHB2 RTC Barecgkup TAMPER-RTC APB2 APB1 AWU EXTI Backup interface 51AF WAKEUP TIM2 4 Channels PA[15:1] GPIOA z TIM3 4 Channels H PB[15:0] GPIOB M 4 RX,TX, CTS, RTS, PC[15:0] GPIOC = 2max USART2 CK, SmartCard as AF PD[2:0] GPIOD 1: F I2C SasC AL,FSDA,SMBAL z B SCMKO,NSSI,SM aISsO A,F SPI 8 MH AP USB 2.0 FS USBDP, USBDM as AF 4 RSmX,aTrXtC, CarTdS a, sR ATSF, USART1 = max W WD G F 2 : B @VDDA AP 16AF 12bitADC1 IF Temp sensor ai15452b 1. AF = alternate function on I/O port pin. 2. T = –40 °C to +85 °C (junction temperature up to 105 °C). A DocID15057 Rev 5 10/78 66

Description STM32F102x4, STM32F102x6 Figure 2. Clock tree (cid:52)(cid:79)(cid:0)(cid:38)(cid:76)(cid:65)(cid:83)(cid:72)(cid:0)(cid:80)(cid:82)(cid:79)(cid:71)(cid:14)(cid:0)(cid:73)(cid:70)(cid:0)(cid:38)(cid:44)(cid:41)(cid:52)(cid:38)(cid:35)(cid:44)(cid:43) (cid:24)(cid:0)(cid:45)(cid:40)(cid:90) (cid:40)(cid:51)(cid:41)(cid:0)(cid:50)(cid:35) (cid:40)(cid:51)(cid:41) (cid:53)(cid:51)(cid:34) (cid:20)(cid:24)(cid:0)(cid:45)(cid:40)(cid:90) (cid:53)(cid:51)(cid:34)(cid:35)(cid:44)(cid:43) (cid:48)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:84)(cid:79)(cid:0)(cid:53)(cid:51)(cid:34)(cid:0)(cid:73)(cid:78)(cid:84)(cid:69)(cid:82)(cid:70)(cid:65)(cid:67)(cid:69) (cid:15)(cid:18) (cid:15)(cid:17)(cid:12)(cid:0)(cid:17)(cid:14)(cid:21) (cid:40)(cid:35)(cid:44)(cid:43) (cid:20)(cid:24)(cid:0)(cid:45)(cid:40)(cid:90)(cid:0)(cid:77)(cid:65)(cid:88) (cid:84)(cid:79)(cid:0)(cid:33)(cid:40)(cid:34)(cid:0)(cid:66)(cid:85)(cid:83)(cid:12)(cid:0)(cid:67)(cid:79)(cid:82)(cid:69)(cid:12)(cid:0) (cid:35)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0) (cid:77)(cid:69)(cid:77)(cid:79)(cid:82)(cid:89)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:36)(cid:45)(cid:33) (cid:37)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69)(cid:0)(cid:8)(cid:19)(cid:0)(cid:66)(cid:73)(cid:84)(cid:83)(cid:9) (cid:15)(cid:24) (cid:84)(cid:79)(cid:0)(cid:35)(cid:79)(cid:82)(cid:84)(cid:69)(cid:88)(cid:0)(cid:51)(cid:89)(cid:83)(cid:84)(cid:69)(cid:77)(cid:0)(cid:84)(cid:73)(cid:77)(cid:69)(cid:82) (cid:48)(cid:44)(cid:44)(cid:51)(cid:50)(cid:35) (cid:51)(cid:55) (cid:48)(cid:44)(cid:44)(cid:45)(cid:53)(cid:44) (cid:38)(cid:35)(cid:44)(cid:43)(cid:0)(cid:35)(cid:79)(cid:82)(cid:84)(cid:69)(cid:88) (cid:40)(cid:51)(cid:41) (cid:70)(cid:82)(cid:69)(cid:69)(cid:0)(cid:82)(cid:85)(cid:78)(cid:78)(cid:73)(cid:78)(cid:71)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75) (cid:14)(cid:14)(cid:14)(cid:12)(cid:0)(cid:88)(cid:17)(cid:22) (cid:51)(cid:57)(cid:51)(cid:35)(cid:44)(cid:43) (cid:33)(cid:40)(cid:34) (cid:33)(cid:48)(cid:34)(cid:17) (cid:18)(cid:20)(cid:0)(cid:45)(cid:40)(cid:90)(cid:0)(cid:77)(cid:65)(cid:88) (cid:48)(cid:35)(cid:44)(cid:43)(cid:17) (cid:88)(cid:18)(cid:12)(cid:0)(cid:88)(cid:19)(cid:12)(cid:0)(cid:88)(cid:20)(cid:0) (cid:48)(cid:44)(cid:44)(cid:35)(cid:44)(cid:43) (cid:20)(cid:24)(cid:0)(cid:45)(cid:40)(cid:90) (cid:48)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:48)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:84)(cid:79)(cid:0)(cid:33)(cid:48)(cid:34)(cid:17) (cid:48)(cid:44)(cid:44) (cid:0)(cid:77)(cid:65)(cid:88) (cid:15)(cid:17)(cid:12)(cid:0)(cid:18)(cid:14)(cid:14)(cid:21)(cid:17)(cid:18) (cid:15)(cid:17)(cid:12)(cid:0)(cid:18)(cid:12)(cid:0)(cid:20)(cid:12)(cid:0)(cid:24)(cid:12)(cid:0)(cid:17)(cid:22) (cid:48)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:82)(cid:65)(cid:76)(cid:0)(cid:35)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:80)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:82)(cid:65)(cid:76)(cid:83) (cid:40)(cid:51)(cid:37) (cid:37)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69)(cid:0)(cid:8)(cid:17)(cid:19)(cid:0)(cid:66)(cid:73)(cid:84)(cid:83)(cid:9) (cid:52)(cid:41)(cid:45)(cid:18)(cid:12)(cid:0)(cid:52)(cid:41)(cid:45)(cid:19) (cid:84)(cid:79)(cid:0)(cid:52)(cid:41)(cid:45)(cid:18)(cid:12)(cid:0)(cid:52)(cid:41)(cid:45)(cid:19) (cid:35)(cid:51)(cid:51) (cid:41)(cid:70)(cid:0)(cid:8)(cid:33)(cid:48)(cid:34)(cid:17)(cid:0)(cid:80)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82)(cid:0)(cid:29)(cid:17)(cid:9)(cid:0)(cid:88)(cid:17) (cid:52)(cid:41)(cid:45)(cid:56)(cid:35)(cid:44)(cid:43) (cid:69)(cid:76)(cid:83)(cid:69)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:88)(cid:18) (cid:48)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:82)(cid:65)(cid:76)(cid:0)(cid:35)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0) (cid:37)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69)(cid:0)(cid:8)(cid:18)(cid:0)(cid:66)(cid:73)(cid:84)(cid:83)(cid:9) (cid:48)(cid:44)(cid:44)(cid:56)(cid:52)(cid:48)(cid:50)(cid:37) (cid:33)(cid:48)(cid:34)(cid:18) (cid:20)(cid:24)(cid:0)(cid:45)(cid:40)(cid:90)(cid:0)(cid:77)(cid:65)(cid:88) (cid:48)(cid:35)(cid:44)(cid:43)(cid:18) (cid:48)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:47)(cid:51)(cid:35)(cid:63)(cid:47)(cid:53)(cid:52) (cid:20)(cid:13)(cid:17)(cid:22)(cid:0)(cid:45)(cid:40)(cid:90) (cid:15)(cid:17)(cid:12)(cid:0)(cid:18)(cid:12)(cid:0)(cid:20)(cid:12)(cid:0)(cid:24)(cid:12)(cid:0)(cid:17)(cid:22) (cid:48)(cid:69)(cid:82)(cid:73)(cid:80)(cid:72)(cid:69)(cid:82)(cid:65)(cid:76)(cid:0)(cid:35)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0) (cid:80)(cid:84)(cid:79)(cid:69)(cid:0)(cid:33)(cid:82)(cid:73)(cid:80)(cid:48)(cid:72)(cid:34)(cid:69)(cid:18)(cid:82)(cid:65)(cid:76)(cid:83) (cid:40)(cid:51)(cid:37)(cid:0)(cid:47)(cid:51)(cid:35) (cid:37)(cid:78)(cid:65)(cid:66)(cid:76)(cid:69)(cid:0)(cid:8)(cid:17)(cid:17)(cid:0)(cid:66)(cid:73)(cid:84)(cid:83)(cid:9) (cid:47)(cid:51)(cid:35)(cid:63)(cid:41)(cid:46)(cid:0) (cid:15)(cid:18) (cid:33)(cid:36)(cid:35) (cid:84)(cid:79)(cid:0)(cid:33)(cid:36)(cid:35) (cid:48)(cid:82)(cid:69)(cid:83)(cid:67)(cid:65)(cid:76)(cid:69)(cid:82) (cid:15)(cid:17)(cid:18)(cid:24) (cid:15)(cid:18)(cid:12)(cid:0)(cid:20)(cid:12)(cid:0)(cid:22)(cid:12)(cid:0)(cid:24) (cid:33)(cid:36)(cid:35)(cid:35)(cid:44)(cid:43) (cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:41)(cid:46) (cid:84)(cid:79)(cid:0)(cid:50)(cid:52)(cid:35) (cid:44)(cid:51)(cid:37)(cid:0)(cid:47)(cid:51)(cid:35) (cid:44)(cid:51)(cid:37) (cid:19)(cid:18)(cid:14)(cid:23)(cid:22)(cid:24)(cid:0)(cid:75)(cid:40)(cid:90) (cid:50)(cid:52)(cid:35)(cid:35)(cid:44)(cid:43) (cid:47)(cid:51)(cid:35)(cid:19)(cid:18)(cid:63)(cid:47)(cid:53)(cid:52) (cid:50)(cid:52)(cid:35)(cid:51)(cid:37)(cid:44)(cid:59)(cid:17)(cid:26)(cid:16)(cid:61)(cid:0) (cid:44)(cid:51)(cid:41)(cid:0)(cid:50)(cid:35) (cid:44)(cid:51)(cid:41) (cid:84)(cid:79)(cid:0)(cid:41)(cid:78)(cid:68)(cid:69)(cid:80)(cid:69)(cid:78)(cid:68)(cid:69)(cid:78)(cid:84)(cid:0)(cid:55)(cid:65)(cid:84)(cid:67)(cid:72)(cid:68)(cid:79)(cid:71)(cid:0)(cid:8)(cid:41)(cid:55)(cid:36)(cid:39)(cid:9) (cid:20)(cid:16)(cid:0)(cid:75)(cid:40)(cid:90) (cid:41)(cid:55)(cid:36)(cid:39)(cid:35)(cid:44)(cid:43) (cid:44)(cid:69)(cid:71)(cid:69)(cid:78)(cid:68)(cid:26) (cid:40)(cid:51)(cid:37)(cid:0)(cid:29)(cid:0)(cid:72)(cid:73)(cid:71)(cid:72)(cid:13)(cid:83)(cid:80)(cid:69)(cid:69)(cid:68)(cid:0)(cid:69)(cid:88)(cid:84)(cid:69)(cid:82)(cid:78)(cid:65)(cid:76)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:83)(cid:73)(cid:71)(cid:78)(cid:65)(cid:76) (cid:40)(cid:51)(cid:41)(cid:0)(cid:29)(cid:0)(cid:72)(cid:73)(cid:71)(cid:72)(cid:13)(cid:83)(cid:80)(cid:69)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:84)(cid:69)(cid:82)(cid:78)(cid:65)(cid:76)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:83)(cid:73)(cid:71)(cid:78)(cid:65)(cid:76) (cid:45)(cid:65)(cid:73)(cid:78) (cid:15)(cid:18) (cid:48)(cid:44)(cid:44)(cid:35)(cid:44)(cid:43) (cid:44)(cid:51)(cid:41)(cid:0)(cid:29)(cid:0)(cid:76)(cid:79)(cid:87)(cid:13)(cid:83)(cid:80)(cid:69)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:84)(cid:69)(cid:82)(cid:78)(cid:65)(cid:76)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:83)(cid:73)(cid:71)(cid:78)(cid:65)(cid:76) (cid:35)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:47)(cid:85)(cid:84)(cid:80)(cid:85)(cid:84) (cid:44)(cid:51)(cid:37)(cid:0)(cid:29)(cid:0)(cid:76)(cid:79)(cid:87)(cid:13)(cid:83)(cid:80)(cid:69)(cid:69)(cid:68)(cid:0)(cid:69)(cid:88)(cid:84)(cid:69)(cid:82)(cid:78)(cid:65)(cid:76)(cid:0)(cid:67)(cid:76)(cid:79)(cid:67)(cid:75)(cid:0)(cid:83)(cid:73)(cid:71)(cid:78)(cid:65)(cid:76) (cid:45)(cid:35)(cid:47)(cid:0) (cid:40)(cid:51)(cid:41) (cid:40)(cid:51)(cid:37) (cid:51)(cid:57)(cid:51)(cid:35)(cid:44)(cid:43) (cid:45)(cid:35)(cid:47)(cid:0) (cid:65)(cid:73)(cid:17)(cid:21)(cid:20)(cid:21)(cid:21)(cid:66) 1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output (USBCLK) at 48MHz. 2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz. 3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock. 11/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description 2.2 Full compatibility throughout the family The STM32F102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to as medium-density devices. Low-density devices are an extension of the STM32F102x8/B devices, they are specified in the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM capacities, a timer and a few communication interfaces less. The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx access line and STM32F103xx performance line devices. Table 3. STM32F102xx USB access line family Low-density STM32F102xx devices Medium-density STM32F102xx devices Pinout 16 KB Flash 32 KB Flash(1) 64 KB Flash 128 KB Flash 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 64 2 × USARTs, 2 × 16-bit timers 3 × USARTs, 3 × 16-bit timers 48 1 × SPI, 1 × I2C, 1 × ADC, 1 × USB 2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB 2 × USARTs, 3 × 16- bit timers 36 - - - 1× SPI, 1× I2C, 1 × ADC, 1 × USB 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices. 2.3 Overview ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM® Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM® core in the memory size usually associated with 8- and 16-bit devices. The STM32F102xx medium-density USB access line having an embedded ARM® core is therefore compatible with all ARM® tools and software. Embedded Flash memory 16 or 32 Kbytes of embedded Flash is available for storing programs and data. DocID15057 Rev 5 12/78 66

Description STM32F102x4, STM32F102x6 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity, In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. Embedded SRAM 4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F102xx medium-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup. however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See Figure2 for details on the clock tree. 13/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description Boot modes At startup, boot pins are used to select one of five boot options: • Boot from User Flash • Boot from System Memory • Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. Power supply schemes • V = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. DD Provided externally through V pins. DD • V , V = 2.0 to 3.6 V: External analog power supplies for ADC. Reset blocks, RCs SSA DDA and PLL (minimum voltage to be applied to V is 2.4 V when the ADC is used). DDA V and V must be connected to V and V , respectively. DDA SSA DD SS • V = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup BAT registers (through power switch) when V is not present. DD For more details on how to connect power pins, refer to Figure8: Power supply scheme. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V is below a specified threshold, V , without the need for an DD POR/PDR external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the V /V power supply and compares it to the V threshold. An interrupt can be DD DDA PVD generated when V /V drops below the V threshold and/or when V /V is DD DDA PVD DD DDA higher than the V threshold. The interrupt service routine can then generate a warning PVD message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table10: Embedded reset and power control block characteristics for the values of V and V . POR/PDR PVD Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop mode • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. DocID15057 Rev 5 14/78 66

Description STM32F102x4, STM32F102x6 Low-power modes The STM32F102xx medium-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on V supply when present or through the V pin. The backup registers are ten 16-bit DD BAT registers used to store 20 bytes of user application data when V power is not present. DD The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare 15/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock. it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source General-purpose timers (TIMx) There are 2 synchronizable general-purpose timers embedded in the STM32F102xx medium-density USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to 12 input captures / output compares / PWMs on the LQFP48 and LQFP64 packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They both have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. I²C bus One I²C bus interface can operate in multi-master and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. The I2C interface can be served by DMA and they support SM Bus 2.0/PM Bus. DocID15057 Rev 5 16/78 66

Description STM32F102x4, STM32F102x6 Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) The SPI is able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPI can be served by the DMA controller. Universal serial bus (USB) The STM32F102xx medium-density USB access line embeds an USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. ADC (analog to digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. Temperature sensor The temperature sensor has to generate a a voltage that varies linearly with temperature. The conversion range is between 2V < V < 3.6V. The temperature sensor is internally DDA connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 17/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Description The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DocID15057 Rev 5 18/78 66

Pinout and pin description STM32F102x4, STM32F102x6 3 Pinout and pin description Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout DD_3 SS_3 B9 B8 OOT0 B7 B6 B5 B4 B3 A15 A14 VVPPBPPPPPPP 48474645 4443424140393837 VBAT 1 36 VDD_2 PC13-TAMPER-RTC 2 35 VSS_2 PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PD0-OSC_IN 5 32 PA11 PD1-OSC_OUT 6 LQFP48 31 PA10 NRST 7 30 PA9 VSSA 8 29 PA8 VDDA 9 28 PB15 PA0-WKUP 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 131415161718192021222324 345670120111 AAAAABBB11__ PPPPPPPPBBSD PPSD VV ai14378d Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout DD_3 SS_3 B9 B8 OOT0 B7 B6 B5 B4 B3 D2 C12 C11 C10 A15 A14 VVPPBPPPPPPPPPPP 64636261605958575655545352515049 VBAT 1 48 VDD_2 PC13-TAMPER-RTC 2 47 VSS_2 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PD0-OSC_IN 5 44 PA11 PD1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 LQFP64 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17181920212223242526272829303132 3444567450120111 A__AAAACCBBB11__ PSDPPPPPPPPPBBSD SD PPSD VV VV ai14387c 19/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Pinout and pin description Table 4. Low-density STM32F102xx pin definitions Pins Alternatefunctions(3) (4) 2) 1) (el Main FP48 FP64 Pin name (Type O lev (fauftnecrt iroens(e3t)) Default Remap LQ LQ I / 1 1 V S - V - - BAT BAT 2 2 PC13-TAMPER-RTC(5) I/O - PC13(6) TAMPER-RTC - 3 3 PC14-OSC32_IN(5) I/O - PC14(6) OSC32_IN - 4 4 PC15-OSC32_OUT(5) I/O - PC15(6) OSC32_OUT - 5 5 OSC_IN I/O FT OSC_IN - PD0(7) 6 6 OSC_OUT I/O FT OSC_OUT - PD1(7) 7 7 NRST I/O - NRST - - - 8 PC0 I/O - PC0 ADC_IN10 - - 9 PC1 I/O - PC1 ADC_IN11 - - 10 PC2 I/O - PC2 ADC_IN12 - - 11 PC3 I/O - PC3 ADC_IN13 - 8 12 V S - V - - SSA SSA 9 13 V S - V - - DDA DDA WKUP/USART2_CTS/ 10 14 PA0-WKUP I/O - PA0 ADC_IN0/ - TIM2_CH1_ETR(8) USART2_RTS/ 11 15 PA1 I/O - PA1 - ADC_IN1/TIM2_CH2(8) USART2_TX/ 12 16 PA2 I/O - PA2 - ADC_IN2/TIM2_CH3(8) USART2_RX/ 13 17 PA3 I/O - PA3 - ADC_IN3/TIM2_CH4(8) - 18 V S - V - - SS_4 SS_4 - 19 V S - V - - DD_4 DD_4 SPI_NSS(8)/ADC_IN4 14 20 PA4 I/O - PA4 - USART2_CK/ 15 21 PA5 I/O - PA5 SPI_SCK(8)/ADC_IN5 - SPI_MISO(8)/ADC_IN6/ 16 22 PA6 I/O - PA6 - TIM3_CH1(8) SPI_MOSI(8)/ADC_IN7/ 17 23 PA7 I/O - PA7 - TIM3_CH2(8) - 24 PC4 I/O - PC4 ADC_IN14 - - 25 PC5 I/O - PC5 ADC_IN15 - 18 26 PB0 I/O - PB0 ADC_IN8/TIM3_CH3(8) - 19 27 PB1 I/O - PB1 ADC_IN9/TIM3_CH4(8) - DocID15057 Rev 5 20/78 66

Pinout and pin description STM32F102x4, STM32F102x6 Table 4. Low-density STM32F102xx pin definitions (continued) Pins Alternatefunctions(3) (4) 2) 1) (el Main FP48 FP64 Pin name (Type O lev (fauftnecrt iroens(e3t)) Default Remap LQ LQ I / 20 28 PB2 I/O FT PB2/BOOT1 - - 21 29 PB10 I/O FT PB10 (8) TIM2_CH3 22 30 PB11 I/O FT PB11 (8) TIM2_CH4 23 31 V S - V - - SS_1 SS_1 24 32 V S - V - - DD_1 DD_1 25 33 PB12 I/O FT PB12 (8) - 26 34 PB13 I/O FT PB13 - - 27 35 PB14 I/O FT PB14 - - 28 36 PB15 I/O FT PB15 - - - 37 PC6 I/O FT PC6 - TIM3_CH1 - 38 PC7 I/O FT PC7 - TIM3_CH2 - 39 PC8 I/O FT PC8 - TIM3_CH3 - 40 PC9 I/O FT PC9 - TIM3_CH4 29 41 PA8 I/O FT PA8 USART1_CK/MCO - 30 42 PA9 I/O FT PA9 USART1_TX(8) - 31 43 PA10 I/O FT PA10 USART1_RX(8) - 32 44 PA11 I/O FT PA11 USART1_CTS/USB_DM - 33 45 PA12 I/O FT PA12 USART1_RTS/USB_DP - JTMS- 34 46 PA13 I/O FT - PA13 SWDIO 35 47 V S - V - - SS_2 SS_2 36 48 V S - V - - DD_2 DD_2 JTCK/ 37 49 PA14 I/O FT - PA14 SWCLK TIM2_CH1_ETR 38 50 PA15 I/O FT JTDI - / PA15 /SPI_NSS - 51 PC10 I/O FT PC10 - - - 52 PC11 I/O FT PC11 - - - 53 PC12 I/O FT PC12 - - - 54 PD2 I/O FT PD2 - - TIM2_CH2/ PB3/ 39 55 PB3 I/O FT JTDO - TRACESWO/ SPI_SCK 21/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Pinout and pin description Table 4. Low-density STM32F102xx pin definitions (continued) Pins Alternatefunctions(3) (4) 2) 1) (el Main FP48 FP64 Pin name (Type O lev (fauftnecrt iroens(e3t)) Default Remap LQ LQ I / TIM3_CH1 / PB4 40 56 PB4 I/O FT JNTRST - SPI_MISO TIM3_CH2 / 41 57 PB5 I/O - PB5 I2C_SMBA SPI_MOSI 42 58 PB6 I/O FT PB6 I2C_SCL(8) USART1_TX 43 59 PB7 I/O FT PB7 I2C_SDA(8) USART1_RX 44 60 BOOT0 I - BOOT0 - - 45 61 PB8 I/O FT PB8 - I2C_SCL 46 62 PB9 I/O FT PB9 - I2C_SDA 47 63 V S - V - - SS_3 SS_3 48 64 V S - V - - DD_3 DD_3 1. I = input, O = output, S = supply. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table3 on page12. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the STMicroelectronics website: www.st.com. 7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. DocID15057 Rev 5 22/78 66

Memory mapping STM32F102x4, STM32F102x6 4 Memory mapping The memory map is shown in Figure5. Figure 5. Memory map APB memory space 0xFFFF FFFF reserved 0xFFFF FFFF 0xE010 0000 Cortex-M3 internal 0xE000 0000 peripherals 0x4002 3400 reserved 7 CRC 0x4002 3000 reserved 0xE010 0000 0x4002 2400 Cortex-M3 internal 0xE000 0000 peripherals 0x4002 2000 Flash interface 0x4002 1400 reserved RCC 0x4002 1000 6 0x4002 0400 reserved 0x4002 0000 DMA 0xC000 0000 reserved 0x4001 3C00 USART1 0x4001 3800 reserved 5 0x4001 3400 SPI 0x4001 3000 reserved 0xA000 0000 0x4001 2C00 reserved 0x4001 2800 ADC1 0x4001 2400 reserved 4 0x1FFF FFFF 0x4001 1800 0x1FFF F80F reserved 0x4001 1400 Port D 0x8000 0000 Option Bytes 0x4001 1000 Port C 0x1FFF F800 0x4001 0C00 Port B 0x4001 0800 Port A 3 System memory 0x4001 0400 EXTI 0x4001 0000 AFIO 0x1FFF F000 reserved 0x6000 0000 0x4000 7400 PWR 0x4000 7000 BKP 0x4000 6C00 2 reserved 0x4000 6400 512 byte USB SRAM reserved 0x4000 6000 Peripherals USB registers 0x4000 0000 0x4000 5C00 reserved 0x4000 5800 0x4000 5400 I2C 1 reserved 0x4000 4800 0x2000 17FF 0x4000 4400 USART2 SRAM 0x2000 0000 reserved 0x0800 FFFF 0x4000 3400 0 0x4000 3000 IWDG Flash memory 0x4000 2C00 WWDG 0x4000 2800 RTC 0x0800 0000 0x4000 0800 reserved 0x0000 0000 Aliased to Flash or 0x4000 0400 TIM3 system memory depending on 0x4000 0000 TIM2 0x0000 0000 BOOT pins Reserved ai15454b 23/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referred to V . SS 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the A DD 2V ≤ V ≤ 3.6V voltage range). They are given only as design guidelines and are not DD tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure7. DocID15057 Rev 5 24/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 6. Pin loading conditions Figure 7. Pin input voltage STM32F102 pin STM32F102 pin C = 50 pF VIN ai14972 ai14973 5.1.6 Power supply scheme Figure 8. Power supply scheme VBAT Backup circuitry 1.8-3.6 V Power switch (OSC32K,RTC, Wake-up logic Backup registers) OUT er hift IO GP I/Os IN vel s Logic Kernel logic e L (CPU, Digital VDD & Memories) VDD 1/2/3/4 Regulator 3 × 100 nF VSS + 1 × 4.7 µF 1/2/3/4 VDD VDDA VREF+ Analog: 10 nF ADC RCs, PLL, + 1 µF ... VREF- VSSA ai14882c Caution: In Figure8, the 4.7 µF capacitor must be connected to V . DD3 25/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5.1.7 Current consumption measurement Figure 9. Current consumption measurement scheme (cid:41)(cid:36)(cid:36)(cid:63)(cid:54)(cid:34)(cid:33)(cid:52) (cid:54)(cid:34)(cid:33)(cid:52) (cid:41)(cid:36)(cid:36) (cid:54)(cid:36)(cid:36) (cid:54)(cid:36)(cid:36)(cid:33) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:18)(cid:22) 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table5: Voltage characteristics, Table6: Current characteristics, and Table7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Voltage characteristics Symbol Ratings Min Max Unit External main supply voltage (including V − V –0.3 4.0 DD SS V and V )(1) DDA DD V Input voltage on five volt tolerant pin V − 0.3 V + 4.0 V (2) SS DD IN Input voltage on any other pin V − 0.3 4.0 SS |ΔV | Variations between different V power pins - 50 DDx DD Variations between all the different ground mV |V − V | - 50 SSX SS pins Electrostatic discharge voltage see Section5.3.11: Absolute maximum V ESD(HBM) (human body model) ratings (electrical sensitivity) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power DD DDA SS SSA supply, in the permitted range. 2. V maximum must always be respected. Refer to Table6: Current characteristics for the maximum IN allowed injected current values. DocID15057 Rev 5 26/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 6. Current characteristics Symbol Ratings Max. Unit I Total current into V /V power lines (source)(1) 150 VDD DD DDA I Total current out of V ground lines (sink)(1) 150 VSS SS Output current sunk by any I/O and control pin 25 I IO Output current source by any I/Os and control pin -25 mA Injected current five volt tolerant pins(3) -5/+0 I (2) INJ(PIN) Injected current on any other pin(4) ± 5 ΣI Total injected current (sum of all I/O and control pins)(5) ± 25 INJ(PIN) 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power DD DDA SS SSA supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. 3. Positive injection is not possible on these I/Os. A negative injection is induced by V <V . I must IN SS INJ(PIN) never be exceeded. Refer to Table5 for maximum allowed input voltage values. 4. A positive injection is induced by V >V while a negative injection is induced by V <V . I must IN DD IN SS INJ(PIN) never be exceeded. Refer to Table5 for maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 7. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range –65 to +150 °C STG T Maximum junction temperature 150 °C J 27/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 8. General operating conditions Symbol Parameter Conditions Min Max Unit f Internal AHB clock frequency - 0 48 HCLK f Internal APB1 clock frequency - 0 24 MHz PCLK1 f Internal APB2 clock frequency - 0 48 PCLK2 V Standard operating voltage - 2 3.6 V DD Analog operating voltage 2 3.6 (ADC not used) Must be the same potential V (1) DDA Analog operating voltage as VDD(2) 2.4 3.6 (ADC used) Standard IO –0.3 VDD+ V 0.3 VIN I/O input voltage FTIO(3) 2 V < VDD ≤ 3.6 V –0.3 5.5 V = 2 V –0.3 5.2 DD BOOT0 0 5.5 LQFP48 - 363 PD Power dissipation at TA = 85°C(4) mW LQFP64 - 444 Maximum power dissipation –40 85 °C TA Ambient temperature Low power dissipation(5) –40 105 °C TJ Junction temperature range - –40 105 °C 1. When the ADC is used, refer to Table45: ADC characteristics. 2. It is recommended to power V and V from the same source. A maximum difference of 300mV DD DDA between V and V can be tolerated during power-up and operation. DD DDA 3. To sustain a voltage higher than V +0.3 V, the internal pull-up/pull-down resistors must be disabled. DD 4. If T is lower, higher P values are allowed as long as T does not exceed T max (see Section6.3: A D J J Thermal characteristics). 5. In low power dissipation state, T can be extended to this range as long as T does not exceed T max (see A J J Section6.3: Thermal characteristics). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for T . A Table 9. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max Unit V rise time rate 0 ∞ DD t - µs/V VDD V fall time rate 20 ∞ DD DocID15057 Rev 5 28/78 66

Electrical characteristics STM32F102x4, STM32F102x6 5.3.3 Embedded reset and power control block characteristics The parameters given in Table10 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD . Table 10. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2.0 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V V PVD detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V V (2) PVD hysteresis - - 100 - mV PVDhyst Power on/power down Falling edge 1.8(1) 1.88 1.96 V V POR/PDR reset threshold Rising edge 1.84 1.92 2.0 V V PDR hysteresis - - 40 - mV PDRhyst t (2) Reset temporization - 1.5 2.5 4.5 ms RSTTEMPO 1. The product behavior is guaranteed by design down to the minimum V value. POR/PDR 2. Guaranteed by design, not tested in production. 5.3.4 Embedded reference voltage The parameters given in Table11 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD 29/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Table 11. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit V Internal reference voltage –40 °C < T < +85 °C 1.16 1.20 1.24 V REFINT A ADC sampling time when reading T (1) - - 5.1 17.1(2) µs S_vrefint the internal reference voltage Internal reference voltage spread V (2) V = 3 V ±10 mV - - 10 mV RERINT over the temperature range DD ppm/ T (2) Temperature coefficient - - - 100 Coeff °C 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure9: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at V or V (no load) DD SS • All peripherals are disabled except if it is explicitly mentioned • The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1 HCLK wait state from 24 to 48 MHz) • Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled f = f , f = f PCLK1 HCLK/2 PCLK2 HCLK The parameters given in Table12 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD DocID15057 Rev 5 30/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 12. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions f Unit HCLK T = 85 °C A 48 MHz 32 36 MHz 26 External clock (2), all 24 MHz 18 peripherals enabled 16 MHz 13 Supply current 8 MHz 7 I mA DD in Run mode 48 MHz 23 36 MHz 19 External clock (2), all 24 MHz 13 peripherals Disabled 16 MHz 10 8 MHz 6 1. Based on characterization results, not tested in production. 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK Table 13. Maximum current consumption in Run mode, code with data processing running from RAM Max Symbol Parameter Conditions f Unit HCLK T = 85 °C(1) A 48 MHz 27 36 MHz 20 External clock (2), all 24 MHz 14 peripherals enabled 16 MHz 10 Supply current in 8 MHz 6 I mA DD Run mode 48 MHz 19 36 MHz 15 External clock(2) all 24 MHz 10 peripherals disabled 16 MHz 7 8 MHz 5 1. Based on characterization, tested in production at V max, f max. DD HCLK 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK 31/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) - code with data processing running from RAM, peripherals enabled 30 25 20 ) A m 48 MHz ( n o 36MHz pti 15 m 16 MHz u ns 8 MHz o C 10 5 0 –40 °C 25 °C 0 °C 70 °C 85 °C Temperature (°C) Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) - code with data processing running from RAM, peripherals disabled 20 18 16 14 ) A m 12 48 MHz ( n o 36 MHz pti 10 m 16 MHz u ns 8 8 MHz o C 6 4 2 0 –40 °C 25 °C 0 °C 70 °C 85 °C Temperature (°C) DocID15057 Rev 5 32/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions f Unit HCLK T = 85 °C A 48 MHz 17 36 MHz 14 External clock(2), all 24 MHz 10 peripherals enabled 16 MHz 7 Supply current in 8 MHz 4 I mA DD Sleep mode 48 MHz 6 36 MHz 5 External clock(2), all 24 MHz 4.5 peripherals disabled 16 MHz 4 8 MHz 3 1. Based on characterization, tested in production at V max and f max with peripherals enabled. DD HCLK 2. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK Table 15. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Max Symbol Parameter Conditions V / Unit DD V /V V /V T = V = DD BAT DD BAT A BAT = 3.3V = 2.0V 85°C 2.4V Regulator in Run mode. Low-speed and high-speed internal RC oscillators and high-speed 21.3 21.7 - 160 oscillator OFF (no independent Supply current watchdog) in Stop mode Regulator in Low Power mode. Low-speed and high-speed internal RC oscillators and high-speed 11.3 11.7 - 145 oscillator OFF (no independent I DD watchdog) Low-speed internal RC oscillator and µA 2.75 3.4 - - independent watchdog ON Supply current Low-speed internal RC oscillator ON, 2.55 3.2 - - in Standby independent watchdog OFF mode(2) Low-speed internal RC oscillator and independent watchdog OFF, low- 1.55 1.9 - 3.2 speed oscillator and RTC OFF Backup I domain supply Low-speed oscillator and RTC ON 1.1 1.4 0.9 1.9(3) DD_VBAT current 1. Typical values are measured at T = 25 °C. A 33/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 2. To have the Standby consumption with RTC ON, add I (Low-speed oscillator and RTC ON) to I Standby (when DD_VBAT DD V is present the Backup Domain is powered by V supply). DD DD 3. Based on characterization, not tested in production. Figure 12. Typical current consumption on V with RTC on versus temperature at different BAT V values BAT 2.5 A ) 2 µ n ( 1.5 2 V o pti 2.4 V m 1 u 3 V s n Co 0.5 3.6 V 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17351 Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V = 3.3V and 3.6 V DD 45 40 35 A) 30 µ on ( 25 3.3 V pti m 20 3.6 V u s n o C 15 10 5 0 –45 °C 25 °C 85 °C Temperature (°C) DocID15057 Rev 5 34/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at V = 3.3V and 3.6 V DD 30 25 A) 20 µ n ( o 3.3 V pti 15 m 3.6 V u s n o C 10 5 0 –45 °C 25 °C 85 °C Temperature (°C) Figure 15. Typical current consumption in Standby mode versus temperature at V = 3.3V and DD 3.6 V 3.5 3 2.5 A) µ n ( 2 o 3.3 V pti m 3.6 V u 1.5 s n o C 1 0.5 0 –45 °C 25 °C 85 °C Temperature (°C) 35/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at V or V (no load) DD SS • All peripherals are disabled except if it is explicitly mentioned • The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1 HCLK wait state from 24 to 48 MHz) • Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled f = f , f = f , f = PCLK1 HCLK/4 PCLK2 HCLK/2 ADCCLK f /4 PCLK2 The parameters given in Table16 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD Table 16. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Typ(1) Symbol Parameter Conditions f Unit HCLK All peripherals All peripherals enabled(2) disabled 48 MHz 21.9 17.4 36 MHz 17.2 13.8 24 MHz 11.2 8.9 16 MHz 8.1 6.6 External 8 MHz 5 4.2 clock(3) 4 MHz 3 2.6 2 MHz 2 1.8 1 MHz 1.5 1.4 500 kHz 1.2 1.2 Supply 125 kHz 1.05 1 I current in mA DD Run mode 48 MHz 21.2 16.7 36 MHz 16.5 13.1 24 MHz 10.5 8.2 Running on high speed 16 MHz 7.4 5.9 internal RC (HSI), AHB 8 MHz 4.3 3.6 prescaler 4 MHz 2.4 2 used to reduce the 2 MHz 1.5 1.3 frequency 1 MHz 1.0 0.9 500 kHz 0.7 0.65 125 kHz 0.5 0.45 1. Typical values are measures at T = 25 °C, V = 3.3 V. A DD 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). DocID15057 Rev 5 36/78 66

Electrical characteristics STM32F102x4, STM32F102x6 3. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Typ(1) Symbol Parameter Conditions f Unit HCLK All peripherals All peripherals enabled(2) disabled 48 MHz 8.7 3.8 36 MHz 6.7 3.1 24 MHz 4.8 2.3 16 MHz 3.4 1.8 8 MHz 2 1.2 External clock(3) 4 MHz 1.5 1.1 2 MHz 1.25 1 1 MHz 1.1 0.98 500 kHz 1.05 0.96 Supply 125 kHz 1 0.95 I current in mA DD Sleep mode 48 MHz 8.1 3.2 36 MHz 6.1 2.5 24 MHz 4.2 1.7 Running on High 16 MHz 2.8 1.2 Speed Internal RC (HSI), AHB 8 MHz 1.4 0.55 prescaler used to 4 MHz 0.9 0.5 reduce the frequency 2 MHz 0.7 0.45 1 MHz 0.55 0.42 500 kHz 0.48 0.4 125 kHz 0.4 0.38 1. Typical values are measures at T = 25 °C, V = 3.3 V. A DD 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when f > 8 MHz. HCLK 37/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table18. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at V or V (no load) DD SS • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on • ambient operating temperature and V supply voltage conditions as summarized in DD Table5. Table 18. Peripheral current consumption(1) Peripheral µA/MHz DMA1 15.97 AHB (up to 48 MHz) CRC 1.67 BusMatrix(2) 8.33 APB1-Bridge 7.22 TIM2 33.33 TIM3 33.61 USART2 12.78 I2C1 10.83 APB1 (up to 24 MHz) USB 16.94 WWDG 3.33 PWR 1.94 BKP 2.78 IWDG 1.39 APB2-Bridge 3.33 GPIOA 7.50 GPIOB 6.81 GPIOC 7.22 APB2 (up to 48 MHz) GPIOD 6.94 SPI1 4.86 USART1 12.78 ADC1(3) (4) 15.54 1. f = 48 MHz, f = f /2, f = f , default prescaler value for each peripheral. HCLK APB1 HCLK APB2 HCLK 2. The BusMatrix is automatically active when at least one master is ON. 3. Specific conditions for ADC: f = 48 MHz, f = f /2, f = f , f = f /4. HCLK APB1 HCLK APB2 HCLK ADCCLK APB2 4. When ADON bit in the ADC_CR2 register is set to 1, there is an additional current consumption of 0, 68 mA. When we enable the ADC, there is an additional current consumption of 0, 06 mA. DocID15057 Rev 5 38/78 66

Electrical characteristics STM32F102x4, STM32F102x6 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table8. Table 19. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit f User external clock source frequency(1) 1 8 25 MHz HSE_ext V OSC_IN input pin high level voltage 0.7V - V HSEH DD DD V V OSC_IN input pin low level voltage V - 0.3V HSEL SS DD t w(HSE) OSC_IN high or low time(1) 5 - - t - w(HSE) ns t r(HSE) OSC_IN rise or fall time(1) - - 20 t f(HSE) C OSC_IN input capacitance(1) - 5 pF in(HSE) DuCy Duty cycle 45 - 55 % (HSE) I OSC_IN Input leakage current V ≤V ≤V - ±1 µA L SS IN DD 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table8. Table 20. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit f User external clock source frequency(1) - 32.768 1000 kHz LSE_ext V OSC32_IN input pin high level voltage 0.7V - V LSEH DD DD V V OSC32_IN input pin low level voltage V - 0.3V LSEL SS DD t w(LSE) OSC32_IN high or low time(1) 450 - - t - w(LSE) ns t r(LSE) OSC32_IN rise or fall time(1) - - 50 t f(LSE) C OSC32_IN input capacitance(1) - 5 - pF in(LSE) DuCy Duty cycle 30 - 70 % (LSE) I OSC32_IN Input leakage current V ≤V ≤V - - ±1 µA L SS IN DD 1. Guaranteed by design, not tested in production. 39/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 16. High-speed external clock source AC timing diagram VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External fHSE_ext IL clock source OSC_IN STM32F102xx ai14975b Figure 17. Low-speed external clock source AC timing diagram VLSEH 90% 10% VLSEL tr(LSE) tf(LSE) tW(LSE) tW(LSE) t TLSE External fLSE_ext OSC32_IN IL clock source STM32F102xx ai14976b DocID15057 Rev 5 40/78 66

Electrical characteristics STM32F102x4, STM32F102x6 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 21. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit f Oscillator frequency - 4 8 16 MHz OSC_IN R Feedback resistor - - 200 - kΩ F Recommended load capacitance C versus equivalent serial R = 30 Ω - 30 - pF S resistance of the crystal (R )(3) S V = 3.3 V i HSE driving current DD - - 1 mA 2 V = V with 30 pF load IN SS g Oscillator transconductance Startup 25 - - mA/V m t (4) Startup time V is stabilized - 2 - ms SU(HSE) DD 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz SU(HSE) oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C and C , it is recommended to use high-quality external ceramic capacitors in the L1 L2 5pF to 25pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure18). C and C are usually the L1 L2 same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C . PCB and MCU pin capacitance must be included (10pF L1 L2 can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . Refer to the application note AN2867 “Oscillator design guide for ST L1 L2 microcontrollers” available from the ST website www.st.com. 41/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN fHSE Bias 8 MHz resonator RF controlled gain CL2 REXT(1) OSC_OUT STM32F102xx ai14977b 1. R value depends on the crystal characteristics. EXT Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. LSE oscillator characteristics (f = 32.768 kHz) LSE Symbol Parameter Conditions Min Typ Max Unit R Feedback resistor - - 5 - MΩ F Recommended load capacitance C(1) versus equivalent serial R = 30 kΩ - - 15 pF S resistance of the crystal (R ) S V = 3.3 V I LSE driving current DD - - 1.4 µA 2 V = V IN SS g Oscillator transconductance - 5 - - µA/V m T = 50°C - 1.5 - A T = 25°C - 2.5 - A T = 10°C - 4.0 - A T = 0°C - 6.0 - t (2) Startup time V is stabilized A s SU(LSE) DD T = -10°C - 10.0 - A T = -20°C - 17.0 - A T = -30°C - 32.0 - A T = -40°C - 60.0 - A 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. t is the startup time measured from the moment it is enabled by software to a stabilized 32.768kHz oscillation is SU(LSE) reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer, PCB layout and humidity. DocID15057 Rev 5 42/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15pF range selected to match the requirements of the crystal or resonator. CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C stray where C is the pin capacitance and board or trace PCB-related capacitance. Typically, it stray is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Bias 32.768 KHz resonator RF controlled gain OSC32_OUT STM32F102xx CL2 ai14978b 5.3.7 Internal clock source characteristics The parameters given in Table23 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD High-speed internal (HSI) RC oscillator Table 23. HSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit f Frequency - - 8 - MHz HSI DuCy Duty cycle - 45 - 55 % (HSI) User-trimmed with the RCC_CR - - 1(3) % register(2) T = –40 to 105°C –2.0 - 2.5 % Accuracy of the HSI A ACC HSI oscillator Factory- TA = –10 to 85°C –1.5 - 2.2 % calibrated(4)(5) T = 0 to 70°C –1.3 - 2 % A T = 25°C –1.1 - 1.8 % A HSI oscillator t (4) - 1 - 2 µs su(HSI) startup time HSI oscillator power I (4) - - 80 100 µA DD(HSI) consumption 1. V = 3.3V, T = –40 to 105°C unless otherwise specified. DD A 43/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. 5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified range. Low-speed internal (LSI) RC oscillator Table 24. LSI oscillator characteristics (1) Symbol Parameter Min(2) Typ Max Unit f Frequency 30 40 60 kHz LSI t (3) LSI oscillator startup time - - 85 µs su(LSI) I (3) LSI oscillator power consumption - 0.65 1.2 µA DD(LSI) 1. V = 3 V, T = −40 to 85 °C unless otherwise specified. DD A 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and V supply DD voltage conditions summarized in Table8. Table 25. Low-power mode wakeup timings Symbol Parameter Typ Unit t (1) Wakeup from Sleep mode 1.8 µs WUSLEEP Wakeup from Stop mode (regulator in run mode) 3.6 tWUSTOP(1) Wakeup from Stop mode (regulator in low-power µs 5.4 mode) t (1) Wakeup from Standby mode 50 µs WUSTDBY 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table26 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table8. DD DocID15057 Rev 5 44/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 26. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz f PLL_IN PLL input clock duty cycle 40 - 60 % f PLL multiplier output clock 16 - 48 MHz PLL_OUT t PLL lock time - - 200 µs LOCK Jitter Cycle-to-cycle jitter - - 300 ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f . PLL_OUT 5.3.9 Memory characteristics Flash memory The characteristics are given at T = –40 to 85 °C unless otherwise specified. A Table 27. Flash memory characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit t 16-bit programming time T = –40 to +85 °C 40 52.5 70 µs prog A t Page (1 KB) erase time T = –40 to +85 °C 20 - 40 ms ERASE A t Mass erase time T = –40 to +85 °C 20 - 40 ms ME A Read mode f = 48 MHz with 2 - - 20 mA HCLK wait states, V = 3.3 V DD Write / Erase modes I Supply current DD f = 48 MHz, V = - - 5 mA HCLK DD 3.3 V Power-down mode / Halt, - - 50 µA V = 3.0 to 3.6 V DD V Programming voltage - 2 - 3.6 V prog 1. Guaranteed by design, not tested in production. Table 28. Flash memory endurance and data retention Value Symbol Parameter Conditions Unit Min(1) Typ Max N Endurance 10 - - kcycles END t Data retention T = 85 °C, 1000 cycles 30 - - Years RET A 1. Based on characterization not tested in production. 45/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and DD V through a 100 pF capacitor, until a functional disturbance occurs. This test is SS compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table29. They are based on the EMS levels and classes defined in application note AN1709. Table 29. EMS characteristics Symbol Parameter Conditions Level/Class V = 3.3 V, T = +25 °C, Voltage limits to be applied on any I/O pin to DD A V f = 48 MHz 2B FESD induce a functional disturbance HCLK conforms to IEC 61000-4-2 Fast transient voltage burst limits to be V = 3.3 V, T = +25 °C, DD A V applied through 100 pF on V and V pins f = 48 MHz 4A EFTB DD SS HCLK to induce a functional disturbance conforms to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations: the software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers, etc.) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). DocID15057 Rev 5 46/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports), This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 30. EMI characteristics Max vs. [f /f ] Monitored HSE HCLK Symbol Parameter Conditions Unit frequency band 8/48 MHz 0.1 MHz to 30 MHz 7 30 MHz to 130 MHz 8 dBµV S Peak level V = 3.3 V, T = 25°C. EMI DD A 130 MHz to 1GHz 13 SAE EMI Level 3.5 - 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) Electrostatic discharge voltage T = +25 °C, conforming V A 2 2000 ESD(HBM) (human body model) to JESD22-A114 V Electrostatic discharge voltage T = +25 °C, conforming V A II 500 ESD(CDM) (charge device model) to ANSI/ESD STM5.3.1 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 32. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +105 °C conforming to JESD78A II level A A 47/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5.3.12 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table33. Table 33. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on OSC_IN32, -0 +0 OSC_OUT32, PA4, PA5, PC13 I mA INJ Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 5.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table34 are derived from tests performed under the conditions summarized in Table8. All I/Os are CMOS and TTL compliant. DocID15057 Rev 5 48/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 34. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit Standard IO input low level - - 0.28*(V -2 V)+0.8 V(1) DD voltage V Low level input voltage IO FT(3) input IL - - 0.32*(V -2V)+0.75 V(1) low level voltage DD All I/Os except - - 0.35V (2) BOOT0 DD Standard IO V input high level 0.41*(V -2 V)+1.3 V(1) - - DD voltage High level input IO FT(3) input V IH voltage high level 0.42*(V -2 V)+1 V(1) - - DD voltage All I/Os except 0.65V (2) - - BOOT0 DD Standard IO Schmitt trigger voltage - 200 - - V hysteresis(4) mV hys IO FT Schmitt trigger - 5% V (5) - - voltage hysteresis(4) DD V ≤ V ≤ V SS IN DD - - ±1 Input leakage current Standard I/Os I µA lkg (6) VIN = 5 V - - 3 I/O FT Weak pull-up R V = V 30 40 50 PU equivalent resistor(7) IN SS kΩ Weak pull-down R V = V 30 40 50 PD equivalent resistor(7) IN DD C I/O pin capacitance - - 5 - pF IO 1. Data based on design simulation. 2. Tested in production. 3. FT = Five-volt tolerant, In order to sustain a voltage higher than V +0.3 the internal pull-up/pull-down resistors must be DD disabled. 4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 5. With a minimum of 100 mV. 6. Leakage could be higher than max, if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). 49/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required), Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure20 and Figure21 for standard I/Os, and in Figure22 and Figure23 for 5V tolerant I/Os. Figure 20. Standard I/O input characteristics - CMOS port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:33)(cid:82)(cid:69)(cid:65)(cid:0)(cid:78)(cid:79)(cid:84)(cid:0) (cid:68)(cid:69)(cid:84)(cid:69)(cid:82)(cid:77)(cid:73)(cid:78)(cid:69)(cid:68) (cid:0) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:22)(cid:21)(cid:54)(cid:36)(cid:18)(cid:15)(cid:36)(cid:26)(cid:23) (cid:54)(cid:34)(cid:65)(cid:41)(cid:40)(cid:83)(cid:29)(cid:69)(cid:16)(cid:68)(cid:14)(cid:0)(cid:20)(cid:79)(cid:17)(cid:78)(cid:8)(cid:0)(cid:54)(cid:68)(cid:69)(cid:36)(cid:83)(cid:36)(cid:73)(cid:71)(cid:13)(cid:78)(cid:18)(cid:0)(cid:9)(cid:83)(cid:11)(cid:73)(cid:17)(cid:77)(cid:14)(cid:19)(cid:85)(cid:76)(cid:65)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:55)(cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:17)(cid:14)(cid:19) (cid:52)(cid:69)(cid:83)(cid:84)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:0)(cid:80)(cid:82)(cid:79)(cid:68)(cid:85)(cid:67)(cid:84)(cid:73)(cid:79)(cid:78) (cid:18)(cid:18)(cid:15)(cid:22)(cid:26) (cid:18)(cid:18)(cid:15)(cid:15)(cid:24)(cid:17)(cid:18)(cid:25) (cid:18)(cid:18)(cid:15)(cid:15)(cid:24)(cid:17)(cid:18)(cid:25) (cid:18)(cid:15)(cid:19)(cid:22) (cid:54)(cid:34)(cid:41)(cid:65)(cid:44)(cid:29)(cid:83)(cid:69)(cid:16)(cid:68)(cid:14)(cid:18)(cid:0)(cid:79)(cid:24)(cid:78)(cid:8)(cid:54)(cid:0)(cid:68)(cid:36)(cid:69)(cid:36)(cid:83)(cid:73)(cid:13)(cid:71)(cid:18)(cid:78)(cid:9)(cid:11)(cid:0)(cid:83)(cid:16)(cid:73)(cid:77)(cid:14)(cid:24)(cid:85)(cid:76)(cid:65)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:55)(cid:41)(cid:44)(cid:77)(cid:65)(cid:88)(cid:16)(cid:14)(cid:24) (cid:35)(cid:45)(cid:47)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:21)(cid:54)(cid:36)(cid:36) (cid:16)(cid:14)(cid:23) (cid:52)(cid:69)(cid:83)(cid:84)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:0)(cid:80)(cid:82)(cid:79)(cid:68)(cid:85)(cid:67)(cid:84)(cid:73)(cid:79)(cid:78) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:23) (cid:19) (cid:19)(cid:14)(cid:19) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:23)(cid:67) Figure 21. Standard I/O input characteristics - TTL port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:33)(cid:82)(cid:69)(cid:65)(cid:0)(cid:78)(cid:79)(cid:84)(cid:0) (cid:68)(cid:69)(cid:84)(cid:69)(cid:82)(cid:77)(cid:73)(cid:78)(cid:69)(cid:68) (cid:55)(cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:18)(cid:14)(cid:16) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0) (cid:54)(cid:41)(cid:40)(cid:29)(cid:18)(cid:54) (cid:17)(cid:14)(cid:25)(cid:22) (cid:34)(cid:54)(cid:65)(cid:41)(cid:83)(cid:40)(cid:69)(cid:29)(cid:68)(cid:16)(cid:0)(cid:14)(cid:79)(cid:20)(cid:78)(cid:17)(cid:0)(cid:8)(cid:68)(cid:54)(cid:69)(cid:36)(cid:83)(cid:73)(cid:36)(cid:71)(cid:78)(cid:13)(cid:18)(cid:0)(cid:83)(cid:9)(cid:11)(cid:73)(cid:77)(cid:17)(cid:85)(cid:14)(cid:19)(cid:76)(cid:65)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:17)(cid:14)(cid:19) (cid:17)(cid:14)(cid:18)(cid:21) (cid:34)(cid:54)(cid:65)(cid:41)(cid:44)(cid:83)(cid:29)(cid:69)(cid:16)(cid:68)(cid:14)(cid:0)(cid:18)(cid:79)(cid:24)(cid:78)(cid:8)(cid:0)(cid:68)(cid:54)(cid:69)(cid:36)(cid:83)(cid:36)(cid:73)(cid:71)(cid:13)(cid:78)(cid:18)(cid:0)(cid:9)(cid:83)(cid:11)(cid:73)(cid:77)(cid:16)(cid:14)(cid:85)(cid:24)(cid:76)(cid:65)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:55) (cid:41)(cid:44)(cid:77)(cid:65)(cid:88) (cid:16)(cid:14)(cid:24) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0) (cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:24)(cid:54) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:17)(cid:22) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:24)(cid:66) DocID15057 Rev 5 50/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 22. 5V tolerant I/O input characteristics - CMOS port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:33)(cid:82)(cid:69)(cid:65)(cid:0)(cid:78)(cid:79)(cid:84)(cid:0) (cid:68)(cid:69)(cid:84)(cid:69)(cid:82)(cid:77)(cid:73)(cid:78)(cid:69)(cid:68) (cid:17)(cid:14)(cid:19) (cid:52)(cid:69)(cid:83)(cid:84)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:0)(cid:80)(cid:0)(cid:82)(cid:79)(cid:68)(cid:85)(cid:67)(cid:84)(cid:73)(cid:79)(cid:78) (cid:35)(cid:45)(cid:47)(cid:17)(cid:51)(cid:14)(cid:20)(cid:0)(cid:18)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:17)(cid:17)(cid:69)(cid:14)(cid:14)(cid:17)(cid:21)(cid:78)(cid:22)(cid:21)(cid:84)(cid:83)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:16)(cid:14)(cid:22)(cid:21)(cid:54)(cid:36)(cid:17)(cid:14)(cid:36)(cid:22)(cid:17)(cid:23) (cid:34)(cid:54)(cid:34)(cid:54)(cid:65)(cid:41)(cid:65)(cid:41)(cid:40)(cid:44)(cid:83)(cid:83)(cid:69)(cid:29)(cid:29)(cid:69)(cid:68)(cid:16)(cid:16)(cid:68)(cid:0)(cid:14)(cid:14)(cid:0)(cid:79)(cid:19)(cid:20)(cid:79)(cid:78)(cid:18)(cid:18)(cid:78)(cid:0)(cid:8)(cid:8)(cid:0)(cid:68)(cid:54)(cid:54)(cid:68)(cid:69)(cid:69)(cid:36)(cid:36)(cid:83)(cid:83)(cid:36)(cid:36)(cid:73)(cid:73)(cid:71)(cid:71)(cid:13)(cid:13)(cid:78)(cid:18)(cid:78)(cid:18)(cid:0)(cid:9)(cid:0)(cid:9)(cid:83)(cid:83)(cid:11)(cid:11)(cid:73)(cid:73)(cid:77)(cid:16)(cid:17)(cid:77)(cid:14)(cid:85)(cid:23)(cid:85)(cid:76)(cid:21)(cid:76)(cid:65)(cid:65)(cid:84)(cid:84)(cid:73)(cid:73)(cid:79)(cid:79)(cid:78)(cid:78)(cid:83)(cid:83) (cid:17) (cid:17)(cid:16)(cid:14)(cid:14)(cid:18)(cid:25)(cid:25)(cid:23)(cid:21)(cid:21) (cid:35)(cid:45)(cid:17)(cid:14)(cid:47)(cid:16)(cid:23)(cid:51)(cid:0)(cid:83)(cid:84)(cid:65)(cid:78)(cid:68)(cid:65)(cid:82)(cid:68)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:19)(cid:21)(cid:54)(cid:36)(cid:36) (cid:16)(cid:14)(cid:23)(cid:21) (cid:16)(cid:14)(cid:23) (cid:52)(cid:69)(cid:83)(cid:84)(cid:69)(cid:68)(cid:0)(cid:73)(cid:78)(cid:0)(cid:80)(cid:82)(cid:79)(cid:68)(cid:85)(cid:67)(cid:84)(cid:73)(cid:79)(cid:78) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:23) (cid:19) (cid:19)(cid:14)(cid:19) (cid:19)(cid:14)(cid:22) (cid:54)(cid:36)(cid:36) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:23)(cid:25)(cid:67) Figure 23. 5V tolerant I/O input characteristics - TTL port (cid:54)(cid:41)(cid:40)(cid:15)(cid:54)(cid:41)(cid:44)(cid:0)(cid:8)(cid:54)(cid:9) (cid:33)(cid:82)(cid:69)(cid:65)(cid:0)(cid:78)(cid:79)(cid:84)(cid:0) (cid:68)(cid:69)(cid:84)(cid:69)(cid:82)(cid:77)(cid:73)(cid:78)(cid:69)(cid:68) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:0)(cid:0)(cid:54)(cid:41)(cid:40)(cid:29)(cid:18)(cid:54) (cid:18)(cid:14)(cid:16) (cid:17)(cid:14)(cid:22)(cid:23) (cid:34)(cid:54)(cid:65)(cid:41)(cid:40)(cid:83)(cid:29)(cid:69)(cid:16)(cid:68)(cid:14)(cid:0)(cid:20)(cid:79)(cid:18)(cid:78)(cid:10)(cid:0)(cid:68)(cid:8)(cid:54)(cid:69)(cid:83)(cid:36)(cid:73)(cid:71)(cid:36)(cid:78)(cid:13)(cid:18)(cid:0)(cid:83)(cid:9)(cid:73)(cid:11)(cid:77)(cid:17)(cid:85)(cid:76)(cid:65)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:55)(cid:41)(cid:40)(cid:77)(cid:73)(cid:78) (cid:17) (cid:34)(cid:54)(cid:65)(cid:41)(cid:83)(cid:44)(cid:69)(cid:29)(cid:68)(cid:16)(cid:0)(cid:14)(cid:79)(cid:19)(cid:78)(cid:18)(cid:0)(cid:10)(cid:68)(cid:8)(cid:54)(cid:69)(cid:83)(cid:36)(cid:73)(cid:71)(cid:36)(cid:78)(cid:13)(cid:0)(cid:18)(cid:83)(cid:9)(cid:73)(cid:11)(cid:77)(cid:16)(cid:85)(cid:14)(cid:23)(cid:76)(cid:65)(cid:21)(cid:84)(cid:73)(cid:79)(cid:78)(cid:83) (cid:55) (cid:41)(cid:44)(cid:77)(cid:65)(cid:88) (cid:16)(cid:14)(cid:24) (cid:16)(cid:14)(cid:23)(cid:21) (cid:52)(cid:52)(cid:44)(cid:0)(cid:82)(cid:69)(cid:81)(cid:85)(cid:73)(cid:82)(cid:69)(cid:77)(cid:69)(cid:78)(cid:84)(cid:83)(cid:0)(cid:54)(cid:41)(cid:44)(cid:29)(cid:16)(cid:14)(cid:24)(cid:54)(cid:0) (cid:54)(cid:36)(cid:36)(cid:0)(cid:8)(cid:54)(cid:9) (cid:18) (cid:18)(cid:14)(cid:17)(cid:22) (cid:19)(cid:14)(cid:22) (cid:65)(cid:73)(cid:17)(cid:23)(cid:18)(cid:24)(cid:16)(cid:66) Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ± 8mA, and sink or source up to ± 20mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can OL OH sink or source up to ±3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section5.2. • The sum of the currents sourced by all the I/Os on V plus the maximum Run DD, consumption of the MCU sourced on V cannot exceed the absolute maximum rating DD, I (see Table6). VDD • The sum of the currents sunk by all the I/Os on V plus the maximum Run SS consumption of the MCU sunk on V cannot exceed the absolute maximum rating SS I (see Table6). VSS 51/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table35 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table8. All I/Os are CMOS and TTL compliant. Table 35. Output voltage characteristics Symbol Parameter Conditions Min Max Unit Output Low level voltage for an I/O pin VOL(1) when 8 pins are sunk at the same time CMOS port(2). - 0.4 I = +8mA. V IO VOH(3) Owhuetpnu 8t Hpiignhs alervee sl ovuorlctaegde a fto trh aen s aI/mO ep itnim e 2.7V < VDD < 3.6V VDD–0.4 - Output low level voltage for an I/O pin VOL(1) when 8 pins are sunk at the same time TTL port(2) - 0.4 I = +8 mA V IO Output high level voltage for an I/O pin VOH(3) when 8 pins are sourced at the same time 2.7V < VDD < 3.6V 2.4 - Output low level voltage for an I/O pin V (1) - 1.3 OL when 8 pins are sunk at the same time I = +20 mA(4) IO V V (3) Output high level voltage for an I/O pin 2.7V < VDD < 3.6V V –1.3 - OH when 8 pins are sourced at the same time DD Output low level voltage for an I/O pin V (1) - 0.4 OL when 8 pins are sunk at the same time I = +6 mA(4) IO V V (3) Output high level voltage for an I/O pin 2.0V < VDD < 2.7 V V –0.4 - OH when 8 pins are sourced at the same time DD 1. The I current sunk by the device must always respect the absolute maximum rating specified in Table6 IO and the sum of I (I/O ports and control pins) must not exceed I . IO VSS 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The I current sourced by the device must always respect the absolute maximum rating specified in IO Table6 and the sum of I (I/O ports and control pins) must not exceed I . IO VDD 4. Based on characterization data, not tested in production. DocID15057 Rev 5 52/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure24 and Table36, respectively. Unless otherwise specified, the parameters given in Table36 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table8. Table 36. I/O AC characteristics(1) MODEx [1:0] bit Symbol Parameter Conditions Max Unit value(1) f Maximum frequency(2) C = 50pF, V = 2 V to 3.6 V 2 MHz max(IO)out L DD Output high to low level fall t 125(3) 10 f(IO)out time C = 50pF, V = 2 V to 3.6 V ns L DD Output low to high level rise t 125(3) r(IO)out time f Maximum frequency(2) C = 50pF, V = 2 V to 3.6 V 10 MHz max(IO)out L DD Output high to low level fall t 25(3) 01 f(IO)out time C = 50pF, V = 2 V to 3.6 V ns L DD Output low to high level rise t 25(3) r(IO)out time C = 30 pF, V = 2.7 V to 3.6 V 50 MHz L DD F Maximum Frequency(2) C = 50 pF, V = 2.7 V to 3.6 V 30 MHz max(IO)out L DD C = 50 pF, V = 2 V to 2.7 V 20 MHz L DD C = 30pF, V = 2.7 V to 3.6 V 5(3) L DD Output high to low level fall 11 t C = 50pF, V = 2.7 V to 3.6 V 8(3) f(IO)out time L DD C = 50pF, V = 2 V to 2.7 V 12(3) L DD ns C = 30pF, V = 2.7 V to 3.6 V 5(3) L DD Output low to high level rise t C = 50pF, V = 2.7 V to 3.6 V 8(3) r(IO)out time L DD C = 50pF, V = 2 V to 2.7 V 12(3) L DD Pulse width of external - t signals detected by the EXTI - 10 ns EXTIpw controller 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure24. 3. Guaranteed by design, not tested in production. 53/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 24. I/O AC characteristics definition (cid:25)(cid:16)(cid:5) (cid:17)(cid:16)(cid:5) (cid:21)(cid:16)(cid:5) (cid:21)(cid:16)(cid:5) (cid:17)(cid:16)(cid:5) (cid:25)(cid:16)(cid:5) (cid:37)(cid:56)(cid:52)(cid:37)(cid:50)(cid:46)(cid:33)(cid:44) (cid:84)(cid:82)(cid:8)(cid:41)(cid:47)(cid:9)(cid:79)(cid:85)(cid:84) (cid:84)(cid:70)(cid:8)(cid:41)(cid:47)(cid:9)(cid:79)(cid:85)(cid:84) (cid:47)(cid:53)(cid:52)(cid:48)(cid:53)(cid:52) (cid:47)(cid:46)(cid:0)(cid:21)(cid:16)(cid:80)(cid:38) (cid:52) (cid:45)(cid:65)(cid:88)(cid:73)(cid:77)(cid:85)(cid:77)(cid:0)(cid:70)(cid:82)(cid:69)(cid:81)(cid:85)(cid:69)(cid:78)(cid:67)(cid:89)(cid:0)(cid:73)(cid:83)(cid:0)(cid:65)(cid:67)(cid:72)(cid:73)(cid:69)(cid:86)(cid:69)(cid:68)(cid:0)(cid:73)(cid:70)(cid:0)(cid:8)(cid:84) (cid:11)(cid:0)(cid:84)(cid:9)(cid:0)(cid:148)(cid:0)(cid:18)(cid:15)(cid:19)(cid:9)(cid:52)(cid:0)(cid:65)(cid:78)(cid:68)(cid:0)(cid:73)(cid:70)(cid:0)(cid:84)(cid:72)(cid:69)(cid:0)(cid:68)(cid:85)(cid:84)(cid:89)(cid:0)(cid:67)(cid:89)(cid:67)(cid:76)(cid:69)(cid:0)(cid:73)(cid:83)(cid:0)(cid:8)(cid:20)(cid:21)(cid:13)(cid:21)(cid:21)(cid:5)(cid:9)(cid:0) (cid:82)(cid:0) (cid:70) (cid:87)(cid:72)(cid:69)(cid:78)(cid:0)(cid:76)(cid:79)(cid:65)(cid:68)(cid:69)(cid:68)(cid:0)(cid:66)(cid:89)(cid:0)(cid:21)(cid:16)(cid:80)(cid:38) (cid:0) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:19)(cid:17)(cid:67) 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R (see Table34). PU Unless otherwise specified, the parameters given in Table37 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in DD Table8. Table 37. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit V (1) NRST Input low level voltage - –0.5 - 0.8 IL(NRST) V V (1) NRST Input high level voltage - 2 - V +0.5 IH(NRST) DD NRST Schmitt trigger voltage V - - 200 - mV hys(NRST) hysteresis R Weak pull-up equivalent resistor(2) V = V 30 40 50 kΩ PU IN SS V (1) NRST Input filtered pulse - - - 100 ns F(NRST) V (1) NRST Input not filtered pulse - 300 - - ns NF(NRST) 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). DocID15057 Rev 5 54/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 25. Recommended NRST pin protection (cid:57)(cid:39)(cid:39) (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:11)(cid:20)(cid:12) (cid:49)(cid:53)(cid:54)(cid:55)(cid:11)(cid:21)(cid:12) (cid:53)(cid:51)(cid:56) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:53)(cid:72)(cid:86)(cid:72)(cid:87) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:20)(cid:3)(cid:151)(cid:41) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:21)(cid:70) 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table39. Otherwise the reset will not be taken into account by the device. 55/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics 5.3.15 TIM timer characteristics The parameters given in Table38 are guaranteed by design. Refer to Section5.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38. TIMx(1) characteristics Symbol Parameter Conditions Min Max Unit - 1 - t TIMxCLK t Timer resolution time res(TIM) f = 48 MHz 20.84 - ns TIMxCLK Timer external clock - 0 fTIMxCLK/2 MHz f EXT frequency on CH1 to CH4 f = 48 MHz 0 24 MHz TIMxCLK Res Timer resolution - - 16 bit TIM 16-bit counter clock period - 1 65536 t TIMxCLK t when internal clock is COUNTER selected fTIMxCLK = 48 MHz 0.0208 1365 µs - - 65536 × 65536 t TIMxCLK t Maximum possible count MAX_COUNT f = 48 MHz - 89.48 s TIMxCLK 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 5.3.16 Communications interfaces I2C interface characteristics The STM32F102xx medium-density USB access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table39. Refer also to Section5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). DocID15057 Rev 5 56/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 39. I2C characteristics Standard mode I2C(1)(2) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max t SCL clock low time 4.7 - 1.3 - w(SCLL) µs t SCL clock high time 4.0 - 0.6 - w(SCLH) t SDA setup time 250 - 100 - su(SDA) t SDA data hold time - 3450(3) - 900(3) h(SDA) tr(SDA) SDA and SCL rise time - 1000 - 300 ns t r(SCL) t f(SDA) SDA and SCL fall time - 300 - 300 t f(SCL) t Start condition hold time 4.0 - 0.6 - h(STA) Repeated Start condition setup µs t 4.7 - 0.6 - su(STA) time t Stop condition setup time 4.0 - 0.6 - µs su(STO) Stop to Start condition time (bus t 4.7 - 1.3 - µs w(STO:STA) free) Pulse width of spikes that are t 0 50(4) 0 50(4) ns SP suppressed by the analog filter C Capacitive load for each bus line - 400 - 400 pF b 1. Values guaranteed by design, not tested in production. 2. f must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4MHz to aPcChLiKe1ve fast mode I2C frequencies. It must be a multiple of 10MHz to reach the 400kHz maximum I2C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. 4. The analog filter minimum filtered spikes is above t to ensure that spikes width up to t are SP(max) SP(max) filtered. 57/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 26. I2C bus AC waveforms and measurement circuit(1) (cid:54)(cid:36)(cid:36)(cid:63)(cid:41)(cid:18)(cid:35) (cid:54)(cid:36)(cid:36)(cid:63)(cid:41)(cid:18)(cid:35) (cid:53)(cid:83) (cid:53)(cid:83) (cid:51)(cid:52)(cid:45)(cid:19)(cid:18)(cid:38)(cid:17)(cid:16)(cid:88) (cid:53)(cid:86) (cid:51)(cid:36)(cid:33) (cid:41)(cid:163)(cid:35)(cid:0)(cid:66)(cid:85)(cid:83) (cid:53)(cid:86) (cid:51)(cid:35)(cid:44) (cid:51)(cid:84)(cid:65)(cid:82)(cid:84)(cid:0)(cid:82)(cid:69)(cid:80)(cid:69)(cid:65)(cid:84)(cid:69)(cid:68) (cid:51)(cid:84)(cid:65)(cid:82)(cid:84) (cid:51)(cid:84)(cid:65)(cid:82)(cid:84) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:33)(cid:9) (cid:51)(cid:36)(cid:33) (cid:84)(cid:70)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:84)(cid:82)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:51)(cid:84)(cid:79)(cid:80) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:47)(cid:26)(cid:51)(cid:52)(cid:33)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:52)(cid:33)(cid:9) (cid:84)(cid:87)(cid:8)(cid:51)(cid:35)(cid:44)(cid:44)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:51)(cid:35)(cid:44) (cid:84)(cid:87)(cid:8)(cid:51)(cid:35)(cid:44)(cid:40)(cid:9) (cid:84)(cid:82)(cid:8)(cid:51)(cid:35)(cid:44)(cid:9) (cid:84)(cid:70)(cid:8)(cid:51)(cid:35)(cid:44)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:47)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:19)(cid:19)(cid:69) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. Table 40. SCL frequency (f = 36 MHz, V = 3.3 V)(1)(2) PCLK1 DD_I2C I2C_CCR value f SCL (kHz) R = 4.7 kΩ P 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. R = External pull-up resistance, f = I2C speed. P SCL 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. DocID15057 Rev 5 58/78 66

Electrical characteristics STM32F102x4, STM32F102x6 SPI interface characteristics Unless otherwise specified, the parameters given in Table41 are derived from tests performed under ambient temperature, f frequency and V supply voltage conditions PCLKx DD summarized in Table8. Refer to Section5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode - 18 SCK SPI clock frequency MHz 1/tc(SCK) Slave mode - 18 t SPI clock rise and fall r(SCK) Capacitive load: C = 30 pF - 8 ns t time f(SCK) SPI slave input clock DuCy(SCK) Slave mode 30 70 % duty cycle t (1) NSS setup time Slave mode 4t - su(NSS) PCLK t (1) NSS hold time Slave mode 2t - h(NSS) PCLK t (1) Master mode, f = 36 MHz, w(SCKH) SCK high and low time PCLK 50 60 t (1) presc = 4 w(SCKL) t (1) Master mode 5 - su(MI) Data input setup time tsu(SI)(1) Slave mode 5 - t (1) Master mode 5 - h(MI) Data input hold time t (1) Slave mode 4 - h(SI) ns t (1)(2) Data output access time Slave mode, f = 20 MHz 0 3t a(SO) PCLK PCLK t (1)(3) Data output disable time Slave mode 2 10 dis(SO) t (1) Data output valid time Slave mode (after enable edge) - 25 v(SO) Master mode (after enable t (1) Data output valid time - 5 v(MO) edge) t (1) Slave mode (after enable edge) 15 - h(SO) Data output hold time Master mode (after enable t (1) 2 - h(MO) edge) 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 59/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Figure 27. SPI timing diagram - slave mode and CPHA=0 (cid:69)(cid:94)(cid:94)(cid:3)(cid:349)(cid:374)(cid:393)(cid:437)(cid:410) (cid:410)(cid:272)(cid:894)(cid:94)(cid:18)(cid:60)(cid:895) (cid:410)(cid:94)(cid:104)(cid:894)(cid:69)(cid:94)(cid:94)(cid:895) (cid:410)(cid:346)(cid:894)(cid:69)(cid:94)(cid:94)(cid:895) (cid:18)(cid:87)(cid:44)(cid:4)(cid:1089)(cid:1004) (cid:410) (cid:393)(cid:437) (cid:18)(cid:87)(cid:75)(cid:62)(cid:1089)(cid:1004) (cid:374) (cid:410)(cid:449)(cid:894)(cid:94)(cid:18)(cid:60)(cid:44)(cid:895) (cid:60)(cid:3)(cid:47) (cid:18)(cid:87)(cid:44)(cid:4)(cid:1089)(cid:1004) (cid:410)(cid:449)(cid:894)(cid:94)(cid:18)(cid:60)(cid:62)(cid:895) (cid:18) (cid:18)(cid:87)(cid:75)(cid:62)(cid:1089)(cid:1005) (cid:94) (cid:410)(cid:258)(cid:894)(cid:94)(cid:75)(cid:895) (cid:410)(cid:448)(cid:894)(cid:94)(cid:75)(cid:895) (cid:410)(cid:346)(cid:894)(cid:94)(cid:75)(cid:895) (cid:410)(cid:396)(cid:894)(cid:94)(cid:18)(cid:60)(cid:895) (cid:410)(cid:282)(cid:349)(cid:400)(cid:894)(cid:94)(cid:75)(cid:895) (cid:410)(cid:296)(cid:894)(cid:94)(cid:18)(cid:60)(cid:895) (cid:68)(cid:47)(cid:94)(cid:75) (cid:68)(cid:94)(cid:17)(cid:75)(cid:104)(cid:100) (cid:17)(cid:47)(cid:100)(cid:1010) (cid:75)(cid:104)(cid:100) (cid:62)(cid:94)(cid:17) (cid:75)(cid:104)(cid:100) (cid:75)(cid:104)(cid:100)(cid:87)(cid:104)(cid:100) (cid:410)(cid:400)(cid:437)(cid:894)(cid:94)(cid:47)(cid:895) (cid:68)(cid:75)(cid:94)(cid:47) (cid:68)(cid:94)(cid:17) (cid:47)(cid:69) (cid:17)(cid:47)(cid:100)(cid:1005) (cid:47)(cid:69) (cid:62)(cid:94)(cid:17) (cid:47)(cid:69) (cid:47)(cid:69)(cid:87)(cid:104)(cid:100) (cid:410)(cid:346)(cid:894)(cid:94)(cid:47)(cid:895) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:23)(cid:70) Figure 28. SPI timing diagram - slave mode and CPHA=1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:54)(cid:38)(cid:46)(cid:3)(cid:44)(cid:81) (cid:38)(cid:38)(cid:51)(cid:51)(cid:50)(cid:43)(cid:47)(cid:36)(cid:32)(cid:32)(cid:20)(cid:20) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25) (cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37) (cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37) (cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20) (cid:44)(cid:49) (cid:47)(cid:54)(cid:37) (cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. DocID15057 Rev 5 60/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 29. SPI timing diagram - master mode(1) (cid:40)(cid:73)(cid:71)(cid:72) (cid:46)(cid:51)(cid:51)(cid:0)(cid:73)(cid:78)(cid:80)(cid:85)(cid:84) (cid:84)(cid:67)(cid:8)(cid:51)(cid:35)(cid:43)(cid:9) (cid:80)(cid:85)(cid:84) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:16) (cid:85)(cid:84) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:16) (cid:47) (cid:43)(cid:0) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:16) (cid:51)(cid:35) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:17) (cid:80)(cid:85)(cid:84) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:17) (cid:85)(cid:84) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:16) (cid:47) (cid:43)(cid:0) (cid:35)(cid:48)(cid:40)(cid:33)(cid:29)(cid:17) (cid:51)(cid:35) (cid:35)(cid:48)(cid:47)(cid:44)(cid:29)(cid:17) (cid:84)(cid:83)(cid:85)(cid:8)(cid:45)(cid:41)(cid:9) (cid:84)(cid:84)(cid:87)(cid:87)(cid:8)(cid:8)(cid:51)(cid:51)(cid:35)(cid:35)(cid:43)(cid:43)(cid:40)(cid:44)(cid:9)(cid:9) (cid:84)(cid:84)(cid:82)(cid:70)(cid:8)(cid:8)(cid:51)(cid:51)(cid:35)(cid:35)(cid:43)(cid:43)(cid:9)(cid:9) (cid:45)(cid:41)(cid:51)(cid:47) (cid:45)(cid:51)(cid:34)(cid:41)(cid:46) (cid:34)(cid:41)(cid:52)(cid:22)(cid:0)(cid:41)(cid:46) (cid:44)(cid:51)(cid:34)(cid:0)(cid:41)(cid:46) (cid:41)(cid:46)(cid:48)(cid:53)(cid:52) (cid:84)(cid:72)(cid:8)(cid:45)(cid:41)(cid:9) (cid:45)(cid:47)(cid:51)(cid:41) (cid:45)(cid:51)(cid:34)(cid:0)(cid:47)(cid:53)(cid:52) (cid:34)(cid:41)(cid:52)(cid:17)(cid:0)(cid:47)(cid:53)(cid:52) (cid:44)(cid:51)(cid:34)(cid:0)(cid:47)(cid:53)(cid:52) (cid:47)(cid:53)(cid:52)(cid:48)(cid:53)(cid:52) (cid:84)(cid:86)(cid:8)(cid:45)(cid:47)(cid:9) (cid:84)(cid:72)(cid:8)(cid:45)(cid:47)(cid:9) (cid:65)(cid:73)(cid:17)(cid:20)(cid:17)(cid:19)(cid:22)(cid:54)(cid:18) 1. Measurement points are done at CMOS levels: 0.3V and 0.7V DD DD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time Symbol Parameter Max Unit t USB transceiver startup time 1 µs STARTUP 61/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Table 43. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit V USB operating voltage(2) - 3.0(3) 3.6 V DD Input VDI(4) Differential input sensitivity I(USB_DP, USB_DM) 0.2 - levels V (4) Differential common mode range Includes V range 0.8 2.5 V CM DI V (4) Single ended receiver threshold - 1.3 2.0 SE Output VOL Static output level low RL of 1.5kΩ to 3.6 V(5) - 0.3 V levels V Static output level high R of 15kΩ to V (5) 2.8 3.6 OH L SS 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V voltage range. DD 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 30. USB timings: definition of data signal rise and fall time Crossover points Differential Data Lines VCRS VSS tf tr ai14137 Table 44. USB: Full speed electrical characteristics of the driver(1) Symbol Parameter Conditions Min Max Unit t Rise time(2) C = 50 pF 4 20 ns r L t Fall time(2) C = 50 pF 4 20 ns f L t Rise/ fall time matching t / t 90 110 % rfm r f V Output signal crossover voltage - 1.3 2.0 V CRS 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table45 are derived from tests performed under ambient temperature, f frequency and V supply voltage PCLK2 DDA conditions summarized in Table8. Note: It is recommended to perform a calibration after each power-up. DocID15057 Rev 5 62/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V Power supply - 2.4 - 3.6 V DDA f ADC clock frequency - 0.6 - 12 MHz ADC f (1) Sampling rate - 0.05 - 0.85 Msps S f = 12 MHz - - 823 kHz f (1) External trigger frequency ADC TRIG - - - 17 1/f ADC 0 (V or SSA V Conversion voltage range(2) - V tied to - V V AIN REF- REF+ ground) See Equation 1 R (1) External input impedance and Table46 - - 50 κΩ AIN for details R (1) Sampling switch resistance - - - 1 κΩ ADC Internal sample and hold C (1) - - - 8 pF ADC capacitor f = 12 MHz 5.9 µs t (1) Calibration time ADC CAL - 83 1/f ADC t (1) Injection trigger conversion fADC = 12 MHz - - 0.214 µs lat latency - - - 3(3) 1/f ADC t (1) Regular trigger conversion fADC = 12 MHz - - 0.143 µs latr latency - - - 2(3) 1/f ADC f = 12 MHz 0.125 - 19.95 µs t (1) Sampling time ADC S - 1.5 - 239.5 1/f ADC t (1) Power-up time - 0 0 1 µs STAB f = 12 MHz 1.2 - 21 µs ADC Total conversion time tCONV(1) (including sampling time) - 14 to 252 (tS for sampling +12.5 1/f for successive approximation) ADC 1. Guaranteed by design, not tested in production. 2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 3. For external triggers, a delay of 1/f must be added to the latency specified in Table46. PCLK2 Equation 1: R max formula: AIN T R <---------------------------------S------------------------------–R AIN f × C × ln(2N+2) ADC ADC ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). 63/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics Table 46. R max for f = 12 MHz(1) AIN ADC T (cycles) t (µs) R max (kΩ) s S AIN 1.5 0.13 0.4 7.5 0.63 5.9 13.5 1.13 11.4 28.5 2.38 25.2 41.5 3.46 37.2 55.5 4.63 50 71.5 5.96 NA 239.5 19.96 NA 1. Data guaranteed by design, not tested in production. Table 47. ADC accuracy - limited test conditions(1) Symbol Parameter Test conditions Typ Max(2) Unit ET Total unadjusted error ±1.3 ±2 f = 48 MHz. PCLK2 EO Offset error fADC = 12 MHz, RAIN < 10 kΩ. ±1 ±1.5 V = 3 V to 3.6 V EG Gain error DDA ±0.5 ±1.5 LSB T = 25 °C A ED Differential linearity error Measurements made after ±0.7 ±1 ADC calibration EL Integral linearity error ±0.8 ±1.5 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 48. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions Typ Max(4) Unit ET Total unadjusted error ±2 ±5 f = 48 MHz. PCLK2 EO Offset error f = 12 MHz, R < 10 kΩ. ±1.5 ±2.5 ADC AIN EG Gain error V = 2.4 V to 3.6 V ±1.5 ±3 LSB DDA Measurements made after ED Differential linearity error ±1 ±2 ADC calibration EL Integral linearity error ±1.5 ±3 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted V , frequency and temperature ranges. DD 3. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for I and ΣI in Section5.3.13 does not INJ(PIN) INJ(PIN) affect the ADC accuracy. 4. Based on characterization, not tested in production. DocID15057 Rev 5 64/78 66

Electrical characteristics STM32F102x4, STM32F102x6 Figure 31. ADC accuracy characteristics V [1LSB = DDA IDEAL 4096 EG (1) Example of an actual transfer curve 4095 (2) The ideal transfer curve 4094 (3) End point correlation line 4093 (2) ET=Total unadjusted error: maximum deviation 7 ET (3) bEeOt=wOefefsne tth ee rarocrt:u dael avinadti othne b iedtewael etrna nthsefe frir csut ravcetsu.al (1) transition and the first ideal one. 6 EG=Gain error: deviation between the last ideal 5 transition and the last actual one. 4 EO EL EbeDt=wDeieffne raecnttuiaall lsinteepasri tayn edr rtohre: idmeaaxl imonuem. deviation 3 ED bEeLt=wIneteeng raanl yl inaecaturiatyl trearnrosri:tionm aanxdim tuhme ednedv iaptoioinnt 2 correlation line. 1 1LSBIDEAL 0 1 2 3 4 5 6 7 4093409440954096 VSSA VDDA ai15497 Figure 32. Typical connection diagram using the ADC VDD STM32F102 Sample and hold ADC VT converter 0.6 V RAIN(1) AINx RADC(1) 12-bit converter VAIN Cparasitic 0V.6T V IL±1 µA CADC(1) ai14974b 1. Refer to Table46 for the values of R , R and C . AIN ADC ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC 65/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure33. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 33. Power supply and reference decoupling STM32F102xx V DDA 1 µF // 10 nF V SSA ai14980b 5.3.18 Temperature sensor characteristics Table 49. TS characteristics Symbol Parameter Min Typ Max Unit T (1) V linearity with temperature - ±1.5 - °C L SENSE Avg_Slope(1) Average slope - 4.35 - mV/°C V (1) Voltage at 25°C - 1.42 - V 25 t (2) Startup time 4 - 10 µs START ADC sampling time when reading the T (3)(2) - - 17.1 µs S_temp temperature 1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. DocID15057 Rev 5 66/78 66

Package characteristics STM32F102x4, STM32F102x6 6 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LQFP64 package information Figure 34. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:70) (cid:36) (cid:70)(cid:70)(cid:70) (cid:38) (cid:20) (cid:39) (cid:36) (cid:46) (cid:39)(cid:20) (cid:47) (cid:39)(cid:22) (cid:47)(cid:20) (cid:23)(cid:27) (cid:22)(cid:22) (cid:22)(cid:21) (cid:23)(cid:28) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20) (cid:20)(cid:25) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:72) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:24)(cid:58)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. Table 50. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 67/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Package characteristics Table 50. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 35. LQFP64 - 64-pin, 10 x 10mm low-profile quad flat package recommended footprint (cid:20)(cid:24) (cid:19)(cid:19) (cid:16)(cid:14)(cid:19) (cid:20)(cid:25) (cid:16)(cid:14)(cid:21) (cid:19)(cid:18) (cid:17)(cid:18)(cid:14)(cid:23) (cid:17)(cid:16)(cid:14)(cid:19) (cid:17)(cid:16)(cid:14)(cid:19) (cid:22)(cid:20) (cid:17)(cid:23) (cid:17)(cid:14)(cid:18) (cid:17) (cid:17)(cid:22) (cid:23)(cid:14)(cid:24) (cid:17)(cid:18)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:25)(cid:67) 1. Dimensions are expressed in millimeters. DocID15057 Rev 5 68/78 75

Package characteristics STM32F102x4, STM32F102x6 Device marking for LQFP64 Figure36 is an example of topside marking orientation versus pin 1 identifier location. Figure 36. LQFP64 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:20)(cid:19)(cid:21) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3) (cid:70)(cid:82)(cid:71)(cid:72) (cid:53)(cid:25)(cid:55)(cid:25)(cid:36)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:53) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:11)(cid:92)(cid:72)(cid:68)(cid:85)(cid:3)(cid:14)(cid:3)(cid:90)(cid:72)(cid:72)(cid:78)(cid:12) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3) (cid:60)(cid:3)(cid:58)(cid:58) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:22)(cid:27)(cid:21)(cid:20)(cid:23)(cid:57)(cid:20) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 69/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Package characteristics 6.2 LQFP48 package information Figure 37. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33)(cid:33) (cid:17) (cid:33) (cid:67) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:43) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:20)(cid:24) (cid:17)(cid:19) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:17)(cid:18) (cid:69) (cid:21)(cid:34)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:18) 1. Drawing is not to scale. DocID15057 Rev 5 70/78 75

Package characteristics STM32F102x4, STM32F102x6 Table 51. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 71/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Package characteristics Figure 38. LQFP48 - 48-pin, 7 x 7mm low-profile quad flat package recommended footprint (cid:16)(cid:14)(cid:21)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:16)(cid:14)(cid:18)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:24) (cid:17)(cid:19) (cid:17) (cid:17)(cid:18) (cid:17)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:17)(cid:17)(cid:68) 1. Dimensions are expressed in millimeters. Device marking for LQFP48 Figure39 gives an example of topside marking orientation versus pin 1 identifier location. Figure 39. LQFP48 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3) (cid:70)(cid:82)(cid:71)(cid:72) (cid:20)(cid:19)(cid:21)(cid:38)(cid:23)(cid:55)(cid:25)(cid:36)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:53) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:11)(cid:92)(cid:72)(cid:68)(cid:85)(cid:3)(cid:14)(cid:3)(cid:90)(cid:72)(cid:72)(cid:78)(cid:12) (cid:36) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3) (cid:60)(cid:3)(cid:3)(cid:58)(cid:58)(cid:3)(cid:3) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:22)(cid:27)(cid:21)(cid:20)(cid:22)(cid:57)(cid:20) 1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. Only if ST has authorized in writing the customer qualification Engineering Samples can be used for reliability qualification trials. DocID15057 Rev 5 72/78 75

Package characteristics STM32F102x4, STM32F102x6 6.3 Thermal characteristics The maximum chip junction temperature (T max) must never exceed the values given in J Table8: General operating conditions. The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated J using the following equation: T max = T max + (P max × Θ ) J A D JA Where: • T max is the maximum ambient temperature in °C, A • Θ is the package junction-to-ambient thermal resistance, in °C/W, JA • P max is the sum of P max and P max (P max = P max + P max), D INT I/O D INT I/O • P max is the product of I andV , expressed in Watts. This is the maximum chip INT DD DD internal power. P max represents the maximum power dissipation on output pins where: I/O PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 52. Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction-ambient 55 LQFP48 - 7 × 7 mm / 0.5 mm pitch Θ °C/W JA Thermal resistance junction-ambient 45 LQFP64 - 10 × 10 mm / 0.5 mm pitch 6.4 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 73/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Package characteristics 6.4.1 Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table53: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F102xx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature T = 82 °C (measured according to JESD51-2), Amax I = 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output OL OL mode at low level with I = 20 mA, V = 1.3 V OL OL P 50 mA × 3.5 V= 175 mW INTmax = P × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW IOmax = 20 This gives: P = 175 mW and P = 272 mW INTmax IOmax P 175 272 = 447 mW Dmax = + Thus: P = 447 mW Dmax Using the values obtained in Table52 T is calculated as follows: Jmax – For LQFP64, 45 °C/W T = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C Jmax This is within the junction temperature range of the STM32F102xx (–40 < T < 105 °C). J Figure 40. LQFP64 P max vs. T D A 700 600 500 ) W 400 m ( 300 Suffix 6 D P 200 100 0 65 75 85 95 105 115 T (°C) A DocID15057 Rev 5 74/78 75

Ordering information scheme STM32F102x4, STM32F102x6 7 Ordering information scheme Table 53. Ordering information scheme Example: STM32 F 102C 6 T 6 A xxx Device family STM32 = ARM®-based 32-bit microcontroller Product type F = general-purpose Device subfamily 102 = USB access line, USB 2.0 full-speed interface Pin count C = 48 pins R = 64 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Internal code “A” or blank(1) Options xxx = programmed parts TR = tape and reel 1. For STM32F102x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet available from the ST website: www.st.com. 75/78 DocID15057 Rev 5

Revision history STM32F102x4, STM32F102x6 8 Revision history Table 54. Document revision history Date Revision Changes 23-Sep-2008 1 Initial release. I/O information clarified on page 1. Figure1: STM32F102T8 medium- density USB access line block diagram and Figure5: Memory map modified. In Table4: low-density STM32F102xx pin definitions: PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, Note4. added. P value added for LQFP64 package in Table8: General operating D conditions. Note modified in Table13: Maximum current consumption in Run mode, 09-Apr-2009 2 code with data processing running from Flash and Table15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure13, Figure14 and Figure15 show typical curves. Figure31: ADC accuracy characteristics modified. Figure33: Power supply and reference decoupling modified. Small text changes. Table20: High-speed external user clock characteristics and Table21: Low-speed external user clock characteristics modified. ACC max values modified in Table24: HSI oscillator characteristics. HSI Note5. updated and Note4. added in Table4: low-density STM32F102xx pin definitions. Typical I value added in Table16: Typical and DD_VBAT maximum current consumptions in Stop and Standby modes. Figure12: Typical current consumption on V with RTC on versus temperature at BAT different V values added. BAT f min modified in Table20: High-speed external user clock HSE_ext characteristics. C and C replaced by C in Table22: HSE 4-16 MHz oscillator L1 L2 characteristics and Table23: LSE oscillator characteristics (f = 32.768 LSE kHz), notes modified and moved below the tables. Table24: HSI oscillator 24-Sep-2009 3 characteristics modified. Conditions removed from Table26: Low-power mode wakeup timings. Note1. modified below Figure18: Typical application with an 8 MHz crystal. Figure25: Recommended NRST pin protection modified. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC61967-2 in Section5.3.10: EMC characteristics on page46. Jitter added to Table27: PLL characteristics. C and R parameters modified in Table47: ADC characteristics. ADC AIN R max values modified in Table48: R max for f = 12 MHz. AIN AIN ADC 76/78 DocID15057 Rev 5

STM32F102x4, STM32F102x6 Revision history Table 54. Document revision history (continued) Date Revision Changes Figure2: Clock tree: added FLITFCLK and Note3., and modified Note1.. Removed sentence in “Unless otherwise specified the parameters ...” in I2C interface characteristics section. Added V in Table8: General operating conditions. IN Added note 5 in Table23: HSI oscillator characteristics Added DuCy in Table23: HSI oscillator characteristics (HSI) Table24: LSI oscillator characteristics: removed note 2 related to oscillator selection, updated Note2., and t ) specified for various SU(LSE ambient temperature values. Modified charge device model in Table33: I/O current injection susceptibility. Updated ‘V ’ and ‘V ’ in Table34: I/O static characteristics. IL IH Added notes to Figure20: Standard I/O input characteristics - CMOS port, Figure21: Standard I/O input characteristics - TTL port, Figure22: 5V 02-Aug-2013 4 tolerant I/O input characteristics - CMOS port and Figure23: 5V tolerant I/O input characteristics - TTL port Table37: Output voltage characteristics: updated V and V conditions OL OH for TTL and CMOS outputs and added Note2. Updated Figure24: I/O AC characteristics definition Updated Figure25: Recommended NRST pin protection Updated note 2. and 3. in Table39: I2C characteristics Updated Figure26: I2C bus AC waveforms and measurement circuit(1) Updated title of Table40: SCL frequency (f = 36 MHz, V = 3.3 PCLK1 DD_I2C V) In Table43: SPI characteristics, removed note 1 related to SPI1 remapped characteristics. Updated Table47: ADC characteristics Updated Section6.1: Package mechanical data Updated Table18: Peripheral current consumption and Table39: I2C characteristics. Updated Section6: Package characteristics. Updated Section6.1: LQFP64 package information with addition of 14-May-2015 5 Device marking for LQFP64 and Figure36. Updated Section6.2: LQFP48 package information with addition of Device marking for LQFP48 and Figure39. Updated Disclaimer. DocID15057 Rev 5 77/78 77

STM32F102x4, STM32F102x6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 78/78 DocID15057 Rev 5

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