STM32F051x4 STM32F051x6 STM32F051x8 ® ARM -based 32-bit MCU, 16 to 64 KB Flash, 11 timers, ADC, DAC and communication interfaces, 2.0-3.6 V Datasheet - production data Features (cid:41)(cid:37)(cid:42)(cid:36) • Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz LQFP64 10x10mm UFQFPN48 7x7mm UFBGA64 WLCSP36 • Memories LLQQFFPP4382 77xx77mmmm UFQFPN32 5x5mm 5x5mm 2.6x2.7mm – 16 to 64 Kbytes of Flash memory – One 16-bit timer, with 2 IC/OC, 1 OCN, – 8 Kbytes of SRAM with HW parity checking deadtime generation and emergency stop • CRC calculation unit – Two 16-bit timers, each with IC/OC and • Reset and power management OCN, deadtime generation, emergency stop and modulator gate for IR control – Digital and I/O supply: V = 2.0 V to 3.6 V DD – One 16-bit timer with 1 IC/OC – Analog supply: V = from V to 3.6 V DDA DD – Independent and system watchdog timers – Power-on/Power down reset (POR/PDR) – SysTick timer: 24-bit downcounter – Programmable voltage detector (PVD) – One 16-bit basic timer to drive the DAC – Low power modes: Sleep, Stop, Standby • Calendar RTC with alarm and periodic wakeup – V supply for RTC and backup registers BAT from Stop/Standby • Clock management • Communication interfaces – 4 to 32 MHz crystal oscillator – Up to two I2C interfaces, one supporting – 32 kHz oscillator for RTC with calibration Fast Mode Plus (1 Mbit/s) with 20 mA – Internal 8 MHz RC with x6 PLL option current sink, SMBus/PMBus and wakeup – Internal 40 kHz RC oscillator from Stop mode • Up to 55 fast I/Os – Up to two USARTs supporting master synchronous SPI and modem control, one – All mappable on external interrupt vectors with ISO7816 interface, LIN, IrDA – Up to 36 I/Os with 5 V tolerant capability capability, auto baud rate detection and • 5-channel DMA controller wakeup feature • One 12-bit, 1.0 µs ADC (up to 16 channels) – Up to two SPIs (18 Mbit/s) with 4 to 16 – Conversion range: 0 to 3.6 V programmable bit frame, one with I2S interface multiplexed – Separate analog supply from 2.4 up to 3.6 • One 12-bit DAC channel • HDMI CEC interface, wakeup on header reception • Two fast low-power analog comparators with • Serial wire debug (SWD) programmable input and output • Up to 18 capacitive sensing channels • 96-bit unique ID supporting touchkey, linear and rotary touch • All packages ECOPACK®2 sensors • Up to 11 timers Table 1. Device summary – One 16-bit 7-channel advanced-control Reference Part number timer for 6 channels PWM output, with STM32F051C4, STM32F051K4, STM32F051R4 deadtime generation and emergency stop STM32F051C6, STM32F051K6, STM32F051R6 STM32F051xx STM32F051C8, STM32F051K8, STM32F051R8, – One 32-bit and one 16-bit timer, with up to STM32F051T8 4 IC/OC, usable for IR control decoding January 2017 DocID022265 Rev 7 1/122 This is information on a product in full production. www.st.com

Contents STM32F051x4 STM32F051x6 STM32F051x8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 17 3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.2 Internal voltage reference (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REFINT 3.10.3 V battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BAT 3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22 3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Contents 3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25 3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26 3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 47 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 48 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DocID022265 Rev 7 3/122 4

Contents STM32F051x4 STM32F051x6 STM32F051x8 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.20 V monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 BAT 6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.1 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.7 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 112 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F051xx family device features and peripheral count. . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Capacitive sensing GPIOs available on STM32F051xx devices . . . . . . . . . . . . . . . . . . . . 20 Table 6. Effective number of capacitive sensing channels on STM32F051xx . . . . . . . . . . . . . . . . . 20 Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Comparison of I2C analog and digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. STM32F051xx I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. STM32F051xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. STM32F051xx SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12. Legend/abbreviations used in the pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 37 Table 15. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 38 Table 16. STM32F051xx peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 23. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25. Typical and maximum current consumption from V at 3.6 V . . . . . . . . . . . . . . . . . . . . . 50 DD Table 26. Typical and maximum current consumption from the V supply . . . . . . . . . . . . . . . . . 51 DDA Table 27. Typical and maximum current consumption in Stop and Standby modes . . . . . . . . . . . . 52 Table 28. Typical and maximum current consumption from the V supply. . . . . . . . . . . . . . . . . . . 53 BAT Table 29. Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 31. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 32. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 33. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 34. Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 35. HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36. LSE oscillator characteristics (f = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LSE Table 37. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 38. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 39. LSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 40. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 41. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 42. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 43. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 44. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 45. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 46. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 47. I/O current injection susceptibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DocID022265 Rev 7 5/122 6

List of tables STM32F051x4 STM32F051x6 STM32F051x8 Table 48. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 49. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 50. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 51. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 52. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 53. R max for f = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 AIN ADC Table 54. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 55. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 56. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 57. TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 58. V monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 BAT Table 59. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 60. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 61. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 64. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 65. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 66. UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 67. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 68. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 69. UFQFPN48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 70. WLCSP36 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 71. WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 72. LQFP32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 73. UFQFPN32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 74. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 75. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 76. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 List of figures List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. LQFP64 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 4. UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 5. LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 7. WLCSP36 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8. LQFP32 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 10. STM32F051x8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 17. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 18. Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 64 Figure 20. HSI14 oscillator accuracy characterization results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 21. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 25. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 26. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 27. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 28. Maximum V scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 83 REFINT Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 30. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 31. SPI timing diagram - master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 32. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 33. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 34. UFBGA64 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 35. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 36. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 37. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 38. Recommended footprint for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 39. LQFP64 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 40. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 41. Recommended footprint for LQFP48 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 42. LQFP48 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 43. UFQFPN48 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 44. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 45. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 46. WLCSP36 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 47. Recommended pad footprint for WLCSP36 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 48. WLCSP36 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DocID022265 Rev 7 7/122 8

List of figures STM32F051x4 STM32F051x6 STM32F051x8 Figure 49. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 50. Recommended footprint for LQFP32 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 51. LQFP32 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 52. UFQFPN32 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 53. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 54. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 55. LQFP64 P max versus T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 D A 8/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F051xx microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website. DocID022265 Rev 7 9/122 26

Description STM32F051x4 STM32F051x6 STM32F051x8 2 Description The STM32F051xx microcontrollers incorporate the high-performance ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 64 Kbytes of Flash memory and 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs, up to two SPIs, one I2S, one HDMI CEC and up to two USARTs), one 12-bit ADC, one 12-bit DAC, six 16-bit timers, one 32-bit timer and an advanced-control PWM timer. The STM32F051xx microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power- saving modes allows the design of low-power applications. The STM32F051xx microcontrollers include devices in seven different packages ranging from 32 pins to 64 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F051xx microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs. 10/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Description Table 2. STM32F051xx family device features and peripheral count Peripheral STM32F051Kx STM32F051T8 STM32F051Cx STM32F051Rx Flash memory (Kbyte) 16 32 64 64 16 32 64 16 32 64 SRAM (Kbyte) 8 Advanced 1 (16-bit) control Timers General 5 (16-bit) purpose 1 (32-bit) Basic 1 (16-bit) SPI [I2S](1) 1 [1](2) 1 [1](2) 1 [1](2) 2 [1] 2 [1] I2C 1(3) 1(3) 1(3) 2 1(3) 2 Comm. interfaces USART 1(4) 2 2 1(4) 2 1(4) 2 CEC 1 12-bit ADC 1 1 (number of channels) (10 ext. + 3 int.) (16 ext. + 3 int.) 12-bit DAC 1 (number of channels) (1) Analog comparator 2 25 (on LQFP32) GPIOs 29 39 55 27 (on UFQFPN32) 13 (on LQFP32) Capacitive sensing channels 14 17 18 14 (on UFQFPN32) Max. CPU frequency 48 MHz Operating voltage 2.0 to 3.6 V Ambient operating temperature: -40°C to 85°C / -40°C to 105°C Operating temperature Junction temperature: -40°C to 105°C / -40°C to 125°C LQFP32 LQFP48 LQFP64 Packages WLCSP36 UFQFPN32 UFQFPN48 UFBGA64 1. The SPI1 interface can be used either in SPI mode or in I2S audio mode. 2. SPI2 is not present. 3. I2C2 is not present. 4. USART2 is not present. DocID022265 Rev 7 11/122 26

Description STM32F051x4 STM32F051x6 STM32F051x8 Figure 1. Block diagram (cid:54)(cid:58)(cid:38)(cid:47)(cid:46)(cid:3) (cid:54)(cid:72)(cid:85)(cid:76)(cid:68)(cid:79)(cid:3)(cid:58)(cid:76)(cid:85)(cid:72)(cid:3) (cid:51)(cid:50)(cid:58)(cid:40)(cid:53) (cid:54)(cid:58)(cid:68)(cid:86)(cid:39)(cid:3)(cid:36)(cid:44)(cid:50)(cid:41) (cid:39)(cid:72)(cid:69)(cid:88)(cid:74) (cid:69)(cid:79) (cid:57)(cid:39)(cid:39)(cid:20)(cid:27) (cid:22)(cid:57)(cid:17)(cid:22)(cid:50)(cid:3)(cid:57)(cid:47)(cid:3)(cid:55)(cid:87)(cid:82)(cid:17)(cid:53)(cid:3)(cid:20)(cid:40)(cid:17)(cid:27)(cid:42)(cid:3)(cid:3)(cid:57) (cid:57)(cid:57)(cid:39)(cid:54)(cid:54)(cid:39)(cid:3)(cid:3)(cid:32)(cid:3)(cid:21)(cid:3)(cid:87)(cid:82)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:38)(cid:50)(cid:73)(cid:48)(cid:53)(cid:36)(cid:55)(cid:59)(cid:3)(cid:40)(cid:32)(cid:59)(cid:3)(cid:23)(cid:16)(cid:27)(cid:48)(cid:3)(cid:48)(cid:19)(cid:3)(cid:43)(cid:38)(cid:93)(cid:51)(cid:56)(cid:3) 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STM32F051x4 STM32F051x6 STM32F051x8 Functional overview 3 Functional overview Figure 1 shows the general block diagram of the STM32F051xx devices. ® ® 3.1 ARM -Cortex -M0 core ® ® The ARM Cortex -M0 is a generation of ARM 32-bit RISC processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. ® ® The ARM Cortex -M0 processors feature exceptional code-efficiency, delivering the high performance expected from an ARM core, with memory sizes usually associated with 8- and 16-bit devices. The STM32F051xx devices embed ARM core and are compatible with all ARM tools and software. 3.2 Memories The device has the following features: • 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. • The non-volatile memory is divided into two arrays: – 16 to 64 Kbytes of embedded Flash memory for programs and data – Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: – Level 0: no readout protection – Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected ® – Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and boot in RAM selection disabled 3.3 Boot modes At startup, the boot pin and boot selector option bit are used to select one of the three boot options: • boot from User Flash memory • boot from System Memory • boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15 or PA9/PA10. DocID022265 Rev 7 13/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 3.4 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 Power management 3.5.1 Power supply schemes • V = V = 2.0 to 3.6 V: external power supply for I/Os (V ) and the internal DD DDIO1 DDIO1 regulator. It is provided externally through VDD pins. • V = from V to 3.6 V: external analog power supply for ADC, DAC, Reset blocks, DDA DD RCs and PLL (minimum voltage to be applied to V is 2.4 V when the ADC or DAC DDA are used). It is provided externally through VDDA pin. The V voltage level must be DDA always greater or equal to the V voltage level and must be established first. DD • V = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and BAT backup registers (through power switch) when V is not present. DD For more details on how to connect power pins, refer to Figure 13: Power supply scheme. 3.5.2 Power supply supervisors The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, V , without the need for an external reset circuit. POR/PDR • The POR monitors only the V supply voltage. During the startup phase it is required DD that V should arrive first and be greater than or equal to V . DDA DD • The PDR monitors both the V and V supply voltages, however the V power DD DDA DDA supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V is higher than or DDA equal to V . DD The device features an embedded programmable voltage detector (PVD) that monitors the V power supply and compares it to the V threshold. An interrupt can be generated DD PVD when V drops below the V threshold and/or when V is higher than the V DD PVD DD PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.5.3 Voltage regulator The regulator has two operating modes and it is always enabled after reset. • Main (MR) is used in normal operating mode (Run). • Low power (LPR) can be used in Stop mode where the power demand is reduced. 14/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). 3.5.4 Low-power modes The STM32F051xx microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,, COMPx or the CEC. The CEC, USART1 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as to get clock for processing incoming data. If this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 3.6 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. DocID022265 Rev 7 15/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 Figure 2. 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(cid:36)(cid:43)(cid:37)(cid:15)(cid:3)(cid:70)(cid:82)(cid:85)(cid:72)(cid:15)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:15)(cid:3)(cid:39)(cid:48)(cid:36)(cid:15)(cid:3) (cid:43)(cid:38)(cid:47)(cid:46) (cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91)(cid:3)(cid:41)(cid:38)(cid:47)(cid:46)(cid:3)(cid:73)(cid:85)(cid:72)(cid:72)(cid:16)(cid:85)(cid:88)(cid:81)(cid:3)(cid:70)(cid:79)(cid:82)(cid:70)(cid:78) (cid:54)(cid:58) (cid:54)(cid:60)(cid:54)(cid:38)(cid:47)(cid:46) (cid:51)(cid:47)(cid:47)(cid:54)(cid:53)(cid:38) (cid:51)(cid:47)(cid:47)(cid:48)(cid:56)(cid:47) (cid:18)(cid:27) (cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91)(cid:3) (cid:86)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:87)(cid:76)(cid:80)(cid:72)(cid:85)(cid:3) (cid:43)(cid:54)(cid:44) (cid:51)(cid:47)(cid:47) (cid:51)(cid:47)(cid:47)(cid:38)(cid:47)(cid:46) (cid:18)(cid:20)(cid:15)(cid:18)(cid:21)(cid:15)(cid:171) (cid:18)(cid:20)(cid:15)(cid:18)(cid:21)(cid:15)(cid:18)(cid:23)(cid:15) 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(cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:87)(cid:85)(cid:72)(cid:72)(cid:3)(cid:72)(cid:79)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:55)(cid:44)(cid:48)(cid:20)(cid:23) (cid:47)(cid:54)(cid:40) (cid:90)(cid:75)(cid:76)(cid:87)(cid:72) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:87)(cid:85)(cid:72)(cid:72)(cid:3)(cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:3)(cid:72)(cid:79)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72) (cid:48)(cid:38)(cid:50) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72) (cid:48)(cid:54)(cid:89)(cid:20)(cid:28)(cid:28)(cid:22)(cid:24)(cid:57)(cid:22) 3.7 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. 16/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.8 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers (except TIM14), DAC and ADC. 3.9 Interrupts and events 3.9.1 Nested vectored interrupt controller (NVIC) The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to ® 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4 priority levels. • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 55 GPIOs can be connected to the 16 external interrupt lines. 3.10 Analog-to-digital converter (ADC) The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature DocID022265 Rev 7 17/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 Temperature sensor The temperature sensor (TS) generates a voltage V that varies linearly with SENSE temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 3. Temperature sensor calibration values Calibration value name Description Memory address TS ADC raw data acquired at a TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF F7B8 - 0x1FFF F7B9 V = 3.3 V (± 10 mV) DDA TS ADC raw data acquired at a TS_CAL2 temperature of 110 °C (± 5 °C), 0x1FFF F7C2 - 0x1FFF F7C3 V = 3.3 V (± 10 mV) DDA 3.10.2 Internal voltage reference (V ) REFINT The internal voltage reference (V ) provides a stable (bandgap) voltage output for the REFINT ADC and comparators. V is internally connected to the ADC_IN17 input channel. The REFINT precise voltage of V is individually measured for each part by ST during production REFINT test and stored in the system memory area. It is accessible in read-only mode. Table 4. Internal voltage reference calibration values Calibration value name Description Memory address Raw data acquired at a VREFINT_CAL temperature of 30 °C (± 5 °C), 0x1FFF F7BA - 0x1FFF F7BB V = 3.3 V (± 10 mV) DDA 18/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview 3.10.3 V battery voltage monitoring BAT This embedded hardware feature allows the application to measure the V battery voltage BAT using the internal ADC channel ADC_IN18. As the V voltage may be higher than V , BAT DDA and thus outside the ADC input range, the V pin is internally connected to a bridge BAT divider by 2. As a consequence, the converted digital value is half the V voltage. BAT 3.11 Digital-to-analog converter (DAC) The 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This digital Interface supports the following features: • Left or right data alignment in 12-bit mode • Synchronized update capability • DMA capability • External triggers for conversion Five DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger outputs and the DAC interface is generating its own DMA requests. 3.12 Comparators (COMP) The device embeds two fast rail-to-rail low-power comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output pins • Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 24: Embedded internal reference voltage for the value and precision of the internal reference voltage. Both comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.13 Touch sensing controller (TSC) The STM32F051xx devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 18 capacitive sensing channels distributed over 6 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists in charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the DocID022265 Rev 7 19/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 hardware touch sensing controller and only requires few external components to operate. For operation, one capacitive sensing GPIO in each group is connected to an external capacitor and cannot be used as effective touch sensing channel. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. Table 5. Capacitive sensing GPIOs available on STM32F051xx devices Capacitive sensing Pin Capacitive sensing Pin Group Group signal name name signal name name TSC_G1_IO1 PA0 TSC_G4_IO1 PA9 TSC_G1_IO2 PA1 TSC_G4_IO2 PA10 1 4 TSC_G1_IO3 PA2 TSC_G4_IO3 PA11 TSC_G1_IO4 PA3 TSC_G4_IO4 PA12 TSC_G2_IO1 PA4 TSC_G5_IO1 PB3 TSC_G2_IO2 PA5 TSC_G5_IO2 PB4 2 5 TSC_G2_IO3 PA6 TSC_G5_IO3 PB6 TSC_G2_IO4 PA7 TSC_G5_IO4 PB7 TSC_G3_IO1 PC5 TSC_G6_IO1 PB11 TSC_G3_IO2 PB0 TSC_G6_IO2 PB12 3 6 TSC_G3_IO3 PB1 TSC_G6_IO3 PB13 TSC_G3_IO4 PB2 TSC_G6_IO4 PB14 T a ble 6. Effective number of capacitive sensing channels on STM32F051xx Number of capacitive sensing channels Analog I/O group STM32F051KxU STM32F051KxT STM32F051Rx STM32F051Cx STM32F051Tx (UFQFPN32) (LQFP32) G1 3 3 3 3 3 G2 3 3 3 3 3 G3 3 2 2 2 1 G4 3 3 3 3 3 G5 3 3 3 3 3 G6 3 3 0 0 0 Number of capacitive 18 17 14 14 13 sensing channels 20/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview 3.14 Timers and watchdogs The STM32F051xx devices include up to six general-purpose timers, one basic timer and an advanced control timer. Table 7 compares the features of the different timers. Table 7. Timer feature comparison DMA Timer Counter Counter Prescaler Capture/compare Complementary Timer request type resolution type factor channels outputs generation Advanced Up, down, integer from TIM1 16-bit Yes 4 3 control up/down 1 to 65536 Up, down, integer from TIM2 32-bit Yes 4 - up/down 1 to 65536 Up, down, integer from TIM3 16-bit Yes 4 - up/down 1 to 65536 General integer from TIM14 16-bit Up No 1 - purpose 1 to 65536 integer from TIM15 16-bit Up Yes 2 1 1 to 65536 TIM16 integer from 16-bit Up Yes 1 1 TIM17 1 to 65536 integer from Basic TIM6 16-bit Up Yes - - 1 to 65536 3.14.1 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for: • input capture • output compare • PWM generation (edge or center-aligned modes) • one-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining. DocID022265 Rev 7 21/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) There are six synchronizable general-purpose timers embedded in the STM32F051xx devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base. TIM2, TIM3 STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced- control timer via the Timer Link feature for synchronization or event chaining. TIM2 and TIM3 both have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Their counters can be frozen in debug mode. TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output. Its counter can be frozen in debug mode. TIM15, TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation. Their counters can be frozen in debug mode. 3.14.3 Basic timer TIM6 This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base. 3.14.4 Independent watchdog (IWDG) The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It 22/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.14.5 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.14.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • a 24-bit down counter • autoreload capability • maskable system interrupt generation when the counter reaches 0 • programmable clock source (HCLK or HCLK/8) 3.15 Real-time clock (RTC) and backup registers The RTC and the five backup registers are supplied through a switch that takes power either on V supply when present or through the V pin. The backup registers are five 32-bit DD BAT registers used to store 20 bytes of user application data when V power is not present. DD They are not reset by a system or power reset, or at wake up from Standby mode. The RTC is an independent BCD timer/counter. Its main features are the following: • calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format • automatic correction for 28, 29 (leap year), 30, and 31 day of the month • programmable alarm with wake up from Stop and Standby mode capability • on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize the RTC with a master clock • digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy • two anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection • timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection • reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision DocID022265 Rev 7 23/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 The RTC clock sources can be: • a 32.768 kHz external crystal • a resonator or oscillator • the internal low-power RC oscillator (typical frequency of 40 kHz) • the high-speed external clock divided by 32 2 3.16 Inter-integrated circuit interface (I C) Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s) and Fast mode (up to 400 kbit/s) and, I2C1 also supports Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive. Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). They also include programmable analog and digital noise filters. Table 8. Comparison of I2C analog and digital filters Aspect Analog filter Digital filter Pulse width of Programmable length from 1 to 15 ≥ 50 ns suppressed spikes I2Cx peripheral clocks –Extra filtering capability vs. Benefits Available in Stop mode standard requirements –Stable length Wakeup from Stop on address Variations depending on Drawbacks match is not available when digital temperature, voltage, process filter is enabled. In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match. The I2C peripherals can be served by the DMA controller. Refer to Table 9 for the differences between I2C1 and I2C2. Table 9. STM32F051xx I2C implementation I2C features(1) I2C1 I2C2 7-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X - Independent clock X - 24/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Functional overview Table 9. STM32F051xx I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X - Wakeup from STOP X - 1. X = supported. 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) The device embeds up to two universal synchronous/asynchronous receivers/transmitters (USART1, USART2) which communicate at speeds of up to 6 Mbit/s. They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode. The USART interfaces can be served by the DMA controller. Table 10. STM32F051xx USART implementation USART modes/features(1) USART1 USART2 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X - LIN mode X - Dual clock domain and wakeup from Stop mode X - Receiver timeout interrupt X - Modbus communication X - Auto baud rate detection X - Driver Enable X X 1. X = supported. DocID022265 Rev 7 25/122 26

Functional overview STM32F051x4 STM32F051x6 STM32F051x8 3.18 Serial peripheral interface (SPI) / Inter-integrated sound 2 interface (I S) Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full- duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. One standard I2S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. Table 11. STM32F051xx SPI/I2S implementation SPI features(1) SPI1 SPI2 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X I2S mode X - TI mode X X 1. X = supported. 3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception. 3.20 Serial wire debug port (SW-DP) An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. 26/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions 4 Pinouts and pin descriptions Figure 3. LQFP64 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:39)(cid:39)(cid:54)(cid:54)(cid:37)(cid:28)(cid:37)(cid:27)(cid:50)(cid:50)(cid:55)(cid:19)(cid:37)(cid:26)(cid:37)(cid:25)(cid:37)(cid:24)(cid:37)(cid:23)(cid:37)(cid:22)(cid:39)(cid:21)(cid:3)(cid:3)(cid:38)(cid:20)(cid:21)(cid:38)(cid:20)(cid:20)(cid:38)(cid:20)(cid:19)(cid:36)(cid:20)(cid:24)(cid:36)(cid:20)(cid:23) (cid:57)(cid:57)(cid:51)(cid:51)(cid:37)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:23) (cid:22) (cid:21) (cid:20) (cid:19) (cid:28) (cid:27) (cid:26) (cid:25) (cid:24) (cid:23) (cid:22) (cid:21) (cid:20) (cid:19) (cid:28) (cid:25) (cid:25) (cid:25) (cid:25) (cid:25) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:24) (cid:23) (cid:57)(cid:37)(cid:36)(cid:55) (cid:20) (cid:23)(cid:27) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:20)(cid:22) (cid:21) (cid:23)(cid:26) (cid:51)(cid:41)(cid:25) (cid:51)(cid:38)(cid:20)(cid:23)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:22) (cid:23)(cid:25) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:38)(cid:20)(cid:24)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:23) (cid:23)(cid:24) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:24) (cid:23)(cid:23) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:25) (cid:23)(cid:22) (cid:51)(cid:36)(cid:20)(cid:19) (cid:49)(cid:53)(cid:54)(cid:55) (cid:26) (cid:23)(cid:21) (cid:51)(cid:36)(cid:28) (cid:51)(cid:38)(cid:19) (cid:27) (cid:47)(cid:52)(cid:41)(cid:51)(cid:25)(cid:23) (cid:23)(cid:20) (cid:51)(cid:36)(cid:27) (cid:51)(cid:38)(cid:20) (cid:28) (cid:23)(cid:19) (cid:51)(cid:38)(cid:28) (cid:51)(cid:38)(cid:21) (cid:20)(cid:19) (cid:22)(cid:28) (cid:51)(cid:38)(cid:27) (cid:51)(cid:38)(cid:22) (cid:20)(cid:20) (cid:22)(cid:27) (cid:51)(cid:38)(cid:26) (cid:57)(cid:54)(cid:54)(cid:36) (cid:20)(cid:21) (cid:22)(cid:26) (cid:51)(cid:38)(cid:25) (cid:57)(cid:39)(cid:39)(cid:36) (cid:20)(cid:22) (cid:22)(cid:25) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:36)(cid:19) (cid:20)(cid:23) (cid:22)(cid:24) (cid:51)(cid:37)(cid:20)(cid:23) (cid:51)(cid:36)(cid:20) (cid:20)(cid:24) (cid:22)(cid:23) (cid:51)(cid:37)(cid:20)(cid:22) (cid:51)(cid:36)(cid:21) (cid:20)(cid:25) (cid:22)(cid:22) (cid:51)(cid:37)(cid:20)(cid:21) (cid:26) (cid:27) (cid:28) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:27) (cid:28) (cid:19) (cid:20) (cid:21) (cid:20) (cid:20) (cid:20) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:22) (cid:22) (cid:22) (cid:22)(cid:23)(cid:24)(cid:23)(cid:24)(cid:25)(cid:26)(cid:23)(cid:24)(cid:19)(cid:20)(cid:21)(cid:19)(cid:20)(cid:54)(cid:39) (cid:51)(cid:36)(cid:51)(cid:41)(cid:51)(cid:41)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:38)(cid:51)(cid:38)(cid:51)(cid:37)(cid:51)(cid:37)(cid:51)(cid:37)(cid:51)(cid:37)(cid:20)(cid:51)(cid:37)(cid:20)(cid:57)(cid:54)(cid:57)(cid:39) (cid:48)(cid:54)(cid:89)(cid:20)(cid:28)(cid:27)(cid:23)(cid:22)(cid:57)(cid:21) DocID022265 Rev 7 27/122 36

Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Figure 4. UFBGA64 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:27) (cid:51)(cid:38)(cid:20)(cid:23)(cid:16) (cid:36) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66) (cid:51)(cid:38)(cid:20)(cid:22) (cid:51)(cid:37)(cid:28) (cid:51)(cid:37)(cid:23) (cid:51)(cid:37)(cid:22) (cid:51)(cid:36)(cid:20)(cid:24) (cid:51)(cid:36)(cid:20)(cid:23) (cid:51)(cid:36)(cid:20)(cid:22) (cid:44)(cid:49) (cid:51)(cid:38)(cid:20)(cid:24)(cid:16) (cid:37) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66) (cid:57)(cid:37)(cid:36)(cid:55) (cid:51)(cid:37)(cid:27) (cid:37)(cid:50)(cid:50)(cid:55)(cid:19) (cid:51)(cid:39)(cid:21) (cid:51)(cid:38)(cid:20)(cid:20) (cid:51)(cid:38)(cid:20)(cid:19) (cid:51)(cid:36)(cid:20)(cid:21) (cid:50)(cid:56)(cid:55) (cid:51)(cid:41)(cid:19)(cid:16) (cid:38) (cid:50)(cid:54)(cid:38)(cid:66) (cid:51)(cid:41)(cid:23) (cid:51)(cid:37)(cid:26) (cid:51)(cid:37)(cid:24) (cid:51)(cid:38)(cid:20)(cid:21) (cid:51)(cid:36)(cid:20)(cid:19) (cid:51)(cid:36)(cid:28) (cid:51)(cid:36)(cid:20)(cid:20) (cid:44)(cid:49) (cid:51)(cid:41)(cid:20)(cid:16) (cid:39) (cid:50)(cid:54)(cid:38)(cid:66) (cid:51)(cid:41)(cid:24) (cid:51)(cid:37)(cid:25) (cid:57)(cid:54)(cid:54) (cid:57)(cid:54)(cid:54) (cid:51)(cid:41)(cid:25) (cid:51)(cid:36)(cid:27) (cid:51)(cid:38)(cid:28) (cid:50)(cid:56)(cid:55) (cid:40) (cid:49)(cid:53)(cid:54)(cid:55) (cid:51)(cid:38)(cid:20) (cid:51)(cid:38)(cid:19) (cid:57)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:26) (cid:51)(cid:38)(cid:27) (cid:41) (cid:57)(cid:54)(cid:54)(cid:36) (cid:51)(cid:38)(cid:21) (cid:51)(cid:36)(cid:21) (cid:51)(cid:36)(cid:24) (cid:51)(cid:37)(cid:19) (cid:51)(cid:38)(cid:25) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:37)(cid:20)(cid:23) (cid:42) (cid:51)(cid:38)(cid:22) (cid:51)(cid:36)(cid:19) (cid:51)(cid:36)(cid:22) (cid:51)(cid:36)(cid:25) (cid:51)(cid:37)(cid:20) (cid:51)(cid:37)(cid:21) (cid:51)(cid:37)(cid:20)(cid:19) (cid:51)(cid:37)(cid:20)(cid:22) (cid:43) (cid:57)(cid:39)(cid:39)(cid:36) (cid:51)(cid:36)(cid:20) (cid:51)(cid:36)(cid:23) (cid:51)(cid:36)(cid:26) (cid:51)(cid:38)(cid:23) (cid:51)(cid:38)(cid:24) (cid:51)(cid:37)(cid:20)(cid:20) (cid:51)(cid:37)(cid:20)(cid:21) (cid:56)(cid:41)(cid:37)(cid:42)(cid:36)(cid:25)(cid:23) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:23)(cid:57)(cid:21) Figure 5. LQFP48 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:55)(cid:19) (cid:39)(cid:39)(cid:54)(cid:54)(cid:37)(cid:28)(cid:37)(cid:27)(cid:50)(cid:50)(cid:37)(cid:26)(cid:37)(cid:25)(cid:37)(cid:24)(cid:37)(cid:23)(cid:37)(cid:22)(cid:36)(cid:20)(cid:24)(cid:36)(cid:20)(cid:23) (cid:57)(cid:57)(cid:51)(cid:51)(cid:37)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:27) (cid:26) (cid:25) (cid:24) (cid:23) (cid:22) (cid:21) (cid:20) (cid:19) (cid:28) (cid:27) (cid:26) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:22) (cid:22) (cid:22) (cid:57)(cid:37)(cid:36)(cid:55) (cid:20) (cid:22)(cid:25) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:20)(cid:22) (cid:21) (cid:22)(cid:24) (cid:51)(cid:41)(cid:25) (cid:51)(cid:38)(cid:20)(cid:23)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:22) (cid:22)(cid:23) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:38)(cid:20)(cid:24)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:23) (cid:22)(cid:22) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:24) (cid:22)(cid:21) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:25) (cid:47)(cid:52)(cid:41)(cid:51)(cid:23)(cid:27) (cid:22)(cid:20) (cid:51)(cid:36)(cid:20)(cid:19) (cid:49)(cid:53)(cid:54)(cid:55) (cid:26) (cid:22)(cid:19) (cid:51)(cid:36)(cid:28) (cid:57)(cid:54)(cid:54)(cid:36) (cid:27) (cid:21)(cid:28) (cid:51)(cid:36)(cid:27) (cid:57)(cid:39)(cid:39)(cid:36) (cid:28) (cid:21)(cid:27) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:36)(cid:19) (cid:20)(cid:19) (cid:21)(cid:26) (cid:51)(cid:37)(cid:20)(cid:23) (cid:51)(cid:36)(cid:20) (cid:20)(cid:20) (cid:21)(cid:25) (cid:51)(cid:37)(cid:20)(cid:22) (cid:51)(cid:36)(cid:21) (cid:20)(cid:21) (cid:21)(cid:24) (cid:51)(cid:37)(cid:20)(cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:27) (cid:28) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:19)(cid:20)(cid:21)(cid:19)(cid:20)(cid:54)(cid:39) (cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:36)(cid:51)(cid:37)(cid:51)(cid:37)(cid:51)(cid:37)(cid:51)(cid:37)(cid:20)(cid:51)(cid:37)(cid:20)(cid:57)(cid:54)(cid:57)(cid:39) (cid:48)(cid:54)(cid:89)(cid:20)(cid:28)(cid:27)(cid:23)(cid:21)(cid:57)(cid:21) 28/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Figure 6. UFQFPN48 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:19) (cid:55) (cid:39)(cid:39) (cid:54)(cid:54) (cid:37)(cid:28) (cid:37)(cid:27) (cid:50)(cid:50) (cid:37)(cid:26) (cid:37)(cid:25) (cid:37)(cid:24) (cid:37)(cid:23) (cid:37)(cid:22) (cid:36)(cid:20)(cid:24) (cid:36)(cid:20)(cid:23) (cid:57) (cid:57) (cid:51) (cid:51) (cid:37) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:51) (cid:27) (cid:26) (cid:25) (cid:24) (cid:23) (cid:22) (cid:21) (cid:20) (cid:19) (cid:28) (cid:27) (cid:26) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:23) (cid:22) (cid:22) (cid:22) (cid:57)(cid:37)(cid:36)(cid:55) (cid:20) (cid:22)(cid:25) (cid:51)(cid:41)(cid:26) (cid:51)(cid:38)(cid:20)(cid:22) (cid:21) (cid:22)(cid:24) (cid:51)(cid:41)(cid:25) (cid:51)(cid:38)(cid:20)(cid:23)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:22) (cid:22)(cid:23) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:38)(cid:20)(cid:24)(cid:16)(cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:23) (cid:22)(cid:22) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:24) (cid:22)(cid:21) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:25) (cid:56)(cid:41)(cid:52)(cid:41)(cid:51)(cid:49)(cid:23)(cid:27) (cid:22)(cid:20) (cid:51)(cid:36)(cid:20)(cid:19) (cid:49)(cid:53)(cid:54)(cid:55) (cid:26) (cid:22)(cid:19) (cid:51)(cid:36)(cid:28) (cid:57)(cid:54)(cid:54)(cid:36) (cid:27) (cid:21)(cid:28) (cid:51)(cid:36)(cid:27) (cid:57)(cid:39)(cid:39)(cid:36) (cid:28) (cid:21)(cid:27) (cid:51)(cid:37)(cid:20)(cid:24) (cid:51)(cid:36)(cid:19) (cid:20)(cid:19) (cid:40)(cid:40)(cid:91)(cid:91)(cid:83)(cid:83)(cid:82)(cid:82)(cid:86)(cid:86)(cid:72)(cid:72)(cid:71)(cid:71)(cid:3)(cid:3)(cid:83)(cid:83)(cid:68)(cid:68)(cid:71)(cid:71) (cid:21)(cid:26) (cid:51)(cid:37)(cid:20)(cid:23) (cid:51)(cid:36)(cid:20) (cid:20)(cid:20) (cid:21)(cid:25) (cid:51)(cid:37)(cid:20)(cid:22) (cid:51)(cid:36)(cid:21) (cid:20)(cid:21) (cid:21)(cid:24) (cid:51)(cid:37)(cid:20)(cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:27) (cid:28) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:20) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:19) (cid:20) (cid:21) (cid:19) (cid:20) (cid:54) (cid:39) (cid:51)(cid:36) (cid:51)(cid:36) (cid:51)(cid:36) (cid:51)(cid:36) (cid:51)(cid:36) (cid:51)(cid:37) (cid:51)(cid:37) (cid:51)(cid:37) (cid:51)(cid:37)(cid:20) (cid:51)(cid:37)(cid:20) (cid:57)(cid:54) (cid:57)(cid:39) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:24)(cid:57)(cid:21) Figure 7. WLCSP36 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:36) (cid:51)(cid:36)(cid:20)(cid:21) (cid:51)(cid:36)(cid:20)(cid:24) (cid:51)(cid:37)(cid:23) (cid:51)(cid:37)(cid:26) (cid:57)(cid:39)(cid:39) (cid:51)(cid:38)(cid:20)(cid:22) (cid:51)(cid:41)(cid:19)(cid:16) (cid:51)(cid:38)(cid:20)(cid:23)(cid:16) (cid:37) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:36)(cid:20)(cid:23) (cid:51)(cid:37)(cid:22) (cid:37)(cid:50)(cid:50)(cid:55)(cid:19) (cid:50)(cid:54)(cid:38)(cid:66) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66) (cid:44)(cid:49) (cid:44)(cid:49) (cid:51)(cid:41)(cid:20)(cid:16) (cid:51)(cid:38)(cid:20)(cid:24)(cid:16) (cid:38) (cid:51)(cid:36)(cid:20)(cid:19) (cid:51)(cid:36)(cid:20)(cid:20) (cid:51)(cid:36)(cid:23) (cid:51)(cid:37)(cid:25) (cid:50)(cid:54)(cid:38)(cid:66) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66) (cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55) (cid:39) (cid:51)(cid:36)(cid:28) (cid:51)(cid:37)(cid:21) (cid:51)(cid:36)(cid:24) (cid:51)(cid:36)(cid:20) (cid:49)(cid:53)(cid:54)(cid:55) (cid:57)(cid:54)(cid:54) (cid:40) (cid:57)(cid:39)(cid:39) (cid:51)(cid:36)(cid:27) (cid:51)(cid:36)(cid:25) (cid:51)(cid:36)(cid:21) (cid:57)(cid:39)(cid:39)(cid:36) (cid:51)(cid:37)(cid:24) (cid:41) (cid:57)(cid:54)(cid:54) (cid:51)(cid:37)(cid:20) (cid:51)(cid:37)(cid:19) (cid:51)(cid:36)(cid:26) (cid:51)(cid:36)(cid:22) (cid:51)(cid:36)(cid:19) (cid:58)(cid:47)(cid:38)(cid:54)(cid:51)(cid:22)(cid:25) (cid:48)(cid:54)(cid:89)(cid:22)(cid:28)(cid:19)(cid:21)(cid:27)(cid:57)(cid:22) 1. The above figure shows the package in top view, changing from bottom view in the previous document versions. DocID022265 Rev 7 29/122 36

Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Figure 8. LQFP32 package pinout (cid:19) (cid:55) (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:54)(cid:54)(cid:50)(cid:50)(cid:37)(cid:26)(cid:37)(cid:25)(cid:37)(cid:24)(cid:37)(cid:23)(cid:37)(cid:22)(cid:36)(cid:20)(cid:24) (cid:57)(cid:37)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:21) (cid:20) (cid:19) (cid:28) (cid:27) (cid:26) (cid:25) (cid:24) (cid:22) (cid:22) (cid:22) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:57)(cid:39)(cid:39) (cid:20) (cid:21)(cid:23) (cid:51)(cid:36)(cid:20)(cid:23) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:21) (cid:21)(cid:22) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:22) (cid:21)(cid:21) (cid:51)(cid:36)(cid:20)(cid:21) (cid:49)(cid:53)(cid:54)(cid:55) (cid:23) (cid:47)(cid:52)(cid:41)(cid:51)(cid:22)(cid:21) (cid:21)(cid:20) (cid:51)(cid:36)(cid:20)(cid:20) (cid:57)(cid:39)(cid:39)(cid:36) (cid:24) (cid:21)(cid:19) (cid:51)(cid:36)(cid:20)(cid:19) (cid:51)(cid:36)(cid:19) (cid:25) (cid:20)(cid:28) (cid:51)(cid:36)(cid:28) (cid:51)(cid:36)(cid:20) (cid:26) (cid:20)(cid:27) (cid:51)(cid:36)(cid:27) (cid:51)(cid:36)(cid:21) (cid:27) (cid:20)(cid:26) (cid:57)(cid:39)(cid:39) (cid:28) (cid:20)(cid:19) (cid:20)(cid:20) (cid:20)(cid:21) (cid:20)(cid:22) (cid:20)(cid:23) (cid:20)(cid:24) (cid:20)(cid:25) (cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:19)(cid:20)(cid:54) (cid:36)(cid:36)(cid:36)(cid:36)(cid:36)(cid:37)(cid:37)(cid:54) (cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:57) (cid:48)(cid:54)(cid:89)(cid:22)(cid:19)(cid:23)(cid:26)(cid:24)(cid:57)(cid:21) Figure 9. UFQFPN32 package pinout (cid:55)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:19) (cid:55) (cid:37)(cid:27)(cid:50)(cid:50)(cid:37)(cid:26)(cid:37)(cid:25)(cid:37)(cid:24)(cid:37)(cid:23)(cid:37)(cid:22)(cid:36)(cid:20)(cid:24) (cid:51)(cid:37)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:21) (cid:20) (cid:19) (cid:28) (cid:27) (cid:26) (cid:25) (cid:24) (cid:22) (cid:22) (cid:22) (cid:21) (cid:21) (cid:21) (cid:21) (cid:21) (cid:57)(cid:39)(cid:39) (cid:20) (cid:21)(cid:23) (cid:51)(cid:36)(cid:20)(cid:23) (cid:19) (cid:51)(cid:41)(cid:19)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:21) (cid:21)(cid:22) (cid:51)(cid:36)(cid:20)(cid:22) (cid:51)(cid:41)(cid:20)(cid:16)(cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:22) (cid:21)(cid:21) (cid:51)(cid:36)(cid:20)(cid:21) (cid:49)(cid:53)(cid:54)(cid:55) (cid:23) (cid:56)(cid:41)(cid:52)(cid:41)(cid:51)(cid:49)(cid:22)(cid:21) (cid:21)(cid:20) (cid:51)(cid:36)(cid:20)(cid:20) (cid:57)(cid:39)(cid:39)(cid:36) (cid:24) (cid:21)(cid:19) (cid:51)(cid:36)(cid:20)(cid:19) (cid:51)(cid:36)(cid:19) (cid:25) (cid:20)(cid:28) (cid:51)(cid:36)(cid:28) (cid:51)(cid:36)(cid:20) (cid:26) (cid:40)(cid:40)(cid:91)(cid:91)(cid:83)(cid:83)(cid:82)(cid:82)(cid:86)(cid:86)(cid:72)(cid:72)(cid:71)(cid:71)(cid:3)(cid:3)(cid:83)(cid:83)(cid:68)(cid:68)(cid:71)(cid:71) (cid:20)(cid:27) (cid:51)(cid:36)(cid:27) (cid:51)(cid:36)(cid:21) (cid:27) (cid:20)(cid:26) (cid:57)(cid:39)(cid:39) (cid:28) (cid:20)(cid:19) (cid:20)(cid:20) (cid:20)(cid:21) (cid:20)(cid:22) (cid:20)(cid:23) (cid:20)(cid:24) (cid:20)(cid:25) (cid:57)(cid:54)(cid:54) (cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:19)(cid:20)(cid:21) (cid:36)(cid:36)(cid:36)(cid:36)(cid:36)(cid:37)(cid:37)(cid:37) (cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51)(cid:51) (cid:48)(cid:54)(cid:89)(cid:20)(cid:28)(cid:27)(cid:23)(cid:23)(cid:57)(cid:22) 30/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and Pin name after reset is the same as the actual pin name S Supply pin Pin type I Input-only pin I/O Input / output pin FT 5 V-tolerant I/O FTf 5 V-tolerant I/O, FM+ capable TTa 3.3 V-tolerant I/O directly connected to ADC I/O structure TC Standard 3.3 V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after Notes reset. Alternate Functions selected through GPIOx_AFR registers Pin functions functions Additional Functions directly selected/enabled through peripheral registers functions Table 13. Pin definitions Pin number Pin functions 8 4 e N r LQFP64 UFBGA64 P48/UFQFP WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structu Notes Alternate functions Afudndcittiioonnasl F Q L 1 B2 1 - - - VBAT S - - Backup power supply RTC_TAMP1, RTC_TS, 2 A2 2 A6 - - PC13 I/O TC (1)(2) - RTC_OUT, WKUP2 PC14-OSC32_IN 3 A1 3 B6 - - I/O TC (1)(2) - OSC32_IN (PC14) PC15-OSC32_OUT 4 B1 4 C6 - - I/O TC (1)(2) - OSC32_OUT (PC15) PF0-OSC_IN 5 C1 5 B5 2 2 I/O FT - - OSC_IN (PF0) PF1-OSC_OUT 6 D1 6 C5 3 3 I/O FT - - OSC_OUT (PF1) DocID022265 Rev 7 31/122 36

Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13. Pin definitions (continued) Pin number Pin functions 8 4 e LQFP64 UFBGA64 P48/UFQFPN WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structur Notes Alternate functions Afudndcittiioonnasl F Q L Device reset input / internal reset output 7 E1 7 D5 4 4 NRST I/O RST - (active low) 8 E3 - - - - PC0 I/O TTa - EVENTOUT ADC_IN10 9 E2 - - - - PC1 I/O TTa - EVENTOUT ADC_IN11 10 F2 - - - - PC2 I/O TTa - EVENTOUT ADC_IN12 11 G1 - - - - PC3 I/O TTa - EVENTOUT ADC_IN13 12 F1 8 D6 16 0 VSSA S - (3) Analog ground 13 H1 9 E5 5 5 VDDA S - - Analog power supply USART2_CTS, ADC_IN0, TIM2_CH1_ETR, COMP1_INM6, 14 G2 10 F6 6 6 PA0 I/O TTa - COMP1_OUT, RTC_TAMP2, TSC_G1_IO1 WKUP1 USART2_RTS, TIM2_CH2, ADC_IN1, 15 H2 11 D4 7 7 PA1 I/O TTa - TSC_G1_IO2, COMP1_INP EVENTOUT USART2_TX, TIM2_CH3, ADC_IN2, 16 F3 12 E4 8 8 PA2 I/O TTa - TIM15_CH1, COMP2_INM6 COMP2_OUT, TSC_G1_IO3 USART2_RX, TIM2_CH4, ADC_IN3, 17 G3 13 F5 9 9 PA3 I/O TTa - TIM15_CH2, COMP2_INP TSC_G1_IO4 18 C2 - - - - PF4 I/O FT - EVENTOUT - 19 D2 - - - - PF5 I/O FT - EVENTOUT - SPI1_NSS, ADC_IN4, I2S1_WS, COMP1_INM4, 20 H3 14 C3 10 10 PA4 I/O TTa - USART2_CK, COMP2_INM4, TIM14_CH1, DAC_OUT1 TSC_G2_IO1 SPI1_SCK, ADC_IN5, I2S1_CK, CEC, 21 F4 15 D3 11 11 PA5 I/O TTa - COMP1_INM5, TIM2_CH1_ETR, COMP2_INM5 TSC_G2_IO2 32/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 13. Pin definitions (continued) Pin number Pin functions 8 4 e LQFP64 UFBGA64 P48/UFQFPN WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structur Notes Alternate functions Afudndcittiioonnasl F Q L SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, 22 G4 16 E3 12 12 PA6 I/O TTa - ADC_IN6 TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, 23 H4 17 F4 13 13 PA7 I/O TTa - TIM1_CH1N, ADC_IN7 TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT 24 H5 - - - - PC4 I/O TTa - EVENTOUT ADC_IN14 25 H6 - - - - PC5 I/O TTa - TSC_G3_IO1 ADC_IN15 TIM3_CH3, TIM1_CH2N, 26 F5 18 F3 14 14 PB0 I/O TTa - ADC_IN8 TSC_G3_IO2, EVENTOUT TIM3_CH4, TIM14_CH1, 27 G5 19 F2 15 15 PB1 I/O TTa - ADC_IN9 TIM1_CH3N, TSC_G3_IO3 28 G6 20 D2 - 16 PB2 I/O FT (4) TSC_G3_IO4 - I2C2_SCL, CEC, 29 G7 21 - - - PB10 I/O FT (5) - TIM2_CH3, TSC_SYNC I2C2_SDA, TIM2_CH4, 30 H7 22 - - - PB11 I/O FT (5) - TSC_G6_IO1, EVENTOUT 31 D4 23 F1 16 0 VSS S - - Ground 32 E4 24 E1 17 17 VDD S - - Digital power supply DocID022265 Rev 7 33/122 36

Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13. Pin definitions (continued) Pin number Pin functions 8 4 e LQFP64 UFBGA64 P48/UFQFPN WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structur Notes Alternate functions Afudndcittiioonnasl F Q L SPI2_NSS, TIM1_BKIN, 33 H8 25 - - - PB12 I/O FT (5) - TSC_G6_IO2, EVENTOUT SPI2_SCK, 34 G8 26 - - - PB13 I/O FT (5) TIM1_CH1N, - TSC_G6_IO3 SPI2_MISO, TIM1_CH2N, 35 F8 27 - - - PB14 I/O FT (5) - TIM15_CH1, TSC_G6_IO4 SPI2_MOSI, TIM1_CH3N, 36 F7 28 - - - PB15 I/O FT (5) RTC_REFIN TIM15_CH1N, TIM15_CH2 37 F6 - - - - PC6 I/O FT - TIM3_CH1 - 38 E7 - - - - PC7 I/O FT - TIM3_CH2 - 39 E8 - - - - PC8 I/O FT - TIM3_CH3 - 40 D8 - - - - PC9 I/O FT - TIM3_CH4 - USART1_CK, TIM1_CH1, 41 D7 29 E2 18 18 PA8 I/O FT - - EVENTOUT, MCO USART1_TX, TIM1_CH2, 42 C7 30 D1 19 19 PA9 I/O FT - - TIM15_BKIN, TSC_G4_IO1 USART1_RX, TIM1_CH3, 43 C6 31 C1 20 20 PA10 I/O FT - - TIM17_BKIN, TSC_G4_IO2 USART1_CTS, TIM1_CH4, 44 C8 32 C2 21 21 PA11 I/O FT - COMP1_OUT, - TSC_G4_IO3, EVENTOUT 34/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 13. Pin definitions (continued) Pin number Pin functions 8 4 e LQFP64 UFBGA64 P48/UFQFPN WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structur Notes Alternate functions Afudndcittiioonnasl F Q L USART1_RTS, TIM1_ETR, 45 B8 33 A1 22 22 PA12 I/O FT - COMP2_OUT, - TSC_G4_IO4, EVENTOUT PA13 IR_OUT, 46 A8 34 B1 23 23 I/O FT (6) - (SWDIO) SWDIO 47 D6 35 - - - PF6 I/O FT - I2C2_SCL - 48 E6 36 - - - PF7 I/O FT - I2C2_SDA - PA14 USART2_TX, 49 A7 37 B2 24 24 I/O FT (6) - (SWCLK) SWCLK SPI1_NSS, I2S1_WS, 50 A6 38 A2 25 25 PA15 I/O FT - USART2_RX, - TIM2_CH1_ETR, EVENTOUT 51 B7 - - - - PC10 I/O FT - - 52 B6 - - - - PC11 I/O FT - - 53 C5 - - - - PC12 I/O FT - - 54 B5 - - - - PD2 I/O FT - TIM3_ETR - SPI1_SCK, I2S1_CK, 55 A5 39 B3 26 26 PB3 I/O FT - TIM2_CH2, - TSC_G5_IO1, EVENTOUT SPI1_MISO, I2S1_MCK, 56 A4 40 A3 27 27 PB4 I/O FT - TIM3_CH1, - TSC_G5_IO2, EVENTOUT SPI1_MOSI, I2S1_SD, 57 C4 41 E6 28 28 PB5 I/O FT - I2C1_SMBA, - TIM16_BKIN, TIM3_CH2 DocID022265 Rev 7 35/122 36

Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13. Pin definitions (continued) Pin number Pin functions 8 4 e LQFP64 UFBGA64 P48/UFQFPN WLCSP36 LQFP32 UFQFPN32 (fuPncirntei osnenatm )uep on Pin type I/O structur Notes Alternate functions Afudndcittiioonnasl F Q L I2C1_SCL, USART1_TX, 58 D3 42 C4 29 29 PB6 I/O FTf - - TIM16_CH1N, TSC_G5_IO3 I2C1_SDA, USART1_RX, 59 C3 43 A4 30 30 PB7 I/O FTf - - TIM17_CH1N, TSC_G5_IO4 60 B4 44 B4 31 31 BOOT0 I B - Boot memory selection I2C1_SCL, CEC, 61 B3 45 - - 32 PB8 I/O FTf (4)(5) - TIM16_CH1, TSC_SYNC I2C1_SDA, IR_OUT, 62 A3 46 - - - PB9 I/O FTf (5) - TIM17_CH1, EVENTOUT 63 D5 47 D6 32 0 VSS S - - Ground 64 E5 48 A5 1 1 VDD S - - Digital power supply 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the main reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual. 3. Distinct VSSA pin is only available on packages with 48 and more pins. For all other packages, the pin number corresponds to the VSS pin to which VSSA pad of the silicon die is connected. 4. On the LQFP32 package, PB2 and PB8 must be set to defined levels by software, as their corresponding pads on the silicon die are left unconnected. Apply the same recommendations as for unconnected pins. 5. On the WLCSP36 package, PB8, PB9, PB10, PB11, PB12, PB13, PB14 and PB15 must be set to defined levels by software, as their corresponding pads on the silicon die are left unconnected. Apply the same recommendations as for unconnected pins. 6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated. 36/122 DocID022265 Rev 7

S T Table 14. Alternate functions selected through GPIOA_AFR registers for port A M 3 Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 2 F 0 5 PA0 - USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 - - COMP1_OUT 1 x 4 PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 - - S T PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 - - - COMP2_OUT M 3 2 PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4 - - - - F 0 5 PA4 SPI1_NSS, I2S1_WS USART2_CK - TSC_G2_IO1 TIM14_CH1 - - - 1 x 6 PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 - - - - S T PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 TIM16_CH1 EVENTOUT COMP1_OUT M 3 PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT 2 F 0 PA8 MCO USART1_CK TIM1_CH1 EVENTOUT - - - 5 D 1x oc PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1 - - - - 8 ID 0 2 PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 - - - - 2 2 6 PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 - - - COMP1_OUT 5 R e PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 - - - COMP2_OUT v 7 PA13 SWDIO IR_OUT - - - - - PA14 SWCLK USART2_TX - - - - - - PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT - - - 3 7 /1 2 2

3 8 /1 2 Table 15. Alternate functions selected through GPIOB_AFR registers for port B 2 Pin name AF0 AF1 AF2 AF3 PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 PB2 TSC_G3_IO4 PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 D PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC o c ID PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT 0 2 2 PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC 2 6 5 PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1 R e v PB12 SPI2_NSS EVENTOUT TIM1_BKIN TSC_G6_IO2 S 7 T M PB13 SPI2_SCK TIM1_CH1N TSC_G6_IO3 3 2 PB14 SPI2_MISO TIM15_CH1 TIM1_CH2N TSC_G6_IO4 F 0 5 PB15 SPI2_MOSI TIM15_CH2 TIM1_CH3N TIM15_CH1N 1x 4 S T M 3 2 F 0 5 1 x 6 S T M 3 2 F 0 5 1 x 8

STM32F051x4 STM32F051x6 STM32F051x8 Memory mapping 5 Memory mapping To the difference of STM32F051x8 memory map in Figure 10, the two bottom code memory spaces of STM32F051x4/STM32F051x6 end at 0x0000 3FFF/0x0000 7FFF and 0x0800 3FFF/0x0000 7FFF, respectively. Figure 10. STM32F051x8 memory map (cid:19)(cid:91)(cid:41)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:19)(cid:91)(cid:23)(cid:27)(cid:19)(cid:19)(cid:3)(cid:20)(cid:26)(cid:41)(cid:41) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:36)(cid:43)(cid:37)(cid:21) (cid:26) (cid:19)(cid:91)(cid:23)(cid:27)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:40)(cid:19)(cid:20)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:38)(cid:82)(cid:85)(cid:87)(cid:72)(cid:91)(cid:16)(cid:48)(cid:19)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3) (cid:19)(cid:91)(cid:40)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:83)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:25) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:38)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:23)(cid:22)(cid:41)(cid:41) (cid:36)(cid:43)(cid:37)(cid:20) (cid:24) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:21)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:36)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:27)(cid:19)(cid:19)(cid:19) (cid:23) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:41)(cid:41)(cid:41) (cid:36)(cid:51)(cid:37) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:38)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:20)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:37)(cid:92)(cid:87)(cid:72)(cid:86) (cid:19)(cid:91)(cid:27)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:41)(cid:27)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:54)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:27)(cid:19)(cid:19)(cid:19) (cid:22) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:20)(cid:41)(cid:41)(cid:41)(cid:3)(cid:40)(cid:38)(cid:19)(cid:19) (cid:36)(cid:51)(cid:37) (cid:19)(cid:91)(cid:25)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:21) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19)(cid:91)(cid:23)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:51)(cid:72)(cid:85)(cid:76)(cid:83)(cid:75)(cid:72)(cid:85)(cid:68)(cid:79)(cid:86) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:20)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:20) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:3)(cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92) (cid:19)(cid:91)(cid:21)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:54)(cid:53)(cid:36)(cid:48) (cid:19)(cid:91)(cid:19)(cid:27)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:53)(cid:72)(cid:86)(cid:72)(cid:85)(cid:89)(cid:72)(cid:71) (cid:19) (cid:38)(cid:50)(cid:39)(cid:40) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:20)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:41)(cid:79)(cid:68)(cid:86)(cid:75)(cid:15)(cid:3)(cid:86)(cid:92)(cid:86)(cid:87)(cid:72)(cid:80)(cid:3) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:82)(cid:85)(cid:3)(cid:54)(cid:53)(cid:36)(cid:48)(cid:15)(cid:3) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:71)(cid:72)(cid:83)(cid:72)(cid:81)(cid:71)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:81)(cid:3)(cid:37)(cid:50)(cid:50)(cid:55)(cid:3) (cid:70)(cid:82)(cid:81)(cid:73)(cid:76)(cid:74)(cid:88)(cid:85)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:19)(cid:91)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:19)(cid:19)(cid:19)(cid:19) (cid:48)(cid:54)(cid:22)(cid:21)(cid:20)(cid:28)(cid:21)(cid:57)(cid:21) DocID022265 Rev 7 39/122 41

Memory mapping STM32F051x4 STM32F051x6 STM32F051x8 Table 16. STM32F051xx peripheral register boundary addresses Bus Boundary address Size Peripheral 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB Reserved 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD AHB2 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 3 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved AHB1 0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0400 - 0x4002 0FFF 3 KB Reserved 0x4002 0000 - 0x4002 03FF 1 KB DMA 0x4001 8000 - 0x4001 FFFF 32 KB Reserved 0x4001 5C00 - 0x4001 7FFF 9 KB Reserved 0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU 0x4001 4C00 - 0x4001 57FF 3 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1 APB 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB Reserved 0x4001 2400 - 0x4001 27FF 1 KB ADC 0x4001 0800 - 0x4001 23FF 7 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP 0x4000 8000 - 0x4000 FFFF 32 KB Reserved 40/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Memory mapping Table 16. STM32F051xx peripheral register boundary addresses (continued) Bus Boundary address Size Peripheral 0x4000 7C00 - 0x4000 7FFF 1 KB Reserved 0x4000 7800 - 0x4000 7BFF 1 KB CEC 0x4000 7400 - 0x4000 77FF 1 KB DAC 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 5C00 - 0x4000 6FFF 5 KB Reserved 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 4800 - 0x4000 53FF 3 KB Reserved 0x4000 4400 - 0x4000 47FF 1 KB USART2 0x4000 3C00 - 0x4000 43FF 2 KB Reserved 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 APB 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB Reserved 0x4000 2000 - 0x4000 23FF 1 KB TIM14 0x4000 1400 - 0x4000 1FFF 3 KB Reserved 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0800 - 0x4000 0FFF 2 KB Reserved 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 DocID022265 Rev 7 41/122 41

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V . SS 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by A A A the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They A DD DDA are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 11. Pin loading conditions Figure 12. Pin input voltage (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:48)(cid:38)(cid:56)(cid:3)(cid:83)(cid:76)(cid:81) (cid:38)(cid:3)(cid:32)(cid:3)(cid:24)(cid:19)(cid:3)(cid:83)(cid:41) (cid:57)(cid:44)(cid:49) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:19)(cid:57)(cid:20) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:20)(cid:57)(cid:20) 42/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics 6.1.6 Power supply scheme Figure 13. Power supply scheme (cid:57) (cid:37)(cid:36)(cid:55) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:85)(cid:92) (cid:20)(cid:17)(cid:25)(cid:24)(cid:3)(cid:177)(cid:3)(cid:22)(cid:17)(cid:25)(cid:3)(cid:57) (cid:11)(cid:47)(cid:54)(cid:40)(cid:15)(cid:3)(cid:53)(cid:55)(cid:38)(cid:15) (cid:37)(cid:68)(cid:70)(cid:78)(cid:88)(cid:83)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:86)(cid:12) (cid:51)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:86)(cid:90)(cid:76)(cid:87)(cid:70)(cid:75) (cid:57)(cid:39)(cid:39) (cid:57)(cid:38)(cid:50)(cid:53)(cid:40) (cid:21)(cid:3)(cid:91)(cid:3)(cid:57) (cid:39)(cid:39) (cid:53)(cid:72)(cid:74)(cid:88)(cid:79)(cid:68)(cid:87)(cid:82)(cid:85) (cid:57) (cid:39)(cid:39)(cid:44)(cid:50)(cid:20) (cid:50)(cid:56)(cid:55) (cid:72)(cid:85) (cid:46)(cid:72)(cid:85)(cid:81)(cid:72)(cid:79)(cid:3)(cid:79)(cid:82)(cid:74)(cid:76)(cid:70) (cid:14)(cid:21)(cid:20)(cid:3)(cid:91)(cid:3)(cid:91)(cid:3)(cid:20)(cid:3)(cid:23)(cid:19)(cid:17)(cid:19)(cid:26)(cid:3)(cid:3)(cid:81)(cid:151)(cid:41)(cid:41) (cid:42)(cid:51)(cid:3)(cid:44)(cid:18)(cid:50)(cid:86) (cid:44)(cid:49) (cid:72)(cid:89)(cid:72)(cid:79)(cid:3)(cid:86)(cid:75)(cid:76)(cid:73)(cid:87) (cid:79)(cid:82)(cid:44)(cid:50)(cid:74)(cid:76)(cid:70) (cid:11)(cid:9)(cid:38)(cid:3)(cid:48)(cid:51)(cid:56)(cid:72)(cid:80)(cid:15)(cid:3)(cid:39)(cid:82)(cid:76)(cid:85)(cid:74)(cid:76)(cid:72)(cid:76)(cid:87)(cid:86)(cid:68)(cid:12)(cid:79) (cid:47) (cid:21)(cid:3)(cid:91)(cid:3)(cid:57) (cid:54)(cid:54) (cid:57) (cid:39)(cid:39)(cid:36) (cid:57) (cid:39)(cid:39)(cid:36) (cid:20)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:53)(cid:40)(cid:41)(cid:14) (cid:36)(cid:39)(cid:38)(cid:18) (cid:36)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74)(cid:29) (cid:14)(cid:20)(cid:3)(cid:151)(cid:41) (cid:39)(cid:36)(cid:38) (cid:11)(cid:53)(cid:38)(cid:86)(cid:15)(cid:3)(cid:51)(cid:47)(cid:47)(cid:15)(cid:3)(cid:171)(cid:12) (cid:57)(cid:53)(cid:40)(cid:41)(cid:16) (cid:57) (cid:54)(cid:54)(cid:36) (cid:48)(cid:54)(cid:22)(cid:23)(cid:28)(cid:23)(cid:23)(cid:57)(cid:20) Caution: Each power supply pair (V /V , V /V etc.) must be decoupled with filtering ceramic DD SS DDA SSA capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DocID022265 Rev 7 43/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6.1.7 Current consumption measurement Figure 14. Current consumption measurement scheme (cid:44)(cid:39)(cid:39)(cid:66)(cid:57)(cid:37)(cid:36)(cid:55) (cid:57)(cid:37)(cid:36)(cid:55) (cid:44)(cid:39)(cid:39) (cid:57)(cid:39)(cid:39) (cid:44)(cid:39)(cid:39)(cid:36) (cid:57)(cid:39)(cid:39)(cid:36) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:22)(cid:57)(cid:20) 44/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics, Table 18: Current characteristics and Table 19: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 17. Voltage characteristics(1) Symbol Ratings Min Max Unit V –V External main supply voltage - 0.3 4.0 V DD SS V –V External analog supply voltage - 0.3 4.0 V DDA SS V –V Allowed voltage difference for V > V - 0.4 V DD DDA DD DDA V –V External backup supply voltage - 0.3 4.0 V BAT SS Input voltage on FT and FTf pins V - 0.3 V + 4.0(3) V SS DDIOx Input voltage on TTa pins V - 0.3 4.0 V V (2) SS IN BOOT0 0 9.0 V Input voltage on any other pin V - 0.3 4.0 V SS |∆V | Variations between different V power pins - 50 mV DDx DD Variations between all the different ground |V - V | - 50 mV SSx SS pins Electrostatic discharge voltage see Section 6.3.12: Electrical V - ESD(HBM) (human body model) sensitivity characteristics 1. All main power (V , V ) and ground (V , V ) pins must always be connected to the external power DD DDA SS SSA supply, in the permitted range. 2. V maximum must always be respected. Refer to Table 18: Current characteristics for the maximum IN allowed injected current values. 3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V. DocID022265 Rev 7 45/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 18. Current characteristics Symbol Ratings Max. Unit ΣI Total current into sum of all VDD power lines (source)(1) 120 VDD ΣI Total current out of sum of all VSS ground lines (sink)(1) -120 VSS I Maximum current into each VDD power pin (source)(1) 100 VDD(PIN) I Maximum current out of each VSS ground pin (sink)(1) -100 VSS(PIN) Output current sunk by any I/O and control pin 25 I IO(PIN) Output current source by any I/O and control pin -25 Total output current sunk by sum of all I/Os and control pins(2) 80 ΣI IO(PIN) Total output current sourced by sum of all I/Os and control pins(2) -80 mA Injected current on B, FT and FTf pins -5/+0(4) I (3) Injected current on TC and RST pin ± 5 INJ(PIN) Injected current on TTa pins(5) ± 5 ΣI Total injected current (sum of all I/O and control pins)(6) ± 25 INJ(PIN) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. A positive injection is induced by V > V while a negative injection is induced by V < V . I must never be IN DDIOx IN SS INJ(PIN) exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. On these I/Os, a positive injection is induced by V > V . Negative injection disturbs the analog performance of the device. See note (2) below Table 54: ADC accuracIyN. DDA 6. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the positive and INJ(PIN) negative injected currents (instantaneous values). Table 19. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range –65 to +150 °C STG T Maximum junction temperature 150 °C J 46/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 20. General operating conditions Symbol Parameter Conditions Min Max Unit f Internal AHB clock frequency - 0 48 HCLK MHz f Internal APB clock frequency - 0 48 PCLK V Standard operating voltage - 2.0 3.6 V DD Analog operating voltage V 3.6 (ADC and DAC not used) Must have a potential equal DD V V DDA Analog operating voltage to or higher than VDD 2.4 3.6 (ADC and DAC used) V Backup operating voltage - 1.65 3.6 V BAT TC and RST I/O –0.3 V +0.3 DDIOx TTa I/O –0.3 V +0.3(1) DDA V I/O input voltage V IN FT and FTf I/O –0.3 5.5(1) BOOT0 0 5.5 LQFP64 - 444 LQFP48 - 364 LQFP32 - 357 Power dissipation at TA = 85 °C P for suffix 6 or T = 105 °C for UFQFPN32 - 526 mW D A suffix 7(2) UFQFPN48 - 625 UFBGA64 - 308 WLCSP36 - 333 Ambient temperature for the Maximum power dissipation –40 85 °C suffix 6 version Low power dissipation(3) –40 105 TA Ambient temperature for the Maximum power dissipation –40 105 °C suffix 7 version Low power dissipation(3) –40 125 Suffix 6 version –40 105 TJ Junction temperature range °C Suffix 7 version –40 125 1. For operation with a voltage higher than V + 0.3 V, the internal pull-up resistor must be disabled. DDIOx 2. If T is lower, higher P values are allowed as long as T does not exceed T . See Section 7.8: Thermal characteristics. A D J Jmax 3. In low power dissipation state, T can be extended to this range as long as T does not exceed T (see Section 7.8: A J Jmax Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 21 are derived from tests performed under the ambient temperature condition summarized in Table 20. DocID022265 Rev 7 47/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 21. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max Unit V rise time rate 0 ∞ DD t - VDD V fall time rate 20 ∞ DD µs/V V rise time rate 0 ∞ DDA t - VDDA V fall time rate 20 ∞ DDA 6.3.3 Embedded reset and power control block characteristics The parameters given in Table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 22. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit Power on/power down Falling edge(2) 1.80 1.88 1.96(3) V V (1) POR/PDR reset threshold Rising edge 1.84(3) 1.92 2.00 V V PDR hysteresis - - 40 - mV PDRhyst t (4) Reset temporization - 1.50 2.50 4.50 ms RSTTEMPO 1. The PDR detector monitors V and also V (if kept enabled in the option bytes). The POR detector DD DDA monitors only V . DD 2. The product behavior is guaranteed by design down to the minimum V value. POR/PDR 3. Data based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. Table 23. Programmable voltage detector characteristics Symbol Parameter Conditions Min Typ Max Unit Rising edge 2.1 2.18 2.26 V V PVD threshold 0 PVD0 Falling edge 2 2.08 2.16 V Rising edge 2.19 2.28 2.37 V V PVD threshold 1 PVD1 Falling edge 2.09 2.18 2.27 V Rising edge 2.28 2.38 2.48 V V PVD threshold 2 PVD2 Falling edge 2.18 2.28 2.38 V Rising edge 2.38 2.48 2.58 V V PVD threshold 3 PVD3 Falling edge 2.28 2.38 2.48 V Rising edge 2.47 2.58 2.69 V V PVD threshold 4 PVD4 Falling edge 2.37 2.48 2.59 V Rising edge 2.57 2.68 2.79 V V PVD threshold 5 PVD5 Falling edge 2.47 2.58 2.69 V 48/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 23. Programmable voltage detector characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Rising edge 2.66 2.78 2.9 V V PVD threshold 6 PVD6 Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3 V V PVD threshold 7 PVD7 Falling edge 2.66 2.78 2.9 V V (1) PVD hysteresis - - 100 - mV PVDhyst I PVD current consumption - - 0.15 0.26(1) µA DD(PVD) 1. Guaranteed by design, not tested in production. 6.3.4 Embedded reference voltage The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 24. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit V Internal reference voltage –40 °C < T < +105 °C 1.2 1.23 1.25 V REFINT A ADC_IN17 buffer startup t - - - 10(1) µs START time ADC sampling time when tS_vrefint reading the internal - 4(1) - - µs reference voltage Internal reference voltage ∆VREFINT spread over the VDDA = 3 V - - 10(1) mV temperature range TCoeff Temperature coefficient - - 100(1) - 100(1) ppm/°C 1. Guaranteed by design, not tested in production. 6.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. DocID022265 Rev 7 49/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted to the f frequency: HCLK – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz • When the peripherals are enabled f = f PCLK HCLK The parameters given in Table 25 to Table 31 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. T able 25. Typical and maximum current consumption from V at 3.6 V DD All peripherals enabled All peripherals disabled Symbol Parameter Conditions f Max @ T (1) Max @ T (1) Unit HCLK A A Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 48 MHz 22.0 22.8 22.8 23.8 11.8 12.7 12.7 13.3 HSE bypass, 32 MHz 15.0 15.5 15.5 16.0 7.6 8.7 8.7 9.0 PLL on 24 MHz 12.2 13.2 13.2 13.6 7.2 7.9 7.9 8.1 Supply current in HSE 8 MHz 4.4 5.2 5.2 5.4 2.7 2.9 2.9 3.0 Run mode, bypass, code PLL off 1 MHz 1.0 1.3 1.3 1.4 0.7 0.9 0.9 0.9 executing 48 MHz 22.0 22.8 22.8 23.8 11.8 12.7 12.7 13.3 from Flash HSI clock, memory 32 MHz 15.0 15.5 15.5 16.0 7.6 8.7 8.7 9.0 PLL on 24 MHz 12.2 13.2 13.2 13.6 7.2 7.9 7.9 8.1 HSI clock, 8 MHz 4.4 5.2 5.2 5.4 2.7 2.9 2.9 3.0 PLL off I mA DD 48 MHz 22.2 23.2(2) 23.2 24.4(2) 12.0 12.7(2) 12.7 13.3(2) HSE bypass, 32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0 PLL on 24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1 Supply HSE 8 MHz 4.0 4.5 4.5 4.7 1.9 2.9 2.9 3.0 current in bypass, Run mode, PLL off 1 MHz 0.6 0.8 0.8 0.9 0.3 0.6 0.6 0.7 code executing 48 MHz 22.2 23.2 23.2 24.4 12.0 12.7 12.7 13.3 from RAM HSI clock, 32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0 PLL on 24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1 HSI clock, 8 MHz 4.0 4.5 4.5 4.7 1.9 2.9 2.9 3.0 PLL off 50/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 25. Typical and maximum current consumption from V at 3.6 V (continued) DD All peripherals enabled All peripherals disabled Symbol Parameter Conditions f Max @ T (1) Max @ T (1) Unit HCLK A A Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 48 MHz 14.0 15.3(2) 15.3 16.0(2) 2.8 3.0(2) 3.0 3.2(2) HSE bypass, 32 MHz 9.5 10.2 10.2 10.7 2.0 2.1 2.1 2.3 PLL on 24 MHz 7.3 7.8 7.8 8.3 1.5 1.7 1.7 1.9 HSE 8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8 Supply bypass, I current in PLL off 1 MHz 0.4 0.6 0.6 0.6 0.2 0.4 0.4 0.4 mA DD Sleep mode 48 MHz 14.0 15.3 15.3 16.0 3.8 4.0 4.1 4.2 HSI clock, 32 MHz 9.5 10.2 10.2 10.7 2.6 2.7 2.8 2.8 PLL on 24 MHz 7.3 7.8 7.8 8.3 2.0 2.1 2.1 2.1 HSI clock, 8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8 PLL off 1. Data based on characterization results, not tested in production unless otherwise specified. 2. Data based on characterization results and tested in production (using one common test limit for sum of I and I ). DD DDA Ta b le 26. Typical and maximum current consumption from the V supply DDA V =2.4 V V =3.6 V DDA DDA Conditions Symbol Parameter (1) fHCLK Max @ TA(2) Max @ TA(2) Unit Typ Typ 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 48 MHz 150 170(3) 178 182(3) 164 183(3) 195 198(3) HSE bypass, 32 MHz 104 121 126 128 113 129 135 138 Supply PLL on 24 MHz 82 96 100 103 88 102 106 108 current in Run or HSE 8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 Sleep bypass, I mode, PLL off 1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 µA DDA code executing 48 MHz 220 240 248 252 244 263 275 278 from Flash HSI clock, 32 MHz 174 191 196 198 193 209 215 218 memory or PLL on RAM 24 MHz 152 167 173 174 168 183 190 192 HSI clock, 8 MHz 72 79 82 83 83.5 91 94 95 PLL off 1. Current consumption from the V supply is independent of whether the digital peripherals are enabled or disabled, being DDA in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, I is independent of DDA clock frequencies. 2. Data based on characterization results, not tested in production unless otherwise specified. 3. Data based on characterization results and tested in production (using one common test limit for sum of I and I ). DD DDA DocID022265 Rev 7 51/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 27. Typical and maximum current consumption in Stop and Standby modes Typ @V (V = V ) Max(1) DD DD DDA Sym- Para- Conditions Unit bol meter T = T = T = 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V A A A 25 °C 85 °C 105 °C Regulator in run Supply mode, all oscillators 15 15.1 15.3 15.5 15.7 16 (2) (2) current OFF in Stop Regulator in low- mode power mode, all 3.2 3.3 3.4 3.5 3.7 4 (2) (2) I oscillators OFF DD Supply LSI ON and IWDG 0.8 1.0 1.1 1.2 1.4 1.5 - - - current ON in Standby LSI OFF and IWDG 0.7 0.8 0.9 1.0 1.1 1.3 2(2) 2.5 3(2) mode OFF Regulator in run Supply mode, all 1.9 2 2.2 2.3 2.5 2.6 3.5(2) 3.5 4.5(2) current N oscillators OFF O in Stop g Regulator in low- mode orin power mode, all 1.9 2 2.2 2.3 2.5 2.6 3.5(2) 3.5 4.5(2) nit oscillators OFF µA o Supply m LSI ON and A 2.3 2.5 2.7 2.9 3.1 3.3 - - - current D IWDG ON D in V Standby LSI OFF and 1.8 1.9 2 2.2 2.3 2.5 3.5(2) 3.5 4.5(2) mode IWDG OFF I DDA Regulator in run Supply mode, all 1.1 1.2 1.2 1.2 1.3 1.4 - - - current F oscillators OFF F in Stop g O Regulator in low- mode n power mode, all 1.1 1.2 1.2 1.2 1.3 1.4 - - - nitori oscillators OFF o Supply m LSI ON and current A IWDG ON 1.5 1.6 1.7 1.8 1.9 2.0 - - - D in VD Standby LSI OFF and 1 1.0 1.1 1.1 1.2 1.2 - - - mode IWDG OFF 1. Data based on characterization results, not tested in production unless otherwise specified. 2. Data based on characterization results and tested in production (using one common test limit for sum of I and I ). DD DDA 52/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 28. Typical and maximum current consumption from the V supply BAT Typ @ V Max(1) BAT Symbol Parameter Conditions 1.65 V 1.8 V 2.4 V 2.7 V 3.3 V 3.6 V 2T5A °=C 8T5A ° =C 1T0A5 °=C Unit LSE & RTC ON; “Xtal mode”: lower driving 0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.3 1.7 RTC capability; domain LSEDRV[1:0] = '00' I _ µA DD VBAT supply LSE & RTC ON; “Xtal current mode” higher driving 0.8 0.8 0.9 1.0 1.1 1.2 1.3 1.6 2.1 capability; LSEDRV[1:0] = '11' 1. Data based on characterization results, not tested in production. Typical current consumption The MCU is placed under the following conditions: • V = V = 3.3 V DD DDA • All I/O pins are in analog input configuration • The Flash memory access time is adjusted to f frequency: HCLK – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz • When the peripherals are enabled, f = f PCLK HCLK • PLL is used for frequencies greater than 8 MHz • AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and 500 kHz respectively DocID022265 Rev 7 53/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 29. Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal Typical consumption in Typical consumption in Run mode Sleep mode Symbol Parameter f Unit HCLK Peripherals Peripherals Peripherals Peripherals enabled disabled enabled disabled 48 MHz 23.2 13.3 13.2 3.1 36 MHz 17.6 10.3 10.1 2.6 32 MHz 15.6 9.3 9.0 2.4 24 MHz 12.1 7.4 7.0 2.0 Current consumption 16 MHz 8.4 5.1 5.0 1.6 I mA DD from V DD 8 MHz 4.5 3.0 2.8 1.1 supply 4 MHz 2.8 2.0 2.0 1.1 2 MHz 1.9 1.5 1.5 1.0 1 MHz 1.5 1.3 1.3 1.0 500 kHz 1.2 1.2 1.1 1.0 48 MHz 151 36 MHz 113 32 MHz 101 24 MHz 79 Current consumption 16 MHz 57 I μA DDA from VDDA 8 MHz 2.2 supply 4 MHz 2.2 2 MHz 2.2 1 MHz 2.2 500 kHz 2.2 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 48: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt 54/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 31: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I = V × f × C SW DDIOx SW where I is the current sunk by a switching I/O to charge/discharge the capacitive load SW V is the I/O supply voltage DDIOx f is the I/O switching frequency SW C is the total capacitance seen by the I/O pin: C = C + C + C INT EXT S C is the PCB board capacitance including the pad pin. S The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID022265 Rev 7 55/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 30. Switching output I/O current consumption I/O toggling Symbol Parameter Conditions(1) Typ Unit frequency (f ) SW 4 MHz 0.07 8 MHz 0.15 V = 3.3 V DDIOx C =C 16 MHz 0.31 INT 24 MHz 0.53 48 MHz 0.92 4 MHz 0.18 8 MHz 0.37 V = 3.3 V DDIOx C = 0 pF 16 MHz 0.76 EXT C = C + C + C INT EXT S 24 MHz 1.39 48 MHz 2.188 4 MHz 0.32 8 MHz 0.64 V = 3.3 V DDIOx C = 10 pF 16 MHz 1.25 EXT C = C + C + C INT EXT S 24 MHz 2.23 I/O current 48 MHz 4.442 I mA SW consumption 4 MHz 0.49 V = 3.3 V DDIOx 8 MHz 0.94 C = 22 pF EXT 16 MHz 2.38 C = C + C + C INT EXT S 24 MHz 3.99 4 MHz 0.64 V = 3.3 V DDIOx 8 MHz 1.25 C = 33 pF EXT 16 MHz 3.24 C = C + C + C INT EXT S 24 MHz 5.02 V = 3.3 V 4 MHz 0.81 DDIOx C = 47 pF EXT 8 MHz 1.7 C = C + C + C INT EXT S C = C 16 MHz 3.67 int 4 MHz 0.66 V = 2.4 V DDIOx C = 47 pF 8 MHz 1.43 EXT C = CINT + CEXT+ CS 16 MHz 2.45 C = C int 24 MHz 4.97 1. C = 7 pF (estimated value). S 56/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 31. The MCU is placed under the following conditions: • All I/O pins are in analog mode • All peripherals are disabled unless otherwise mentioned • The given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on • Ambient operating temperature and supply voltage conditions summarized in Table 17: Voltage characteristics Table 31. Peripheral current consumption Peripheral Typical consumption at 25 °C Unit BusMatrix(1) 5 DMA1 7 SRAM 1 Flash memory interface 14 CRC 2 GPIOA 9 AHB µA/MHz GPIOB 12 GPIOC 2 GPIOD 1 GPIOF 1 TSC 6 All AHB peripherals 55 DocID022265 Rev 7 57/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 31. Peripheral current consumption (continued) Peripheral Typical consumption at 25 °C Unit APB-Bridge(2) 3 SYSCFG 3 ADC(3) 5 TIM1 17 SPI1 10 USART1 19 TIM15 11 TIM16 8 TIM17 8 DBG (MCU Debug Support) 0.5 TIM2 17 APB TIM3 13 µA/MHz TIM6 3 TIM14 6 WWDG 1 SPI2 7 USART2 7 I2C1 4 I2C2 5 DAC 2 PWR 1 CEC 2 All APB peripherals 149 1. The BusMatrix automatically is active when at least one master is ON (CPU or DMA1) 2. The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus. 3. The power consumption of the analog part (I ) of peripherals such as ADC is not included. Refer to the DDA tables of characteristics in the subsequent sections. 58/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics 6.3.6 Wakeup time from low-power mode The wakeup times given in Table 32 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture. The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz. The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode. The wakeup source from Standby mode is the WKUP1 pin (PA0). All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 32. Low-power mode wakeup timings Typ @VDD = VDDA Symbol Parameter Conditions Max Unit = 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V Regulator in run 3.2 3.1 2.9 2.9 2.8 5 Wakeup from Stop mode t WUSTOP mode Regulator in low 7.0 5.8 5.2 4.9 4.6 9 power mode µs Wakeup from t - 60.4 55.6 53.5 52 51 - WUSTANDBY Standby mode Wakeup from Sleep t - 4 SYSCLK cycles - WUSLEEP mode 6.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15: High-speed external clock source AC timing diagram. Table 33. High-speed external user clock characteristics Symbol Parameter(1) Min Typ Max Unit f User external clock source frequency - 8 32 MHz HSE_ext V OSC_IN input pin high level voltage 0.7 V - V HSEH DDIOx DDIOx V V OSC_IN input pin low level voltage V - 0.3 V HSEL SS DDIOx t w(HSEH) OSC_IN high or low time 15 - - t w(HSEL) ns t r(HSE) OSC_IN rise or fall time - - 20 t f(HSE) DocID022265 Rev 7 59/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 1. Guaranteed by design, not tested in production. Figure 15. High-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:43)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:43)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:43)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:43)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:43)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:23)(cid:57)(cid:21) Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 16. Table 34. Low-speed external user clock characteristics Symbol Parameter(1) Min Typ Max Unit f User external clock source frequency - 32.768 1000 kHz LSE_ext V OSC32_IN input pin high level voltage 0.7 V - V LSEH DDIOx DDIOx V V OSC32_IN input pin low level voltage V - 0.3 V LSEL SS DDIOx t w(LSEH) OSC32_IN high or low time 450 - - t w(LSEL) ns t r(LSE) OSC32_IN rise or fall time - - 50 t f(LSE) 1. Guaranteed by design, not tested in production. Figure 16. Low-speed external clock source AC timing diagram (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:43)(cid:12) (cid:57)(cid:47)(cid:54)(cid:40)(cid:43) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:57)(cid:47)(cid:54)(cid:40)(cid:47) (cid:87)(cid:85)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:73)(cid:11)(cid:47)(cid:54)(cid:40)(cid:12) (cid:87)(cid:90)(cid:11)(cid:47)(cid:54)(cid:40)(cid:47)(cid:12) (cid:87) (cid:55)(cid:47)(cid:54)(cid:40) (cid:48)(cid:54)(cid:20)(cid:28)(cid:21)(cid:20)(cid:24)(cid:57)(cid:21) 60/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 35. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 35. HSE oscillator characteristics Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit f Oscillator frequency - 4 8 32 MHz OSC_IN R Feedback resistor - - 200 - kΩ F During startup(3) - - 8.5 V = 3.3 V, DD Rm = 30 Ω, - 0.4 - CL = 10 pF@8 MHz V = 3.3 V, DD Rm = 45 Ω, - 0.5 - CL = 10 pF@8 MHz IDD HSE current consumption VDD = 3.3 V, mA Rm = 30 Ω, - 0.8 - CL = 5 pF@32 MHz V = 3.3 V, DD Rm = 30 Ω, - 1 - CL = 10 pF@32 MHz V = 3.3 V, DD Rm = 30 Ω, - 1.5 - CL = 20 pF@32 MHz g Oscillator transconductance Startup 10 - - mA/V m t (4) Startup time V is stabilized - 2 - ms SU(HSE) DD 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design, not tested in production. 3. This consumption level occurs during the first 2/3 of the t startup time SU(HSE) 4. t is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz SU(HSE) oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C and C , it is recommended to use high-quality external ceramic capacitors in the L1 L2 5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17). C and C are usually the L1 L2 same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C . PCB and MCU pin capacitance must be included (10 pF L1 L2 can be used as a rough estimate of the combined pin and board capacitance) when sizing C and C . L1 L2 Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. DocID022265 Rev 7 61/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 17. Typical application with an 8 MHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3) (cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38) (cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:66)(cid:44)(cid:49) (cid:73) (cid:43)(cid:54)(cid:40) (cid:37)(cid:76)(cid:68)(cid:86)(cid:3) (cid:27)(cid:3)(cid:48)(cid:43)(cid:93)(cid:3) (cid:70)(cid:82)(cid:81)(cid:87)(cid:85)(cid:82)(cid:79)(cid:79)(cid:72)(cid:71)(cid:3) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:53)(cid:41) (cid:74)(cid:68)(cid:76)(cid:81) (cid:53) (cid:11)(cid:20)(cid:12) (cid:50)(cid:54)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55) (cid:40)(cid:59)(cid:55) (cid:38) (cid:47)(cid:21) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:26)(cid:25)(cid:57)(cid:20) 1. R value depends on the crystal characteristics. EXT Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 36. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 36. LSE oscillator characteristics (f = 32.768 kHz) LSE Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit low drive capability - 0.5 0.9 medium-low drive capability - - 1 I LSE current consumption µA DD medium-high drive capability - - 1.3 high drive capability - - 1.6 low drive capability 5 - - medium-low drive capability 8 - - Oscillator g µA/V m transconductance medium-high drive capability 15 - - high drive capability 25 - - t (3) Startup time V is stabilized - 2 - s SU(LSE) DDIOx 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. Guaranteed by design, not tested in production. 3. t is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is SU(LSE) reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 62/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 18. Typical application with a 32.768 kHz crystal (cid:53)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3) (cid:70)(cid:68)(cid:83)(cid:68)(cid:70)(cid:76)(cid:87)(cid:82)(cid:85)(cid:86) (cid:38) (cid:47)(cid:20) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:44)(cid:49) (cid:73) (cid:47)(cid:54)(cid:40) (cid:39)(cid:85)(cid:76)(cid:89)(cid:72)(cid:3) (cid:22)(cid:21)(cid:17)(cid:26)(cid:25)(cid:27)(cid:3)(cid:78)(cid:43)(cid:93)(cid:3) (cid:83)(cid:85)(cid:82)(cid:74)(cid:85)(cid:68)(cid:80)(cid:80)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3) (cid:85)(cid:72)(cid:86)(cid:82)(cid:81)(cid:68)(cid:87)(cid:82)(cid:85) (cid:68)(cid:80)(cid:83)(cid:79)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:50)(cid:54)(cid:38)(cid:22)(cid:21)(cid:66)(cid:50)(cid:56)(cid:55) (cid:38) (cid:47)(cid:21) (cid:48)(cid:54)(cid:22)(cid:19)(cid:21)(cid:24)(cid:22)(cid:57)(cid:21) Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.8 Internal clock source characteristics The parameters given in Table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. The provided curves are characterization results, not tested in production. DocID022265 Rev 7 63/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 High-speed internal (HSI) RC oscillator Table 37. HSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit f Frequency - - 8 - MHz HSI TRIM HSI user trimming step - - - 1(2) % DuCy Duty cycle - 45(2) - 55(2) % (HSI) T = -40 to 105°C -2.8(3) - 3.8(3) A T = -10 to 85°C -1.9(3) - 2.3(3) A Accuracy of the HSI TA = 0 to 85°C -1.9(3) - 2(3) ACC % HSI oscillator T = 0 to 70°C -1.3(3) - 2(3) A T = 0 to 55°C -1(3) - 2(3) A T = 25°C(4) -1 - 1 A t HSI oscillator startup time - 1(2) - 2(2) µs su(HSI) HSI oscillator power I - - 80 100(2) µA DDA(HSI) consumption 1. V = 3.3 V, T = -40 to 105°C unless otherwise specified. DDA A 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. 4. Factory calibrated, parts not soldered. Figure 19. HSI oscillator accuracy characterization results for soldered parts (cid:21)(cid:6) (cid:46)(cid:34)(cid:57) (cid:46)(cid:42)(cid:47) (cid:20)(cid:6) (cid:19)(cid:6) (cid:18)(cid:6) (cid:17)(cid:6) (cid:53)(cid:34)(cid:1)(cid:1)(cid:1)(cid:60)(cid:1)(cid:143)(cid:36)(cid:62) (cid:14)(cid:21)(cid:17) (cid:14)(cid:19)(cid:17) (cid:17) (cid:19)(cid:17) (cid:21)(cid:17) (cid:23)(cid:17) (cid:25)(cid:17) (cid:18)(cid:17)(cid:17) (cid:18)(cid:19)(cid:17) (cid:14)(cid:18)(cid:6) (cid:14)(cid:19)(cid:6) (cid:14)(cid:20)(cid:6) (cid:14)(cid:21)(cid:6) (cid:48)(cid:54)(cid:22)(cid:19)(cid:28)(cid:27)(cid:24)(cid:57)(cid:23) 64/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 38. HSI14 oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit f Frequency - - 14 - MHz HSI14 TRIM HSI14 user-trimming step - - - 1(2) % DuCy Duty cycle - 45(2) - 55(2) % (HSI14) T = –40 to 105 °C –4.2(3) - 5.1(3) % A Accuracy of the HSI14 TA = –10 to 85 °C –3.2(3) - 3.1(3) % ACC HSI14 oscillator (factory calibrated) T = 0 to 70 °C –2.5(3) - 2.3(3) % A T = 25 °C –1 - 1 % A t HSI14 oscillator startup time - 1(2) - 2(2) µs su(HSI14) HSI14 oscillator power I - - 100 150(2) µA DDA(HSI14) consumption 1. V = 3.3 V, T = –40 to 105 °C unless otherwise specified. DDA A 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 20. HSI14 oscillator accuracy characterization results (cid:24)(cid:8) (cid:48)(cid:36)(cid:59) (cid:48)(cid:44)(cid:49) (cid:23)(cid:8) (cid:22)(cid:8) (cid:21)(cid:8) (cid:20)(cid:8) (cid:55)(cid:3)(cid:3)(cid:62)(cid:131)(cid:38)(cid:64) (cid:19)(cid:8) (cid:36) (cid:16)(cid:23)(cid:19) (cid:16)(cid:21)(cid:19) (cid:19) (cid:21)(cid:19) (cid:23)(cid:19) (cid:25)(cid:19) (cid:27)(cid:19) (cid:20)(cid:19)(cid:19) (cid:20)(cid:21)(cid:19) (cid:16)(cid:20)(cid:8) (cid:16)(cid:21)(cid:8) (cid:16)(cid:22)(cid:8) (cid:16)(cid:23)(cid:8) (cid:16)(cid:24)(cid:8) (cid:48)(cid:54)(cid:22)(cid:19)(cid:28)(cid:27)(cid:25)(cid:57)(cid:21) DocID022265 Rev 7 65/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Low-speed internal (LSI) RC oscillator Table 39. LSI oscillator characteristics(1) Symbol Parameter Min Typ Max Unit f Frequency 30 40 50 kHz LSI t (2) LSI oscillator startup time - - 85 µs su(LSI) I (2) LSI oscillator power consumption - 0.75 1.2 µA DDA(LSI) 1. V = 3.3 V, T = –40 to 105 °C unless otherwise specified. DDA A 2. Guaranteed by design, not tested in production. 6.3.9 PLL characteristics The parameters given in Table 40 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 40. PLL characteristics Value Symbol Parameter Unit Min Typ Max PLL input clock(1) 1(2) 8.0 24(2) MHz f PLL_IN PLL input clock duty cycle 40(2) - 60(2) % f PLL multiplier output clock 16(2) - 48 MHz PLL_OUT t PLL lock time - - 200(2) µs LOCK Jitter Cycle-to-cycle jitter - - 300(2) ps PLL 1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by f . PLL_OUT 2. Guaranteed by design, not tested in production. 6.3.10 Memory characteristics Flash memory The characteristics are given at T = –40 to 105 °C unless otherwise specified. A Table 41. Flash memory characteristics Symbol Parameter Conditions Min Typ Max(1) Unit t 16-bit programming time T = - 40 to +105 °C 40 53.5 60 µs prog A t Page (1 KB) erase time T = - 40 to +105 °C 20 - 40 ms ERASE A t Mass erase time T = - 40 to +105 °C 20 - 40 ms ME A Write mode - - 10 mA I Supply current DD Erase mode - - 12 mA 1. Guaranteed by design, not tested in production. 66/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 42. Flash memory endurance and data retention Symbol Parameter Conditions Min(1) Unit N Endurance T = –40 to +105 °C 10 kcycle END A 1 kcycle(2) at T = 85 °C 30 A t Data retention 1 kcycle(2) at T = 105 °C 10 Year RET A 10 kcycle(2) at T = 55 °C 20 A 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and DD V through a 100 pF capacitor, until a functional disturbance occurs. This test is SS compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 43. They are based on the EMS levels and classes defined in application note AN1709. Table 43. EMS characteristics Level/ Symbol Parameter Conditions Class V = 3.3 V, LQFP64, T = +25 °C, Voltage limits to be applied on any I/O pin DD A V f = 48 MHz, 2B FESD to induce a functional disturbance HCLK conforming to IEC 61000-4-2 Fast transient voltage burst limits to be V = 3.3 V, LQFP64, T = +25°C, DD A V applied through 100 pF on V and V f = 48 MHz, 4B EFTB DD SS HCLK pins to induce a functional disturbance conforming to IEC 61000-4-4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. DocID022265 Rev 7 67/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 44. EMI characteristics Max vs. [f /f ] Monitored HSE HCLK Symbol Parameter Conditions Unit frequency band 8/48 MHz 0.1 to 30 MHz -3 V = 3.6 V, T = 25 °C, DD A LQFP64 package 30 to 130 MHz 28 dBµV S Peak level EMI compliant with 130 MHz to 1 GHz 23 IEC 61967-2 EMI Level 4 - 6.3.12 Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. 68/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 45. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Packages Class Unit value(1) Electrostatic discharge voltage T = +25 °C, conforming V A All 2 2000 V ESD(HBM) (human body model) to JESD22-A114 Electrostatic discharge voltage T = +25 °C, conforming V A All C3 250 V ESD(CDM) (charge device model) to ANSI/ESD STM5.3.1 1. Data based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 46. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +105 °C conforming to JESD78A II level A A 6.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V or SS above V (for standard, 3.3 V-capable I/O pins) should be avoided during normal DDIOx product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 47. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. DocID022265 Rev 7 69/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 47. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on BOOT0 –0 NA Injected current on PA10, PA12, PB4, PB5, PB10, PB15 and PD2 pins with induced leakage current on adjacent pins less –5 NA than –10 µA I mA INJ Injected current on all other FT and FTf pins –5 NA Injected current on PA6 and PC0 –0 +5 Injected current on all other TTa, TC and RST pins –5 +5 6.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 20: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 48. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit TC and TTa I/O - - 0.3 V +0.07(1) DDIOx FT and FTf I/O - - 0.475 V –0.2(1) DDIOx Low level input VIL voltage BOOT0 - - 0.3 VDDIOx–0.3(1) V All I/Os except - - 0.3 V BOOT0 pin DDIOx TC and TTa I/O 0.445 V +0.398(1) - - DDIOx FT and FTf I/O 0.5 V +0.2(1) - - DDIOx High level input VIH voltage BOOT0 0.2 VDDIOx+0.95(1) - - V All I/Os except 0.7 V - - BOOT0 pin DDIOx TC and TTa I/O - 200(1) - Schmitt trigger Vhys hysteresis FT and FTf I/O - 100(1) - mV BOOT0 - 300(1) - 70/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 48. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit TC, FT and FTf I/O TTa in digital mode - - ± 0.1 V ≤ V ≤ V SS IN DDIOx TTa in digital mode Ilkg Icnupruret nlet(a2)kage VDDIOx ≤ VIN ≤ VDDA - - 1 µA TTa in analog mode - - ± 0.2 V ≤ V ≤ V SS IN DDA FT and FTf I/O - - 10 V ≤ V ≤ 5 V DDIOx IN Weak pull-up RPU equivalent resistor VIN = VSS 25 40 55 kΩ (3) Weak pull-down R equivalent V = - V 25 40 55 kΩ PD IN DDIOx resistor(3) C I/O pin capacitance - - 5 - pF IO 1. Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection susceptibility. 3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 21 for standard I/Os, and in Figure 22 for 5 V-tolerant I/Os. The following curves are design simulation results, not tested in production. DocID022265 Rev 7 71/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 21. TC and TTa I/O input characteristics (cid:22) (cid:21)(cid:17)(cid:24) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:49)(cid:3)(cid:11)(cid:57)(cid:12)(cid:21) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:20)(cid:17)(cid:24) (cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:26)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81) (cid:14)(cid:3)(cid:19)(cid:17)(cid:22)(cid:28)(cid:27) (cid:56)(cid:49)(cid:39)(cid:40)(cid:41)(cid:44)(cid:49)(cid:40)(cid:39)(cid:3)(cid:44)(cid:49)(cid:51)(cid:56)(cid:55)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81)(cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:23)(cid:23)(cid:24)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91)(cid:3) (cid:20) (cid:19)(cid:17)(cid:24) (cid:57)(cid:57)(cid:44)(cid:47)(cid:44)(cid:47)(cid:80)(cid:80)(cid:68)(cid:68)(cid:91)(cid:91)(cid:3)(cid:3)(cid:32)(cid:32)(cid:3)(cid:3)(cid:19)(cid:19)(cid:17)(cid:17)(cid:22)(cid:22)(cid:3)(cid:3)(cid:57)(cid:57)(cid:39)(cid:39)(cid:39)(cid:39)(cid:44)(cid:50)(cid:44)(cid:50)(cid:91)(cid:91)(cid:3)(cid:14)(cid:3)(cid:3)(cid:3)(cid:3)(cid:19)(cid:3)(cid:3)(cid:17)(cid:3)(cid:19)(cid:3)(cid:3)(cid:26)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:19) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:19) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22)(cid:17)(cid:19) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57) (cid:3)(cid:11)(cid:57)(cid:12) (cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:19)(cid:57)(cid:23) Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics (cid:22) (cid:21)(cid:17)(cid:24) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:57)(cid:44)(cid:49)(cid:3)(cid:11)(cid:57)(cid:12)(cid:21) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:20)(cid:17)(cid:24) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81)(cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:26)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:56)(cid:49)(cid:39)(cid:40)(cid:41)(cid:44)(cid:49)(cid:40)(cid:39)(cid:3)(cid:44)(cid:49)(cid:51)(cid:56)(cid:55)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:14)(cid:3)(cid:19)(cid:17)(cid:21) (cid:3)(cid:32)(cid:3)(cid:19)(cid:17)(cid:24)(cid:3)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:91)(cid:3) (cid:20) (cid:57)(cid:44)(cid:43)(cid:80)(cid:76)(cid:81) (cid:16)(cid:3)(cid:19)(cid:17)(cid:21) (cid:19)(cid:17)(cid:24) (cid:57)(cid:57)(cid:44)(cid:44)(cid:47)(cid:47)(cid:80)(cid:80)(cid:68)(cid:68)(cid:91)(cid:91)(cid:3)(cid:3)(cid:32)(cid:32)(cid:3)(cid:3)(cid:19)(cid:19)(cid:17)(cid:17)(cid:23)(cid:22)(cid:26)(cid:3)(cid:57)(cid:24)(cid:3)(cid:39)(cid:57)(cid:39)(cid:39)(cid:44)(cid:50)(cid:39)(cid:91)(cid:44)(cid:3)(cid:50)(cid:3)(cid:91)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:11)(cid:38)(cid:48)(cid:50)(cid:54)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:12) (cid:55)(cid:55)(cid:47)(cid:3)(cid:86)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:85)(cid:72)(cid:84)(cid:88)(cid:76)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:55)(cid:40)(cid:54)(cid:55)(cid:40)(cid:39)(cid:3)(cid:53)(cid:36)(cid:49)(cid:42)(cid:40) (cid:19) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:19) (cid:21)(cid:17)(cid:21) (cid:21)(cid:17)(cid:23) (cid:21)(cid:17)(cid:25) (cid:21)(cid:17)(cid:27) (cid:22)(cid:17)(cid:19) (cid:22)(cid:17)(cid:21) (cid:22)(cid:17)(cid:23) (cid:22)(cid:17)(cid:25) (cid:57) (cid:3)(cid:11)(cid:57)(cid:12) (cid:39)(cid:39)(cid:44)(cid:50)(cid:91) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:22)(cid:20)(cid:57)(cid:23) 72/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V /V ). OL OH In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on V , plus the maximum DDIOx consumption of the MCU sourced on V , cannot exceed the absolute maximum rating DD ΣI (see Table 17: Voltage characteristics). VDD • The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of SS the MCU sunk on V , cannot exceed the absolute maximum rating ΣI (see SS VSS Table 17: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified). Table 49. Output voltage characteristics(1) Symbol Parameter Conditions Min Max Unit V Output low level voltage for an I/O pin CMOS port(2) - 0.4 OL |I | = 8 mA V IO VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–0.4 - V Output low level voltage for an I/O pin TTL port(2) - 0.4 OL |I | = 8 mA V IO VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V 2.4 - VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3 V VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–1.3 - V (3) Output low level voltage for an I/O pin - 0.4 OL |I | = 6 mA V V (3) Output high level voltage for an I/O pin IO V –0.4 - OH DDIOx |I | = 20 mA VOLFm+(3) OFmut+p umt olodwe level voltage for an FTf I/O pin in VDIODIOx ≥ 2.7 V - 0.4 V |I | = 10 mA - 0.4 V IO 1. The I current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17: IO Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Data based on characterization results. Not tested in production. DocID022265 Rev 7 73/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 50, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 50. I/O AC characteristics(1)(2) OSPEEDRy [1:0] Symbol Parameter Conditions Min Max Unit value(1) f Maximum frequency(3) - 2 MHz max(IO)out x0 t Output fall time C = 50 pF - 125 f(IO)out L ns t Output rise time - 125 r(IO)out f Maximum frequency(3) - 10 MHz max(IO)out 01 t Output fall time C = 50 pF - 25 f(IO)out L ns t Output rise time - 25 r(IO)out C = 30 pF, V ≥ 2.7 V - 50 L DDIOx f Maximum frequency(3) C = 50 pF, V ≥ 2.7 V - 30 MHz max(IO)out L DDIOx C = 50 pF, V < 2.7 V - 20 L DDIOx C = 30 pF, V ≥ 2.7 V - 5 L DDIOx 11 t Output fall time C = 50 pF, V ≥ 2.7 V - 8 f(IO)out L DDIOx C = 50 pF, V < 2.7 V - 12 L DDIOx ns C = 30 pF, V ≥ 2.7 V - 5 L DDIOx t Output rise time C = 50 pF, V ≥ 2.7 V - 8 r(IO)out L DDIOx C = 50 pF, V < 2.7 V - 12 L DDIOx f Maximum frequency(3) - 2 MHz Fm+ max(IO)out configuration t Output fall time C = 50 pF - 12 f(IO)out L (4) ns t Output rise time - 34 r(IO)out Pulse width of external - t signals detected by - 10 - ns EXTIpw the EXTI controller 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design, not tested in production. 3. The maximum frequency is defined in Figure 23. 4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration. 74/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 23. I/O AC characteristics definition (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:24)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:28)(cid:19)(cid:8) (cid:87)(cid:85)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:87)(cid:73)(cid:11)(cid:44)(cid:50)(cid:12)(cid:82)(cid:88)(cid:87) (cid:55) (cid:48)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:76)(cid:86)(cid:3)(cid:68)(cid:70)(cid:75)(cid:76)(cid:72)(cid:89)(cid:72)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:11)(cid:87)(cid:3)(cid:3)(cid:14)(cid:3)(cid:87)(cid:3)(cid:3)(cid:12)(cid:3)(cid:148)(cid:3)(cid:21) (cid:55)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:73)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:71)(cid:88)(cid:87)(cid:92)(cid:3)(cid:70)(cid:92)(cid:70)(cid:79)(cid:72)(cid:3)(cid:76)(cid:86)(cid:3)(cid:11)(cid:23)(cid:24)(cid:16)(cid:24)(cid:24)(cid:8)(cid:12) (cid:85) (cid:73) (cid:22) (cid:90)(cid:75)(cid:72)(cid:81)(cid:3)(cid:79)(cid:82)(cid:68)(cid:71)(cid:72)(cid:71)(cid:3)(cid:69)(cid:92)(cid:3)(cid:38)(cid:45)(cid:3)(cid:3)(cid:11)(cid:86)(cid:72)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:87)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:44)(cid:18)(cid:50)(cid:3)(cid:36)(cid:38)(cid:3)(cid:70)(cid:75)(cid:68)(cid:85)(cid:68)(cid:70)(cid:87)(cid:72)(cid:85)(cid:76)(cid:86)(cid:87)(cid:76)(cid:70)(cid:86)(cid:3)(cid:71)(cid:72)(cid:73)(cid:76)(cid:81)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:12) (cid:48)(cid:54)(cid:22)(cid:21)(cid:20)(cid:22)(cid:21)(cid:57)(cid:22) 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull- up resistor, R . PU Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 51. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit V NRST input low level voltage - - - 0.3 V +0.07(1) IL(NRST) DD V V NRST input high level voltage - 0.445 V +0.398(1) - - IH(NRST) DD NRST Schmitt trigger voltage V - - 200 - mV hys(NRST) hysteresis Weak pull-up equivalent RPU resistor(2) VIN = VSS 25 40 55 kΩ V NRST input filtered pulse - - - 100(1) ns F(NRST) 2.7 < V < 3.6 300(3) - - DD V NRST input not filtered pulse ns NF(NRST) 2.0 < V < 3.6 500(3) - - DD 1. Data based on design simulation only. Not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 3. Data based on design simulation only. Not tested in production. DocID022265 Rev 7 75/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 24. Recommended NRST pin protection (cid:40)(cid:91)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:70)(cid:76)(cid:85)(cid:70)(cid:88)(cid:76)(cid:87)(cid:11)(cid:20)(cid:12) (cid:57)(cid:39)(cid:39) (cid:53)(cid:51)(cid:56) (cid:49)(cid:53)(cid:54)(cid:55)(cid:11)(cid:21)(cid:12) (cid:44)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87) (cid:41)(cid:76)(cid:79)(cid:87)(cid:72)(cid:85) (cid:19)(cid:17)(cid:20)(cid:3)(cid:151)(cid:41) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:26)(cid:27)(cid:57)(cid:22) 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table 51: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 6.3.16 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the conditions summarized in Table 20: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 52. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Analog supply voltage for V - 2.4 - 3.6 V DDA ADC ON Current consumption of I V = 3.3 V - 0.9 - mA DDA (ADC) the ADC(1) DDA f ADC clock frequency - 0.6 - 14 MHz ADC f (2) Sampling rate 12-bit resolution 0.043 - 1 MHz S f = 14 MHz, ADC - - 823 kHz f (2) External trigger frequency 12-bit resolution TRIG 12-bit resolution - - 17 1/f ADC VAIN Conversion voltage range - 0 - VDDA V See Equation 1 and R (2) External input impedance - - 50 kΩ AIN Table 53 for details Sampling switch R (2) - - - 1 kΩ ADC resistance Internal sample and hold C (2) - - - 8 pF ADC capacitor f = 14 MHz 5.9 µs ADC t (2)(3) Calibration time CAL - 83 1/f ADC 76/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 52. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 1.5 ADC 1.5 ADC ADC clock = HSI14 cycles + 2 - cycles + 3 - fPCLK cycles fPCLK cycles ADC_DR register ready W (2)(4) f LATENCY latency ADC clock = PCLK/2 - 4.5 - PCLK cycle f ADC clock = PCLK/4 - 8.5 - PCLK cycle f = f /2 = 14 MHz 0.196 µs ADC PCLK f = f /2 5.5 1/f ADC PCLK PCLK t (2) Trigger conversion latency f = f /4 = 12 MHz 0.219 µs latr ADC PCLK f = f /4 10.5 1/f ADC PCLK PCLK f = f = 14 MHz 0.179 - 0.250 µs ADC HSI14 ADC jitter on trigger JitterADC conversion fADC = fHSI14 - 1 - 1/fHSI14 f = 14 MHz 0.107 - 17.1 µs ADC t (2) Sampling time S - 1.5 - 239.5 1/f ADC t (2) Stabilization time - 14 1/f STAB ADC f = 14 MHz, ADC 1 - 18 µs Total conversion time 12-bit resolution t (2) CONV (including sampling time) 14 to 252 (t for sampling +12.5 for 12-bit resolution S 1/f successive approximation) ADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I and 60 µA DDA on I should be taken into account. DD 2. Guaranteed by design, not tested in production. 3. Specified value includes only ADC timing. It does not include the latency of the register access. 4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time. Equation 1: R max formula AIN T R <---------------------------------S-------------------------------–R AIN f × C × ln(2N+2) ADC ADC ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 53. R max for f = 14 MHz AIN ADC T (cycles) t (µs) R max (kΩ)(1) s S AIN 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 DocID022265 Rev 7 77/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 53. R max for f = 14 MHz (continued) AIN ADC T (cycles) t (µs) R max (kΩ)(1) s S AIN 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 54. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) Unit ET Total unadjusted error ±1.3 ±2 EO Offset error fPCLK = 48 MHz, ±1 ±1.5 f = 14 MHz, R < 10 kΩ ADC AIN EG Gain error ±0.5 ±1.5 LSB V = 3 V to 3.6 V DDA ED Differential linearity error T = 25 °C ±0.7 ±1 A EL Integral linearity error ±0.8 ±1.5 ET Total unadjusted error ±3.3 ±4 EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8 f = 14 MHz, R < 10 kΩ ADC AIN EG Gain error ±2.8 ±3 LSB V = 2.7 V to 3.6 V DDA ED Differential linearity error T = - 40 to 105 °C ±0.7 ±1.3 A EL Integral linearity error ±1.2 ±1.7 ET Total unadjusted error ±3.3 ±4 EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8 f = 14 MHz, R < 10 kΩ ADC AIN EG Gain error ±2.8 ±3 LSB V = 2.4 V to 3.6 V DDA ED Differential linearity error T = 25 °C ±0.7 ±1.3 A EL Integral linearity error ±1.2 ±1.7 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I and ΣI in Section 6.3.14 does not affect the ADC INJ(PIN) INJ(PIN) accuracy. 3. Better performance may be achieved in restricted V , frequency and temperature ranges. DDA 4. Data based on characterization results, not tested in production. 78/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 25. ADC accuracy characteristics (cid:57)(cid:54)(cid:54)(cid:36) (cid:40)(cid:42) (cid:11)(cid:20)(cid:12)(cid:3)(cid:40)(cid:91)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:82)(cid:73)(cid:3)(cid:68)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:24) (cid:11)(cid:21)(cid:12)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72) (cid:23)(cid:19)(cid:28)(cid:23) (cid:11)(cid:22)(cid:12)(cid:3)(cid:40)(cid:81)(cid:71)(cid:3)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72) (cid:23)(cid:19)(cid:28)(cid:22) (cid:40)(cid:55)(cid:3)(cid:32)(cid:3)(cid:55)(cid:82)(cid:87)(cid:68)(cid:79)(cid:3)(cid:56)(cid:81)(cid:68)(cid:77)(cid:88)(cid:86)(cid:87)(cid:72)(cid:71)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:11)(cid:21)(cid:12) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:73)(cid:72)(cid:85)(cid:3)(cid:70)(cid:88)(cid:85)(cid:89)(cid:72)(cid:86)(cid:17) (cid:40)(cid:55) (cid:11)(cid:22)(cid:12) (cid:40)(cid:50)(cid:3)(cid:32)(cid:3)(cid:50)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:26) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:76)(cid:85)(cid:86)(cid:87) (cid:11)(cid:20)(cid:12) (cid:25) (cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:40)(cid:42)(cid:3)(cid:32)(cid:3)(cid:42)(cid:68)(cid:76)(cid:81)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3) (cid:24) (cid:40)(cid:50) (cid:40)(cid:47) (cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:68)(cid:86)(cid:87)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:17) (cid:23) (cid:40)(cid:39)(cid:3)(cid:32)(cid:3)(cid:39)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:87)(cid:76)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3) (cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:86)(cid:87)(cid:72)(cid:83)(cid:86)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79)(cid:3)(cid:82)(cid:81)(cid:72)(cid:86)(cid:17) (cid:22) (cid:40)(cid:39) (cid:40)(cid:47)(cid:3)(cid:32)(cid:3)(cid:44)(cid:81)(cid:87)(cid:72)(cid:74)(cid:85)(cid:68)(cid:79)(cid:3)(cid:47)(cid:76)(cid:81)(cid:72)(cid:68)(cid:85)(cid:76)(cid:87)(cid:92)(cid:3)(cid:40)(cid:85)(cid:85)(cid:82)(cid:85)(cid:29)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:21) (cid:69)(cid:72)(cid:87)(cid:90)(cid:72)(cid:72)(cid:81)(cid:3)(cid:68)(cid:81)(cid:92)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:72)(cid:81)(cid:71)(cid:3)(cid:83)(cid:82)(cid:76)(cid:81)(cid:87)(cid:3) (cid:20) (cid:20)(cid:3)(cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:39)(cid:40)(cid:36)(cid:47) (cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:17) (cid:19) (cid:57)(cid:39)(cid:39)(cid:36) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:23)(cid:19)(cid:28)(cid:22)(cid:23)(cid:19)(cid:28)(cid:23) (cid:23)(cid:19)(cid:28)(cid:24) (cid:23)(cid:19)(cid:28)(cid:25) (cid:48)(cid:54)(cid:20)(cid:28)(cid:27)(cid:27)(cid:19)(cid:57)(cid:21) Figure 26. Typical connection diagram using the ADC (cid:57)(cid:39)(cid:39)(cid:36) (cid:54)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:75)(cid:82)(cid:79)(cid:71)(cid:3)(cid:36)(cid:39)(cid:38) (cid:57)(cid:55) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:53)(cid:36)(cid:44)(cid:49)(cid:11)(cid:20)(cid:12) (cid:36)(cid:44)(cid:49)(cid:91) (cid:53)(cid:36)(cid:39)(cid:38) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:44)(cid:47)(cid:147)(cid:20)(cid:151)(cid:36) (cid:38)(cid:83)(cid:68)(cid:85)(cid:68)(cid:86)(cid:76)(cid:87)(cid:76)(cid:70)(cid:11)(cid:21)(cid:12) (cid:57)(cid:55) (cid:57)(cid:36)(cid:44)(cid:49) (cid:38)(cid:36)(cid:39)(cid:38) (cid:48)(cid:54)(cid:22)(cid:22)(cid:28)(cid:19)(cid:19)(cid:57)(cid:21) 1. Refer to Table 52: ADC characteristics for the values of R , R and C . AIN ADC ADC 2. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7 pF). A high C value will downgrade conversion accuracy. To remedy parasitic this, f should be reduced. ADC General PCB design guidelines Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DocID022265 Rev 7 79/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6.3.17 DAC electrical specifications Table 55. DAC characteristics Symbol Parameter Min Typ Max Unit Comments Analog supply voltage for V 2.4 - 3.6 V - DDA DAC ON R (1) Resistive load with buffer 5 - - kΩ Load connected to VSSA LOAD ON 25 - - kΩ Load connected to V DDA When the buffer is OFF, the Impedance output with Minimum resistive load between R (1) - - 15 kΩ O buffer OFF DAC_OUT and V to have a SS 1% accuracy is 1.5 MΩ Maximum capacitive load at C (1) Capacitive load - - 50 pF DAC_OUT pin (when the buffer LOAD is ON). It gives the maximum output DAC_OUT Lower DAC_OUT voltage 0.2 - - V excursion of the DAC. min(1) with buffer ON It corresponds to 12-bit input code (0x0E0) to (0xF1C) at DAC_OUT Higher DAC_OUT voltage V = 3.6 V and (0x155) and - - V – 0.2 V DDA max(1) with buffer ON DDA (0xEAB) at V = 2.4 V DDA DAC_OUT Lower DAC_OUT voltage - 0.5 - mV min(1) with buffer OFF It gives the maximum output DAC_OUT Higher DAC_OUT voltage excursion of the DAC. - - V – 1LSB V max(1) with buffer OFF DDA With no load, middle code DAC DC current - - 600 µA (0x800) on the input I (1) consumption in quiescent DDA mode(2) - - 700 µA With no load, worst code (0xF1C) on the input Given for the DAC in 10-bit Differential non linearity - - ±0.5 LSB configuration DNL(3) Difference between two consecutive code-1LSB) Given for the DAC in 12-bit - - ±2 LSB configuration Integral non linearity Given for the DAC in 10-bit - - ±1 LSB (difference between configuration measured value at Code i INL(3) and the value at Code i on a Given for the DAC in 12-bit line drawn between Code 0 - - ±4 LSB configuration and last Code 1023) - - ±10 mV - Offset error (difference between Given for the DAC in 10-bit at - - ±3 LSB Offset(3) measured value at Code VDDA = 3.6 V (0x800) and the ideal value Given for the DAC in 12-bit at = V /2) - - ±12 LSB DDA V = 3.6 V DDA 80/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 55. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Given for the DAC in 12-bit Gain error(3) Gain error - - ±0.5 % configuration Settling time (full scale: for a 10-bit input code transition between the lowest and the t (3) - 3 4 µs C ≤ 50 pF, R ≥ 5 kΩ SETTLING highest input codes when LOAD LOAD DAC_OUT reaches final value ±1LSB Max frequency for a correct Update DAC_OUT change when - - 1 MS/s C ≤ 50 pF, R ≥ 5 kΩ rate(3) small variation in the input LOAD LOAD code (from code i to i+1LSB) Wakeup time from off state C ≤ 50 pF, R ≥ 5 kΩ LOAD LOAD t (3) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and WAKEUP DAC Control register) highest possible ones. Power supply rejection ratio PSRR+ (1) (to V ) (static DC - –67 –40 dB No R , C = 50 pF DDA LOAD LOAD measurement 1. Guaranteed by design, not tested in production. 2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Figure 27. 12-bit buffered / non-buffered DAC (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:18)(cid:49)(cid:82)(cid:81)(cid:16)(cid:69)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:71)(cid:3)(cid:39)(cid:36)(cid:38) (cid:37)(cid:88)(cid:73)(cid:73)(cid:72)(cid:85)(cid:11)(cid:20)(cid:12) (cid:53)(cid:47) (cid:20)(cid:21)(cid:16)(cid:69)(cid:76)(cid:87)(cid:3)(cid:71)(cid:76)(cid:74)(cid:76)(cid:87)(cid:68)(cid:79) (cid:39)(cid:36)(cid:38)(cid:66)(cid:50)(cid:56)(cid:55)(cid:91) (cid:87)(cid:82)(cid:3)(cid:68)(cid:81)(cid:68)(cid:79)(cid:82)(cid:74) (cid:70)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:72)(cid:85) (cid:38)(cid:47) (cid:48)(cid:54)(cid:22)(cid:28)(cid:19)(cid:19)(cid:28)(cid:57)(cid:20) 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID022265 Rev 7 81/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6.3.18 Comparator characteristics Table 56. Comparator characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit V Analog supply voltage - V - 3.6 V DDA DD Comparator input V - 0 - V - IN voltage range DDA V scaler offset V REFINT - - ±5 ±10 mV SC voltage First V scaler activation after device 1000 REFINT - - t VREFINT scaler startup power on (2) ms S_SC time from power down Next activations - - 0.2 Comparator startup Startup time to reach propagation delay t - - 60 µs START time specification Ultra-low power mode - 2 4.5 Low power mode - 0.7 1.5 µs Propagation delay for 200 mV step with Medium power mode - 0.3 0.6 100 mV overdrive V ≥ 2.7 V - 50 100 DDA High speed mode ns V < 2.7 V - 100 240 DDA t D Ultra-low power mode - 2 7 Low power mode - 0.7 2.1 µs Propagation delay for full range step with Medium power mode - 0.3 1.2 100 mV overdrive V ≥ 2.7 V - 90 180 DDA High speed mode ns V < 2.7 V - 110 300 DDA V Comparator offset error - - ±4 ±10 mV offset Offset error dV /dT - - 18 - µV/°C offset temperature coefficient Ultra-low power mode - 1.2 1.5 Low power mode - 3 5 COMP current I µA DD(COMP) consumption Medium power mode - 10 15 High speed mode - 75 100 82/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 56. Comparator characteristics (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit No hysteresis - - 0 - (COMPxHYST[1:0]=00) High speed mode 3 13 Low hysteresis 8 (COMPxHYST[1:0]=01) All other power 5 10 modes V Comparator hysteresis High speed mode 7 26 mV hys Medium hysteresis 15 (COMPxHYST[1:0]=10) All other power 9 19 modes High speed mode 18 49 High hysteresis 31 (COMPxHYST[1:0]=11) All other power 19 40 modes 1. Data based on characterization results, not tested in production. 2. For more details and conditions see Figure 28: Maximum V scaler startup time from power down. REFINT Figure 28. Maximum V scaler startup time from power down REFINT (cid:1006)(cid:856)(cid:1004)(cid:115)(cid:3)(cid:1095)(cid:3)(cid:115) (cid:1092)(cid:3)(cid:1006)(cid:856)(cid:1008)(cid:115) (cid:24)(cid:24)(cid:4) (cid:1005)(cid:1004)(cid:1004)(cid:1004) (cid:1006)(cid:856)(cid:1008)(cid:115)(cid:3)(cid:1095)(cid:3)(cid:115) (cid:1092)(cid:3)(cid:1007)(cid:856)(cid:1004)(cid:115) (cid:24)(cid:24)(cid:4) (cid:1007)(cid:856)(cid:1004)(cid:115)(cid:3)(cid:1095)(cid:3)(cid:115) (cid:1092)(cid:3)(cid:1007)(cid:856)(cid:1010)(cid:115) (cid:24)(cid:24)(cid:4) (cid:1005)(cid:1004)(cid:1004) (cid:400)(cid:895) (cid:373) (cid:894) (cid:454)(cid:895) (cid:258) (cid:373) (cid:18)(cid:894) (cid:94) (cid:890) (cid:94) (cid:1005)(cid:1004) (cid:410) (cid:1005) (cid:882)(cid:1008)(cid:1004) (cid:882)(cid:1006)(cid:1004) (cid:1004) (cid:1006)(cid:1004) (cid:1008)(cid:1004) (cid:1010)(cid:1004) (cid:1012)(cid:1004) (cid:20)(cid:19)(cid:19) (cid:100)(cid:286)(cid:373)(cid:393)(cid:286)(cid:396)(cid:258)(cid:410)(cid:437)(cid:396)(cid:286)(cid:3)(cid:894)(cid:931)(cid:18)(cid:895) DocID022265 Rev 7 83/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6.3.19 Temperature sensor characteristics Table 57. TS characteristics Symbol Parameter Min Typ Max Unit T (1) V linearity with temperature - ± 1 ± 2 °C L SENSE Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C V Voltage at 30 °C (± 5 °C)(2) 1.34 1.43 1.52 V 30 t (1) ADC_IN16 buffer startup time - - 10 µs START ADC sampling time when reading the t (1) 4 - - µs S_temp temperature 1. Guaranteed by design, not tested in production. 2. Measured at V = 3.3 V ± 10 mV. The V ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3: DDA 30 Temperature sensor calibration values. 6.3.20 V monitoring characteristics BAT Table 58. V monitoring characteristics BAT Symbol Parameter Min Typ Max Unit R Resistor bridge for V - 2 x 50 - kΩ BAT Q Ratio on V measurement - 2 - - BAT Er(1) Error on Q –1 - +1 % t (1) ADC sampling time when reading the V 4 - - µs S_vbat BAT 1. Guaranteed by design, not tested in production. 6.3.21 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 59. TIMx characteristics Symbol Parameter Conditions Min Typ Max Unit - - 1 - tTIMxCLK tres(TIM) Timer resolution time f = 48 MHz - 20.8 - ns TIMxCLK Timer external clock - - fTIMxCLK/2 - MHz fEXT frequency on CH1 to CH4 fTIMxCLK = 48 MHz - 24 - MHz 16-bit timer maximum - - 216 - tTIMxCLK period f = 48 MHz - 1365 - µs TIMxCLK t MAX_COUNT 32-bit counter - - 232 - tTIMxCLK maximum period f = 48 MHz - 89.48 - s TIMxCLK 84/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 60. IWDG min/max timeout period at 40 kHz (LSI)(1) Min timeout RL[11:0]= Max timeout RL[11:0]= Prescaler divider PR[2:0] bits Unit 0x000 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 ms /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 61. WWDG min/max timeout value at 48 MHz (PCLK) Prescaler WDGTB Min timeout value Max timeout value Unit 1 0 0.0853 5.4613 2 1 0.1706 10.9226 ms 4 2 0.3413 21.8453 8 3 0.6826 43.6906 6.3.22 Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V is disabled, but is still present. Only FTf I/O pins DDIOx support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: DocID022265 Rev 7 85/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 62. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit Maximum width of spikes that are t 50(2) 260(3) ns AF suppressed by the analog filter 1. Guaranteed by design, not tested in production. 2. Spikes with widths below t are filtered. AF(min) 3. Spikes with widths above t are not filtered AF(max) SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S are derived from tests performed under the ambient temperature, f frequency and PCLKx supply voltage conditions summarized in Table 20: General operating conditions. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 63. SPI characteristics(1) Symbol Parameter Conditions Min Max Unit f Master mode - 18 SCK SPI clock frequency MHz 1/tc(SCK) Slave mode - 18 t SPI clock rise and fall r(SCK) Capacitive load: C = 15 pF - 6 ns t time f(SCK) t NSS setup time Slave mode 4Tpclk - su(NSS) t NSS hold time Slave mode 2Tpclk + 10 - h(NSS) t Master mode, f = 36 MHz, w(SCKH) SCK high and low time PCLK Tpclk/2 -2 Tpclk/2 + 1 t presc = 4 w(SCKL) Master mode 4 - t su(MI) Data input setup time tsu(SI) Slave mode 5 - t Master mode 4 - h(MI) Data input hold time ns t Slave mode 5 - h(SI) t (2) Data output access time Slave mode, f = 20 MHz 0 3Tpclk a(SO) PCLK t (3) Data output disable time Slave mode 0 18 dis(SO) t Data output valid time Slave mode (after enable edge) - 22.5 v(SO) t Data output valid time Master mode (after enable edge) - 6 v(MO) t Slave mode (after enable edge) 11.5 - h(SO) Data output hold time t Master mode (after enable edge) 2 - h(MO) SPI slave input clock DuCy(SCK) Slave mode 25 75 % duty cycle 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 86/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 29. SPI timing diagram - slave mode and CPHA = 0 (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87) (cid:87) (cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87) (cid:87) (cid:87) (cid:86)(cid:88)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:43)(cid:12) (cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:83) (cid:81) (cid:46)(cid:3)(cid:76) (cid:38) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87) (cid:87) (cid:87) (cid:87) (cid:87) (cid:87) (cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:47)(cid:12) (cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87) (cid:41)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:50)(cid:56)(cid:55) (cid:49)(cid:72)(cid:91)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:68)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:50)(cid:56)(cid:55) (cid:87) (cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:87) (cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:41)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:44)(cid:49) (cid:49)(cid:72)(cid:91)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:3)(cid:44)(cid:49) (cid:47)(cid:68)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:44)(cid:49) (cid:48)(cid:54)(cid:89)(cid:23)(cid:20)(cid:25)(cid:24)(cid:27)(cid:57)(cid:20) Figure 30. SPI timing diagram - slave mode and CPHA = 1 (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87) (cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87) (cid:87) (cid:87) (cid:87) (cid:86)(cid:88)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:43)(cid:12) (cid:73)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:83) (cid:81) (cid:46)(cid:3)(cid:76) (cid:38) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87) (cid:87) (cid:87) (cid:87) (cid:87) (cid:87) (cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:90)(cid:11)(cid:54)(cid:38)(cid:46)(cid:47)(cid:12) (cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:85)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87) (cid:41)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:50)(cid:56)(cid:55) (cid:49)(cid:72)(cid:91)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:68)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:50)(cid:56)(cid:55) (cid:87) (cid:87) (cid:86)(cid:88)(cid:11)(cid:54)(cid:44)(cid:12) (cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:41)(cid:76)(cid:85)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:44)(cid:49) (cid:49)(cid:72)(cid:91)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:86)(cid:3)(cid:44)(cid:49) (cid:47)(cid:68)(cid:86)(cid:87)(cid:3)(cid:69)(cid:76)(cid:87)(cid:3)(cid:44)(cid:49) (cid:48)(cid:54)(cid:89)(cid:23)(cid:20)(cid:25)(cid:24)(cid:28)(cid:57)(cid:20) 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DocID022265 Rev 7 87/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 31. SPI timing diagram - master mode (cid:43)(cid:76)(cid:74)(cid:75) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:83) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:50) (cid:46)(cid:3) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:54)(cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:86)(cid:88)(cid:11)(cid:48)(cid:44)(cid:12) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:48)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:89)(cid:11)(cid:48)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:48)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:25)(cid:70) 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 64. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit Master mode (data: 16 bits, Audio fCK I2S clock frequency frequency = 48 kHz) 1.597 1.601 MHz 1/t c(CK) Slave mode 0 6.5 t I2S clock rise time - 10 r(CK) Capacitive load C = 15 pF t I2S clock fall time L - 12 f(CK) tw(CKH) I2S clock high time Master fPCLK= 16 MHz, audio 306 - t I2S clock low time frequency = 48 kHz 312 - w(CKL) ns t WS valid time Master mode 2 - v(WS) t WS hold time Master mode 2 - h(WS) t WS setup time Slave mode 7 - su(WS) t WS hold time Slave mode 0 - h(WS) I2S slave input clock duty DuCy(SCK) Slave mode 25 75 % cycle 88/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 64. I2S characteristics(1) (continued) Symbol Parameter Conditions Min Max Unit t Master receiver 6 - su(SD_MR) Data input setup time t Slave receiver 2 - su(SD_SR) t (2) Master receiver 4 - h(SD_MR) Data input hold time t (2) Slave receiver 0.5 - h(SD_SR) ns t (2) Master transmitter - 4 v(SD_MT) Data output valid time t (2) Slave transmitter - 20 v(SD_ST) t Master transmitter 0 - h(SD_MT) Data output hold time t Slave transmitter 13 - h(SD_ST) 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on f . For example, if f = 8 MHz, then T = 1/f = 125 ns. PCLK PCLK PCLK PLCLK Figure 32. I2S slave timing diagram (Philips protocol) (cid:87)(cid:70)(cid:11)(cid:38)(cid:46)(cid:12) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:19) (cid:88)(cid:87) (cid:83) (cid:81) (cid:46)(cid:3)(cid:44) (cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:20) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:43)(cid:12) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:47)(cid:12) (cid:87)(cid:75)(cid:11)(cid:58)(cid:54)(cid:12) (cid:58)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:58)(cid:54)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:55)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:55)(cid:12) (cid:54)(cid:39)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:47)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:53)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:54)(cid:53)(cid:12) (cid:54)(cid:39)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:48)(cid:54)(cid:89)(cid:22)(cid:28)(cid:26)(cid:21)(cid:20)(cid:57)(cid:20) 1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID022265 Rev 7 89/122 90

Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 33. I2S master timing diagram (Philips protocol) (cid:28)(cid:19)(cid:8) (cid:20)(cid:19)(cid:8) (cid:87)(cid:73)(cid:11)(cid:38)(cid:46)(cid:12) (cid:87)(cid:85)(cid:11)(cid:38)(cid:46)(cid:12) (cid:87)(cid:70)(cid:11)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:19) (cid:83) (cid:82)(cid:88)(cid:87) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:43)(cid:12) (cid:46)(cid:3) (cid:38) (cid:38)(cid:51)(cid:50)(cid:47)(cid:3)(cid:32)(cid:3)(cid:20) (cid:87)(cid:89)(cid:11)(cid:58)(cid:54)(cid:12) (cid:87)(cid:90)(cid:11)(cid:38)(cid:46)(cid:47)(cid:12) (cid:87)(cid:75)(cid:11)(cid:58)(cid:54)(cid:12) (cid:58)(cid:54)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87) (cid:87)(cid:89)(cid:11)(cid:54)(cid:39)(cid:66)(cid:48)(cid:55)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:48)(cid:55)(cid:12) (cid:54)(cid:39)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:47)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:47)(cid:54)(cid:37)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:39)(cid:66)(cid:48)(cid:53)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:39)(cid:66)(cid:48)(cid:53)(cid:12) (cid:54)(cid:39)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:11)(cid:21)(cid:12) (cid:48)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:37)(cid:76)(cid:87)(cid:81)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:47)(cid:54)(cid:37)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72) (cid:48)(cid:54)(cid:89)(cid:22)(cid:28)(cid:26)(cid:21)(cid:19)(cid:57)(cid:20) 1. Data based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 90/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array package. Figure 34. UFBGA64 package outline (cid:61) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:36)(cid:23) (cid:36)(cid:22)(cid:36)(cid:21) (cid:36)(cid:20) (cid:36) (cid:40)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3) (cid:59) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:40) (cid:72) (cid:41) (cid:36) (cid:41) (cid:39)(cid:20) (cid:39) (cid:72) (cid:60) (cid:43) (cid:27) (cid:20) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:69)(cid:3)(cid:11)(cid:25)(cid:23)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:12) (cid:55)(cid:50)(cid:51)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:145)(cid:72)(cid:72)(cid:72)(cid:48) (cid:61) (cid:60) (cid:59) (cid:145)(cid:73)(cid:73)(cid:73) (cid:48) (cid:61) (cid:36)(cid:19)(cid:20)(cid:28)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:20) 1. Drawing is not to scale. Table 65. UFBGA64 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 DocID022265 Rev 7 91/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 65. UFBGA64 package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 35. Recommended footprint for UFBGA64 package (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:36)(cid:19)(cid:20)(cid:28)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:21) Table 66. UFBGA64 recommended PCB design rules Dimension Recommended values Pitch 0.5 Dpad 0.280 mm 0.370 mm typ. (depends on the soldermask Dsm registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm 92/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 36. UFBGA64 package marking example (cid:87)(cid:396)(cid:381)(cid:282)(cid:437)(cid:272)(cid:410)(cid:3) (cid:41)(cid:19)(cid:24)(cid:20)(cid:53)(cid:27)(cid:43)(cid:26) (cid:894)(cid:1005)(cid:895) (cid:349)(cid:282)(cid:286)(cid:374)(cid:410)(cid:349)(cid:296)(cid:349)(cid:272)(cid:258)(cid:410)(cid:349)(cid:381)(cid:374) (cid:24)(cid:258)(cid:410)(cid:286)(cid:3)(cid:272)(cid:381)(cid:282)(cid:286) (cid:60) (cid:58)(cid:58) (cid:94)(cid:410)(cid:258)(cid:374)(cid:282)(cid:258)(cid:396)(cid:282)(cid:3)(cid:94)(cid:100)(cid:3)(cid:367)(cid:381)(cid:336)(cid:381) (cid:90)(cid:286)(cid:448)(cid:349)(cid:400)(cid:349)(cid:381)(cid:374)(cid:3)(cid:272)(cid:381)(cid:282)(cid:286) (cid:53) (cid:17)(cid:258)(cid:367)(cid:367)(cid:3)(cid:1005)(cid:3)(cid:349)(cid:282)(cid:286)(cid:374)(cid:410)(cid:349)(cid:296)(cid:349)(cid:286)(cid:396) (cid:68)(cid:94)(cid:1007)(cid:1012)(cid:1007)(cid:1004)(cid:1006)(cid:115)(cid:1005) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID022265 Rev 7 93/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 7.2 LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 37. LQFP64 package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:70) (cid:36) (cid:70)(cid:70)(cid:70) (cid:38) (cid:20) (cid:39) (cid:36) (cid:46) (cid:39)(cid:20) (cid:47) (cid:39)(cid:22) (cid:47)(cid:20) (cid:23)(cid:27) (cid:22)(cid:22) (cid:22)(cid:21) (cid:23)(cid:28) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20) (cid:20)(cid:25) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:72) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:24)(cid:58)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. Table 67. LQFP64 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - 94/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 67. LQFP64 package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38. Recommended footprint for LQFP64 package (cid:23)(cid:27) (cid:22)(cid:22) (cid:19)(cid:17)(cid:22) (cid:23)(cid:28) (cid:19)(cid:17)(cid:24) (cid:22)(cid:21) (cid:20)(cid:21)(cid:17)(cid:26) (cid:20)(cid:19)(cid:17)(cid:22) (cid:20)(cid:19)(cid:17)(cid:22) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20)(cid:17)(cid:21) (cid:20) (cid:20)(cid:25) (cid:26)(cid:17)(cid:27) (cid:20)(cid:21)(cid:17)(cid:26) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:19)(cid:28)(cid:70) 1. Dimensions are expressed in millimeters. DocID022265 Rev 7 95/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 39. LQFP64 package marking example (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53) (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41)(cid:19)(cid:24)(cid:20) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:53)(cid:27)(cid:55)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:23)(cid:24)(cid:25)(cid:57)(cid:20) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 96/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information 7.3 LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 40. LQFP48 package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:21) (cid:36)(cid:36) (cid:20) (cid:36) (cid:70) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:70)(cid:70)(cid:70) (cid:38) (cid:39) (cid:46) (cid:20) (cid:47) (cid:36) (cid:39)(cid:20) (cid:47)(cid:20) (cid:39)(cid:22) (cid:22)(cid:25) (cid:21)(cid:24) (cid:22)(cid:26) (cid:21)(cid:23) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:23)(cid:27) (cid:20)(cid:22) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:20) (cid:20)(cid:21) (cid:72) (cid:24)(cid:37)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:21) 1. Drawing is not to scale. DocID022265 Rev 7 97/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 68. LQFP48 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41. Recommended footprint for LQFP48 package (cid:19)(cid:17)(cid:24)(cid:19) (cid:20)(cid:17)(cid:21)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:22)(cid:25) (cid:21)(cid:24) (cid:22)(cid:26) (cid:21)(cid:23) (cid:19)(cid:17)(cid:21)(cid:19) (cid:26)(cid:17)(cid:22)(cid:19) (cid:28)(cid:17)(cid:26)(cid:19) (cid:24)(cid:17)(cid:27)(cid:19) (cid:26)(cid:17)(cid:22)(cid:19) (cid:23)(cid:27) (cid:20)(cid:22) (cid:20) (cid:20)(cid:21) (cid:20)(cid:17)(cid:21)(cid:19) (cid:24)(cid:17)(cid:27)(cid:19) (cid:28)(cid:17)(cid:26)(cid:19) (cid:68)(cid:76)(cid:20)(cid:23)(cid:28)(cid:20)(cid:20)(cid:71) 1. Dimensions are expressed in millimeters. 98/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. LQFP48 package marking example (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:19)(cid:24)(cid:20)(cid:38)(cid:27)(cid:55)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:23)(cid:24)(cid:27)(cid:57)(cid:20) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID022265 Rev 7 99/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 7.4 UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 43. UFQFPN48 package outline (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:79)(cid:68)(cid:86)(cid:72)(cid:85)(cid:3)(cid:80)(cid:68)(cid:85)(cid:78)(cid:76)(cid:81)(cid:74)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39) (cid:36) (cid:40) (cid:40) (cid:55) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3) (cid:71)(cid:71)(cid:71) (cid:36)(cid:20) (cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:72) (cid:69) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:60) (cid:39) (cid:60) (cid:40)(cid:91)(cid:83)(cid:82)(cid:86)(cid:72)(cid:71)(cid:3)(cid:83)(cid:68)(cid:71)(cid:3) (cid:39)(cid:21) (cid:68)(cid:85)(cid:72)(cid:68) (cid:20) (cid:47) (cid:23)(cid:27) (cid:38)(cid:3)(cid:19)(cid:17)(cid:24)(cid:19)(cid:19)(cid:91)(cid:23)(cid:24)(cid:131) (cid:83)(cid:76)(cid:81)(cid:20)(cid:3)(cid:70)(cid:82)(cid:85)(cid:81)(cid:72)(cid:85) (cid:53)(cid:3)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:3)(cid:87)(cid:92)(cid:83)(cid:17) (cid:40)(cid:21) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:61) (cid:20) (cid:23)(cid:27) (cid:61) (cid:36)(cid:19)(cid:37)(cid:28)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 100/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 69. UFQFPN48 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. Recommended footprint for UFQFPN48 package (cid:26)(cid:17)(cid:22)(cid:19) (cid:25)(cid:17)(cid:21)(cid:19) (cid:23)(cid:27) (cid:22)(cid:26) (cid:20) (cid:22)(cid:25) (cid:19)(cid:17)(cid:21)(cid:19) (cid:24)(cid:17)(cid:25)(cid:19) (cid:26)(cid:17)(cid:22)(cid:19) (cid:24)(cid:17)(cid:27)(cid:19) (cid:25)(cid:17)(cid:21)(cid:19) (cid:24)(cid:17)(cid:25)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:20)(cid:21) (cid:21)(cid:24) (cid:20)(cid:22) (cid:21)(cid:23) (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24)(cid:24) (cid:24)(cid:17)(cid:27)(cid:19) (cid:36)(cid:19)(cid:37)(cid:28)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:21) 1. Dimensions are expressed in millimeters. DocID022265 Rev 7 101/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 45. UFQFPN48 package marking example (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:19)(cid:24)(cid:20)(cid:38)(cid:27)(cid:56)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:23)(cid:25)(cid:19)(cid:57)(cid:20) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 102/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information 7.5 WLCSP36 package information WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 46. WLCSP36 package outline (cid:72)(cid:20) (cid:36)(cid:20)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:69)(cid:69)(cid:69)(cid:61) (cid:41) (cid:72) (cid:36) (cid:42) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:72)(cid:21) (cid:72) (cid:41) (cid:25) (cid:20) (cid:36)(cid:22) (cid:36)(cid:21) (cid:36) (cid:37)(cid:88)(cid:80)(cid:83)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:54)(cid:76)(cid:71)(cid:72)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) (cid:24) (cid:59) (cid:60) (cid:36)(cid:22) (cid:37)(cid:88)(cid:80)(cid:83) (cid:36)(cid:20)(cid:3) (cid:82)(cid:85)(cid:76)(cid:72)(cid:81)(cid:87)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:28) (cid:72)(cid:72)(cid:72) (cid:61) (cid:36)(cid:20) (cid:85)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72) (cid:68)(cid:68)(cid:68) (cid:61) (cid:61) (cid:145)(cid:69)(cid:3)(cid:11)(cid:22)(cid:25)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:12) (cid:69) (cid:54)(cid:72)(cid:68)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:79)(cid:68)(cid:81)(cid:72) (cid:70)(cid:70)(cid:70) (cid:61)(cid:59)(cid:60) (cid:58)(cid:68)(cid:73)(cid:72)(cid:85)(cid:3)(cid:69)(cid:68)(cid:70)(cid:78)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72) (cid:71)(cid:71)(cid:71) (cid:61) (cid:39)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:36) (cid:85)(cid:82)(cid:87)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:28)(cid:19)(cid:131) (cid:4)(cid:1004)(cid:127)(cid:62)(cid:890)(cid:68)(cid:28)(cid:890)(cid:115)(cid:1006) 1. Drawing is not to scale. Table 70. WLCSP36 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.570 2.605 2.640 0.1012 0.1026 0.1039 E 2.668 2.703 2.738 0.1050 0.1064 0.1078 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - DocID022265 Rev 7 103/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 70. WLCSP36 package mechanical data (continued) millimeters inches(1) Symbol Min Typ Max Min Typ Max F - 0.3025 - - 0.0119 - G - 0.3515 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 47. Recommended pad footprint for WLCSP36 package (cid:39)(cid:83)(cid:68)(cid:71) (cid:39)(cid:86)(cid:80) (cid:48)(cid:54)(cid:20)(cid:27)(cid:28)(cid:25)(cid:24)(cid:57)(cid:21) Table 71. WLCSP36 recommended PCB design rules Dimension Recommended values Pitch 0.4 mm 260 µm max. (circular) Dpad 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed 104/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 48. WLCSP36 package marking example (cid:24)(cid:381)(cid:410) (cid:87)(cid:396)(cid:381)(cid:282)(cid:437)(cid:272)(cid:410)(cid:3)(cid:349)(cid:282)(cid:286)(cid:374)(cid:410)(cid:349)(cid:296)(cid:349)(cid:272)(cid:258)(cid:410)(cid:349)(cid:381)(cid:374) (cid:894)(cid:1005)(cid:895) (cid:41)(cid:19)(cid:24)(cid:20)(cid:27)(cid:25) (cid:90)(cid:286)(cid:448)(cid:349)(cid:400)(cid:349)(cid:381)(cid:374)(cid:3)(cid:272)(cid:381)(cid:282)(cid:286) (cid:53) (cid:24)(cid:258)(cid:410)(cid:286)(cid:3)(cid:272)(cid:381)(cid:282)(cid:286) (cid:60) (cid:58)(cid:58) (cid:68)(cid:94)(cid:1007)(cid:1013)(cid:1004)(cid:1006)(cid:1011)(cid:115)(cid:1005) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID022265 Rev 7 105/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 7.6 LQFP32 package information LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 49. LQFP32 package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:21) (cid:36) (cid:36) (cid:20) (cid:70) (cid:36) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:70)(cid:70)(cid:70) (cid:38) (cid:46) (cid:39) (cid:20) (cid:47) (cid:36) (cid:39)(cid:20) (cid:47)(cid:20) (cid:39)(cid:22) (cid:21)(cid:23) (cid:20)(cid:26) (cid:21)(cid:24) (cid:20)(cid:25) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:22)(cid:21) (cid:28) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:20) (cid:27) (cid:72) (cid:22)(cid:55)(cid:64)(cid:46)(cid:38)(cid:64)(cid:55)(cid:19) 1. Drawing is not to scale. 106/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 72. LQFP32 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 50. Recommended footprint for LQFP32 package (cid:19)(cid:17)(cid:27)(cid:19) (cid:20)(cid:17)(cid:21)(cid:19) (cid:19)(cid:21) (cid:18)(cid:24) (cid:19)(cid:22) (cid:18)(cid:23) (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:26)(cid:17)(cid:22)(cid:19) (cid:25)(cid:17)(cid:20)(cid:19) (cid:28)(cid:17)(cid:26)(cid:19) (cid:26)(cid:17)(cid:22)(cid:19) (cid:20)(cid:19) (cid:26) (cid:18) (cid:25) (cid:20)(cid:17)(cid:21)(cid:19) (cid:25)(cid:17)(cid:20)(cid:19) (cid:28)(cid:17)(cid:26)(cid:19) (cid:24)(cid:57)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:21) 1. Dimensions are expressed in millimeters. DocID022265 Rev 7 107/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 51. LQFP32 package marking example (cid:54)(cid:55)(cid:48)(cid:22)(cid:21)(cid:41) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:19)(cid:24)(cid:20)(cid:46)(cid:27)(cid:55)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:23)(cid:24)(cid:28)(cid:57)(cid:20) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 7.7 UFQFPN32 package information UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package. 108/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Figure 52. UFQFPN32 package outline (cid:39) (cid:36) (cid:71)(cid:71)(cid:71) (cid:38) (cid:72) (cid:36)(cid:20) (cid:36)(cid:21) (cid:38) (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:39)(cid:20) (cid:69) (cid:72) (cid:40)(cid:21) (cid:69) (cid:40)(cid:20) (cid:40) (cid:20) (cid:47) (cid:22)(cid:21) (cid:39)(cid:21) (cid:47) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20)(cid:3)(cid:44)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:36)(cid:19)(cid:37)(cid:27)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:21) 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must be connected. It is referred to as pin 0 in Table: Pin definitions. DocID022265 Rev 7 109/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 73. UFQFPN32 package mechanical data millimeters inches(1) Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.900 5.000 5.100 0.1929 0.1969 0.2008 E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 53. Recommended footprint for UFQFPN32 package (cid:24)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:27)(cid:19) (cid:19)(cid:17)(cid:25)(cid:19) (cid:20)(cid:19) (cid:19)(cid:22) (cid:18) (cid:19)(cid:21) (cid:22)(cid:17)(cid:23)(cid:24) (cid:24)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:27)(cid:19) (cid:22)(cid:17)(cid:23)(cid:24) (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:25) (cid:18)(cid:24) (cid:26) (cid:18)(cid:23) (cid:19)(cid:17)(cid:26)(cid:24) (cid:22)(cid:17)(cid:27)(cid:19) (cid:36)(cid:19)(cid:37)(cid:27)(cid:66)(cid:41)(cid:51)(cid:66)(cid:57)(cid:21) 1. Dimensions are expressed in millimeters. 110/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 54. UFQFPN32 package marking example (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:11)(cid:20)(cid:12) (cid:41)(cid:19)(cid:24)(cid:20)(cid:46)(cid:27)(cid:25) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:60) (cid:58)(cid:58) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:53) (cid:39)(cid:82)(cid:87)(cid:3)(cid:11)(cid:83)(cid:76)(cid:81)(cid:3)(cid:20)(cid:12)(cid:3)(cid:3) (cid:48)(cid:54)(cid:89)(cid:22)(cid:25)(cid:23)(cid:25)(cid:21)(cid:57)(cid:20) 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID022265 Rev 7 111/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 7.8 Thermal characteristics The maximum chip junction temperature (T max) must never exceed the values given in J Table 20: General operating conditions. The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated J using the following equation: T max = T max + (P max x Θ ) J A D JA Where: • T max is the maximum ambient temperature in °C, A • Θ is the package junction-to-ambient thermal resistance, in °C/W, JA • P max is the sum of P max and P max (P max = P max + P max), D INT I/O D INT I/O • P max is the product of I and V , expressed in Watts. This is the maximum chip INT DD DD internal power. P max represents the maximum power dissipation on output pins where: I/O PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 74. Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction-ambient 45 LQFP64 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient 55 LQFP48 - 7 × 7 mm Thermal resistance junction-ambient 56 LQFP32 - 7 × 7 mm Thermal resistance junction-ambient Θ 65 °C/W JA UFBGA64 - 5 × 5 mm Thermal resistance junction-ambient 32 UFQFPN48 - 7 × 7 mm Thermal resistance junction-ambient 38 UFQFPN32 - 5 × 5 mm Thermal resistance junction-ambient 60 WLCSP36 - 2.6 × 2.7 mm 7.8.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.8.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. 112/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Package information Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F051xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature T = 82 °C (measured according to JESD51-2), Amax I = 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output OL OL at low level with I = 20 mA, V = 1.3 V OL OL P =50 mA × 3.5 V= 175 mW INTmax P =20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW IOmax This gives: P = 175 mW and P = 272 mW: INTmax IOmax P =175+272 = 447 mW Dmax Using the values obtained in Table 74 T is calculated as follows: Jmax – For LQFP64, 45 °C/W T = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C Jmax This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Table 20: J General operating conditions. In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Ordering information). Note: With this given P we can find the T allowed for a given device temperature range Dmax Amax (order code suffix 6 or 7). Suffix 6: T = T - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C Amax Jmax Suffix 7: T = T - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C Amax Jmax Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T remains within the J specified range. Assuming the following application conditions: Maximum ambient temperature T = 100 °C (measured according to JESD51-2), Amax I = 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low DDmax DD level with I = 8 mA, V = 0.4 V OL OL P =20 mA × 3.5 V= 70 mW INTmax P =20 × 8 mA × 0.4 V = 64 mW IOmax This gives: P = 70 mW and P = 64 mW: INTmax IOmax P =70+64 = 134 mW Dmax Thus: P = 134 mW Dmax DocID022265 Rev 7 113/122 115

Package information STM32F051x4 STM32F051x6 STM32F051x8 Using the values obtained in Table 74 T is calculated as follows: Jmax – For LQFP64, 45 °C/W T = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C Jmax This is above the range of the suffix 6 version parts (–40 < T < 105 °C). J In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 55 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. Figure 55. LQFP64 P max versus T D A (cid:26)(cid:19)(cid:19) (cid:25)(cid:19)(cid:19) (cid:24)(cid:19)(cid:19) (cid:12) (cid:58) (cid:80) (cid:23)(cid:19)(cid:19) (cid:54)(cid:88)(cid:73)(cid:73)(cid:76)(cid:91)(cid:3)(cid:25) (cid:11) (cid:3)(cid:39) (cid:22)(cid:19)(cid:19) (cid:51) (cid:54)(cid:88)(cid:73)(cid:73)(cid:76)(cid:91)(cid:3)(cid:26) (cid:21)(cid:19)(cid:19) (cid:20)(cid:19)(cid:19) (cid:19) (cid:25)(cid:24) (cid:26)(cid:24) (cid:27)(cid:24) (cid:28)(cid:24) (cid:20)(cid:19)(cid:24) (cid:20)(cid:20)(cid:24) (cid:20)(cid:21)(cid:24) (cid:20)(cid:22)(cid:24) (cid:55) (cid:3)(cid:11)(cid:131)(cid:38)(cid:12) (cid:36) (cid:48)(cid:54)(cid:89)(cid:22)(cid:21)(cid:20)(cid:23)(cid:22)(cid:57)(cid:20) 114/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Ordering information 8 Ordering information For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 75. Ordering information scheme Example: STM32 F 051 R 8 T 6 x Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 051 = STM32F051xx Pin count K = 32 pins T = 36 pins C = 48 pins R = 64 pins User code memory size 4 = 16 Kbyte 6 = 32 Kbyte 8 = 64 Kbyte Package H = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = –40 °C to +85 °C 7 = –40 °C to +105 °C Options xxx = code ID of programmed parts (includes packing type) TR = tape and reel packing blank = tray packing DocID022265 Rev 7 115/122 115

Revision history STM32F051x4 STM32F051x6 STM32F051x8 9 Revision history Table 76. Document revision history Date Revision Changes 05-Apr-2012 1 Initial release Updated Table: STM32F051xx family device features and peripheral counts for SPI and I2C in 32-pin package. Corrected Group 3 pin order in Table: Capacitive sensing GPIOs 25-Apr-2012 2 available on STM32F051xx devices. Updated the current consumption values in Section: Electrical characteristics. Updated Table: HSI14 oscillator characteristics Features reorganized and Figure: Block diagram structure changed. Added LQFP32 package. Updated Section: Cyclic redundancy check calculation unit (CRC). Modified the number of priority levels in Section: Nested vectored interrupt controller (NVIC). Added note 3. for PB2 and PB8, changed TIM2_CH_ETR into TIM2_CH1_ETR in Table: Pin definitions and Table: Alternate functions selected through GPIOA_AFR registers for port A. Added Table: Alternate functions selected through GPIOB_AFR registers for port B. Updated I , I , and I in Table: Current VDD VSS INJ(PIN) 23-Jul-2012 3 characteristics. Updated ACC in Table: HSI oscillator characteristics and HSI Table: HSI14 oscillator characteristics. Updated Table: I/O current injection susceptibility. Added BOOT0 input low and high level voltage in Table: I/O static characteristics. Modified number of pins in V and V description, and OL OH changed condition for V in Table: Output voltage OLFM+ characteristics. Changed V to V in Figure: Typical connection diagram DD DDA using the ADC. Updated Ts_temp in Table: TS characteristics. Updated Figure: I/O AC characteristics definition. 116/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history (continued) Date Revision Changes Modified datasheet title. Added packages UFQFPN48 and UFBGA64. Replaced “backup domain with “RTC domain” throughout the document. Changed SRAM value from “4 to 8 Kbyte” to “8 Kbyte” Replaced IWWDG with IWDG in Figure: Block diagram. Added inputs LSI and LSE to the multiplexer in Figure: Clock tree. Added feature “Reference clock detection” in Section: Real-time clock (RTC) and backup registers. Modified junction temperature in Table: Thermal characteristics. Renamed Table: Internal voltage reference calibration values. Replaced V with V and V with ΔV in Table: DD DDA RERINT REFINT Embedded internal reference voltage. Rephrased introduction of Section: Touch sensing controller (TSC). 13-Jan-2014 4 Rephrased Section: Voltage regulator. Added sentence “If this is used when the voltage regulator is put in low power mode...” under “Stop mode” in Section: Low-power modes. Removed sentence “The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.” in Section: Comparators (COMP). Removed feature “Periodic wakeup from Stop/Standby” in Section: Real-time clock (RTC) and backup registers. Replaced I with I in Table: HSI oscillator characteristics, DD DDA Table: HSI14 oscillator characteristics and Table: LSI oscillator characteristics. Moved section “Wakeup time from low-power mode” to Section 6.3.6 and rephrased the section. Added lines D2 and E2 in Table: UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package mechanical data. Added “The peripheral clock used is 48 MHz.” in Section On- chip peripheral current consumption. DocID022265 Rev 7 117/122 121

Revision history STM32F051x4 STM32F051x6 STM32F051x8 Table 76. Document revision history (continued) Date Revision Changes Added “Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection” in Section Functional susceptibility to I/O current injection. Replaced reference "JESD22-C101" with "ANSI/ESD STM5.3.1" in Table : ESD absolute maximum ratings. Merged Table: Typical and maximum VDD consumption in Stop and Standby modes and Table: Typical and maximum VDDA consumption in Stop and Standby modes into Table: Typical and maximum current consumption in Stop and Standby modes. Updated: – Table: Temperature sensor calibration values, – Table: Internal voltage reference calibration values, – Table: Current characteristics, – Table: General operating conditions, – Table: Typical and maximum current consumption from the VDDA supply, – Table: Low-power mode wakeup timings, – Table: I/O current injection susceptibility, – Table: I/O static characteristics, 4 13-Jan-2014 – Table: Output voltage characteristics, (continued) – Table: NRST pin characteristics, – Table: I2C analog filter characteristics, – Figure: Power supply scheme, – Figure: TC and TTa I/O input characteristics, – Figure: Five volt tolerant (FT and FTf) I/O input characteristics, – Figure: I/O AC characteristics definition, – Figure: ADC accuracy characteristics, – Figure: Typical connection diagram using the ADC, – Figure: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline, – Figure: LQFP64 recommended footprint, – Figure: LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline, – Figure: LQFP48 recommended footprint, – Figure: LQFP32 – 7 x 7 mm 32-pin low-profile quad flat package outline, – Figure: LQFP32 recommended footprint, – Figure: UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package outline. 118/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history (continued) Date Revision Changes Updated the following: – DAC and power management feature descriptions in Features – Table 2: STM32F051xx family device features and peripheral count – Section 3.5.1: Power supply schemes – Figure 13: Power supply scheme – Table 17: Voltage characteristics – Table 20: General operating conditions: updated the footnote for V parameter IN – Table 28: Typical and maximum current consumption from the V supply BAT – Table 52: ADC characteristics – Table 33: High-speed external user clock characteristics: replaced V with V DD DDIOX – Table 34: Low-speed external user clock characteristics: replaced V with V DD DDIOX – Table 37: HSI oscillator characteristics and Figure 19: HSI oscillator accuracy characterization results for soldered parts – Table 38: HSI14 oscillator characteristics: changed the min value for ACC HSI14 – Table 41: Flash memory characteristics: changed the values for t and I in write mode ME DD 28-Aug-2015 5 – Table 43: EMS characteristics: changed the value of V EFTB – Table 45: ESD absolute maximum ratings – Figure 10: STM32F051x8 memory map – Figure 21: TC and TTa I/O input characteristics – Figure 22: Five volt tolerant (FT and FTf) I/O input characteristics – Figure 23: I/O AC characteristics definition – t definition in Table 24: Embedded internal reference START voltage – t characteristics in Table 52: ADC characteristics STAB – Table 56: Comparator characteristics: changed the description and values for V , V and V SC DDA REFINT parameters. Added Figure 28: Maximum V scaler REFINT startup time from power down – Table 57: TS characteristics: changed the min value for T S- temp – Table 58: V monitoring characteristics: changed the min BAT value for T and the typical value for R parameters S-vbat – Section 6.3.22: Communication interfaces: updated the description and features in the subsection I2C interface characteristics – Table 64: I2S characteristics: updated the min values for data input hold time (master and slave receiver) DocID022265 Rev 7 119/122 121

Revision history STM32F051x4 STM32F051x6 STM32F051x8 Table 76. Document revision history (continued) Date Revision Changes – Table 31: Peripheral current consumption Addition of WLCSP36 package. Updates in: – Section 2: Description – Table 2: STM32F051xx family device features and peripheral count – Section 4: Pinouts and pin descriptions with the addition of Figure 7: WLCSP36 package pinout 5 28-Aug-2015 – Table 13: Pin definitions (continued) – Table 20: General operating conditions – Section 7: Package information with the addition of Section 7.5: WLCSP36 package information – Table 74: Package thermal characteristics – Section 8: Part numbering Update of the device marking examples in Section 7: Package information. Section 2: Description: – Table 2: STM32F051xx family device features and peripheral count - number of SPIs corrected for 64-pin packages – Figure 1: Block diagram modified Section 3: Functional overview: – Figure 2: Clock tree modified; divider for CEC corrected – Table 8: Comparison of I2C analog and digital filters - adding 20 mA information for FastPlus mode Section 4: Pinouts and pin descriptions: – Package pinout figures updated (look and feel) – Figure 7: WLCSP36 package pinout - now presented in top view – Table 13: Pin definitions - notes added (VSSA corrected to pin 16 on LQFP32); note 5 added Section 5: Memory mapping: 16-Dec-2015 6 – added information on STM32F051x4/x6 difference versus STM32F051x8 map in Figure 10 Section 6: Electrical characteristics: – Table 24: Embedded internal reference voltage - removed - 40°C-85°C temperature range line and the associated note – Table 48: I/O static characteristics - removed note – Section 6.3.16: 12-bit ADC characteristics - changed introductory sentence – Table 52: ADC characteristics updated and table footnotes 3 and 4 added – Table 56: Comparator characteristics - VDDA min modified – Table 59: TIMx characteristics modified – Table 64: I2S characteristics reorganized – Figure 52: UFQFPN32 package outline - figure footnotes added 120/122 DocID022265 Rev 7

STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history (continued) Date Revision Changes Section 6: Electrical characteristics: – Table 36: LSE oscillator characteristics (f = 32.768 kHz) - LSE information on configuring different drive capabilities removed. See the corresponding reference manual. – Table 24: Embedded internal reference voltage - V REFINT values 06-Jan-2017 7 – Table 55: DAC characteristics - min. R to V defined LOAD DDA – Figure 29: SPI timing diagram - slave mode and CPHA = 0 and Figure 30: SPI timing diagram - slave mode and CPHA = 1 enhanced and corrected Section 8: Ordering information: – The name of the section changed from the previous “Part numbering” DocID022265 Rev 7 121/122 121

STM32F051x4 STM32F051x6 STM32F051x8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 122/122 DocID022265 Rev 7