STL60N32N3LL Ω Dual N-channel 30 V, 0.005 , 15 A PowerFLAT™ 5x6 asymmetrical double island, STripFET™ Power MOSFET Features Order code V R I DSS DS(on) D Q 30 V < 0.0092 Ω 13.6 A 4 1 3 STL60N32N3LL 2 Q 30 V < 0.0055 Ω 15 A 1 D1 S2 2 S1/D2 ■ RDS(on) * Qg industry benchmark G1 6 5 7 ■ Extremely low on-resistance RDS(on) G2 8 ■ Very low switching gate charge PowerFLAT™5x6 asymmetrical double island ■ High avalanche ruggedness ■ Low gate drive power losses Application ■ Switching applications Figure 1. Internal schematic diagram Description (cid:21) (cid:51)(cid:18) (cid:49)(cid:18) (cid:36)(cid:17) (cid:20) This device is a dual N-channel Power MOSFET which utilizes the latest generation of design rules for ST's proprietary STripFET™ V and (cid:22) (cid:51)(cid:18) (cid:36)(cid:17) (cid:19) STripFET™ VI DeepGATE™ technology. The lowest available RDS(on)* Qg in this chip scale package renders the device suitable for the most (cid:23) (cid:51)(cid:18) (cid:36)(cid:17) (cid:18) demanding DC-DC converter applications, where high power density is required. (cid:49)(cid:17) (cid:24) (cid:39)(cid:18) (cid:39)(cid:17) (cid:17) (top view) (cid:33)(cid:45)(cid:16)(cid:19)(cid:24)(cid:19)(cid:23)(cid:86)(cid:17) Table 1. Device summary Order code Marking Package Packaging PowerFLAT™5x6 STL60N32N3LL 60N32N3LL Tape and reel asymmetrical double island February 2012 Doc ID 17266 Rev 3 1/14 www.st.com 14

Contents STL60N32N3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Graphs for Q1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 Graphs for Q2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 Doc ID 17266 Rev 3

STL60N32N3LL Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Type Value Unit Q 30 V V Drain-source voltage 1 DS Q 30 V 2 Q ± 20 V V Gate- source voltage 1 GS Q ± 20 V 2 Q 32 A I (1) Drain current (continuous) at T = 25 °C 1 D C Q 60 A 2 Drain current (continuous) at Q 23 A I (1) 1 D T = 100 °C Q 37 A C 2 I (2) Drain current (continuous) at Q1 13.6 A D Tpcb = 25 °C Q2 15 A Drain current (continuous) at Q 8.5 A I (2) 1 D T = 100 °C Q 9.3 A pcb 2 Q 54.4 A I (2),(3) Drain current (pulsed) 1 DM Q 60 A 2 Q 23 W P (1) Total dissipation at T = 25 °C 1 TOT C Q 50 W 2 Q 3.12 W P (2) Total dissipation at T = 25 °C 1 TOT pcb Q 3.12 W 2 T Operating junction temperature j -55 to 150 °C T Storage temperature stg 1. This value is according toR thj-c 2. This value is according toR thj-pcb 3. Pulse width limited by safe operating area Table 3. Thermal data Symbol Parameter Type Value Unit R (1) Thermal resistance junction-pcb max 40 °C/W thj-pcb Q 5.5 R Thermal resistance junction-case 1 °C/W thj-c Q 2.5 2 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Doc ID 17266 Rev 3 3/14

Electrical characteristics STL60N32N3LL 2 Electrical characteristics (T =25°C unless otherwise specified) CASE Table 4. On/off states Symbol Parameter Test conditions Type Min. Typ. Max. Unit Drain-source Q 30 V V I = 250 µA, V = 0 1 (BR)DSS Breakdown voltage D GS Q 30 V 2 Zero gate voltage Q 1 µA I V = 30 V 1 DSS Drain current (V = 0) DS Q 1 µA GS 2 Zero gate voltage Q 10 µA I V =30 V, T =125°C 1 DSS Drain current (V = 0) DS C Q 10 µA GS 2 Gate-body leakage Q ±100 nA I V = ± 20 V 1 GSS current (V = 0) GS Q ±100 nA DS 2 V = V , Q 1 V V Gate threshold voltage DS GS 1 GS(th) I = 250 µA Q 1 V D 2 R Static drain-source on VGS = 10 V, ID = 6.8 A Q1 0.0085 0.0092 Ω DS(on) resistance V = 10 V, I = 7.5 A Q 0.005 0.0055 Ω GS D 2 R Static drain-source on VGS = 4.5 V, ID = 6.8 A Q1 0.0109 0.012 Ω DS(on) resistance V = 4.5 V, I = 7.5 A Q 0.0065 0.0073 Ω GS D 2 Table 5. Dynamic Symbol Parameter Test conditions Type Min. Typ. Max. Unit Q 950 pF C Input capacitance 1 - - iss Q 1690 pF 2 V = 25 V, f = 1 MHz, Q 193 pF C Output capacitance DS 1 - - oss V = 0 Q 291 pF GS 2 C Reverse transfer Q1 - 27.6 - pF rss capacitance Q 176 pF 2 Q 6.6 nC Q Total gate charge 1 - - g Q 17 nC 2 V = 15 V, I = 15 A, DD D Q 3.3 nC Q Gate-source charge V = 4.5 V 1 - - gs GS Q 8 nC (see Figure 25) 2 Q 2.4 nC Q Gate-drain charge 1 - - gd Q 6 nC 2 4/14 Doc ID 17266 Rev 3

STL60N32N3LL Electrical characteristics T able 6. Switching times Symbol Parameter Test conditions Type Min. Typ. Max. Unit t V =15 V, I =7.5 A, Q 10.8 ns d(on) DD D 1 Turn-on delay time R =4.7 Ω, Q 9.5 ns G 2 - - t Rise time V = 4.5 V Q 15.6 ns r GS 1 (see Figure 29) Q 30 ns 2 t V =15 V, I =7.5 A, Q 14.2 ns d(off) DD D 1 Turn-off delay time RG=4.7 Ω, Q2 - 37 - ns t Fall time V = 4.5V Q 6 ns f GS 1 (see Figure 29) Q 12 ns 2 T able 7. Source drain diode Symbol Parameter Test conditions Type Min. Typ. Max. Unit V =15 V, I =7.5 A DD D Q 13.6 A I Source-drain current R =4.7 Ω, 1 - SD G Q 15 A V =4.5 V 2 GS V =15 V, I = 7.5 A I (1) Source-drain current RDD=4.7 Ω, D Q1 - 54.4 A SDM (pulsed) G Q 60 A V =4.5 V 2 GS Q 1.1 V V (2) Forward on voltage I = 15 A, V = 0 1 - SD SD GS Q 1.1 V 2 t Reverse recovery time Q 20 ns rr I = 15 A, 1 SD Q 24 ns V = 15 V 2 Q Reverse recovery charge DD Q 10 nC rr di/dt = 100 A/µs, 1 - Q 16.8 nC T = 150°C 2 I Reverse recovery current j Q 1 A RRM (see Figure 29) 1 Q 1.4 A 2 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Doc ID 17266 Rev 3 5/14

Electrical characteristics STL60N32N3LL 2.1 Electrical characteristics (curves) 2.1.1 Graphs for Q1 Figure 2. Safe operating area Figure 3. Thermal impedance ID AM11199v1 K PCB_PowerFLAT (A) Tj=150°C Tc=25°C 11000 OpLiermiattieodn ibny tmhias x arReDaS (iosn) 1S0in0glme psulse 11000-1 00δ..1=20.5 0.05 1 10ms 10-2 0.02 1s 0.01 0.1 10-3 Single pulse 0.01 10-4 0.1 1 10 VDS(V) 10-3 10-2 10-1 100 101 102 tp(s) Figure 4. Output characteristics Figure 5. Transfer characteristics AM11200v1 AM11201v1 ID ID (A) (A) 4V 50 50 VDS=3V 40 40 30 30 20 20 3V 10 10 0 0 0 1 2 3 4 VDS(V) 0 1 2 3 4 VGS(V) Figure 6. Normalized B vs temperature Figure 7. Static drain-source on resistance VDSS BVDSS AM11202v1 RDS(on) AM11203v1 (norm) (mΩ) 1.12 VGS=10V ID=1mA 12.5 1.08 10.5 1.04 8.5 1.00 0.96 6.5 0.92 4.5 -25 25 75 125 TJ(°C) 2 4 6 8 10 12 ID(A) 6/14 Doc ID 17266 Rev 3

STL60N32N3LL Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations VGS AM11204v1 C AM11205v1 (V) (pF) VDD=15V 1410 10 ID=13.6A 1210 8 1010 Ciss 6 810 610 4 410 2 210 Coss 0 10 Crss 0 2 4 6 8 10 12 14 Qg(nC) 0 10 20 VDS(V) Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs vs temperature temperature VGS(th) AM11206v1 RDS(on) AM11207v1 (norm) (norm) ID=250µA 1.2 1.8 1.6 1.0 1.4 0.8 1.2 0.6 1.0 0.4 0.8 0.2 0.6 0 0.4 -25 25 75 125 TJ(°C) -25 25 75 125 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD AM11208v1 (V) TJ=-55°C 0.9 TJ=25°C 0.8 0.7 TJ=175°C 0.6 0.5 0.4 2 4 6 8 10 12 ISD(A) Doc ID 17266 Rev 3 7/14

Electrical characteristics STL60N32N3LL 2.1.2 Graphs for Q2 Figure 13. Safe operating area Figure 14. Thermal impedance ID AM11209v1 K PCB_PowerFLAT (A) Tj=150°C Tc=25°C 11000 OpLiermiattieodn ibny tmhias x arReDaS (iosn) 1S0in0glme psulse 11000-1 00δ..1=20.5 0.05 1 10ms 10-2 0.02 1s 0.01 0.1 10-3 Single pulse 0.01 10-4 0.1 1 10 VDS(V) 10-3 10-2 10-1 100 101 102 tp(s) Figure 15. Output characteristics Figure 16. Transfer characteristics AM11210v1 AM11211v1 ID ID (A) (A) 60 60 4V VDS=3V 50 50 40 40 3V 30 30 20 20 10 10 0 0 0 1 2 3 4 5 VDS(V) 0 1 2 3 4 VGS(V) Figure 17. Normalized B vs temperature Figure 18. Static drain-source on resistance VDSS BVDSS AM11212v1 RDS(on) AM11213v1 (norm) (mΩ) VGS=10V ID=1mA 1.04 8 1.00 6 0.96 4 0.92 2 -25 25 75 125 TJ(°C) 0 2 4 6 8 10 ID(A) 8/14 Doc ID 17266 Rev 3

STL60N32N3LL Electrical characteristics Figure 19. Gate charge vs gate-source voltage Figure 20. Capacitance variations VGS AM11214v1 C AM11215v1 (V) (pF) VDD=15V 12 ID=15A 1600 10 Ciss 1100 8 6 600 4 100 2 Coss Crss 0 0 5 10 15 20 25 30 35 Qg(nC) 0 10 20 VDS(V) Figure 21. Normalized gate threshold voltage Figure 22. Normalized on resistance vs vs temperature temperature VGS(th) AM11216v1 RDS(on) AM11217v1 (norm) (norm) ID=250µA 1.2 1.6 1.1 1.4 1.0 0.9 1.2 0.8 1.0 0.7 0.8 0.6 0.6 0.5 0.4 0.4 -25 25 75 125 TJ(°C) -75 -25 25 75 125 175 TJ(°C) Figure 23. Source-drain diode forward characteristics VSD AM11218v1 (V) 0.9 TJ=-55°C 0.8 TJ=25°C 0.7 0.6 TJ=175°C 0.5 0.4 0 2 4 6 8 10 ISD(A) Doc ID 17266 Rev 3 9/14

Test circuits STL60N32N3LL 3 Test circuits Figure 24. Switching times test circuit for Figure 25. Gate charge test circuit resistive load VDD 12V 47kΩ 1kΩ 100nF RL 2μ20F0 3μ.F3 VDD IG=CONST VD Vi=20V=VGMAX 100Ω D.U.T. VGS 2200 RG D.U.T. μF 2.7kΩ VG PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 26. Test circuit for inductive load Figure 27. Unclamped inductive load test switching and diode recovery times circuit L A A A D FAST L=100μH VD G D.U.T. DIODE 2200 3.3 μF μF VDD S B 3.3 1000 B B μF μF 25Ω D VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 28. Unclamped inductive waveform Figure 29. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf 90% 90% IDM 10% ID 0 10% VDS VDD VDD 90% VGS AM01472v1 0 10% AM01473v1 10/14 Doc ID 17266 Rev 3

STL60N32N3LL Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. PowerFLAT™ 5x6 asymmetrical double island dimentions mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.05 b 0.45 0.55 D 4.90 5.00 5.10 E 5.90 6.00 6.10 e 1.27 L 0.40 0.60 aaa 0.10 bbb 0.10 ccc 0.10 Doc ID 17266 Rev 3 11/14

Package mechanical data STL60N32N3LL Figure 30. Package drawing 8202594_Rev_B Figure 31. Recommended footprint (dimensions are in mm) footprint 12/14 Doc ID 17266 Rev 3

STL60N32N3LL Revision history 5 Revision history T able 9. Document revision history Date Revision Changes 15-Mar-2010 1 First release Document status promoted from target specification to preliminary 07-Feb-2011 2 data. Document status promoted from preliminary data to datasheet. Section2.1: Electrical characteristics (curves) has been added. 21-Feb-2012 3 Section4: Package mechanical data has been updated. Minor text changes. Doc ID 17266 Rev 3 13/14

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