STL140N4LLF5 N-channel 40 V, 2.2 mΩ typ., 32 A STripFET™ F5 Power MOSFET in a PowerFLAT™ 5x6 package Datasheet - production data Features Order code VDS RDS(on) max. ID STL140N4LLF5 40 V 2.75 mΩ 32 A  Low on-resistance R DS(on)  High avalanche ruggedness  Low gate drive power loss Applications  Switching applications Description Figure 1: Internal schematic diagram This N-channel Power MOSFET is developed using the STripFET™ F5 technology and has been optimized to achieve very low on-state resistance, contributing to a FoM that is among the best in its class. Table 1: Device summary Order code Marking Package Packing STL140N4LLF5 140N4LF5 PowerFLAT™ 5x6 Tape and reel August 2017 DocID17586 Rev 4 1/14 This is information on a product in full production. www.st.com

Contents STL140N4LLF5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 PowerFLAT™ 5x6 type C package information ................................ 9 4.2 PowerFLAT™ 5x6 packing information ........................................... 11 5 Revision history ............................................................................ 13 2/14 DocID17586 Rev 4

STL140N4LLF5 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ±22 V ID(1) Drain current (continuous) at TC = 25 °C 140 A ID(1) Drain current (continuous) at TC = 100 °C 88 A ID(2) Drain current (continuous) at Tpcb = 25 °C 32 A ID(2) Drain current (continuous) at Tpcb = 100 °C 20 A IDM(3) Drain current (pulsed) 128 A PTOT(1) Total dissipation at TC = 25 °C 80 W PTOT(2) Total dissipation at Tpcb = 25 °C 4 W Tstg Storage temperature range -55 to 150 °C Tj Operating junction temperature range Notes: (1)This value is rated according to Rthj-case. (2)This value is rated according to Rthj-pcb. (3)Pulse width limited by safe operating area. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 1.56 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2 oz Cu t <10 sec Table 4: Avalanche characteristics Symbol Parameter Value Unit Not-repetitive avalanche current, IAV (pulse width limited by Tjmax) 16 A Single pulse avalanche energy EAS (starting TJ = 25 °C, ID = IAV, VDD = 24 V) 300 mJ DocID17586 Rev 4 3/14

Electrical characteristics STL140N4LLF5 2 Electrical characteristics T = 25 °C unless otherwise specified C Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown V(BR)DSS voltage VGS = 0 V, ID = 250 µA 40 V VGS = 0 V, VDS = 40 V 1 µA Zero gate voltage drain IDSS current VGS = 0 V, VDS = 40 V, 10 µA TC= 125 °C (1) Gate body leakage IGSS current VDS = 0 V, VGS= ±22 V ±100 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1 V Static drain-source VGS = 10 V, ID = 16 A 2.2 2.75 mΩ RDS(on) on-resistance VGS = 4.5 V, ID = 16 A 2.4 3.1 mΩ Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 5900 - pF Coss Output capacitance VDS = 25 V, f = 1 MHz, - 870 - pF Reverse transfer VGS = 0 V Crss capacitance - 130 - pF Qg Total gate charge VDD = 15 V, ID = 32 A - 45 - nC Qgs Gate-source charge VGS= 0 to 4.5 V, - 14 - nC see ( Figure 14: "Test circuit Qgd Gate-drain charge for gate charge behavior") - 17 - nC f=1 MHz, RG Gate input resistance gate DC bias = 0 V, test signal - 1.2 - Ω level = 20 mV, ID = 0 A Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD= 15 V, ID = 16 A, - 19 - ns tr Rise time RG = 4.7 Ω - 29 - ns VGS = 10 V, td(off) Turn-off delay time (see Figure 13: "Test circuit for - 90 - ns resistive load switching times" tf Fall time and Figure 18: "Switching time - 21 - ns waveform") 4/14 DocID17586 Rev 4

STL140N4LLF5 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Forward on voltage - 32 A Source-drain current ISDM(1) (pulsed) - 128 A VSD(2) Forward on voltage ISD = 32 A, VGS=0 V - 1.1 V trr Reverse recovery time ISD = 32 A, di/dt = 100 A/μs, - 44 ns Qrr Reverse recovery charge V(sDeDe= F2i5g uVre 15: "Test circuit for - 57 nC inductive load switching and IRRM Reverse recovery current diode recovery times") - 2.6 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration=300μs, duty cycle 1.5%. DocID17586 Rev 4 5/14

Electrical characteristics STL140N4LLF5 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance K 10-1 10-2 10-3 10-4 10-3 10-2 10-1 100 101 102 tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/14 DocID17586 Rev 4

STL140N4LLF5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source- drain diode forward characteristics DocID17586 Rev 4 7/14

Test circuits STL140N4LLF5 3 Test circuits Figure 13: Test circuit for resistive load Figure 14: Test circuit for gate charge switching times behavior Figure 15: Test circuit for inductive load Figure 16: Unclamped inductive load test switching and diode recovery times circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform 8/14 DocID17586 Rev 4

STL140N4LLF5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 PowerFLAT™ 5x6 type C package information Figure 19: PowerFLAT™ 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_A0ER_Rev15 DocID17586 Rev 4 9/14

Package information STL140N4LLF5 Table 9: PowerFLAT™ 5x6 type C package mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 4.45 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 1.27 E 5.95 6.15 6.35 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 0.15 0.25 θ 0° 12° Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_15 10/14 DocID17586 Rev 4

STL140N4LLF5 Package information 4.2 PowerFLAT™ 5x6 packing information Figure 21: PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. Base and bulk quantity 3000 pcs All dimensions are in millimeters (II) Cumulative tolerance of 10 sprocket holes is ±0.20. (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape DocID17586 Rev 4 11/14

Package information STL140N4LLF5 Figure 23: PowerFLAT™ 5x6 reel 12/14 DocID17586 Rev 4

STL140N4LLF5 Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 03-Jun-2010 1 First release. 29-Apr-2011 2 Document status promoted from preliminary data to datasheet. Section 4: Package mechanical data has been updated. 10-Nov-2011 3 Minor text changes. Modified Table 1: "Device summary". 08-Aug-2017 4 Updated Section 5: "Package information". Minor text changes. DocID17586 Rev 4 13/14

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