STF8NK100Z STP8NK100Z Ω N-CHANNEL 1000V - 1.60 - 6.5A - TO-220 - TO-220FP Zener-Protected SuperMESH™ MOSFET General features Type VDSS RDS(on) ID Pw STF8NK100Z 1000 V <1.85Ω 6.5 ANote1 40 W STP8NK100Z 1000 V <1.85Ω 6.5 A 160 W ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE RATED 123 123 ■ IMPROVED ESD CAPABILITY TO-220 TO-220FP ■ VERY LOW INTRINSIC CAPACITANCE Description Internal schematic diagram The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Applications ■ HIGH CURRENT,SWITCHING APPLICATION ■ IDEAL FOR OFF-LINE POWER SUPPLIES Order codes Sales Type Marking Package Packaging STF8NK100Z F8NK100Z TO-220FP TUBE STP8NK100Z P8NK100Z TO-220 TUBE Rev 1 November 2005 1/13 www.st.com 13

1 Electrical ratings STF8NK100Z - STP8NK100Z 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit TO-220 TO-220FP VDS Drain-source Voltage (VGS=0) 1000 V VDGR Drain-gate Voltage 1000 V VGS Gate-Source Voltage ± 30 V ID Note1 Drain Current (continuous) at TC = 25°C 6.5 6.5 A ID Drain Current (continuous) at TC = 100°C 4.3 4.3 A IDM Note2 Drain Current (pulsed) 16 16 A PTOT Total Dissipation at TC = 25°C 160 40 W Derating Factor 1.28 0.32 W/°C VESD(G-S) Gate source ESD (HBM-C=100pF, R=1.5KΩ) 4000 V dv/dt Note3 Peak Diode Recovery voltage slope 4.5 V/ns VISO Insulation Withstand Voltage (DC) -- 2500 V Tj Operating Junction Temperature -55 to 150 °C T Storage Temperature stg Table 2. Thermal data TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 0.78 3.1 °C/W Rthj-a Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Tl Purpose 300 °C Table 3. Avalanche Characteristics Symbol Parameter Value Unit Avalanche Current, Repetitive or IAR Not-Repetitive (pulse width limited by Tj max) 6.5 A Single Pulse Avalanche Energy EAS (starting Tj= 25°C, I =I , V =50V) 320 mJ D AR DD 2/13

STF8NK100Z - STP8NK100Z 2 Electrical characteristics 2 Electrical characteristics (T = 25 °C unless otherwise specified) CASE Table 4. On/off states Symbol Parameter Test Conditions Min. Typ. Max. Unit Drain-Source Breakdown V(BR)DSS Voltage ID = 1mA, VGS= 0 1000 V Zero Gate Voltage Drain VDS = Max Rating, 1 µA I DSS Current (VGS = 0) VDS = Max Rating,Tc = 125°C 50 µA Gate Body Leakage Current IGSS (V = 0) VGS = ±20V ±10 µA DS VGS(th) Gate Threshold Voltage VDS= VGS, ID = 100 µA 3 3.75 4.5 V Static Drain-Source On RDS(on) Resistance VGS= 10 V, ID= 3.15 A 1.60 1.85 Ω Table 5. Dynamic Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs Note6 Forward Transconductance VDS =15V, ID=3.15 A 7 S Ciss Input Capacitance 2180 pF Coss Output Capacitance VDS =25V, f=1 MHz, VGS=0 174 pF C Reverse Transfer Capacitance 36 pF rss CNoostse e5q. ECqaupiavcailteanntc Oeutput VGS=0V, VDS=0 to 800V 83 pF Qg Total Gate Charge VDD=800V, ID = 6.3A 73 102 nC Qgs Gate-Source Charge VGS =10V 12 nC Qgd Gate-Drain Charge (see Figure 17) 40 nC 3/13

2 Electrical characteristics STF8NK100Z - STP8NK100Z Table 6. Switching times Symbol Parameter Test Conditions Min. Typ. Max. Unit V =500 V, I = 3.15 A, td(on) Turn-on Delay Time RDD=4.7Ω, V D=10V 28 ns t Rise Time G GS 19 ns r (see Figure 18) V =500 V, I =3.15 A, td(off) Turn-off Delay Time RDD=4.7Ω, V D=10V 59 ns t FallTime G GS 30 ns f (see Figure 18) Table 7. Source drain diode Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 6.5 A I Note3 Source-drain Current (pulsed) 26 A SDM VSDNote2 Forward on Voltage ISD=6.3A, VGS=0 1.6 V trr Reverse Recovery Time 620 ns I =6.3A, di/dt = 100A/µs, Qrr Reverse Recovery Charge VSD =50 V, Tj=25°C 5.3 µC DD I Reverse Recovery Current 17 A RRM trr Reverse Recovery Time 840 ns I =6.3A, di/dt = 100A/µs, Qrr Reverse Recovery Charge VSD =50 V, Tj=150°C 7.5 µC DD I Reverse Recovery Current 18 A RRM Table 8. Gate-source zener diode Symbol Parameter Test Conditions Min. Typ. Max. Unit BVGSO Gate-Source Breakdown Igs = ± 1mA (Open Drain) 30 V Note4 Voltage (1) Limited only by maximum temperature allowed (2)I ≤ 6.5 A, di/dt ≤ 200A/µs, V ≤ V Tj≤ Tjmax SD DS (BR)DSS, (3) Pulse width limited by safe operating area (4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device’s ESD capability, but also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. (5) C is defined as a constant equivalent capacitance giving the same charging time as C when V increases from 0 oss eq. oss DS to 80% V DSS (6) Pulsed: pulse duartion = 300µs, duty cycle 1.5% 4/13

STF8NK100Z - STP8NK100Z 2 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 1. Safe Operating Area for TO-220 Figure 2. Thermal Impedance for TO-220 Figure 3. Safe Operating Area for TO-220FP Figure 4. Thermal Impedance for TO-220FP Figure 5. Output Characteristics Figure 6. Transfer Characteristics 5/13

2 Electrical characteristics STF8NK100Z - STP8NK100Z Figure 7. Transconductance Figure 8. Static Drain-source on Resistance Figure 9. Gate Charge vs Gate-source Volatge Figure 10. Capacitance Variations Figure 11. Normalized Gate Threshold Voltage Figure 12. Normalized On Resistance vs. vs. Temperature Temperature 6/13

STF8NK100Z - STP8NK100Z 2 Electrical characteristics Figure 13. Source-drain Diode Forward Figure 14. Normalized BVDSS vs Temperature Characteristics Figure 15. Maximum Avalanche Energy vs Temperature 7/13

3 Test circuits STF8NK100Z - STP8NK100Z 3 Test circuits Figure 16. Switching Times Test Circuit For Figure 17. Gate Charge Test Circuit Resistive Load Figure 18. Test Circuit For Indictive Load Figure 20. Unclamped Inductive Load Test Switching and Diode Recovery Circuit Times Figure 19. Unclamped Inductive Waveform 8/13

STF8NK100Z - STP8NK100Z 4 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13

4 Package mechanical data STF8NK100Z - STP8NK100Z TO-220FP MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 E A D B L3 L6 L7 1 F F 1 G H G 2 F 1 2 3 L5 L2 L4 10/13

STF8NK100Z - STP8NK100Z 4 Package mechanical data TO-220 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L30 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 11/13

5 Revision History STF8NK100Z - STP8NK100Z 5 Revision History Date Revision Changes 04-Nov-2005 1 First release 12/13

STF8NK100Z - STP8NK100Z 5 Revision History Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: STF8NK100Z STP8NK100Z