STEF12 Electronic fuse for 12 V line Datasheet - production data Description The STEF12 is an integrated electronic fuse optimized for monitoring output current and input voltage. Connected in series to a 12 V rail, it is capable of protecting the electronic circuitry on its output from overcurrent and overvoltage. The DFN10 (3x3 mm) device has a controlled delay and turn-on time. When an overload condition occurs, the STEF12 limits the output current to a predefined safe value. If the anomalous overload condition Features persists it goes into an open state, disconnecting the load from the power supply. If a continuous • Continuous current (typ): 3.6 A short-circuit is present on the board, when power • N-channel on-resistance (typ): 53 mΩ is re-applied the E-fuse initially limits the output • Enable/Fault functions current to a safe value and then again goes into an open state. The device is equipped with a • Output clamp voltage (typ):15 V thermal protection circuit. The intervention of the • Undervoltage lockout thermal protection is signalled to the board • Short-circuit limit monitoring circuits through a signal on the Fault pin. Unlike the mechanical fuses, which must be • Overload current limit physically replaced after a single event, the E- • Controlled output voltage ramp fuse does not degrade in its performance after • Thermal latch (typ): 165 °C short-circuit/thermal protection interventions and it is reset either by recycling the supply voltage or • Uses tiny capacitors using the Enable pin. The companion chip for the • Operating junction temp. - 40 °C to 125 °C 5 V power rails is also available with part number • Available in DFN10 (3x3 mm) package STEF05. Applications • Hard disk drives • Solid state drives (SSD) • Hard disk and SSD arrays • Set-top boxes • DVD and Blu-ray disc drivers Table 1. Device summary Order code Package Packing STEF12PUR DFN10 (3x3 mm) Tape and reel August 2015 DocID019056 Rev 6 1/20 This is information on a product in full production. www.st.com

Contents STEF12 Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 R limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Enable/Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 DFN10L (3x3 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 DFNxx (3x3 mm) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 DocID019056 Rev 6

STEF12 Device block diagram 1 Device block diagram Figure 1. STEF12 block diagram AM09891v1 DocID019056 Rev 6 3/20 20

Pin configuration STEF12 2 Pin configuration Figure 2. Pin configuration (top view) GND Source dv/dt Source V En/fault Source CC I-Limit Source N/C Source AM09880v1 Table 2. Pin description Pin n° Symbol Note 1 GND Ground pin The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1ms. An external capacitor can be 2 dv/dt added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. 3 En/Fault If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. A resistor between this pin and the Source pin sets the overload and short-circuit current 4 I-Limit limit levels. 5 NC Not connected Connected to the source of the internal power MOSFET and to the output terminal of the 6 to 10 V /Source OUT fuse 11 V Exposed pad. Positive input voltage must be connected to V . CC CC 4/20 DocID019056 Rev 6

STEF12 Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit Positive power supply voltage (steady state) -0.3 to 18 V V CC Positive power supply voltage (max 100ms) -0.3 to 25 V /source (max 100ms) -0.3 to Vcc+0.3 V OUT I-Limit (max 100ms) -0.3 to 25 V En/Fault -0.3 to 7 V dv/dt -0.3 to 7 V T Operating junction temperature range (1) -40 to 125 °C op T Storage temperature range -65 to 150 °C STG T Lead temperature (soldering) 10 sec 260 °C LEAD 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit R Thermal resistance junction-ambient 52.7 °C/W thJA R Thermal resistance junction-case 17.4 °C/W thJC Table 5. ESD performance Symbol Parameter Test conditions Value Unit HBM 2 kV ESD ESD protection MM 200 V CDM 500 V DocID019056 Rev 6 5/20 20

Electrical characteristics STEF12 4 Electrical characteristics V = 12 V, V = 3.3 V, C = 10 µF, C = 47 µF, T = 25 °C (unless otherwise specified). CC EN I O J Table 6. Electrical characteristics for STEF12 Symbol Parameter Test Conditions Min. Typ. Max. Unit Under/Overvoltage protection V Output clamping voltage V = 18 V 13.8 15 16.2 V Clamp CC V Undervoltage lockout Turn-on, voltage rising 7.7 8.5 9.3 V UVLO V UVLO hysteresis 0.80 V Hyst Power MOSFET Enabling of chip to I = 100 mA t Delay time D 350 µs dly with a 1 A resistive load (1) 35 53 70 R On-resistance mΩ DSon - 40 °C < T < 125 °C (2) 82 J V = 18 V, V = 0, R = V Off state output voltage CC GS L 40 100 mV OFF infinite 0.5in2 pad, T = 25 °C (1) 3.6 A I Continuous current A D Minimum copper, T = 80 °C 1.7 A Current limit I Short-circuit current limit R = 22 Ω 3.3 4.4 5.5 A Short Limit I Overload current limit R = 22 Ω 4.4 A Lim Limit dv/dt circuit Enable to V = 11.7 V, No dv/dt Output voltage ramp time OUT 0.5 0.9 2.6 ms C dv/dt Enable/Fault V Low level input voltage Output disabled 0.35 0.58 0.81 V IL V Intermediate level input voltage Thermal fault, output disabled 0.82 1.4 1.95 V I(INT) V High level input voltage Output enabled 1.96 2.64 3.3 V IH V High state maximum voltage 3.4 4.3 5.4 V I(MAX) I Low level input current (sink) V = 0 V -10 -30 µA IL Enable High level leakage current for I V = 3.3 V 1 µA I external switch Enable Total numbers of chips that can Maximum fan-out for fault signal be connected to this pin for 3 Units simultaneous shutdown 6/20 DocID019056 Rev 6

STEF12 Electrical characteristics Table 6. Electrical characteristics for STEF12 (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit Total device Device operational 1.5 2 I Bias current mA Bias Thermal shutdown 1 V Minimum operating voltage 7.6 V min Thermal latch TSD Shutdown temperature (1) 165 °C 1. Pulse test: Pulse width = 300 µs, Duty cycle = 2% 2. Guaranteed by design, but not tested in production DocID019056 Rev 6 7/20 20

Typical application STEF12 5 Typical application Figure 3. Application circuit Figure 4. Typical HDD application circuit 5.1 Operating modes 5.1.1 Turn-on When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry. After an initial delay time of typically 350 µs, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1 ms (refer to Figure5, 15) 8/20 DocID019056 Rev 6

STEF12 Typical application 5.1.2 Normal operating condition The STEF12 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET R . DSOn 5.1.3 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 15 V, if the input voltage exceeds this threshold. 5.1.4 Current limiting When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor R (Figure3). Limit 5.1.5 Thermal shutdown If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set at an intermediate voltage, in order to signal the overtemperature event. In this condition the E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the V threshold and then releasing it. il 5.2 R limit calculation As shown in Figure3, the device uses an internal N-channel sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user. The R value for achieving the requested current limitation can be estimated by using the Limit following theoretical formula, together with the graph in Figure13: Current limit vs. RLimit. Equation 1 95 RLimit = -------------- IShort 5.3 C calculation dv/dt Connecting a capacitor between the C pin and GND allows the modification of the dv/dt output voltage ramp-up time. Given the desired time interval Δt during which the output voltage goes from zero to its maximum value, the capacitance to be added on the C pin can be calculated using the dv/dt following theoretical formula: Equation 2 C = 3.92×10–8Δt–35.3×10–12 dv⁄dt Where C is expressed in Farads and the time in seconds. dv/dt DocID019056 Rev 6 9/20 20

Typical application STEF12 The addition of an external C influences also the initial delay time, defined as the time dv/dt between the Enable signal going high and the start of the V slope (Figure5). OUT The contribution of the external capacitor to this time interval can be estimated by using the following theoretical formula: Equation 3 delay time [s] = 35×10–5+71×105×C [F] dvdt Figure 5. Delay time and V ramp-up time OUT AM09882v1 12 En/Fault delay ramp-up 10 VOUT time time 8 V 6 4 2 0 Time 5.4 Enable/Fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. When it is used as a standard Enable pin, it should be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it turns the output of the E-Fuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept ON, in normal operating conditions. In case of thermal fault, the pin is pulled to an intermediate state (Figure6). This signal can be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can be directly connected to the Enable/Fault pins of other STEFxx devices on the same application in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the V threshold and then releasing it. il 10/20 DocID019056 Rev 6

STEF12 Typical application Figure 6. Enable/Fault pin status 5 Normal operating condition 4 ] V [ e g a 3 t ol v t ul a 2 F N/ Thermal fault condition E 1 Off/Reset 0 time AM09871v1 DocID019056 Rev 6 11/20 20

Typical performance characteristics STEF12 6 Typical performance characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at T = 25 °C. A Figure 7. C lamping voltage vs. temperature Figure 8. UVLO voltage vs. temperature 16.5 AM09883v1 9.5 AM09884v1 VCC = 18 V 9.3 VCC= from 0 to 12 V, RLIMIT = 15 Ω 16 9.1 8.9 15.5 V) V) Output Voltage ( 141.55 UVLO Voltage ( 888...357 8.1 7.9 14 7.7 13.5 7.5 -40 -25 0 25 55 85 125 150 -40 -25 0 25 55 85 125 150 Temperature °C Temperature °C Figure 9. UVLO hysteresis vs. temperature Figure 10. Off-state voltage vs. temperature 1.4 AM09885v1 250 AM09886v1 VCCfrom 12 to 0 V, RLIMIT= 15 Ω VCC = 18 V, VGS = 0, RL = infinite 1.2 200 UVLO Hysteresys(V) 00..168 Output Voltage (mV) 110500 50 0.4 0.2 0 -40 -25 0 25 55 85 125 150 -40 -25 0 25 55 85 125 150 Temperature °C Temperature °C Figure 11. Bias current (device operational) Figure 12. ON resistance vs. temperature 3 AM09887v1 90 AM09888v1 VCC= 12 V, RLIMIT = 15 Ω 80 VCC = 12 V, RLIMIT = 15 Ω, ILOAD = 1 A 2.5 70 2 Current (mA) 1.5 ΩRON (m)DS 5600 1 40 0.5 30 0 20 -40 -25 0 25 55 85 125 150 -40 -25 0 25 55 85 125 Temperature °C Temperature °C 12/20 DocID019056 Rev 6

STEF12 Typical performance characteristics Figure 13. Current limit vs. R Figure 14. Thermal latch delay vs. power Limit AM09890v1 9.00 AM09889v1 800 VCC = 12 V, T = 25 °C 8.00 Limit & Short Current (A) 234567......000000000000 IISLIHMORT Thermal Action Time (ms) 808 TTT===258555 °°°CCC 1.00 0.00 0 10 20 30 40 50 60 70 80 0.8 External Sensing Resistor (Ω) 0 10 20 30 40 50 60 Power (W) Figure 15. V ramp-up vs. Enable Figure 16. V clamping OUT OUT V = 12 V, C = 10 µF, C = 10 µF, R = 22 Ω, No V = 18 V, C = 10 µF, R = 22 Ω, No C ,T = 25°C CC IN OUT LIMIT CC IN LIMIT dv/dt C T = 25°C dv/dt, Figure 17. Line transient Figure 18. Startup into output short-circuit VCC = from 12 to 18 V RLIMIT = 22 Ω; IOUT = 500 mA, TRISE VCC = 12 V, RLIMIT = 22 Ω, VOUT = Connected to GND = 100 µs DocID019056 Rev 6 13/20 20

Typical performance characteristics STEF12 Figure 19. Thermal latch from 2 A load to Figure 20. Startup into output short-circuit short-circuit (fast rise) V = 12 V, R = 22 Ω, V = Connected to GND CC LIMIT OUT 14/20 DocID019056 Rev 6

STEF12 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID019056 Rev 6 15/20 20

Package information STEF12 7.1 DFN10L (3x3 mm) package information Figure 21. DFN10L package outline 7426335_H 16/20 DocID019056 Rev 6

STEF12 Package information Table 7. DFN10L (3x3 mm.) mechanical data mm. Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.02 0.05 A2 0.55 0.65 0.80 A3 0.20 b 0.18 0.25 0.30 D 2.85 3.00 3.15 D2 2.20 2.70 E 2.85 3.00 3.15 E2 1.40 1.75 E3 0.230 E4 0.365 e 0.50 L 0.30 0.40 0.50 ddd 0.08 Figure 22. DFN10L (3x3 mm) recommended footprint (dimensions in mm.) 7426335_H DocID019056 Rev 6 17/20 20

Package information STEF12 7.2 DFNxx (3x3 mm) packing information Figure 23. DFNxx (3x3 mm) tape and reel outline Table 8. DFNxx (3x3 mm) tape and reel mechanical data mm. Dim. Min. Typ. Max. A 330 C 12.8 13.2 D 20.2 N 60 T 18.4 Ao 3.3 Bo 3.3 Ko 1.1 Po 4 P 8 18/20 DocID019056 Rev 6

STEF12 Revision history 8 Revision history Table 9. Document revision history Date Revision Changes 15-Jul-2011 1 Initial release. 08-Aug-2011 2 Modified definition for T in Table3: Absolute maximum ratings. op 14-Dec-2011 3 Removed V and I rows from dv/dt circuit Table6 on page6. dv/dt dv/dt Updated: package mechanical data Table7 on page17, Figure21 on page16 06-Mar-2012 4 and Figure24 on page19. Updated: package mechanical data Table7 on page17 and Figure21 on 14-Jan-2013 5 page16. Updated Equation 2, Equation 3 and Section7: Package information. 03-Aug-2015 6 Minor text changes. DocID019056 Rev 6 19/20 20

STEF12 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 20/20 DocID019056 Rev 6