STD25NF10LA Ω N-channel 100 V, 0.030 , 25 A DPAK STripFET™ II Power MOSFET Features Order code V R max I DSS DS(on) D STD25NF10LA 100 V < 0.035 Ω 25 A TAB ■ Exceptional dv/dt capability ■ 100% avalanche tested 3 1 ■ Logic level device DPAK Applications ■ Switching application ■ Automotive Description Figure 1. Internal schematic diagram This Power MOSFET has been developed using D(TAB) STMicroelectronics’ unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving G(1) requirements. S(3) AM09016v1 Table 1. Device summary Order code Marking Package Packaging STD25NF10LA D25NF10LA DPAK Tape and reel October 2011 Doc ID 022319 Rev 1 1/15 www.st.com 15

Contents STD25NF10LA Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 Doc ID 022319 Rev 1

STD25NF10LA Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Drain-source voltage 100 V DS V Gate- source voltage ± 16 V GS I (1) Drain current (continuous) at T = 25 °C 25 A D C I Drain current (continuous) at T = 100 °C 21 A D C I (2) Drain current (pulsed) 100 A DM P Total dissipation at T = 25 °C 100 W tot C Derating Factor 0.67 W/°C dv/dt(3) Peak diode recovery avalanche energy 20 V/ns E (4) Single pulse avalanche energy 450 mJ AS T Storage temperature stg -55 to 175 °C T Max. operating junction temperature j 1. Current limited by package 2. Pulse width limited by safe operating area. 3. I ≤ 25 A, di/dt ≤ 300 A/µs, V =V , T ≤ T SD DD (BR)DSS J JMAX 4. Starting T = 25 °C, I = 12.5 A V = 50 V j D DD Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 1.5 °C/W Rthj-pcb Thermal resistance junction-pcb max (1) 50 °C/W 1. When Mounted on 1 inch2 FR-4 board, 2 oz. of Cu. Doc ID 022319 Rev 1 3/15

Electrical characteristics STD25NF10LA 2 Electrical characteristics (T =25°C unless otherwise specified) CASE Table 4. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source V I = 250 µA, V =0 100 V (BR)DSS breakdown voltage D GS V = 100 V Zero gate voltage DS 1 µA IDSS drain current VDS= 100 V, TC = 125 °C 10 µA V =0 GS Gate-body leakage I V = ± 16 V, V = 0 ±100 nA GSS current GS DS V Gate threshold voltage V = V , I = 250 µA 1 2.5 V GS(th) DS GS D R Static drain-source on VGS = 10 V, ID = 12.5 A 0.030 0.035 Ω DS(on) resistance V = 4.5 V, I = 12.5 A 0.035 0.040 Ω GS D Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Input capacitance C 1710 pF Ciss Output capacitance VDS = 25 V, f = 1 MHz, - 250 pF Coss Reverse transfer VGS = 0 110 pF rss capacitance t Turn-on delay time 20 ns d(on) V = 50 V, I = 12.5 A t Rise time DD D 40 ns r R =4.7 Ω V = 5 V - t Turn-off delay time G GS 58 ns d(off) (see Figure13) t Fall time 20 ns f Q Total gate charge V = 80 V, I = 25 A, 38 52 nC g DD D Q Gate-source charge V = 5 V, R =4.7 Ω - 8.5 nC gs GS G Q Gate-drain charge (see Figure14) 21 nC gd 4/15 Doc ID 022319 Rev 1

STD25NF10LA Electrical characteristics Table 6. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I Source-drain current 25 A SD - ISDM (1) Source-drain current (pulsed) 100 A V (2) Forward on voltage I = 25 A, V = 0 - 1.5 V SD SD GS t Reverse recovery time I = 25 A, di/dt = 100 A/µs, 88 ns rr SD Q Reverse recovery charge V = 50 V, T = 150 °C - 317 nC rr DD j I Reverse recovery current (see Figure15) 7.2 A RRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 022319 Rev 1 5/15

Electrical characteristics STD25NF10LA 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized breakdown voltage vs. Figure 7. Static drain-source on resistance temperature 6/15 Doc ID 022319 Rev 1

STD25NF10LA Electrical characteristics Figure 8. Gate charge vs. gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs. vs. temperature temperature Figure 12. Source-drain diode forward characteristics Doc ID 022319 Rev 1 7/15

Test circuit STD25NF10LA 3 Test circuit Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit resistive load VDD 12V 47kΩ 1kΩ 100nF RL 2μ20F0 3μ.F3 VDD IG=CONST VD Vi=20V=VGMAX 100Ω D.U.T. VGS 2200 RG D.U.T. μF 2.7kΩ VG PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit L A A A D FAST L=100μH VD G D.U.T. DIODE 2200 3.3 μF μF VDD S B 3.3 1000 B B μF μF 25Ω D VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf 90% 90% IDM 10% ID 0 10% VDS VDD VDD 90% VGS AM01472v1 0 10% AM01473v1 8/15 Doc ID 022319 Rev 1

STD25NF10LA Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 022319 Rev 1 9/15

Package mechanical data STD25NF10LA Table 7. DPAK (TO-252) mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 5.10 E 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 1.50 L1 2.80 L2 0.80 L4 0.60 1 R 0.20 V2 0° 8° 10/15 Doc ID 022319 Rev 1

STD25NF10LA Package mechanical data Figure 19. DPAK (TO-252) drawing 0068772_H Figure 20. DPAK footprint(a) 6.7 1.8 3 1.6 2.3 6.7 2.3 1.6 AM08850v1 a. All dimensions are in millimeters Doc ID 022319 Rev 1 11/15

Packing mechanical data STD25NF10LA 5 Packing mechanical data Table 8. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 12/15 Doc ID 022319 Rev 1

STD25NF10LA Packing mechanical data Figure 21. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm Top cover P0 D P2 T tape E F K0 W B1 B0 For machine ref. only A0 P1 D1 including draft and radii concentric around B0 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 22. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot G measured at hub in core for tape start 25 mm min. width AM08851v2 Doc ID 022319 Rev 1 13/15

Revision history STD25NF10LA 6 Revision history T able 9. Revision history Date Revision Changes 05-Oct-2011 1 First release. 14/15 Doc ID 022319 Rev 1

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