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STD14NM50N产品简介:
ICGOO电子元器件商城为您提供STD14NM50N由STMicroelectronics设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 STD14NM50N价格参考。STMicroelectronicsSTD14NM50N封装/规格:晶体管 - FET,MOSFET - 单, 表面贴装 N 沟道 500V 12A(Tc) 90W(Tc) DPAK。您可以下载STD14NM50N参考资料、Datasheet数据手册功能说明书,资料中有STD14NM50N 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | |
描述 | MOSFET N-CH 500V 12A DPAKMOSFET N-Ch 500V 0.246 ohm 12 A MDmesh II |
产品分类 | FET - 单分离式半导体 |
FET功能 | 标准 |
FET类型 | MOSFET N 通道,金属氧化物 |
Id-ContinuousDrainCurrent | 12 A |
Id-连续漏极电流 | 12 A |
品牌 | STMicroelectronics |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 晶体管,MOSFET,STMicroelectronics STD14NM50NMDmesh™ II |
数据手册 | |
产品型号 | STD14NM50N |
Pd-PowerDissipation | 90 W |
Pd-功率耗散 | 90 W |
Qg-GateCharge | 42 nC |
Qg-栅极电荷 | 42 nC |
RdsOn-Drain-SourceResistance | 900 mOhms |
RdsOn-漏源导通电阻 | 900 mOhms |
Vds-Drain-SourceBreakdownVoltage | 500 V |
Vds-漏源极击穿电压 | 500 V |
Vgs-Gate-SourceBreakdownVoltage | 2 V |
Vgs-栅源极击穿电压 | 2 V |
Vgsth-Gate-SourceThresholdVoltage | 4 V |
Vgsth-栅源极阈值电压 | 4 V |
上升时间 | 9 ns |
下降时间 | 32 ns |
不同Id时的Vgs(th)(最大值) | 4V @ 100µA |
不同Vds时的输入电容(Ciss) | 816pF @ 50V |
不同Vgs时的栅极电荷(Qg) | 27nC @ 10V |
不同 Id、Vgs时的 RdsOn(最大值) | 320 毫欧 @ 6A,10V |
产品培训模块 | http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=26067 |
产品种类 | MOSFET |
供应商器件封装 | D-Pak |
其它名称 | 497-10646-2 |
其它有关文件 | http://www.st.com/web/catalog/sense_power/FM100/CL824/SC1167/PF248450?referrer=70071840 |
典型关闭延迟时间 | 12 ns |
功率-最大值 | 90W |
包装 | 带卷 (TR) |
商标 | STMicroelectronics |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | TO-252-3,DPak(2 引线+接片),SC-63 |
封装/箱体 | DPAK-2 |
工厂包装数量 | 2500 |
晶体管极性 | N-Channel |
最大工作温度 | + 150 C |
标准包装 | 2,500 |
漏源极电压(Vdss) | 500V |
电流-连续漏极(Id)(25°C时) | 12A (Tc) |
系列 | STD14NM50N |
配置 | Single |
STB14NM50N N-channel 500 V, 0.28 Ω typ., 12 A MDmesh™ II Power MOSFET in a D²PAK package - Datasheet production data Features Order code V @ T R max I DS Jmax DS(on) D STB14NM50N 550 V 0.32 Ω 12 A TAB • 100% avalanche tested • Low input capacitance and gate charge 3 1 • Low gate input resistance D2PAK Applications • Switching applications Description Figure 1. Internal schematic diagram This device is an N-channel Power MOSFET developed using the second generation of (cid:39)(cid:11)(cid:21)(cid:15)(cid:262)(cid:55)(cid:36)(cid:37)(cid:12) MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is (cid:42)(cid:11)(cid:20)(cid:12) therefore suitable for the most demanding high efficiency converters. (cid:54)(cid:11)(cid:22)(cid:12) (cid:36)(cid:48)(cid:19)(cid:20)(cid:23)(cid:26)(cid:24)(cid:89)(cid:20) Table 1. Device summary Order code Marking Package Packaging STB14NM50N 14NM50N D²PAK Tape and reel June 2014 DocID024666 Rev 1 1/15 This is information on a product in full production. www.st.com
Contents STB14NM50N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 DocID024666 Rev 1
STB14NM50N Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Drain-source voltage 500 V DS V Gate-source voltage ± 25 V GS I Drain current (continuous) at T = 25 °C 12 A D C I Drain current (continuous) at T = 100 °C 8 A D C I (1) Drain current (pulsed) 48 A DM P Total dissipation at T = 25 °C 90 W TOT C dv/dt (2) Peak diode recovery voltage slope 15 V/ns T Storage temperature - 55 to 150 °C stg T Max. operating junction temperature 150 °C j 1. Pulse width limited by safe operating area. 2. I ≤ 12 A, di/dt ≤ 400 A/s,V peak ≤ V , V = 80% V SD DS (BR)DSS DD (BR)DSS. Table 3. Thermal data Symbol Parameter Value Unit R Thermal resistance junction-case max 1.39 °C/W thj-case R (1) Thermal resistance junction-pcb max 30 °C/W thj-pcb 1. When mounted on 1inch² FR-4 board, 2 oz Cu. Table 4. Avalanche data Symbol Parameter Value Unit Avalanche current, repetitive or not-repetitive I 4 A AR (pulse width limited by T max) j Single pulse avalanche energy E 172 mJ AS (starting T = 25°C, I = I , V = 50 V) j D AR DD DocID024666 Rev 1 3/15 15
Electrical characteristics STB14NM50N 2 Electrical characteristics (T = 25 °C unless otherwise specified) C Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source V V = 0, I = 1 mA 500 V (BR)DSS breakdown voltage GS D V = 0, V = 500 V 1 μA GS DS Zero gate voltage IDSS drain current VGS = 0, VDS = 500 V, 100 μA T =125 °C C Gate-body leakage I V = 0, V = ± 25 V ± 100 nA GSS current DS GS V Gate threshold voltage V = V , I = 250 μA 2 3 4 V GS(th) DS GS D Static drain-source RDS(on) on-resistance VGS = 10 V, ID = 6 A 0.28 0.32 Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C Input capacitance - 816 - pF iss C Output capacitance - 60 - pF oss V = 0, V = 50 V, f = 1 MHz GS DS Reverse transfer C - 3 - pF rss capacitance Equivalent output C (1) V = 0, V = 0 to 50 V - 157 - pF oss eq. capacitance GS DS Intrinsic gate R f = 1 MHz open drain - 4.5 - Ω G resistance Q Total gate charge - 27 - nC g V =400 V, I =12 A, Q Gate-source charge DD D - 5 - nC gs V =10 V (see Figure13) GS Q Gate-drain charge - 15 - nC gd 1. C is defined as a constant equivalent capacitance giving the same charging time as C when V oss eq. oss DS increases from 0 to 80% V DS 4/15 DocID024666 Rev 1
STB14NM50N Electrical characteristics Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-on delay time - 12 - ns d(on) V = 400 V, I = 12 A, t Rise time DD D - 16 - ns r R =4.7 Ω, V = 10 V G GS t Turn-off-delay time - 42 - ns d(off) (see Figure13) t Fall time - 22 - ns f Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I Source-drain current - 12 A SD I (1) Source-drain current (pulsed) - 48 A SDM V (2) Forward on voltage V = 0, I = 12 A - 1.6 V SD GS SD t Reverse recovery time - 252 ns rr I = 12 A, di/dt = 100 A/μs, SD Q Reverse recovery charge V = 60 V - 2.8 μC rr DD (see Figure17) I Reverse recovery current - 22 A RRM t Reverse recovery time - 300 ns rr I = 12 A, di/dt = 100 A/μs, SD Q Reverse recovery charge V = 60 V, T = 150 °C - 3.3 μC rr DD J (see Figure17) I Reverse recovery current - 22.2 A RRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5% DocID024666 Rev 1 5/15 15
Electrical characteristics STB14NM50N 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance ID AM07199v1 (A) 10 Operatimiotne id n btyh ism aarx eRa iDsS(on) 11000µµss 1 Li 1ms 10ms Tj=150°C Tc=25°C Single pulse 0.1 0.1 1 10 100 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics AM07202v1 AM07203v1 ID ID (A) (A) VGS=10V 25 25 VDS=18V 20 20 6V 15 15 10 10 5V 5 5 0 0 0 5 10 15 20 VDS(V) 0 2 4 6 8 10VGS(V) Figure 6. Normalized V vs temperature Figure 7. Static drain-source on-resistance BR(DSS) VBR(DSS) AM09028v1 RDS(on) AM07205v1 (norm) ID=1mA (Ohm) 1.10 0.300 VGS=10V 1.08 0.295 1.06 0.290 1.04 1.02 0.285 1.00 0.280 0.98 0.275 0.96 0.270 0.94 0.92 0.265 -50 -25 0 25 50 75 100 TJ(°C) 0 2 4 6 8 10 12 ID(A) 6/15 DocID024666 Rev 1
STB14NM50N Electrical characteristics Figure 8. Capacitance variations Figure 9. Gate charge vs gate-source voltage C AM07206v1 VGS AMV0D7S204v1 (pF) (V) (V) 400 12 VDD=400V VDS ID=12A 350 1000 Ciss 10 300 8 250 100 200 6 Coss 150 4 10 100 Crss 2 50 1 0 0 0.1 1 10 100 VDS(V) 0 5 10 15 20 25 30 Qg(nC) Figure 10. Normalized gate threshold voltage vs Figure 11. Normalized on-resistance vs temperature temperature VGS(th) AM07208v1 RDS(on) AM07209v1 (norm) ID=250µA (norm) 1.10 2.1 ID=6A 1.00 1.7 VGS=10 V 0.90 1.3 0.80 0.9 0.70 0.5 -50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD AM15616v1 (V) 1.4 TJ= -50 °C 1.2 1 TJ= 25 °C 0.8 TJ= 150 °C 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 11 ISD(A) DocID024666 Rev 1 7/15 15
Test circuits STB14NM50N 3 Test circuits Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit resistive load VDD 12V 47kΩ 1kΩ 100nF RL 2μ20F0 3μ.F3 VDD IG=CONST VD Vi=20V=VGMAX 100Ω D.U.T. VGS 2200 RG D.U.T. μF 2.7kΩ VG PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test circuit switching and diode recovery times L A A A D FAST L=100μH VD G D.U.T. DIODE 2200 3.3 μF μF VDD S B 3.3 1000 B B μF μF 25Ω D VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf 90% 90% IDM 10% ID 0 10% VDS VDD VDD 90% VGS AM01472v1 0 10% AM01473v1 8/15 DocID024666 Rev 1
STB14NM50N Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID024666 Rev 1 9/15 15
Package mechanical data STB14NM50N Figure 19. D²PAK (TO-263) drawing 0079457_T 10/15 DocID024666 Rev 1
STB14NM50N Package mechanical data Table 9. D²PAK (TO-263) mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0° 8° Figure 20. D²PAK footprint(a) 16.90 12.20 5.08 1.60 3.50 9.75 Footprint DocID024666 Rev 1 11/15 15
Packaging mechanical data STB14NM50N 5 Packaging mechanical data Figure 21. Tape 10 pitches cumulative tolerance on tape +/- 0.2 mm Top cover P0 D P2 T tape E F K0 W B1 B0 For machine ref. only A0 P1 D1 including draft and radii concentric around B0 User direction of feed R Bending radius User direction of feed AM08852v1 a. All dimensions are in millimeters 12/15 DocID024666 Rev 1
STB14NM50N Packaging mechanical data Figure 22. Reel T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius Tape slot G measured at hub in core for tape start 25 mm min. width AM08851v2 Table 10. D²PAK (TO-263) and DPAK tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 10.5 10.7 A 330 B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 13.2 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 26.4 F 11.4 11.6 N 100 K0 4.8 5.0 T 30.4 P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID024666 Rev 1 13/15 15
Revision history STB14NM50N 6 Revision history Table 11. Document revision history Date Revision Changes 27-Jun-2014 1 First release. 14/15 DocID024666 Rev 1
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