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  • 型号: STB120N4F6
  • 制造商: STMicroelectronics
  • 库位|库存: xxxx|xxxx
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STB120N4F6产品简介:

ICGOO电子元器件商城为您提供STB120N4F6由STMicroelectronics设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 STB120N4F6价格参考。STMicroelectronicsSTB120N4F6封装/规格:晶体管 - FET,MOSFET - 单, 表面贴装 N 沟道 40V 80A(Tc) 110W(Tc) D2PAK。您可以下载STB120N4F6参考资料、Datasheet数据手册功能说明书,资料中有STB120N4F6 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

分立半导体产品

描述

MOSFET N-CH 40V 80A D2PAKMOSFET N-Ch 40V 4mOhm 80A STripFET VI DeepGATE

产品分类

FET - 单分离式半导体

FET功能

逻辑电平门

FET类型

MOSFET N 通道,金属氧化物

Id-ContinuousDrainCurrent

80 A

Id-连续漏极电流

80 A

品牌

STMicroelectronics

产品手册

点击此处下载产品Datasheet

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

晶体管,MOSFET,STMicroelectronics STB120N4F6DeepGATE™, STripFET™ VI

数据手册

点击此处下载产品Datasheet

产品型号

STB120N4F6

Pd-PowerDissipation

110 W

Pd-功率耗散

110 W

Qg-GateCharge

65 nC

Qg-栅极电荷

65 nC

RdsOn-Drain-SourceResistance

4 mOhms

RdsOn-漏源导通电阻

4 mOhms

Vds-Drain-SourceBreakdownVoltage

40 V

Vds-漏源极击穿电压

40 V

Vgs-Gate-SourceBreakdownVoltage

20 V

Vgs-栅源极击穿电压

20 V

Vgsth-Gate-SourceThresholdVoltage

4 V

Vgsth-栅源极阈值电压

4 V

不同Id时的Vgs(th)(最大值)

4V @ 250µA

不同Vds时的输入电容(Ciss)

3850pF @ 25V

不同Vgs时的栅极电荷(Qg)

65nC @ 10V

不同 Id、Vgs时的 RdsOn(最大值)

4 毫欧 @ 40A,10V

产品培训模块

http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=26067

产品种类

MOSFET

供应商器件封装

D2PAK

其它名称

497-10768-5

其它有关文件

http://www.st.com/web/catalog/sense_power/FM100/CL824/SC1164/PF250321?referrer=70071840

功率-最大值

110W

包装

管件

商标

STMicroelectronics

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

TO-263-3,D²Pak(2 引线+接片),TO-263AB

封装/箱体

D2PAK-2

工厂包装数量

1000

晶体管极性

N-Channel

最大工作温度

+ 175 C

最小工作温度

- 55 C

标准包装

1,000

漏源极电压(Vdss)

40V

特色产品

http://www.digikey.cn/product-highlights/cn/zh/stmicroelectronics-stripfet-vi-deepgate-mosfets/3393

电流-连续漏极(Id)(25°C时)

80A (Tc)

系列

STB120N4F6

配置

Single

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PDF Datasheet 数据手册内容提取

STB120N4F6, STD120N4F6 Automotive-grade N-channel 40 V, 3.5 mΩ typ., 80 A STripFET™ F6 Power MOSFETs in DPAK and D²PAK packages Datasheet - production data Features Order codes V R max. I DS DS(on) D STB120N4F6 40 V 4 mΩ 80 A TAB STD120N4F6 40 V 4 mΩ 80 A TAB • Designed for automotive applications and 3 3 AEC-Q101 qualified 1 1 DPAK D²PAK • Very low on-resistance • Very low gate charge • High avalanche ruggedness • Low gate drive power loss Application Figure 1. Internal schematic diagram • Switching applications (cid:39)(cid:3)(cid:11)(cid:55)(cid:36)(cid:37)(cid:3)(cid:82)(cid:85)(cid:3)(cid:21)(cid:12) Description These devices are N-channel Power MOSFETs developed using the 6th generation of STripFET™ DeepGATE™ technology, with a new gate (cid:42)(cid:11)(cid:20)(cid:12) structure. The resulting Power MOSFETs exhibits the lowest R in all packages. DS(on) (cid:54)(cid:11)(cid:22)(cid:12) (cid:36)(cid:48)(cid:19)(cid:20)(cid:23)(cid:26)(cid:23)(cid:89)(cid:20) Table 1. Device summary Order codes Marking Package Packaging STB120N4F6 D²PAK 120N4F6 Tape and reel STD120N4F6 DPAK September 2015 DocID17042 Rev 6 1/19 This is information on a product in full production. www.st.com

Contents STB120N4F6, STD120N4F6 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 D2PAK (TO-263) type A package information . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . 12 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Drain-source voltage 40 V DS V Gate-source voltage ± 20 V GS I (1) Drain current (continuous) at T = 25 °C 80 A D C I (1) Drain current (continuous) at T = 100 °C 80 A D C I (2) Drain current (pulsed) 320 A DM P Total dissipation at T = 25 °C 110 W TOT C T Storage temperature stg -55 to 175 °C T Operating junction temperature j 1. Current limited by package 2. Pulse width limited by safe operating area Table 3. Thermal resistance Value Symbol Parameter Unit DPAK D²PAK R Thermal resistance junction-case max 1.36 °C/W thj-case R Thermal resistance junction-pcb max (1) 50 35 °C/W thj-pcb 1. When mounted on 1 inch2 2 oz. Cu board. Table 4. Thermal resistance Symbol Parameter Value Unit I (1) Avalanche current, repetitive or not-repetitive 40 A AR E (2) Single pulse avalanche energy 394 mJ AS 1. Pulse width limited by Tj max 2. Starting Tj = 25 °C, I = 40 A, V = 25 V D DD DocID17042 Rev 6 3/19 19

Electrical characteristics STB120N4F6, STD120N4F6 2 Electrical characteristics (T = 25 °C unless otherwise specified) CASE Table 5. Static Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown V I = 250 µA, V = 0 40 V (BR)DSS Voltage D GS I Zero gate voltage drain VDS = 20 V 1 µA DSS current (VGS = 0) VDS = 20 V, Tc = 125 °C 10 µA Gate body leakage current IGSS (V = 0) VGS = ± 20 V ±100 nA DS V Gate threshold voltage V = V , I = 250 µA 2 4 V GS(th) DS GS D Static drain-source on R V = 10 V, I = 40 A 3.5 4.0 mΩ DS(on) resistance GS D Table 6. Dynamic Symbol Parameter Test conditions Min Typ. Max. Unit C Input capacitance - 3850 - pF iss Coss Output capacitance VDS = 25 V, f=1 MHz, - 650 - pF V = 0 V Reverse transfer GS C - 350 - pF rss capacitance Q Total gate charge - 65 - nC g V = 20 V, I = 80 A DD D Q Gate-source charge V = 10 V - 20 - nC gs GS (see Figure 14) Q Gate-drain charge - 16 - nC gd R Intrinsic gate resistance f = 1 MHz open drain - 1.5 - Ω G Table 7. Switching on/off (inductive load) Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-on delay time - 20 - ns d(on) V = 20 V, I = 40 A, t Rise time DD D - 70 - ns r R = 4.7 Ω, V = 10 V G GS t Turn-off delay time - 40 - ns d(off) (see Figure 15) t Fall time - 20 - ns f 4/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I Source-drain current 80 A SD - I (1) Source-drain current (pulsed) 320 A SDM V (2) Forward on voltage I = 40 A, V = 0 - 1.1 V SD SD GS t Reverse recovery time I = 80 A, - 40 ns rr SD di/dt = 100 A/µs, Q Reverse recovery charge - 56 nC rr V = 30 V DD IRRM Reverse recovery current (see Figure 17) - 2.8 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID17042 Rev 6 5/19 19

Electrical characteristics STB120N4F6, STD120N4F6 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance ID AM08627v1 (A) Tj=175°C 100 Opermaittieodn ibny thmisa xa rReDa Si(son) TScin=g2le5 °pCulse 100µs Li 1ms 10 10ms 1 0.1 0.1 1 10 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics AM08628v1 AM08629v1 ID(A) ID VGS=10V (A) VDS=2V 350 300 300 6V 200 250 200 150 150 5V 100 100 50 50 4V 0 0 0 1 2 3 4 5 6 7 8 VDS(V) 0 1 2 3 4 5 VGS(V) Figure 6. Normalized B vs temperature Figure 7. Static drain-source on resistance (BR)DSS V(BR)DSS AM08630v1 RDS(on) AM08631v1 (norm) (mΩ) 1.15 VGS=10V ID = 250 μA 4.5 1.10 4.0 1.05 1.00 3.5 0.95 3.0 0.90 2.5 0.85 0.80 2.0 -75 -25 25 75 125 175 TJ(°C) 20 40 60 80 ID(A) 6/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations VGS AM08632v1 C AM08633v1 (V) (pF) 10 VDD=20V Ciss ID=80A 8 1000 Coss 6 Crss 4 100 f = 1 MHz 2 0 10 0 10 20 30 40 50 60 70 Qg(nC) 0.1 1 10 VDS(V) Figure 10. Normalized gate threshold voltage vs Figure 11. Normalized on resistance vs temperature temperature VGS(th) AM08634v1 RDS(on) AM08635v1 (norm) (norm) VGS=10V 1.2 ID=40A 2.0 1.0 1.5 0.8 ID = 250 μA 1.0 0.6 0.5 0.4 0.2 0 -75 -25 25 75 125 175 TJ(°C) -75 -25 25 75 125 175 TJ(°C) Figure 12. Source-drain diode forward characteristics VSD AM08636v1 (V) TJ=-55°C 1.0 0.9 0.8 TJ=25°C 0.7 TJ=175°C 0.6 0.5 0.4 10 20 30 40 50 60 70 80 ISD(A) DocID17042 Rev 6 7/19 19

Test circuits STB120N4F6, STD120N4F6 3 Test circuits Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit resistive load V DD 12V 47kΩ 1kΩ 100nF RL 2μ20F0 3μ.F3 VDD I =CONST VD V=20V=V G 100Ω D.U.T. VGS i 2G2M0AX0 RG D.U.T. mF 2.7kΩ V G PW 47kΩ 1kΩ PW AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test circuit switching and diode recovery times L A A A D FAST L=100μH VD G D.U.T. DIODE 2200 3.3 μF μF VDD S B 3.3 1000 B B μF μF 25Ω D VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf 90% 90% IDM 10% ID 0 10% VDS VDD VDD 90% VGS AM01472v1 0 10% AM01473v1 8/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and products status are available at: www.st.com. ECOPACK is an ST trademark. 2 4.1 D PAK (TO-263) type A package information Figure 19. D²PAK (TO-263) type A package outline DocID17042 Rev 6 9/19 19

Package information STB120N4F6, STD120N4F6 Table 9. D²PAK (TO-263) type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10 10.40 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0° 8° 10/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Package information Figure 20. D²PAK recommended footprint(a) (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87) a. All dimension are in millimeters DocID17042 Rev 6 11/19 19

Package information STB120N4F6, STD120N4F6 4.2 DPAK (TO-252) type A2 package information Figure 21. DPAK (TO-252) type A2 package outline (cid:19)(cid:19)(cid:25)(cid:27)(cid:26)(cid:26)(cid:21)(cid:66)(cid:87)(cid:92)(cid:83)(cid:72)(cid:16)(cid:36)(cid:21)(cid:66)(cid:85)(cid:72)(cid:89)(cid:20)(cid:28) 12/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Package information Table 10. DPAK (TO-252) type A2 mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 5.10 5.25 E 6.40 6.60 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 1.00 R 0.20 V2 0° 8° DocID17042 Rev 6 13/19 19

Package information STB120N4F6, STD120N4F6 Figure 22. DPAK (TO-252) recommended footprint (b) (cid:41)(cid:51)(cid:66)(cid:19)(cid:19)(cid:25)(cid:27)(cid:26)(cid:26)(cid:21)(cid:66)(cid:53)(cid:20)(cid:28) b. All dimensions are in millimeters 14/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Packaging mechanical data 5 Packaging mechanical data Figure 23. Tape for DPAK (TO-252) and D²PAK (TO-263) 10 pitches cumulative tolerance on tape +/- 0.2 mm Top cover P0 D P2 T tape E F K0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v2 DocID17042 Rev 6 15/19 19

Packaging mechanical data STB120N4F6, STD120N4F6 Figure 24. Reel for DPAK (TO-252) and D²PAK (TO-263) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot G measured at hub in core for tape start 25 mm min. width AM08851v2 Table 11. D²PAK (TO-263) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 10.5 10.7 A 330 B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 13.2 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 26.4 F 11.4 11.6 N 100 K0 4.8 5.0 T 30.4 P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 16/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 Packaging mechanical data Table 12. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID17042 Rev 6 17/19 19

Revision history STB120N4F6, STD120N4F6 6 Revision history Table 13. Document revision history Date Revision Changes 09-Feb-2010 1 First release 29-Oct-2010 2 Document status promoted from preliminary data to datasheet. 11-Nov-2010 3 Corrected R value in Table5: Static. DS(on) 13-May-2011 4 Removed package and mechanical data: TO-220 17-May-2011 5 Description in cover page has been updated. Updated title, features and description in cover page. 23-Sep-2015 6 Updated Section4: Package information. 18/19 DocID17042 Rev 6

STB120N4F6, STD120N4F6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID17042 Rev 6 19/19 19