ST7LITE0xY0, ST7LITESxY0 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI ■ Memories – 1K or 1.5 Kbytes single voltage Flash Pro- gram memory with read-out protection, In-Cir- cuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, SO16 data retention: 20 years at 55 °C. DIP16 150” – 128 bytes RAM. – 128 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, QFN20 data retention: 20 years at 55 °C. ■ Clock, Reset and Supply Management – One 12-bit Auto-reload Timer (AT) with output – 3-level low voltage supervisor (LVD) and aux- compare function and PWM iliary voltage detector (AVD) for safe power- on/off procedures ■ 1 Communication Interface – Clock sources: internal 1MHz RC 1% oscilla- – SPI synchronous serial interface tor or external clock ■ A/D Converter – PLL x4 or x8 for 4 or 8 MHz internal clock – 8-bit resolution for 0 to V DD – Four Power Saving Modes: Halt, Active-Halt, – Fixed gain Op-amp for 11-bit resolution in 0 to Wait and Slow 250 mV range (@ 5V V ) DD ■ Interrupt Management – 5 input channels – 10 interrupt vectors plus TRAP and RESET ■ Instruction Set – 4 external interrupt lines (on 4 vectors) – 8-bit data manipulation ■ I/O Ports – 63 basic instructions with illegal opcode de- – 13 multifunctional bidirectional I/O lines tection – 9 alternate function lines – 17 main addressing modes – 6 high sink outputs – 8 x 8 unsigned multiply instruction ■ 2 Timers ■ Development Tools – One 8-bit Lite Timer (LT) with prescaler in- – Full hardware/software development package cluding: watchdog, 1 realtime base and 1 in- put capture. Device Summary ST7LITESxY0 (ST7SUPERLITE) ST7LITE0xY0 Features ST7LITES2Y0 ST7LITES5Y0 ST7LITE02Y0 ST7LITE05Y0 ST7LITE09Y0 Program memory - bytes 1K 1K 1.5K 1.5K 1.5K RAM (stack) - bytes 128 (64) 128 (64) 128 (64) 128 (64) 128 (64) Data EEPROM - bytes - - - - 128 LT Timer w/ Wdg, LT Timer w/ Wdg, LT Timer w/ Wdg, LT Timer w/ Wdg, Peripherals AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, SPI, SPI SPI, 8-bit ADC SPI 8-bit ADC w/ Op-Amp Operating Supply 2.4V to 5.5V CPU Frequency 1MHz RC 1% + PLLx4/8MHz Operating Temperature -40°C to +85°C Packages SO16 150”, DIP16, QFN20 Rev 6 November 2007 1/124 1

Table of Contents ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 2. 4. . 38 9.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2/124 2

Table of Contents 10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . . 93 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102 13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 114 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD- WARE WATCHDOG OPTION 121 16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 121 16.4 RECOMMENDATIONS WHEN LVD IS ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 121 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3/124 3

Table of Contents To obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page121. 4/124 1

ST7LITE0xY0, ST7LITESxY0 1 DESCRIPTION The ST7LITE0x and ST7SUPERLITE The enhanced instruction set and addressing (ST7LITESx) are members of the ST7 microcon- modes of the ST7 offer both power and flexibility to troller family. All ST7 devices are based on a com- software developers, enabling the design of highly mon industry-standard 8-bit core, featuring an en- efficient and compact application code. In addition hanced instruction set. to standard 8-bit data management, all ST7 micro- controllers feature true bit manipulation, 8x8 un- The ST7LITE0x and ST7SUPERLITE feature signed multiplication and indirect addressing FLASH memory with byte-by-byte In-Circuit Pro- modes. gramming (ICP) and In-Application Programming (IAP) capability. For easy reference, all parametric data are located in section 13 on page 81. Under software control, the ST7LITE0x and ST7SUPERLITE devices can be placed in WAIT, SLOW, or HALT mode, reducing power consump- tion when the application is in idle or standby state. Figure 1. General Block Diagram Internal CLOCK 1 MHz. RC OSC + PLL x 4 or x 8 LITE TIMER w/ WATCHDOG LVD/AVD V DD POWER PORT A PA7:0 SUPPLY (8 bits) V SS A 12-BIT AUTO- D RESET CONTROL D RELOAD TIMER R E S S 8-BIT CORE A N ALU D D AT SPI A FLASH B U S MEMORY PORT B PB4:0 (1 or 1.5K Bytes) (5 bits) 8-BITADC RAM (128 Bytes) DATA EEPROM (128 Bytes) 5/124 1

ST7LITE0xY0, ST7LITESxY0 2 PIN DESCRIPTION Figure 2. 20-Pin QFN Package Pinout C N0 TI S/AI HS)/L 0/S D S 0 ( B D S A P V V P 20 19 18 17 RESET 1 e3 e0 16 PA1 (HS) NC 2 15 PA2 (HS)/ATPWM0 NC 3 14 PA3 (HS) NC 4 13 NC MISO/AIN2/PB2 5 12 PA4 (HS) ei2 ei1 SCK/AIN1/PB1 6 11 PA5 (HS)/ICCDATA 7 8 9 10 3 4 7 6 B B A A P P P P 3/ 4/ K/ N N L AI AI C SI/ N/ CC MO LKI O/I C C M (HS) 20mA Highsinkcapability eix associatedexternalinterruptvector Figure 3. 16-Pin SO and DIP Package Pinout k VSS 1 ei0 16 PA0 (HS)/LTIC VDD 2 15 PA1 (HS) RESET 3 14 PA2 (HS)/ATPWM0 SS/AIN0/PB0 4 ei3 13 PA3 (HS) SCK/AIN1/PB1 5 12 PA4 (HS) MISO/AIN2/PB2 6 11 PA5 (HS)/ICCDATA MOSI/AIN3/PB3 7 ei2 10 PA6/MCO/ICCCLK CLKIN/AIN4/PB4 8 ei1 9 PA7 (HS) 20mAhighsinkcapability ei associatedexternalinterruptvector x 6/124 1

ST7LITE0xY0, ST7LITESxY0 PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: C= CMOS 0.15V /0.85V with input trigger DD DD C = CMOS 0.3V /0.7V with input trigger T DD DD Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain, PP = push-pull Table 1. Device Pin Description Pin n° Level Port / Control 16 e Input Output Main QFN20 O16/DIP Pin Name Typ Input Output float wpu int ana OD PP (aFftuenrc rteiosnet) Alternate Function S 18 1 V S Ground SS 19 2 V S Main power supply DD 1 3 RESET I/O C X X Top priority non maskable interrupt (active low) T ADC Analog Input 0 or SPI Slave 20 4 PB0/AIN0/SS I/O C X ei3 X X X Port B0 T Select (active low) ADC Analog Input 1 or SPI Clock Caution: No negative current in- 6 5 PB1/AIN1/SCK I/O C X X X X X Port B1 jection allowed on this pin. For T details, refer to section 13.2.2 on page 82 ADC Analog Input 2 or SPI Mas- 5 6 PB2/AIN2/MISO I/O C X X X X X Port B2 T ter In/ Slave Out Data ADC Analog Input 3 or SPI Mas- 7 7 PB3/AIN3/MOSI I/O C X ei2 X X X Port B3 T ter Out / Slave In Data ADC Analog Input 4 or External 8 8 PB4/AIN4/CLKIN I/O C X X X X X Port B4 T clock input 9 9 PA7 I/O C X ei1 X X Port A7 T Main Clock Output/In Circuit Communication Clock. Caution: During normal opera- tion this pin must be pulled- up, internally or externally (external PA6 /MCO/ pull-up of 10k mandatory in noisy 10 10 I/O C X X X X Port A6 ICCCLK T environment). This is to avoid en- tering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up PA5/ 11 11 I/O C HS X X X X Port A5 In Circuit Communication Data ICCDATA T 12 12 PA4 I/O C HS X X X X Port A4 T 14 13 PA3 I/O C HS X X X X Port A3 T 7/124 1

ST7LITE0xY0, ST7LITESxY0 Pin n° Level Port / Control 16 e Input Output Main QFN20 O16/DIP Pin Name Typ Input Output float wpu int ana OD PP (aFftuenrc rteiosnet) Alternate Function S 15 14 PA2/ATPWM0 I/O C HS X X X X Port A2 Auto-Reload Timer PWM0 T 16 15 PA1 I/O C HS X X X X Port A1 T 17 16 PA0/LTIC I/O C HS X ei0 X X Port A0 Lite Timer Input Capture T Note: In the interrupt input column, “ei ” defines the associated external interrupt vector. If the weak pull-up col- x umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 8/124 1

ST7LITE0xY0, ST7LITESxY0 3 REGISTER & MEMORY MAP As shown in Figure 4 and Figure 5, the MCU is ca- The highest address bytes contain the user reset pable of addressing 64K bytes of memories and I/ and interrupt vectors. O registers. The size of Flash Sector 0 is configurable by Op- The available memory locations consist of up to tion byte. 128 bytes of register locations, 128 bytes of RAM, IMPORTANT: Memory locations marked as “Re- 128 bytes of data EEPROM and up to 1.5 Kbytes served” must never be accessed. Accessing a re- of user program memory. The RAM space in- served area can have unpredictable effects on the cludes up to 64 bytes for the stack from 0C0h to device. 0FFh. Figure 4. Memory Map (ST7LITE0x) 0000h 0080h HW Registers Short Addressing (see Table 2) 007Fh RAM (zero page) 0080h 00BFh RAM 00C0h (128 Bytes) 64BytesStack 00FFh 0100h 00FFh Reserved 0FFFh 1000h 1000h RCCR0 Data EEPROM (128 Bytes) 1001h RCCR1 107Fh 1080h see section 7.1 on page 24 1.5KFLASH Reserved PROGRAMMEMORY F9FFh FA00h FA00h 0.5 Kbytes FBFFh SECTOR1 Flash Memory FC00h 1 Kbytes (1.5K) SECTOR0 FFFFh FFDFh FFDEh FFE0h RCCR0 Interrupt & Reset Vectors (see Table 6) FFDFh RCCR1 FFFFh see section 7.1 on page 24 9/124 1

ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) F igure 5. Memory Map (ST7SUPERLITE) 0000h 0080h HW Registers Short Addressing (see Table 2) 007Fh RAM (zero page) 0080h 00BFh RAM 00C0h (128 Bytes) 64BytesStack 00FFh 0100h 00FFh Reserved 1KFLASH PROGRAMMEMORY FBFFh FC00h FC00h 0.5 Kbytes FDFFh SECTOR1 Flash Memory FE00h 0.5 Kbytes (1K) SECTOR0 FFFFh FFDFh FFE0h Interrupt & Reset Vectors FFDEh RCCR0 (see Table 6) FFFFh RCCR1 FFDFh see section 7.1 on page 24 10/124 1

ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) Legend: x=undefined, R/W=read/write Table 2. Hardware Register Map Register Reset Address Block Register Name Remarks Label Status 0000h PADR Port A Data Register 00h1) R/W 0001h Port A PADDR Port A Data Direction Register 00h R/W 0002h PAOR Port A Option Register 40h R/W 0003h PBDR Port B Data Register E0h 1) R/W 0004h Port B PBDDR Port B Data Direction Register 00h R/W 0005h PBOR Port B Option Register 00h R/W2) 0006h to Reserved area (5 bytes) 000Ah 000Bh LITE LTCSR Lite Timer Control/Status Register xxh R/W 000Ch TIMER LTICR Lite Timer Input Capture Register xxh Read Only 000Dh ATCSR Timer Control/Status Register 00h R/W 000Eh CNTRH Counter Register High 00h Read Only 000Fh CNTRL Counter Register Low 00h Read Only AUTO-RELOAD 0010h ATRH Auto-Reload Register High 00h R/W TIMER 0011h ATRL Auto-Reload Register Low 00h R/W 0012h PWMCR PWM Output Control Register 00h R/W 0013h PWM0CSR PWM 0 Control/Status Register 00h R/W 0014h to Reserved area (3 bytes) 0016h 0017h AUTO-RELOAD DCR0H PWM 0 Duty Cycle Register High 00h R/W 0018h TIMER DCR0L PWM 0 Duty Cycle Register Low 00h R/W 0019h to Reserved area (22 bytes) 002Eh 0002Fh FLASH FCSR Flash Control/Status Register 00h R/W 00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W 0031h SPIDR SPI Data I/O Register xxh R/W 0032h SPI SPICR SPI Control Register 0xh R/W 0033h SPICSR SPI Control/Status Register 00h R/W 0034h ADCCSR A/D Control Status Register 00h R/W 0035h ADC ADCDR A/D Data Register 00h Read Only 0036h ADCAMP A/D Amplifier Control Register 00h R/W 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCCSR Main Clock Control/Status Register 00h R/W CLOCKS 0039h RCCR RC oscillator Control Register FFh R/W 11/124 1

ST7LITE0xY0, ST7LITESxY0 Register Reset Address Block Register Name Remarks Label Status 003Ah SI SICSR System Integrity Control/Status Register 0xh R/W 003Bh to Reserved area (69 bytes) 007Fh Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 12/124 1

ST7LITE0xY0, ST7LITESxY0 4 FLASH PROGRAM MEMORY 4.1 Introduction 4.3.1 In-Circuit Programming (ICP) The ST7 single voltage extended Flash (XFlash) is ICP uses a protocol called ICC (In-Circuit Commu- a non-volatile memory that can be electrically nication) which allows an ST7 plugged on a print- ed circuit board (PCB) to communicate with an ex- erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. ternal programming device connected via cable. ICP is performed in three steps: The XFlash devices can be programmed off-board Switch the ST7 to ICC mode (In-Circuit Communi- (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program- cations). This is done by driving a specific signal ming. sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters The array matrix organisation allows each sector ICC mode, it fetches a specific RESET vector to be erased and reprogrammed without affecting which points to the ST7 System Memory contain- other sectors. ing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. 4.2 Main Features – Download ICP Driver code in RAM from the ICCDATA pin ■ ICP (In-Circuit Programming) ■ IAP (In-Application Programming) – Execute ICP Driver code in RAM to program the FLASH memory ■ ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully ■ Sector 0 size configurable by option byte customized (number of bytes to program, program ■ Read-out and write protection locations, or selection of the serial communication interface for downloading). 4.3 PROGRAMMING MODES 4.3.2 In Application Programming (IAP) The ST7 can be programmed in three different This mode uses an IAP Driver program previously ways: programmed in Sector 0 by the user (in ICP mode). – Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and This mode is fully controlled by user software. This data EEPROM can be programmed or allows it to be adapted to the user application, (us- erased. er-defined strategy for entering programming – In-Circuit Programming. In this mode, FLASH mode, choice of communications protocol used to sectors 0 and 1, option byte row and data EEPROM can be programmed or erased with- fetch the data to be stored etc.) out removing the device from the application IAP mode can be used to program any memory ar- board. eas except Sector 0, which is write/erase protect- – In-Application Programming. In this mode, ed to allow recovery in case errors occur during sector 1 and data EEPROM can be pro- the programming operation. grammed or erased without removing the de- vice from the application board and while the application is running. 13/124 1

ST7LITE0xY0, ST7LITESxY0 FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the appli- ICP needs a minimum of 4 and up to 6 pins to be cation RESET circuit in this case. When using a connected to the programming tool. These pins classical RC network with R>1K or a reset man- are: agement IC with open drain output and pull-up re- – RESET: device reset sistor>1K, no additional components are needed. – V : device power supply ground In all cases the user must ensure that no external SS – ICCCLK: ICC output serial clock pin reset is generated by the application during the ICC session. – ICCDATA: ICC input serial data pin – CLKIN: main clock input for external source 3. The use of Pin 7 of the ICC connector depends – V : application board power supply (option- on the Programming Tool architecture. This pin DD al, see Note 3) must be connected when using most ST Program- Notes: ming Tools (it is used to monitor the application power supply). Please refer to the Programming 1. If the ICCCLK or ICCDATA pins are only used Tool manual. as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is 4. Pin 9 has to be connected to the CLKIN pin of plugged to the board, even if an ICC session is not the ST7 when the clock is not available in the ap- in progress, the ICCCLK and ICCDATA pins are plication or if the selected clock option is not pro- not available for the application. If they are used as grammed in the option byte. inputs by the application, isolation such as a serial Caution: During normal operation, ICCCLK pin resistor has to be implemented in case another de- must be pulled- up, internally or externally (exter- vice forces the signal. Refer to the Programming nal pull-up of 10K mandatory in noisy environ- Tool documentation for recommended resistor val- ment). This is to avoid entering ICC mode unex- ues. pectedly during a reset. In the application, even if 2. During the ICP session, the programming tool the pin is configured as output, any reset will put it must control the RESET pin. This can lead to con- back in input pull-up. flicts between the programming tool and the appli- cation reset circuit if it drives more than 5mA at Figure 6. Typical ICC Interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR (See Note 3) HE10CONNECTORTYPE OPTIONAL APPLICATION BOARD (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION RESET SOURCE See Note 2 APPLICATION See Note 1 and Caution APPLICATION POWER SUPPLY I/O See Note 1 D N T K A VD LKI SE CL AT C E C D ST7 R C C I C I 14/124 1

ST7LITE0xY0, ST7LITESxY0 FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection Write/erase protection is enabled through the FMP_W bit in the option byte. There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.6 Related Documentation 4.5.1 Read out Protection For details on Flash programming and ICC proto- col, refer to the ST7 Flash Programming Refer- Readout protection, when selected provides a pro- ence Manual and to the ST7 ICC Protocol Refer- tection against program memory content extrac- ence Manual. tion and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level 4.7 Register Description of protection for a general purpose microcontroller. Both program and data E2 memory are protected. FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write In flash devices, this protection is removed by re- Reset Value: 000 0000 (00h) programming the option. In this case, both pro- 1st RASS Key: 0101 0110 (56h) gram and data E2 memory are automatically 2nd RASS Key: 1010 1110 (AEh) erased, and the device can be reprogrammed. Read-out protection selection depends on the de- 7 0 vice type: – In Flash devices it is enabled and removed 0 0 0 0 0 OPT LAT PGM through the FMP_R bit in the option byte. – In ROM devices it is enabled by mask option Note: This register is reserved for programming specified in the Option List. using ICP, IAP or other programming methods. It 4.5.2 Flash Write/Erase Protection controls the XFlash programming and erasing op- erations. Write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- When an EPB or another programming tool is ry. It does not apply to E2 data. Its purpose is to used (in socket or ICP mode), the RASS keys are provide advanced security to applications and pre- sent automatically. vent any change being made to the memory con- tent. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Table 3. FLASH Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label FCSR OPT LAT PGM 002Fh Reset Value 0 0 0 0 0 0 0 0 15/124 1

ST7LITE0xY0, ST7LITESxY0 5 DATA EEPROM 5.1 INTRODUCTION 5.2 MAIN FEATURES The Electrically Erasable Programmable Read ■ Up to 32 bytes programmed in the same cycle Only Memory can be used as a non-volatile back- ■ EEPROM mono-voltage (charge pump) up for storing data. Using the EEPROM requires a ■ Chained erase and programming cycles basic access protocol described in this chapter. ■ Internal control of the global programming cycle duration ■ WAIT mode management ■ Read-out protection Figure 7. EEPROM Block Diagram HIGHVOLTAGE PUMP EECSR 0 0 0 0 0 0 E2LATE2PGM EEPROM ADDRESS 4 ROW MEMORYMATRIX DECODER DECODER (1ROW=32x8BITS) 128 128 4 DATA 32x8BITS MULTIPLEXER DATALATCHES 4 ADDRESSBUS DATABUS 16/124 1

ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS the value is latched inside the 32 data latches ac- cording to its address. The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- When PGM bit is set by the software, all the previ- ROM Control/Status register (EECSR). The flow- ous bytes written in the data latches (up to 32) are chart in Figure 8 describes these different memory programmed in the EEPROM cells. The effective access modes. high address (row) is determined by the last EEP- ROM write sequence. To avoid wrong program- Read Operation (E2LAT=0) ming, the user must take care that all the bytes written between two programming sequences The EEPROM can be read as a normal ROM loca- have the same high address: Only the five Least tion when the E2LAT bit of the EECSR register is Significant Bits of the address can change. cleared. At the end of the programming cycle, the PGM and On this device, Data EEPROM can also be used to LAT bits are cleared simultaneously. execute machine code. Take care not to write to the Data EEPROM while executing from it. This Note: Care should be taken during the program- would result in an unexpected code being execut- ming cycle. Writing to the same memory location ed. will over-program the memory (logical AND be- tween the two write access data result) because Write Operation (E2LAT=1) the data latches are only cleared at the end of the To access the write mode, the E2LAT bit has to be programming cycle and by the falling edge of the set by software (the E2PGM bit remains cleared). E2LAT bit. When a write access to the EEPROM area occurs, It is not possible to read the latched data. This note is illustrated by the Figure 10. Figure 8. Data EEPROM Programming Flowchart READMODE WRITEMODE E2LAT=0 E2LAT=1 E2PGM=0 E2PGM=0 WRITEUPTO32BYTES READBYTES INEEPROMAREA INEEPROMAREA (withthesame11MSBoftheaddress) STARTPROGRAMMINGCYCLE E2LAT=1 E2PGM=1(setbysoftware) 0 1 E2LAT CLEAREDBYHARDWARE 17/124 1

ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) Figure 9. Data E2PROM Write Operation ⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address ROW 0 00h...1Fh DEFINITION 1 20h...3Fh ... N Nx20h...Nx20h+1Fh Readoperationimpossible Readoperationpossible Byte1 Byte2 Byte32 Programmingcycle PHASE 1 PHASE 2 Writingdatalatches WaitingE2PGMandE2LATtofall E2LATbit Setby USER application Cleared by hardware E2PGMbit Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed. 18/124 1

ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING Wait mode If a read access occurs while E2LAT=1, then the data bus will not be driven. The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- If a write access occurs while E2LAT=0, then the ler or when the microcontroller enters Active Halt data on the bus will not be latched. mode.The DATA EEPROM will immediately enter If a programming cycle is interrupted (by RESET this mode if there is no programming in progress, action), the integrity of the data in memory will not otherwise the DATA EEPROM will finish the cycle be guaranteed. and then enter WAIT mode. 5.6 DATA EEPROM READ-OUT PROTECTION Active Halt mode The read-out protection is enabled through an op- Refer to Wait mode. tion bit (see option byte section). When this option is selected, the programs and data stored in the EEPROM memory are protected Halt mode against read-out (including a re-write protection). The DATA EEPROM immediately enters HALT In Flash devices, when this protection is removed mode if the microcontroller executes the HALT in- by reprogramming the Option Byte, the entire Pro- struction. Therefore the EEPROM will stop the gram memory and EEPROM is first automatically function in progress, and data may be corrupted. erased. Note: Both Program Memory and data EEPROM are protected using the same option bit. Figure 10. Data EEPROM Programming Cycle READOPERATIONNOTPOSSIBLE READOPERATIONPOSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASECYCLE WRITECYCLE WRITEOF DATA LATCHES t PROG LAT PGM 19/124 1

ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 E2LAT E2PGM Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hard- ware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: If the E2PGM bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed. Table 4. DATA EEPROM Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label EECSR E2LAT E2PGM 0030h Reset Value 0 0 0 0 0 0 0 0 20/124 1

ST7LITE0xY0, ST7LITESxY0 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION Accumulator (A) This CPU has a full 8-bit architecture and contains The Accumulator is an 8-bit general purpose reg- six internal registers allowing efficient 8-bit data ister used to hold operands and the results of the manipulation. arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) 6.2 MAIN FEATURES In indexed addressing modes, these 8-bit registers ■ 63 basic instructions are used to create either effective addresses or ■ Fast 8-bit by 8-bit multiply temporary storage areas for data manipulation. ■ 17 main addressing modes (The Cross-Assembler generates a precede in- struction (PRE) to indicate that the following in- ■ Two 8-bit index registers struction refers to the Y register.) ■ 16-bit stack pointer The Y register is not affected by the interrupt auto- ■ Low power modes matic procedures (not pushed to and popped from ■ Maskable hardware interrupts the stack). ■ Non-maskable software interrupt Program Counter (PC) The program counter is a 16-bit register containing 6.3 CPU REGISTERS the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL The six CPU registers shown in Figure 11 are not (Program Counter Low which is the LSB) and PCH present in the memory mapping and are accessed (Program Counter High which is the MSB). by specific instructions. Figure 11. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 21/124 1

ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the Read/Write end of the routine. If the I bit is cleared by software Reset Value: 111x1xxx in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- 7 0 rent interrupt routine. 1 1 1 H I N Z C Bit 2 = N Negative. The 8-bit Condition Code register contains the in- This bit is set and cleared by hardware. It is repre- terrupt mask and four flags representative of the sentative of the result sign of the last arithmetic, result of the instruction just executed. This register logical or data manipulation. It is a copy of the 7th can also be handled by the PUSH and POP in- bit of the result. structions. 0: The result of the last operation is positive or null. These bits can be individually tested and/or con- 1: The result of the last operation is negative trolled by specific instructions. (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- Bit 4 = H Half carry. tions. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or Bit 1 = Z Zero. ADC instruction. It is reset by hardware during the same instructions. This bit is set and cleared by hardware. This bit in- 0: No half carry has occurred. dicates that the result of the last arithmetic, logical 1: A half carry has occurred. or data manipulation is zero. 0: The result of the last operation is different from This bit is tested using the JRH or JRNH instruc- zero. tion. The H bit is useful in BCD arithmetic subrou- 1: The result of the last operation is zero. tines. This bit is accessed by the JREQ and JRNE test instructions. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- Bit 0 = C Carry/borrow. rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by This bit is set and cleared by hardware and soft- software. ware. It indicates an overflow or an underflow has 0: Interrupts are enabled. occurred during the last arithmetic operation. 1: Interrupts are disabled. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- This bit is driven by the SCF and RCF instructions structions. and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and Note: Interrupts requested while I is set are rotate instructions. latched and can be processed when I is cleared. By default an interrupt routine is not interruptible 22/124 1

ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) Stack Pointer (SP) The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in- Read/Write struction. Reset Value: 00 FFh Note: When the lower limit is exceeded, the Stack 15 8 Pointer wraps around to the stack upper limit, with- out indicating the stack overflow. The previously 0 0 0 0 0 0 0 0 stored information is then overwritten and there- fore lost. The stack also wraps in case of an under- flow. 7 0 The stack is used to save the return address dur- 1 1 SP5 SP4 SP3 SP2 SP1 SP0 ing a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc- tions. In the case of an interrupt, the PCL is stored The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the ways pointing to the next free location in the stack. other registers are stored in the next locations as It is then decremented after data has been pushed shown in Figure 12. onto the stack and incremented before data is – When an interrupt is received, the SP is decre- popped from the stack (see Figure 12). mented and the context is pushed on the stack. Since the stack is 64 bytes deep, the 10 most sig- – On return from interrupt, the SP is incremented nificant bits are forced by hardware. Following an and the context is popped from the stack. MCU Reset, or after a Reset Stack Pointer instruc- tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in- ue (the SP5 to SP0 bits are set) which is the stack terrupt five locations in the stack area. higher address. Figure 12. Stack Manipulation Example CALL Interrupt PUSH Y POP Y IRET RET Subroutine event or RSP @ 00C0h SP SP SP Y CC CC CC A A A X X X PCH PCH PCH SP SP PCL PCL PCL PCH PCH PCH PCH PCH SP @ 00FFh PCL PCL PCL PCL PCL Stack Higher Address = 00FFh Stack Lower Address = 00C0h 23/124 1

ST7LITE0xY0, ST7LITESxY0 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for ST7FLITE05/ securing the application in critical situations (for RCCR Conditions ST7FLITE09 ST7FLITES5 example in case of a power brown-out), and re- Address Address ducing the number of external components. V =5V DD 1000h and Main features RCCR0 T =25°C FFDEh A FFDEh f =1MHz ■ Clock Management RC V =3.0V – 1 MHz internal RC oscillator (enabled by op- DD 1001h and- RCCR1 T =25°C FFDFh tion byte) A FFDFh f =700KHz RC – External Clock Input (enabled by option byte) – These two bytes are systematically programmed – PLL for multiplying the frequency by 4 or 8 by ST, including on FASTROM devices. Conse- (enabled by option byte) quently, customers intending to us e FASTROM ■ Reset Sequence Manager (RSM) service must not use these two bytes. ■ System Integrity Management (SI) – RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after – Main supply Low voltage detection (LVD) with it has been set. See “Read out Protection” on reset generation (enabled by option byte) page15. – Auxiliary Voltage detector (AVD) with interrupt Caution: If the voltage or temperature conditions capability for monitoring the main supply (en- change in the application, the frequency may need abled by option byte) to be recalibrated. Refer to application note AN1324 for information 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT on how to calibrate the RC frequency using an ex- ternal reference signal. The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature 7.2 PHASE LOCKED LOOP and voltage. It must be calibrated to obtain the fre- quency required in the application. This is done by The PLL can be used to multiply a 1MHz frequen- software writing a calibration value in the RCCR cy from the RC oscillator or the external clock by 4 (RC Control Register). or 8 to obtain f of 4 or 8 MHz. The PLL is ena- OSC Whenever the microcontroller is reset, the RCCR bled and the multiplication factor of 4 or 8 is select- returns to its default value (FFh), i.e. each time the ed by 2 option bits. device is reset, the calibration value must be load- – The x4 PLL is intended for operation with V in ed in the RCCR. Predefined calibration values are DD the 2.4V to 3.3V range stored in EEPROM for 3.0 and 5V V supply volt- DD ages at 25°C, as shown in the following table. – The x8 PLL is intended for operation with V in DD the 3.3V to 5.5V range Notes: Refer to Section 15.1 for the option byte descrip- – See “ELECTRICAL CHARACTERISTICS” on tion. page81. for more information on the frequency If the PLL is disabled and the RC oscillator is ena- and accuracy of the RC oscillator. bled, then f 1MHz. OSC = – To improve clock stability and frequency accura- If both the RC oscillator and the PLL are disabled, cy, it is recommended to place a decoupling ca- f is driven by the external clock. OSC pacitor, typically 100nF, between the V and DD V pins as close as possible to the ST7 device. SS 24/124 1

ST7LITE0xY0, ST7LITESxY0 Figure 13. PLL Output Frequency Timing Bit 1 = MCO Main Clock Out enable Diagram This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable LOCKED bit set the MCO output clock. 0: MCO clock disabled, I/O port free for general 4/8 x purpose I/O. input freq. 1: MCO clock enabled. t STAB Bit 0 = SMS Slow Mode select q. t This bit is read/write by software and cleared by e LOCK hardware after a reset. This bit selects the input r ut f clock fOSC or fOSC/32. utp tSTARTUP 01:: NSloorwm mal omdoed (ef (fCPUf = fOS/3C2 ) O CPU = OSC t RC CONTROL REGISTER (RCCR) Read / Write When the PLL is started, after reset or wakeup Reset Value: 1111 1111 (FFh) from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. 7 0 When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 is set. Full PLL accuracy (ACC ) is reached after PLL a stabilization time of t (see Figure 13 and STAB 13.3.4 Internal RC Oscillator and PLL) Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad- justment Bits Refer to section 8.4.4 on page 36 for a description These bits must be written immediately after reset of the LOCKED bit in the SICSR register. to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the 7.3 REGISTER DESCRIPTION correct value for each voltage range in EEPROM and write it to this register at start-up. MAIN CLOCK CONTROL/STATUS REGISTER 00h = maximum available frequency (MCCSR) FFh = lowest available frequency Read / Write Reset Value: 0000 0000 (00h) Note: To tune the oscillator, write a series of differ- ent values in the register until the correct frequen- 7 0 cy is reached. The fastest method is to use a di- chotomy starting with 80h. 0 0 0 0 0 0 MCO SMS Bits 7:2 = Reserved, must be kept cleared. Table 5. Clock Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label MCCSR MCO SMS 0038h Reset Value 0 0 0 0 0 0 0 0 RCCR CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0039h Reset Value 1 1 1 1 1 1 1 1 25/124 1

ST7LITE0xY0, ST7LITESxY0 SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d) Figure 14. Clock Management Block Diagram CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RCCR 1MHz 8MHz Tunable PLL 1MHz -> 8MHz fOSC PLL 1MHz -> 4MHz 1% RCOscillator 4MHz Option byte 0 to 8 MHz CLKIN /2 DIVIDER Option byte 8-BIT fLTIMER LITE TIMER COUNTER (1ms timebase @ 8 MHz f ) OSC fOSC fOSC/32 /32 DIVIDER 1 f CPU TO CPU AND fOSC 0 PERIPHERALS (except LITE TIMER) MCO SMS MCCSR 7 0 f CPU MCO 26/124 1

ST7LITE0xY0, ST7LITESxY0 7.4 RESET SEQUENCE MANAGER (RSM) 7.4.1 Introduction The 256 CPU clock cycle delay allows the oscilla- tor to stabilise and ensures that recovery has tak- The reset sequence manager includes three RE- en place from the Reset state. SET sources as shown in Figure 16: ■ External RESET source pulse The RESET vector fetch phase duration is 2 clock cycles. ■ Internal LVD RESET (Low Voltage Detection) If the PLL is enabled by option byte, it outputs the ■ Internal WATCHDOG RESET clock after an additional delay of t (see STARTUP Note: A reset can also be triggered following the Figure 13). detection of an illegal opcode or prebyte code. Re- fer to section 11.2.1 on page 53 for further details. Figure 15. RESET Sequence Phases These sources act on the RESET pin and it is al- ways kept low during the delay phase. RESET The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. INTERNAL RESET FETCH Active Phase The basic RESET sequence consists of 3 phases 256 CLOCK CYCLES VECTOR as shown in Figure 15: ■ Active Phase depending on the RESET source ■ 256 CPU clock cycle delay ■ RESET vector fetch Figure 16.Reset Block Diagram V DD R ON INTERNAL RESET FILTER RESET WATCHDOGRESET PULSE ILLEGAL OPCODE RESET 1) GENERATOR LVDRESET Note 1: See “Illegal Opcode Reset” on page78. for more details on illegal opcode reset conditions. 27/124 1

ST7LITE0xY0, ST7LITESxY0 RESET SEQUENCE MANAGER (Cont’d) 7.4.2 Asynchronous External RESET pin A proper reset signal for a slow rising V supply DD can generally be provided by an external RC net- The RESET pin is both an input and an open-drain work connected to the RESET pin. output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- 7.4.4 Internal Low Voltage Detector (LVD) cordance with the input voltage. It can be pulled RESET low by external circuitry to reset the device. See Two different RESET sequences caused by the in- Electrical Characteristic section for more details. ternal LVD circuitry can be distinguished: A RESET signal originating from an external source must have a duration of at least t in ■ Power-On RESET h(RSTL)in order to be recognized (see Figure 17). This de- ■ Voltage Drop RESET tection is asynchronous and therefore the MCU The device RESET pin acts as an output that is can enter reset state even in HALT mode. pulled low when V <V (rising edge) or DD IT+ The RESET pin is an asynchronous signal which VDD<VIT- (falling edge) as shown in Figure 17. plays a major role in EMS performance. In a noisy The LVD filters spikes on V larger than t to DD g(VDD) environment, it is recommended to follow the avoid parasitic resets. guidelines mentioned in the electrical characteris- tics section. 7.4.5 Internal Watchdog RESET 7.4.3 External Power-On RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 17. If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by Starting from the Watchdog counter underflow, the means of an external reset circuit that the reset device RESET pin acts as an output that is pulled signal is held low until V is over the minimum low during at least t . DD w(RSTL)out level specified for the selected f frequency. OSC Figure 17. RESET Sequences V DD V IT+(LVD) V IT-(LVD) LVD EXTERNAL WATCHDOG RESET RESET RESET RUN RUN RUN RUN ACTIVE ACTIVE ACTIVE PHASE PHASE PHASE t t w(RSTL)out h(RSTL)in EXTERNAL RESET SOURCE RESETPIN WATCHDOG RESET WATCHDOGUNDERFLOW INTERNALRESET(256 TCPU) VECTOR FETCH 28/124 1

ST7LITE0xY0, ST7LITESxY0 8 INTERRUPTS The ST7 core may be interrupted by one of two dif- 8.1 NON MASKABLE SOFTWARE INTERRUPT ferent methods: Maskable hardware interrupts as This interrupt is entered when the TRAP instruc- listed in the Interrupt Mapping Table and a non- tion is executed regardless of the state of the I bit. maskable software interrupt (TRAP). The Interrupt It is serviced according to the flowchart in Figure processing flowchart is shown in Figure 18. 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed 8.2 EXTERNAL INTERRUPTS when they are enabled (see external interrupts External interrupt vectors can be loaded into the subsection). PC register if the corresponding external interrupt Note: After reset, all interrupts are disabled. occurred and if the I bit is cleared. These interrupts When an interrupt has to be serviced: allow the processor to leave the HALT low power mode. – Normal processing is suspended at the end of the current instruction execution. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if – The PC, X, A and CC registers are saved onto available). the stack. An external interrupt triggered on edge will be – The I bit of the CC register is set to prevent addi- latched and the interrupt request automatically tional interrupts. cleared upon entering the interrupt service routine. – The PC is then loaded with the interrupt vector of Caution: The type of sensitivity defined in the Mis- the interrupt to service and the first instruction of cellaneous or Interrupt register (if available) ap- the interrupt service routine is fetched (refer to plies to the ei source. In case of a NANDed source the Interrupt Mapping Table for vector address- (as described in the I/O ports section), a low level es). on an I/O pin, configured as input with interrupt, The interrupt service routine should finish with the masks the interrupt request even in case of rising- IRET instruction which causes the contents of the edge sensitivity. saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, 8.3 PERIPHERAL INTERRUPTS the I bit is cleared and the main program resumes. Different peripheral interrupt flags in the status Priority Management register are able to cause an interrupt when they By default, a servicing interrupt cannot be inter- are active if both: rupted because the I bit is set by hardware enter- – The I bit of the CC register is cleared. ing in interrupt routine. – The corresponding enable bit is set in the control In the case when several interrupts are simultane- register. ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- If any of these two conditions is false, the interrupt ping Table). is latched and thus remains pending. Interrupts and Low Power Mode Clearing an interrupt request is done by: All interrupts allow the processor to leave the – Writing “0” to the corresponding bit in the status WAIT low power mode. Only external and specifi- register or cally mentioned interrupts allow the processor to – Access to the status register while the flag is set leave the HALT low power mode (refer to the “Exit followed by a read or write of an associated reg- from HALT” column in the Interrupt Mapping Ta- ister. ble). Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed. 29/124 1

ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROMRESET N I BIT SET? Y N INTERRUPT PENDING? Y FETCHNEXTINSTRUCTION N IRET? STACKPC,X,A,CC SETIBIT Y LOADPCFROMINTERRUPTVECTOR EXECUTEINSTRUCTION RESTOREPC,X,A,CCFROMSTACK THISCLEARSIBITBYDEFAULT Table 6. Interrupt Mapping Exit Source Register Priority Address N° Description from Block Label Order Vector HALT RESET Reset Highest yes FFFEh-FFFFh TRAP Software Interrupt Priority no FFFCh-FFFDh 0 Not used FFFAh-FFFBh 1 ei0 External Interrupt 0 N/A FFF8h-FFF9h 2 ei1 External Interrupt 1 FFF6h-FFF7h yes 3 ei2 External Interrupt 2 FFF4h-FFF5h 4 ei3 External Interrupt 3 FFF2h-FFF3h 5 Not used FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SI AVD interrupt SICSR no FFECh-FFEDh 8 AT TIMER Output Compare Interrupt PWM0CSR no FFEAh-FFEBh AT TIMER 9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h 10 LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h LITETIMER 11 LITE TIMER RTC Interrupt LTCSR yes FFE4h-FFE5h 12 SPI SPI Peripheral Interrupts SPICSR Lowest yes FFE2h-FFE3h 13 Not used Priority FFE0h-FFE1h 30/124 1

ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER Notes: (EICR) 1. These 8 bits can be written only when the I bit in Read/Write the CC register is set. Reset Value: 0000 0000 (00h) 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be 7 0 used to clear unwanted pending interrupts. Refer to section “External interrupt function” on page42. IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00 Table 7. Interrupt Sensitivity Bits Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 ISx1 ISx0 External Interrupt Sensitivity (Port B0) according to Table 7. 0 0 Falling edge & low level 0 1 Rising edge only Bit 5:4 = IS2[1:0] ei2 sensitivity 1 0 Falling edge only These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 7. 1 1 Rising and falling edge Bit 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 7. Bit 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 7. 31/124 1

ST7LITE0xY0, ST7LITESxY0 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains Provided the minimum V value (guaranteed for DD the Low voltage Detector (LVD) and Auxiliary Volt- the oscillator frequency) is above V , the IT-(LVD) age Detector (AVD) functions. It is managed by MCU can only be in two modes: the SICSR register. – under full software control Note: A reset can also be triggered following the – in static safe reset detection of an illegal opcode or prebyte code. Re- fer to section 12.2.1 on page 78 for further details. In these conditions, secure operation is always en- sured for the application without the need for ex- 8.4.1 Low Voltage Detector (LVD) ternal reset hardware. The Low Voltage Detector function (LVD) gener- During a Low Voltage Detector Reset, the RESET ates a static reset when the V supply voltage is DD pin is held low, thus permitting the MCU to reset below a V reference value. This means that IT-(LVD) other devices. it secures the power-up as well as the power-down keeping the ST7 in reset. The V reference value for a voltage drop is Notes: IT-(LVD) lower than the V reference value for power- The LVD is an optional function which can be se- IT+(LVD) on in order to avoid a parasitic reset when the lected by option byte. See section 15.1 on page MCU starts running and sinks current on the sup- 112. ply (hysteresis). It allows the device to be used without any external The LVD Reset circuitry generates a reset when RESET circuitry. V is below: DD If the LVD is disabled, an external circuitry must be – V when V is rising used to ensure a proper power-on reset. IT+(LVD) DD – V when V is falling It is recommended to make sure that the V sup- IT-(LVD) DD DD The LVD function is illustrated in Figure 19. ply voltage rises monotonously when the device is exiting from Reset, to ensure the application func- The voltage threshold can be configured by option tions properly. byte to be low, medium or high. See section 15.1 on page 112. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag. Figure 19. Low Voltage Detector vs Reset V DD V hys V IT+(LVD) V IT-(LVD) RESET 32/124 1

ST7LITE0xY0, ST7LITESxY0 Figure 20. Reset and Supply Management Block Diagram WATCHDOG STATUS FLAG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT RESETSEQUENCE AVD Interrupt Request RESET MANAGER SICSR (RSM) LOC LVDAVDAVD 0 0 0 0 KED RF F IE 7 0 LOW VOLTAGE VSS DETECTOR V (LVD) DD AUXILIARYVOLTAGE DETECTOR (AVD) 33/124 1

ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.2 Auxiliary Voltage Detector (AVD) 8.4.2.1 Monitoring the V Main Supply DD The Voltage Detector function (AVD) is based on The AVD voltage threshold value is relative to the an analog comparison between a V and selected LVD threshold configured by option byte IT-(AVD) V reference value and the V main sup- (see section 15.1 on page 112). IT+(AVD) DD ply voltage (V ). The V reference value AVD IT-(AVD) If the AVD interrupt is enabled, an interrupt is gen- for falling voltage is lower than the V refer- IT+(AVD) erated when the voltage crosses the V or ence value for rising voltage in order to avoid par- IT+(LVD) V threshold (AVDF bit is set). asitic detection (hysteresis). IT-(AVD) In the case of a drop in voltage, the AVD interrupt The output of the AVD comparator is directly read- acts as an early warning, allowing software to shut able by the application software through a real down safely before the LVD resets the microcon- time status bit (AVDF) in the SICSR register. This troller. See Figure 21. bit is read only. The interrupt on the rising edge is used to inform Caution: The AVD functions only if the LVD is en- the application that the V warning state is over abled through the option byte. DD Figure 21. Using the AVD to Monitor V DD V DD Early Warning Interrupt (Power has dropped, MCU not not yet in reset) V hyst V IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit 0 1 RESET 1 0 AVD INTERRUPT REQUEST IF AVDIE bit = 1 INTERRUPTCleared by INTERRUPTCleared by reset hardware LVD RESET 34/124 1

ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.3 Low Power Modes set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description Enable Exit Exit No effect on SI. AVD interrupts cause the Event WAIT Interrupt Event Control from from device to exit from Wait mode. Flag Bit Wait Halt The SICSR register is frozen. HALT The AVD remains active but the AVD inter- AVD event AVDF AVDIE Yes No rupt cannot be used to exit from Halt mode. 8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is 35/124 1

ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write If the AVDIE bit is set, an interrupt request is gen- erated when the AVDF bit is set. Refer to Figure Reset Value: 0000 0x00 (0xh) 21 for additional details 0: V over AVD threshold 7 0 DD 1: V under AVD threshold DD LOCK 0 0 0 0 LVDRF AVDF AVDIE ED Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables Bit 7:4 = Reserved, must be kept cleared. an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automati- cally cleared when software enters the AVD inter- Bit 3 = LOCKED PLL Locked Flag rupt routine. This bit is set by hardware. It is cleared only by a 0: AVD interrupt disabled power-on reset. It is set automatically when the 1: AVD interrupt enabled PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked Application notes The LVDRF flag is not cleared when another RE- Bit 2 = LVDRF LVD reset flag SET type occurs (external or watchdog), the This bit indicates that the last Reset was generat- LVDRF flag remains set to keep trace of the origi- ed by the LVD block. It is set by hardware (LVD re- nal failure. set) and cleared by software (writing zero). See In this case, a watchdog reset can be detected by WDGRF flag description in Section 11.1 for more software while an external reset can not. details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. Table 8. System Integrity Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label SICSR LOCKED LVDRF AVDF AVDIE 003Ah Reset Value 0 0 0 0 0 x 0 0 36/124 1

ST7LITE0xY0, ST7LITESxY0 9 POWER SAVING MODES 9.1 INTRODUCTION 9.2 SLOW MODE To give a large measure of flexibility to the applica- This mode has two targets: tion in terms of power consumption, four main – To reduce power consumption by decreasing the power saving modes are implemented in the ST7 internal clock in the device, (see Figure 22): SLOW, WAIT (SLOW WAIT), AC- TIVE HALT and HALT. – To adapt the internal clock frequency (fCPU) to the available supply voltage. After a RESET the normal operating mode is se- lected by default (RUN mode). This mode drives SLOW mode is controlled by the SMS bit in the the device (CPU and embedded peripherals) by MCCSR register which enables or disables Slow means of a master clock which is based on the mode. main oscillator frequency (fOSC). In this mode, the oscillator frequency is divided by From RUN mode, the different power saving 32. The CPU and peripherals are clocked at this modes may be selected by setting the relevant lower frequency. register bits or by calling the specific ST7 software Notes: instruction whose action depends on the oscillator SLOW-WAIT mode is activated when entering status. WAIT mode while the device is already in SLOW mode. Figure 22. Power Saving Mode Transitions SLOW mode has no effect on the Lite Timer which is already clocked at F . OSC/32 High Figure 23. SLOW Mode Clock Transition RUN f /32 f OSC OSC SLOW f CPU WAIT f OSC SLOWWAIT SMS ACTIVEHALT NORMALRUNMODE REQUEST HALT Low POWERCONSUMPTION 37/124 1

ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.3 WAIT MODE Figure 24. WAIT Mode Flow-chart WAIT mode places the MCU in a low power con- OSCILLATOR ON sumption mode by stopping the CPU. PERIPHERALS ON This power saving mode is selected by calling the WFIINSTRUCTION CPU OFF ‘WFI’ instruction. IBIT 0 All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until N RESET an interrupt or RESET occurs, whereupon the Pro- gram Counter branches to the starting address of the interrupt or Reset service routine. N Y INTERRUPT The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Y Refer to Figure 24. OSCILLATOR ON PERIPHERALS OFF CPU ON IBIT 0 256CPUCLOCKCYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON IBIT X1) FETCHRESETVECTOR ORSERVICEINTERRUPT Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 38/124 1

ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4 ACTIVE-HALT AND HALT MODES Figure 25. ACTIVE-HALT Timing Overview ACTIVE-HALT and HALT modes are the two low- ACTIVE est power consumption modes of the MCU. They RUN HALT CYC2L5E6 DCEPLUAY 1) RUN are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ACTIVE-HALT RESET or HALT mode is given by the LTCSR/ATCSR reg- OR ister status as shown in the following table:. HALT INTERRUPT FETCH INSTRUCTION VECTOR ATCSR [Active Halt Enabled] LTCSR ATCSR ATCSR OVFIE Meaning TBIE bit CK1 bit CK0 bit bit Figure 26. ACTIVE-HALT Mode Flow-chart 0 x x 0 ACTIVE-HALT OSCILLATOR ON 0 0 x x mode disabled HALTINSTRUCTION PERIPHERALS2)OFF 0 1 1 1 (Active Halt enabled) CPU OFF IBIT 0 1 x x x ACTIVE-HALT x 1 0 1 mode enabled N 9.4.1 ACTIVE-HALT MODE RESET ACTIVE-HALT mode is the lowest power con- sumption mode of the MCU with a real time clock N Y INTERRUPT3) available. It is entered by executing the ‘HALT’ in- struction when active halt mode is enabled. Y OSCILLATOR ON The MCU can exit ACTIVE-HALT mode on recep- PERIPHERALS2)OFF tion of a Lite Timer / AT Timer interrupt or a RE- CPU ON SET. IBIT X4) – When exiting ACTIVE-HALT mode by means of a RESET, a 256 CPU cycle delay occurs. After 256CPUCLOCKCYCLE the start up delay, the CPU resumes operation DELAY by fetching the reset vector which woke it up (see Figure 26). OSCILLATOR ON – When exiting ACTIVE-HALT mode by means of PERIPHERALS ON an interrupt, the CPU immediately resumes oper- CPU ON ation by servicing the interrupt vector which woke IBITS X4) it up (see Figure 26). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. FETCHRESETVECTOR Therefore, if an interrupt is pending, the MCU ORSERVICEINTERRUPT wakes up immediately. Notes: In ACTIVE-HALT mode, only the main oscillator 1. This delay occurs only if the MCU exits ACTIVE- and the selected timer counter (LT/AT) are running HALT mode by means of a RESET. to keep a wake-up time base. All other peripherals 2. Peripherals clocked with an external clock are not clocked except those which get their clock source can still be active. supply from another clock generator (such as ex- 3. Only the Lite Timer RTC and AT Timer interrupts ternal or auxiliary oscillator). can exit the MCU from ACTIVE-HALT mode. 4. Before servicing an interrupt, the CC register is Caution: As soon as ACTIVE-HALT is enabled, pushed on the stack. The I bit of the CC register is executing a HALT instruction while the Watchdog set during the interrupt routine and cleared when is active does not generate a RESET if the the CC register is popped. WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode. 39/124 1

ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2 HALT MODE Figure 28. HALT Mode Flow-chart The HALT mode is the lowest power consumption HALTINSTRUCTION mode of the MCU. It is entered by executing the (Active Halt disabled) ‘HALT’ instruction when active halt mode is disa- bled. ENABLE WATCHDOG The MCU can exit HALT mode on reception of ei- ther a specific interrupt (see Table6, “Interrupt WDGHALT1) 0 DISABLE Mapping,” on page30) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, 1 the oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize the oscillator. WATCHDOG OSCILLATOR OFF After the start up delay, the CPU resumes opera- RESET PERIPHERALS2)OFF tion by servicing the interrupt or by fetching the re- CPU OFF set vector which woke it up (see Figure 28). IBIT 0 When entering HALT mode, the I bit in the CC reg- ister is forced to 0 to enable interrupts. Therefore, N if an interrupt is pending, the MCU wakes immedi- RESET ately. N Y In HALT mode, the main oscillator is turned off INTERRUPT3) causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. Y OSCILLATOR ON All peripherals are not clocked except the ones PERIPHERALS OFF which get their clock supply from another clock CPU ON generator (such as an external or auxiliary oscilla- IBIT X4) tor). The compatibility of Watchdog operation with 256CPUCLOCKCYCLE HALT mode is configured by the “WDGHALT” op- DELAY tion bit of the option byte. The HALT instruction when executed while the Watchdog system is en- abled, can generate a Watchdog RESET (see sec- OSCILLATOR ON tion 15.1 on page 112 for more details). PERIPHERALS ON CPU ON Figure 27. HALT Timing Overview IBITS X4) 256CPUCYCLE FETCHRESETVECTOR RUN HALT RUN DELAY ORSERVICEINTERRUPT RESET Notes: OR 1. WDGHALT is an option bit. See option byte sec- HALT INTERRUPT tion for more details. INSTRUCTION FETCH 2. Peripheral clocked with an external clock source [Active Halt disabled] VECTOR can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Re- fer to Table6, “Interrupt Mapping,” on page30 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after a delay of t (see Figure 13). STARTUP 40/124 1

ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2.1 HALT Mode Recommendations – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a – Make sure that an external event is available to program counter failure, it is advised to clear all wake up the microcontroller from Halt mode. occurrences of the data value 0x8E from memo- – When using an external interrupt to wake up the ry. For example, avoid defining a constant in microcontroller, reinitialize the corresponding I/O ROM with the value 0x8E. as “Input Pull-up with Interrupt” before executing – As the HALT instruction clears the I bit in the CC the HALT instruction. The main reason for this is register to allow interrupts, the user may choose that the I/O may be wrongly configured due to ex- to clear all pending interrupt bits before execut- ternal interference or by an unforeseen logical ing the HALT instruction. This avoids entering condition. other peripheral interrupt routines after executing – For the same reason, reinitialize the level sensi- the external interrupt routine corresponding to tiveness of each external interrupt as a precau- the wake-up event (reset or external interrupt). tionary measure. 41/124 1

ST7LITE0xY0, ST7LITESxY0 10 I/O PORTS 10.1 INTRODUCTION are logically ANDed. For this reason if one of the interrupt pins is tied low, it may mask the others. The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs External interrupts are hardware interrupts. Fetch- ing the corresponding interrupt vector automatical- and for specific pins: ly clears the request latch. Changing the sensitivity – external interrupt generation of a particular external interrupt clears this pending – alternate signal input/output for the on-chip pe- interrupt. This can be used to clear unwanted ripherals. pending interrupts. An I/O port contains up to 8 pins. Each pin can be Spurious interrupts programmed independently as digital input (with or without interrupt generation) or digital output. When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spu- rious interrupt is generated if the pin level is low 10.2 FUNCTIONAL DESCRIPTION and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is Each port has 2 main registers: switched to '1' when the external interrupt is disa- – Data Register (DR) bled by the OR register. – Data Direction Register (DDR) To avoid this unwanted interrupt, a "safe" edge and one optional register: sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before – Option Register (OR) changing the OR register bit and configuring the Each I/O pin may be programmed using the corre- appropriate sensitivity again. sponding register bits in the DDR and OR regis- Caution: In case a pin level change occurs during ters: bit X corresponding to pin X of the port. The these operations (asynchronous signal input), as same correspondence is used for the DR register. interrupts are generated according to the current The following description takes into account the sensitivity, it is advised to disable all interrupts be- OR register, (for specific ports which do not pro- fore and to reenable them after the complete pre- vide this register refer to the I/O Port Implementa- vious sequence in order to avoid an external inter- tion section). The generic I/O block diagram is rupt occurring on the unwanted edge. shown in Figure 29 This corresponds to the following steps: 10.2.1 Input Modes 1. To enable an external interrupt: The input configuration is selected by clearing the – set the interrupt mask with the SIM instruction corresponding DDR register bit. (in cases where a pin level change could oc- In this case, reading the DR register returns the cur) digital value applied to the external I/O pin. – select rising edge Different input modes can be selected by software – enable the external interrupt through the OR through the OR register. register Note: Writing the DR register modifies the latch – select the desired sensitivity if different from value but does not affect the pin status. rising edge External interrupt function – reset the interrupt mask with the RIM instruc- When an I/O is configured as Input with Interrupt, tion (in cases where a pin level change could an event on this I/O can generate an external inter- occur) rupt request to the CPU. 2. To disable an external interrupt: Each pin can independently generate an interrupt – set the interrupt mask with the SIM instruction request. The interrupt sensitivity is independently SIM (in cases where a pin level change could programmable using the sensitivity bits in the occur) EICR register. – select falling edge Each external interrupt vector is linked to a dedi- – disable the external interrupt through the OR cated group of I/O port pins (see pinout description register and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these – select rising edge 42/124 1

ST7LITE0xY0, ST7LITESxY0 – reset the interrupt mask with the RIM instruc- 10.2.2 Alternate Functions tion (in cases where a pin level change could When an on-chip peripheral is configured to use a occur) pin, the alternate function is automatically select- Output Modes ed. This alternate function takes priority over the standard I/O programming under the following The output configuration is selected by setting the conditions: corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the – When the signal is coming from an on-chip pe- I/O pin through the latch. Then reading the DR reg- ripheral, the I/O pin is automatically configured in ister returns the previously stored value. output mode (push-pull or open drain according to the peripheral). Two different output modes can be selected by software through the OR register: Output push-pull – When the signal is going to an on-chip peripher- and open-drain. al, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally DR register value and output pin status: readable by addressing the DR register. DR Push-pull Open-drain Notes: 0 V Vss SS – Input pull-up configuration can cause unexpect- 1 V Floating DD ed value at the input of the alternate peripheral input. Note: When switching from input to output mode, the DR register has to be written first to drive the – When an on-chip peripheral use a pin as input correct level on the pin as soon as the port is con- and output, this pin has to be configured in input figured as an output. floating mode. 43/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE REGISTER 1 OUTPUT V P-BUFFER ACCESS DD (seetablebelow) 0 ALTERNATE PULL-UP ENABLE (seetablebelow) DR V DD DDR PULL-UP PAD CONDITION OR D A T If implemented A B US OR SEL N-BUFFER DIODES (seetablebelow) DDR SEL ANALOG INPUT CMOS SCHMITT DR SEL 1 TRIGGER 0 ALTERNATE INPUT EXTERNAL FROM INTERRUPT OTHER SOURCE (eix) BITS POLARITY SELECTION Table 9. I/O Port Mode Options Diodes Configuration Mode Pull-Up P-Buffer toV toV DD SS Floating with/without Interrupt Off Input Off Pull-up with/without Interrupt On On On Push-pull On Output Off Open Drain (logic level) Off Legend: NI - not implemented Off - implemented not activated On - implemented and activated 44/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Table 10. I/O Port Configurations HardwareConfiguration DRREGISTERACCESS V DD PULL-UP RPU CONDITION DR W REGISTER DATABUS PAD R 1) T U P ALTERNATEINPUT N FROM I OTHER PINS EXTERNALINTERRUPT SOURCE (ei) x INTERRUPT POLARITY CONDITION SELECTION ANALOGINPUT DRREGISTERACCESS 2) VDD T U P R T PU U DR R/W O PAD REGISTER DATABUS N AI R D N- E P ALTERNATE ALTERNATE O ENABLE OUTPUT DRREGISTERACCESS V 2) DD T U P RPU T DR R/W OU PAD REGISTER DATABUS L L U P H- S U P ALTERNATE ALTERNATE ENABLE OUTPUT Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 45/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- 10.5 INTERRUPTS tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious The external interrupt event generates an interrupt interrupts. if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in Analog alternate function the CC register is not active (RIM instruction). When the pin is used as an ADC input, the I/O must be configured as floating input. The analog Enable Exit Exit Event multiplexer (controlled by the ADC registers) InterruptEvent Control from from Flag switches the analog voltage present on the select- Bit Wait Halt ed pin to the common analog rail which is connect- External interrupt on ed to the ADC input. DDRx selected external - Yes Yes ORx It is recommended not to change the voltage level event or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected an- 10.6 I/O PORT IMPLEMENTATION alog pin. The hardware implementation on each I/O port de- pends on the settings in the DDR and OR registers WARNING: The analog input voltage level must and specific feature of the I/O port such as ADC In- be within the limits stated in the absolute maxi- put. mum ratings. Switching these I/O ports from one state to anoth- er should be done in a sequence that prevents un- 10.3 UNUSED I/O PINS wanted side effects. Recommended safe transi- tions are illustrated in Figure 30 Other transitions Unused I/O pins must be connected to fixed volt- are potentially risky and should be avoided, since age levels. Refer to Section 13.8. they are likely to present unwanted side-effects such as spurious interrupt generation. 10.4 LOW POWER MODES Figure 30. Interrupt I/O Port State Transitions Mode Description No effect on I/O ports. External interrupts WAIT 01 00 10 11 cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts INPUT INPUT OUTPUT OUTPUT HALT cause the device to exit from HALT mode. floating/pull-up floating open-drain push-pull interrupt (reset state) XX = DDR, OR The I/O port register configurations are summa- rised as follows. Table 11. Port Configuration Input (DDR=0) Output (DDR=1) Port Pin name OR = 0 OR = 1 OR = 0 OR = 1 PA7 floating pull-up interrupt open drain push-pull Port A PA6:1 floating pull-up open drain push-pull PA0 floating pull-up interrupt open drain push-pull PB4 floating pull-up open drain push-pull PB3 floating pull-up interrupt open drain push-pull Port B PB2:1 floating pull-up open drain push-pull PB0 floating pull-up interrupt open drain push-pull 46/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label PADR MSB LSB 0000h Reset Value 0 0 0 0 0 0 0 0 PADDR MSB LSB 0001h Reset Value 0 0 0 0 0 0 0 0 PAOR MSB LSB 0002h Reset Value 0 1 0 0 0 0 0 0 PBDR MSB LSB 0003h Reset Value 1 1 1 0 0 0 0 0 PBDDR MSB LSB 0004h Reset Value 0 0 0 0 0 0 0 0 PBOR MSB LSB 0005h Reset Value 0 0 0 0 0 0 0 0 47/124 1

ST7LITE0xY0, ST7LITESxY0 11 ON-CHIP PERIPHERALS 11.1 LITE TIMER (LT) 11.1.1 Introduction ■ Watchdog – Enabled by hardware or software (configura- The Lite Timer can be used for general-purpose ble by option byte) timing functions. It is based on a free-running 8-bit upcounter with two software-selectable timebase – Optional reset on HALT instruction (configura- ble by option byte) periods, an 8-bit input capture register and watch- dog function. – Automatically resets the device unless disable bit is refreshed – Software reset (Forced Watchdog reset) 11.1.2 Main Features – Watchdog reset status flag ■ Realtime Clock – 8-bit upcounter – 1 ms or 2 ms timebase period (@ 8 MHz f ) OSC – Maskable timebase interrupt ■ Input Capture – 8-bit input capture register (LTICR) – Maskable interrupt with wakeup from Halt Mode capability Figure 31. Lite Timer Block Diagram f LTIMER To 12-bit AT TImer f WDG WATCHDOG WATCHDOG RESET f /32 OSC /2 1 Timebase 1 or 2 ms 8-bit UPCOUNTER 0 fLTIMER (@ 8MHz f ) OSC LTICR 8 8-bit LTIC INPUT CAPTURE REGISTER LTCSR WDG ICIE ICF TB TBIE TBF WDGEWDGD RF 7 0 LTTB INTERRUPT REQUEST LTIC INTERRUPT REQUEST 48/124 1

ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.3 Functional Description watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit The value of the 8-bit counter cannot be read or has to be set. written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f /32. A The WDGRF bit also acts as a flag, indicating that OSC counter overflow event occurs when the counter the Watchdog was the source of the reset. It is au- rolls over from F9h to 00h. If f = 8 MHz, then tomatically cleared after it has been read. OSC the time period between two counter overflow Caution: When the WDGRF bit is set, software events is 1 ms. This period can be doubled by set- must clear it, otherwise the next time the watchdog ting the TB bit in the LTCSR register. is enabled (by hardware or software), the micro- When the timer overflows, the TBF bit is set by controller will be immediately reset. hardware and an interrupt request is generated if Hardware Watchdog Option the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGE bit in 11.1.3.1 Watchdog the LTCSR is not used. The watchdog is enabled using the WDGE bit. Refer to the Option Byte description in the "device The normal Watchdog timeout is 2ms (@ = 8 MHz configuration and ordering information" section. f ), after which it then generates a reset. OSC Using Halt Mode with the Watchdog (option) To prevent this watchdog reset occuring, software If the Watchdog reset on HALT option is not se- must set the WDGD bit. The WDGD bit is cleared lected by option byte, the Halt mode can be used by hardware after t . This means that software when the watchdog is enabled. WDG must write to the WDGD bit at regular intervals to In this case, the HALT instruction stops the oscilla- prevent a watchdog reset occurring. Refer to Fig- tor. When the oscillator is stopped, the Lite Timer ure 32. stops counting and is no longer able to generate a If the watchdog is not enabled immediately after Watchdog reset until the microcontroller receives reset, the first watchdog timeout will be shorter an external interrupt or a reset. than 2ms, because this period is counted starting If an external interrupt is received, the WDG re- from reset. Moreover, if a 2ms period has already starts counting after 256 CPU clocks. If a reset is elapsed after the last MCU reset, the watchdog re- generated, the Watchdog is disabled (reset state). set will take place as soon as the WDGE bit is set. If Halt mode with Watchdog is enabled by option For these reasons, it is recommended to enable byte (No watchdog reset on HALT instruction), it is the Watchdog immediately after reset or else to recommended before executing the HALT instruc- set the WDGD bit before the WGDE bit so a tion to refresh the WDG counter, to avoid an unex- watchdog reset will not occur for at least 2ms. pected WDG reset immediately after waking up A Watchdog reset can be forced at any time by the microcontroller. setting the WDGRF bit. To generate a forced 49/124 1

ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Figure 32. Watchdog Timing Diagram HARDWARE CLEARS WDGD BIT t WDG (2ms @ 8MHz f ) OSC f WDG WDGD BIT INTERNAL WATCHDOG RESET SOFTWARE SETS WDGD BIT WATCHDOG RESET 50/124 1

ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Input Capture 11.1.5 Interrupts The 8-bit input capture register is used to latch the Exit free-running upcounter after a rising or falling edge Enable Exit Exit Interrupt Event from is detected on the LTIC pin. When an input capture Control from from Event Flag Active- occurs, the ICF bit is set and the LTICR register Bit Wait Halt Halt contains the value of the free-running upcounter. Timebase An interrupt is generated if the ICIE bit is set. The TBF TBIE Yes Event Yes No ICF bit is cleared by reading the LTICR register. IC Event ICF ICIE No The LTICR is a read only register and always con- tains the data from the last input capture. Input Note: The TBF and ICF interrupt events are con- capture is inhibited if the ICF bit is set. nected to separate interrupt vectors (see Inter- rupts chapter). 11.1.4 Low Power Modes Timebase and IC events generate an interrupt if Mode Description the enable bit is set in the LTCSR register and the No effect on Lite timer interrupt mask in the CC register is reset (RIM in- SLOW (this peripheral is driven directly by struction). f /32) OSC WAIT No effect on Lite timer ACTIVE HALT No effect on Lite timer HALT Lite timer stops counting Figure 33. Input Capture Timing Diagram 4µs (@ 8MHz f ) OSC fCPU fOSC/32 CLEARED BY S/W READING 8-bit COUNTER 01h 02h 03h 04h 05h 06h 07h LTIC REGISTER LTICPIN ICFFLAG LTICRREGISTER xxh 04h 07h t 51/124 1

ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.6 Register Description 0: No counter overflow 1: A counter overflow has occurred LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Bit 2 = WDGRF Force Reset/ Reset Status Flag Reset Value: 0x00 0000 (x0h) This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when 7 0 a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when ICIE ICF TB TBIE TBF WDGR WDGE WDGD an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register. 0: No watchdog reset occurred. Bit 7 = ICIE Interrupt Enable 1: Force a watchdog reset (write), or, a watchdog This bit is set and cleared by software. reset occurred (read). 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. Bit 6 = ICF Input Capture Flag 0: Watchdog disabled This bit is set by hardware and cleared by software 1: Watchdog enabled by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture Bit 0 = WDGD Watchdog Reset Delay 1: An input capture has occurred This bit is set by software. It is cleared by hard- ware at the end of each t period. Note: After an MCU reset, software must initialise WDG 0: Watchdog reset not delayed the ICF bit by reading the LTICR register 1: Watchdog reset delayed LITE TIMER INPUT CAPTURE REGISTER Bit 5 = TB Timebase period selection (LTICR) This bit is set and cleared by software. Read only 0: Timebase period = t * 8000 (1ms @ 8 MHz) Reset Value: 0000 0000 (00h) OSC 1: Timebase period = t * 16000 (2ms @ 8 OSC MHz) 7 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Bit 4 = TBIE Timebase Interrupt enable This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled Bit 7:0 = ICR[7:0] Input Capture Value 1: Timebase (TB) interrupt enabled These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be Bit 3 = TBF Timebase Interrupt Flag captured when a rising or falling edge occurs on This bit is set by hardware and cleared by software the LTIC pin. reading the LTCSR register. Writing to this bit has no effect. Table 13. Lite Timer Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label LTCSR ICIE ICF TB TBIE TBF WDGRF WDGE WDGD 0B Reset Value 0 x 0 0 0 0 0 0 LTICR ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 0C Reset Value 0 0 0 0 0 0 0 0 52/124 1

ST7LITE0xY0, ST7LITESxY0 11.2 12-BIT AUTORELOAD TIMER (AT) 11.2.1 Introduction ■ PWM signal generator The 12-bit Autoreload Timer can be used for gen- ■ Frequency range 2KHz-4MHz (@ 8 MHz fCPU) eral-purpose timing functions. It is based on a free- – Programmable duty-cycle running 12-bit upcounter with a PWM output chan- – Polarity control nel. – Maskable Compare interrupt 11.2.2 Main Features ■ Output Compare Function ■ 12-bit upcounter with 12-bit autoreload register (ATR) ■ Maskable overflow interrupt Figure 34. Block Diagram OVF INTERRUPT 7 ATCSR 0 REQUEST 0 0 0 CK1 CK0 OVF OVFIECMPIE CMP INTERRUPT REQUEST f CMPF0 LTIMER (1 ms timebase @ 8MHz) fCOUNTER 12-BIT UPCOUNTER CNTR Update on OVF Event f CPU 12-BIT AUTORELOAD VALUE ATR OE0 bit DCR0H DCR0L OE0 bit CMPF0 bit N OP0 bit OL Preload Preload O R TI T on OVF Event 10 CPOAMREP- NERA fPWM PAORILT-Y T CON PWM0 E U IF OE0=1 G P M T U 12-BIT DUTY CYCLE VALUE (shadow) W O P 53/124 1

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the PWM Mode preloaded Duty cycle value is transferred to the This mode allows a Pulse Width Modulated sig- Duty Cycle register and the PWM0 signal is set to nals to be generated on the PWM0 output pin with a high level. When the upcounter matches the minimum core processing overhead. The PWM0 DCRx value the PWM0 signals is set to a low level. output signal can be enabled or disabled using the To obtain a signal on the PWM0 pin, the contents OE0 bit in the PWMCR register. When this bit is of the DCR0 register must be greater than the con- set the PWM I/O pin is configured as output push- tents of the ATR register. pull alternate function. The polarity bit can be used to invert the output Note: CMPF0 is available in PWM mode (see signal. PWM0CSR description on page 57). The maximum available resolution for the PWM0 PWM Frequency and Duty Cycle duty cycle is: The PWM signal frequency (f ) is controlled by PWM Resolution = 1 / (4096 - ATR) the counter period and the ATR register value. Note: To get the maximum resolution (1/4096), the f = f / (4096 - ATR) PWM COUNTER ATR register must be 0. With this maximum reso- Following the above formula, if fCPU is 8 MHz, the lution and assuming that DCR=ATR, a 0% or maximum value of fPWM is 4 Mhz (ATR register 100% duty cycle can be obtained by changing the value = 4094), and the minimum value is 2 kHz polarity . (ATR register value = 0). Caution: As soon as the DCR0H is written, the Note: The maximum value of ATR is 4094 be- compare function is disabled and will start only cause it must be lower than the DCR value which when the DCR0L value is written. If the DCR0H must be 4095 in this case. write occurs just before the compare event, the At reset, the counter starts counting from 0. signal on the PWM output may not be set to a low level. In this case, the DCRx register should be up- Software must write the duty cycle value in the dated just after an OVF event. If the DCR and ATR DCR0H and DCR0L preload registers. The values are close, then the DCRx register shouldbe DCR0H register must be written first. See caution updated just before an OVF event, in order not to below. miss a compare event and to have the right signal applied on the PWM output. Figure 35. PWM Function 4095 DUTY CYCLE REGISTER R (DCR0) E T N U O C AUTO-RELOAD REGISTER (ATR) 000 t T U WITH OE0=1 P T AND OP0=0 U O 0 WITH OE0=1 M W AND OP0=1 P 54/124 1

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) Figure 36. PWM Signal Example fCOUNTER ATR= FFDh T UTPUE0=1P0=0 COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh OOO WM0 WITH AND DCR0=FFEh P t Output Compare Mode The compare between DCRx or the shadow regis- ter and the timer counter is locked until DCR0L is To use this function, the OE bit must be 0, other- written. wise the compare is done with the shadow register instead of the DCRx register. Software must then 11.2.4 Low Power Modes write a 12-bit value in the DCR0H and DCR0L reg- Mode Description isters. This value will be loaded immediately (with- out waiting for an OVF event). The input frequency is divided SLOW The DCR0H must be written first, the output com- by 32 pare function starts only when the DCR0L value is WAIT No effect on AT timer written. AT timer halted except if CK0=1, ACTIVE-HALT When the 12-bit upcounter (CNTR) reaches the CK1=0 and OVFIE=1 value stored in the DCR0H and DCR0L registers, HALT AT timer halted the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE 11.2.5 Interrupts bit is set. Note: The output compare function is only availa- Exit ble for DCRx values other than 0 (reset value). Interrupt Event Enable Exit Exit from Event 1) Flag Control from from Active- Bit Wait Halt Halt Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L Overflow OVF OVFIE Yes No Yes2) Event value has not yet been written (in this case, the CMP Event CMPFx CMPIE Yes No No shadow register will contain the new DCR0H value and the old DCR0L value), then: Notes: – If OE=1 (PWM mode): the compare is done be- 1. The interrupt events are connected to separate tween the timer counter and the shadow register interrupt vectors (see Interrupts chapter). (and not DCRx) They generate an interrupt if the enable bit is set in – if OE=0 (OCMP mode): the compare is done be- the ATCSR register and the interrupt mask in the tween the timer counter and DCRx. There is no CC register is reset (RIM instruction). PWM signal. 2. only if CK0=1and CK1=0 55/124 1

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description hardware after a reset. It allows to mask the inter- rupt generation when CMPF bit is set. TIMER CONTROL STATUS REGISTER (ATC- 0: CMPF interrupt disabled SR) 1: CMPF interrupt enabled Read / Write Reset Value: 0000 0000 (00h) COUNTER REGISTER HIGH (CNTRH) 7 0 Read only Reset Value: 0000 0000 (00h) 0 0 0 CK1 CK0 OVF OVFIE CMPIE 15 8 Bit 7:5 = Reserved, must be kept cleared. 0 0 0 0 CN11 CN10 CN9 CN8 Bit 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the COUNTER REGISTER LOW (CNTRL) clock frequency of the counter. Read only Reset Value: 0000 0000 (00h) Counter Clock Selection CK1 CK0 7 0 OFF 0 0 f (1 ms timebase @ 8 MHz) 0 1 LTIMER CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0 f 1 0 CPU Reserved 1 1 Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = CNTR[11:0] Counter Value. Bit 2 = OVF Overflow Flag. This 12-bit register is read by software and cleared This bit is set by hardware and cleared by software by hardware after a reset. The counter is incre- by reading the ATCSR register. It indicates the mented continuously as soon as a counter clock is transition of the counter from FFFh to ATR value. selected. To obtain the 12-bit value, software 0: No counter overflow occurred should read the counter value in two consecutive 1: Counter overflow occurred read operations. The CNTRH register can be in- cremented between the two reads, and in order to Caution: be accurate when f =f , the software TIMER CPU When set, the OVF bit stays high for 1 fCOUNTER should take this into account when CNTRL and cycle, (up to 1ms depending on the clock selec- CNTRH are read. If CNTRL is close to its highest tion). value, CNTRH could be incremented before it is read. When a counter overflow occurs, the counter re- Bit 1 = OVFIE Overflow Interrupt Enable. starts from the value specified in the ATR register. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled 1: OVF interrupt enabled Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and clear by 56/124 1

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) AUTO RELOAD REGISTER (ATRH) PWM0 DUTY CYCLE REGISTER LOW (DCR0L) Read / Write Read / Write Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h) 15 8 7 0 0 0 0 0 ATR11 ATR10 ATR9 ATR8 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 AUTO RELOAD REGISTER (ATRL) Bits 15:12 = Reserved, must be kept cleared. Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value 7 0 This 12-bit value is written by software. The high register must be written first. ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the Bits 15:12 = Reserved, must be kept cleared. PWM0 output signal (see Figure 35). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12- bit upcounter value. Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by soft- ware. The ATR register value is automatically loaded into the upcounter when an overflow oc- PWM0 CONTROL/STATUS REGISTER curs. The register value is used to set the PWM (PWM0CSR) frequency. Read / Write Reset Value: 0000 0000 (00h) PWM0 DUTY CYCLE REGISTER HIGH (DCR0H) 7 0 Read / Write Reset Value: 0000 0000 (00h) 0 0 0 0 0 0 OP0 CMPF0 15 8 Bit 7:2= Reserved, must be kept cleared. 0 0 0 0 DCR11 DCR10 DCR9 DCR8 Bit 1 = OP0 PWM0 Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 = CMPF0 PWM0 Compare Flag. This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 regis- ter value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. 57/124 1

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) PWM OUTPUT CONTROL REGISTER (PWMCR) Bits 7:1 = Reserved, must be kept cleared. Read/Write Reset Value: 0000 0000 (00h) Bit 0 = OE0 PWM0 Output enable. This bit is set and cleared by software. 7 0 0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O) 0 0 0 0 0 0 0 OE0 1: PWM0 output enabled Table 14. Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label ATCSR CK1 CK0 OVF OVFIE CMPIE 0D 0 0 0 Reset Value 0 0 0 0 0 CNTRH CN11 CN10 CN9 CN8 0E 0 0 0 0 Reset Value 0 0 0 0 CNTRL CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0 0F Reset Value 0 0 0 0 0 0 0 0 ATRH ATR11 ATR10 ATR9 ATR8 10 0 0 0 0 Reset Value 0 0 0 0 ATRL ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 11 Reset Value 0 0 0 0 0 0 0 0 PWMCR OE0 12 0 0 0 0 0 0 0 Reset Value 0 PWM0CSR OP CMPF0 13 0 0 0 0 0 0 Reset Value 0 0 DCR0H DCR11 DCR10 DCR9 DCR8 17 0 0 0 0 Reset Value 0 0 0 0 DCR0L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 18 Reset Value 0 0 0 0 0 0 0 0 58/124 1

ST7LITE0xY0, ST7LITESxY0 11.3 SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction software overhead for clearing status flags and to initiate the next transmission sequence. The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with 11.3.3 General Description external devices. An SPI system may consist of a Figure 37 shows the serial peripheral interface master and one or more slaves however the SPI (SPI) block diagram. There are 3 registers: interface can not be a master in a multi-master system. – SPI Control Register (SPICR) 11.3.2 Main Features – SPI Control/Status Register (SPICSR) ■ Full duplex synchronous transfers (on 3 lines) – SPI Data Register (SPIDR) ■ Simplex synchronous transfers (on 2 lines) The SPI is connected to external devices through 3 pins: ■ Master or slave operation ■ Six master mode frequencies (fCPU/4 max.) – MISO: Master In / Slave Out data ■ fCPU/2 max. slave mode frequency (see note) – MOSI: Master Out / Slave In data ■ SS Management by software or hardware – SCK: Serial Clock out by SPI masters and in- put by SPI slaves ■ Programmable clock polarity and phase – SS: Slave select: ■ End of transfer interrupt flag This input signal acts as a ‘chip select’ to let ■ Write collision, Master Mode Fault and Overrun the SPI master communicate with slaves indi- flags vidually and to avoid contention on the data Note: In slave mode, continuous transmission is lines. Slave SS inputs can be driven by stand- not possible at maximum frequency due to the ard I/O ports on the master MCU. Figure 37. Serial Peripheral Interface Block Diagram Data/Address Bus SPIDR Read Interrupt request Read Buffer MOSI 7 SPICSR 0 MISO 8-Bit Shift Register SPIF WCOL OVR MODF 0 SOD SSM SSI Write SOD bit 1 SS SPI 0 SCK STATE CONTROL 7 SPICR 0 SPIE SPE SPR2 MSTRCPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR SS 59/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.1 Functional Description sponds by sending data to the master device via the MISO pin. This implies full duplex communica- A basic example of interconnections between a tion with both data out and data in synchronized single master and a single slave is illustrated in with the same clock signal (which is provided by Figure 38. the master device via the SCK pin). The MOSI pins are connected together and the To use a single data line, the MISO and MOSI pins MISO pins are connected together. In this way must be connected at each node (in this case only data is transferred serially between master and simplex communication is possible). slave (most significant bit first). Four possible data/clock timing relationships may The communication is always initiated by the mas- be chosen (see Figure 41) but master and slave ter. When the master device transmits data to a must be programmed with the same timing mode. slave device via MOSI pin, the slave device re- Figure 38. Single Master/ Single Slave Application MASTER SLAVE MSBit LSBit MSBit LSBit MISO MISO 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI MOSI SPI SCK SCK CLOCK GENERATOR SS SS +5V Not used if SS is managed by software 60/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.2 Slave Select Management In Slave Mode: As an alternative to using the SS pin to control the There are two cases depending on the data/clock Slave Select signal, the application can choose to timing relationship (see Figure 39): manage the Slave Select signal by software. This If CPHA=1 (data latched on 2nd clock edge): is configured by the SSM bit in the SPICSR regis- – SS internal must be held low during the entire ter (see Figure 40) transmission. This implies that in single slave In software management, the external SS pin is applications the SS pin either can be tied to free for other application uses and the internal SS VSS, or made free for standard I/O by manag- ing the SS function by software (SSM= 1 and signal level is driven by writing to the SSI bit in the SSI=0 in the in the SPICSR register) SPICSR register. If CPHA=0 (data latched on 1st clock edge): In Master mode: – SS internal must be held low during byte – SS internal must be held high continuously transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.3.5.3). Figure 39. Generic SS Timing Diagram MOSI/MISO Byte 1 Byte 2 Byte 3 Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 40. Hardware/Software Slave Select Management SSM bit SSI bit 1 SS internal SS external pin 0 61/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.3 Master Mode Operation Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- In master mode, the serial clock is output on the ister is read. SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description 11.3.3.5 Slave Mode Operation of the SPICSR register). In slave mode, the serial clock is received on the Note: The idle state of SCK must correspond to SCK pin from the master device. the polarity selected in the SPICSR register (by To operate the SPI in slave mode: pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). 1.Write to the SPICSR register to perform the fol- lowing actions: How to operate the SPI in master mode – Select the clock polarity and clock phase by To operate the SPI in master mode, perform the configuring the CPOL and CPHA bits (see following steps in order: Figure 41). Note: The slave must have the same CPOL 1.Write to the SPICR register: and CPHA settings as the master. – Select the clock frequency by configuring the – Manage the SS pin as described in Section SPR[2:0] bits. 11.3.3.2 and Figure 39. If CPHA=1 SS must – Select the clock polarity and clock phase by be held low continuously. If CPHA=0 SS must configuring the CPOL and CPHA bits. Figure be held low during byte transmission and 41 shows the four possible configurations. pulled up between each byte to let the slave Note: The slave must have the same CPOL write in the shift register. and CPHA settings as the master. 2.Write to the SPICR register to clear the MSTR 2.Write to the SPICSR register: bit and set the SPE bit to enable the SPI I/O functions. – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for 11.3.3.6 Slave Mode Transmit Sequence the complete byte transmit sequence. When software writes to the SPIDR register, the 3.Write to the SPICR register: data byte is loaded into the 8-bit shift register and – Set the MSTR and SPE bits then shifted out serially to the MISO pin most sig- Note: MSTR and SPE bits remain set only if nificant bit first. SS is high. Important note: if the SPICSR register is not writ- The transmit sequence begins when the slave de- ten first, the SPICR register setting (MSTR bit) vice receives the clock signal and the most signifi- may be not taken into account. cant bit of the data on its MOSI pin. The transmit sequence begins when software When data transfer is complete: writes a byte in the SPIDR register. – The SPIF bit is set by hardware 11.3.3.4 Master Mode Transmit Sequence – An interrupt request is generated if SPIE bit is When software writes to the SPIDR register, the set and interrupt mask in the CCR register is data byte is loaded into the 8-bit shift register and cleared. then shifted out serially to the MOSI pin most sig- Clearing the SPIF bit is performed by the following nificant bit first. software sequence: When data transfer is complete: 1.An access to the SPICSR register while the – The SPIF bit is set by hardware SPIF bit is set. – An interrupt request is generated if the SPIE 2.A write or a read to the SPIDR register. bit is set and the interrupt mask in the CCR Notes: While the SPIF bit is set, all writes to the register is cleared. SPIDR register are inhibited until the SPICSR reg- Clearing the SPIF bit is performed by the following ister is read. software sequence: The SPIF bit can be cleared during a second 1.An access to the SPICSR register while the transmission; however, it must be cleared before SPIF bit is set the second SPIF bit in order to prevent an Overrun condition (see Section 11.3.5.2). 2.A read to the SPIDR register. 62/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4 Clock Phase and Clock Polarity Figure 41, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The di- Four possible timing relationships may be chosen agram may be interpreted as a master or slave by software, using the CPOL and CPHA bits (See timing diagram where the SCK pin, the MISO pin, Figure 41). the MOSI pin are directly connected between the Note: The idle state of SCK must correspond to master and the slave device. the polarity selected in the SPICSR register (by Note: If CPOL is changed at the communication pulling up SCK if CPOL=1 or pulling down SCK if byte boundaries, the SPI must be disabled by re- CPOL=0). setting the SPE bit. The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 41. Data Clock Timing Diagram CPHA =1 SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit (from master) MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit (from slave) SS (to slave) CAPTURE STROBE CPHA =0 SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit (from master) MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit (from slave) SS (to slave) CAPTURE STROBE Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. 63/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Error Flags not cleared the SPIF bit issued from the previously transmitted byte. 11.3.5.1 Master Mode Fault (MODF) When an Overrun occurs: Master mode fault occurs when the master device has its SS pin pulled low. – The OVR bit is set and an interrupt request is generated if the SPIE bit is set. When a Master mode fault occurs: In this case, the receiver buffer contains the byte – The MODF bit is set and an SPI interrupt re- sent after the SPIF bit was last cleared. A read to quest is generated if the SPIE bit is set. the SPIDR register returns this byte. All other – The SPE bit is reset. This blocks all output bytes are lost. from the device and disables the SPI periph- The OVR bit is cleared by reading the SPICSR eral. register. – The MSTR bit is reset, thus forcing the device 11.3.5.3 Write Collision Error (WCOL) into slave mode. Clearing the MODF bit is done through a software A write collision occurs when the software tries to write to the SPIDR register while a data transfer is sequence: taking place with an external device. When this 1.A read access to the SPICSR register while the happens, the transfer continues uninterrupted; MODF bit is set. and the software write will be unsuccessful. 2.A write to the SPICR register. Write collisions can occur both in master and slave Notes: To avoid any conflicts in an application mode. See also Section 11.3.3.2 Slave Select with multiple slaves, the SS pin must be pulled Management. high during the MODF bit clearing sequence. The Note: a "read collision" will never occur since the SPE and MSTR bits may be restored to their orig- received data byte is placed in a buffer in which inal state during or after this clearing sequence. access is always synchronous with the MCU oper- Hardware does not allow the user to set the SPE ation. and MSTR bits while the MODF bit is set except in The WCOL bit in the SPICSR register is set if a the MODF bit clearing sequence. write collision occurs. 11.3.5.2 Overrun Condition (OVR) No SPI interrupt is generated when the WCOL bit An overrun condition occurs, when the master de- is set (the WCOL bit is a status flag only). vice has sent a data byte and the slave device has Clearing the WCOL bit is done through a software sequence (see Figure 42). Figure 42. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step RESULT 2nd Step SPIF =0 Read SPIDR WCOL=0 Clearing sequence before SPIF = 1 (during a data byte transfer) Read SPICSR 1st Step Note: Writing to the SPIDR regis- RESULT ter instead of reading it does not 2nd Step Read SPIDR WCOL=0 reset the WCOL bit 64/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5.4 Single Master Systems Note: To prevent a bus conflict on the MISO line the master allows only one active slave device A typical single master system may be configured, during a transmission. using an MCU as the master and four MCUs as slaves (see Figure 43). For more security, the slave device may respond to the master with the received data byte. Then the The master device selects the individual slave de- master will receive the previous byte back from the vices by using four pins of a parallel port to control slave device if all MISO and MOSI pins are con- the four SS pins of the slave devices. nected and the slave has not written to its SPIDR The SS pins are pulled high during reset since the register. master device ports will be forced to be inputs at Other transmission security methods can use that time, thus disabling the slave devices. ports for handshake lines or data bytes with com- mand fields. Figure 43. Single Master / Multiple Slave Configuration SS SS SS SS SCK SCK SCK SCK Slave Slave Slave Slave MCU MCU MCU MCU MOSI MISO MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master rts MCU o P 5V SS 65/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.6 Low Power Modes SPI exits from Slave mode, it returns to normal state immediately. Mode Description Caution: The SPI can wake up the ST7 from Halt No effect on SPI. mode only if the Slave Select signal (external SS WAIT SPI interrupt events cause the device to exit pin or the SSI bit in the SPICSR register) is low from WAIT mode. when the ST7 enters Halt mode. So if Slave selec- SPI registers are frozen. tion is configured as external (see Section In HALT mode, the SPI is inactive. SPI oper- 11.3.3.2), make sure the master drives a low level ation resumes when the MCU is woken up by on the SS pin when the slave enters Halt mode. an interrupt with “exit from HALT mode” ca- pability. The data received is subsequently 11.3.7 Interrupts HALT read from the SPIDR register when the soft- ware is running (interrupt vector fetching). If Enable Exit Exit Event several data are received before the wake- Interrupt Event Control from from Flag up event, then an overrun error is generated. Bit Wait Halt This error can be detected after the fetch of SPI End of Trans- SPIF Yes Yes the interrupt routine that woke up the device. fer Event Master Mode Fault SPIE MODF Yes No 11.3.6.1 Using the SPI to wakeup the MCU from Event Halt mode Overrun Error OVR Yes No In slave configuration, the SPI is able to wakeup Note: The SPI interrupt events are connected to the ST7 device from HALT mode through a SPIF the same interrupt vector (see Interrupts chapter). interrupt. The data received is subsequently read They generate an interrupt if the corresponding from the SPIDR register when the software is run- Enable Control Bit is set and the interrupt mask in ning (interrupt vector fetch). If multiple data trans- the CC register is reset (RIM instruction). fers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to per- form an extra communications cycle to bring the SPI from Halt mode state to normal state. If the 66/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.8 Register Description CONTROL REGISTER (SPICR) Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit de- Read/Write termines the idle state of the serial Clock. The Reset Value: 0000 xxxx (0xh) CPOL bit affects both the master and slave 7 0 modes. 0: SCK pin has a low level idle state SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by re- setting the SPE bit. Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 2 = CPHA Clock Phase. 1: An SPI interrupt is generated whenever This bit is set and cleared by software. SPIF=1, MODF=1 or OVR=1 in the SPICSR 0: The first clock transition is the first data capture register edge. 1: The second clock transition is the first capture edge. Bit 6 = SPE Serial Peripheral Output Enable. Note: The slave must have the same CPOL and This bit is set and cleared by software. It is also CPHA settings as the master. cleared by hardware when, in master mode, SS=0 (see Section 11.3.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the Bits 1:0 = SPR[1:0] Serial Clock Frequency. SPI peripheral is not initially connected to the ex- These bits are set and cleared by software. Used ternal pins. with the SPR2 bit, they select the baud rate of the 0: I/O pins free for general purpose I/O SPI serial clock SCK output by the SPI in master 1: SPI I/O pin alternate functions enabled mode. Note: These 2 bits have no effect in slave mode. Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is Table 15. SPI Master mode SCK Frequency cleared by reset. It is used with the SPR[1:0] bits to Serial Clock SPR2 SPR1 SPR0 set the baud rate. Refer to Table 15 SPI Master mode SCK Frequency. f /4 1 0 0 CPU 0: Divider by 2 enabled f /8 0 0 0 1: Divider by 2 disabled CPU f /16 0 0 1 Note: This bit has no effect in slave mode. CPU f /32 1 1 0 CPU f /64 0 1 0 Bit 4 = MSTR Master Mode. CPU This bit is set and cleared by software. It is also fCPU/128 0 1 1 cleared by hardware when, in master mode, SS=0 (see Section 11.3.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the func- tions of the MISO and MOSI pins are reversed. 67/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Bit 3 = Reserved, must be kept cleared. Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) Bit 2 = SOD SPI Output Disable. 7 0 This bit is set and cleared by software. When set, it disables the alternate function of the SPI output SPIF WCOL OVR MODF - SOD SSM SSI (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has Bit 1 = SSM SS Management. been completed. An interrupt is generated if This bit is set and cleared by software. When set, it SPIE=1 in the SPICR register. It is cleared by a disables the alternate function of the SPI SS pin software sequence (an access to the SPICSR and uses the SSI bit value instead. See Section register followed by a write or a read to the 11.3.3.2 Slave Select Management. SPIDR register). 0: Hardware management (SS managed by exter- 0: Data transfer is in progress or the flag has been nal pin) cleared. 1: Software management (internal SS signal con- 1: Data transfer between the device and an exter- trolled by SSI bit. External SS pin free for gener- nal device has been completed. al-purpose I/O) Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- Bit 0 = SSI SS Internal Mode. ister is read. This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set. Bit 6 = WCOL Write Collision status (Read only). 0 : Slave selected This bit is set by hardware when a write to the 1 : Slave deselected SPIDR register is done during a transmit se- quence. It is cleared by a software sequence (see Figure 42). DATA I/O REGISTER (SPIDR) 0: No write collision occurred Read/Write 1: A write collision has been detected Reset Value: Undefined 7 0 Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently D7 D6 D5 D4 D3 D2 D1 D0 being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.3.5.2). An interrupt is generated if The SPIDR register is used to transmit and receive SPIE = 1 in the SPICR register. The OVR bit is data on the serial bus. In a master device, a write cleared by software reading the SPICSR register. to this register will initiate transmission/reception 0: No overrun error of another byte. 1: Overrun error detected Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads Bit 4 = MODF Mode Fault flag (Read only). the serial peripheral data I/O register, the buffer is This bit is set by hardware when the SS pin is actually being read. pulled low in master mode (see Section 11.3.5.1 Master Mode Fault (MODF)). An SPI interrupt can While the SPIF bit is set, all writes to the SPIDR be generated if SPIE=1 in the SPICR register. This register are inhibited until the SPICSR register is bit is cleared by a software sequence (An access read. to the SPICSR register while MODF=1 followed by Warning: A write to the SPIDR register places a write to the SPICR register). data directly into the shift register for transmission. 0: No master mode fault detected A read to the SPIDR register returns the value lo- 1: A fault in master mode has been detected cated in the buffer and not the content of the shift register (see Figure 37). 68/124 1

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label SPIDR MSB LSB 31 Reset Value x x x x x x x x SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 32 Reset Value 0 0 0 0 x x x x SPICSR SPIF WCOL OVR MODF SOD SSM SSI 33 Reset Value 0 0 0 0 0 0 0 0 69/124 1

ST7LITE0xY0, ST7LITESxY0 11.4 8-BIT A/D CONVERTER (ADC) 11.4.1 Introduction 11.4.3 Functional Description The on-chip Analog to Digital Converter (ADC) pe- 11.4.3.1 Analog Power Supply ripheral is a 8-bit, successive approximation con- The block diagram is shown in Figure 44. verter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input VDD and VSS are the high and low level reference channels (refer to device pin out description) that voltage pins. allow the peripheral to convert the analog voltage Conversion accuracy may therefore be impacted levels from up to 5 different sources. by voltage drops and noise in the event of heavily The result of the conversion is stored in a 8-bit loaded or badly decoupled power supply lines. Data Register. The A/D converter is controlled For more details, refer to the Electrical character- through a Control/Status Register. istics section. 11.4.2 Main Features 11.4.3.2 Input Voltage Amplifier ■ 8-bit conversion The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADAMP regis- ■ Up to 5 channels with multiplexed input ter. ■ Linear successive approximation When the amplifier is enabled, the input range is ■ Dual input range 0V to 250 mV. – 0 to V or DD For example, if V = 5V, then the ADC can con- DD – 0V to 250mV vert voltages in the range 0V to 250mV with an ■ Data register (DR) which contains the results ideal resolution of 2.4mV (equivalent to 11-bit res- olution with reference to a V to V range). ■ Conversion complete status flag SS DD ■ On/off bit (to reduce consumption) For more details, refer to the Electrical character- istics section. ■ Fixed gain operational amplifier (x8) (not available on ST7LITES5 devices) Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional start- up time is required when the amplifier is selected by the AMPSEL bit. 70/124 1

ST7LITE0xY0, ST7LITESxY0 Figure 44. ADC Block Diagram fCPU DIV4 1 fADC DIV2 0 0 1 SLOW(ADCAMP Register) 7 bit 0 EOC SPEEDADON 0 0 CH2 CH1 CH0 ADCCSR 3 AIN0 HOLDCONTROL R AIN1 ADC ANALOG x 1 or ANALOGTODIGITAL MUX x 8 CONVERTER C ADC AINx AMPSEL bit (ADCAMP Register) ADCDR D7 D6 D5 D4 D3 D2 D1 D0 71/124 1

ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.3.3 Digital A/D Conversion Result ADC Configuration The conversion is monotonic, meaning that the re- The analog input ports must be configured as in- sult never decreases if the analog input does not put, no pull-up, no interrupt. Refer to the «I/O and never increases if the analog input does not. ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as If the input voltage (V ) is greater than or equal AIN a logic input. to V (high-level voltage reference) then the DDA conversion result in the DR register is FFh (full In the CSR register: scale) without overflow indication. – Select the CH[2:0] bits to assign the analog If input voltage (V ) is lower than or equal to channel to be converted. AIN V (low-level voltage reference) then the con- SSA ADC Conversion version result in the DR register is 00h. In the CSR register: The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. – Set the ADON bit to enable the A/D converter and to start the first conversion. From this time The accuracy of the conversion is described in the on, the ADC performs a continuous conver- parametric section. sion of the selected channel. R is the maximum recommended impedance When a conversion is complete AIN for an analog input signal. If the impedance is too – The EOC bit is set by hardware. high, this will result in a loss of accuracy due to – No interrupt is generated. leakage and sampling not being completed in the alloted time. – The result is in the DR register and remains valid until the next conversion has ended. 11.4.3.4 A/D Conversion Phases A write to the ADCCSR register (with ADON set) The A/D conversion is based on two conversion aborts the current conversion, resets the EOC bit phases as shown in Figure 45: and starts a new conversion. ■ Sample capacitor loading [duration: tSAMPLE] Figure 45. ADC Conversion Timings During this phase, the V input voltage to be AIN measured is loaded into the C sample ADC capacitor. ADON ■ A/D conversion [duration: tHOLD] tCONV ADOCPCESRRATWIORNITE During this phase, the A/D conversion is t HOLD computed (8 successive approximations cycles) HOLD and the C sample capacitor is disconnected ADC CONTROL from the analog input pin to get the optimum analog to digital conversion accuracy. t ■ The total conversion time: SAMPLE EOCBITSET t t + t CONV = SAMPLE HOLD While the ADC is on, these two phases are contin- 11.4.4 Low Power Modes uously repeated. Mode Description At the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement WAIT No effect on A/D Converter load. The advantage of this behaviour is that it A/D Converter disabled. minimizes the current consumption on the analog After wakeup from Halt mode, the A/D Con- HALT pin in case of single input channel measurement. verter requires a stabilization time before ac- curate conversions can be performed. 11.4.3.5 Software Procedure Refer to the control/status register (CSR) and data Note: The A/D converter may be disabled by reset- register (DR) in Section 11.4.6 for the bit defini- ting the ADON bit. This feature allows reduced tions and to Figure 45 for the timings. power consumption when no conversion is needed and between single shot conversions. 11.4.5 Interrupts None 72/124 1

ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) DATA REGISTER (ADCDR) Read/Write Read Only Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h) 7 0 7 0 EOC SPEED ADON 0 0 CH2 CH1 CH0 D7 D6 D5 D4 D3 D2 D1 D0 Bit 7 = EOC Conversion Complete This bit is set by hardware. It is cleared by soft- Bits 7:0 = D[7:0] Analog Converted Value ware reading the result in the DR register or writing This register contains the converted analog value to the CSR register. in the range 00h to FFh. 0: Conversion is not complete Note: Reading this register reset the EOC flag. 1: Conversion can be read from the DR register Bit 6 = SPEED ADC clock selection AMPLIFIER CONTROL REGISTER (ADCAMP) This bit is set and cleared by software. It is used Read/Write together with the SLOW bit to configure the ADC Reset Value: 0000 0000 (00h) clock speed. Refer to the table in the SLOW bit de- scription. 7 0 Bit 5 = ADON A/D Converter and Amplifier On This bit is set and cleared by software. 0 0 0 0 SLOW AMP- 0 0 SEL 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on Bit 7:4 = Reserved. Forced by hardware to 0. Note: Amplifier not available on ST7LITES5 Bit 3 = SLOW Slow mode devices This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below. Bits 4:3 = Reserved. must always be cleared. f SLOW SPEED ADC Bits 2:0 = CH[2:0] Channel Selection f /2 0 0 These bits are set and cleared by software. They CPU f 0 1 select the analog input to convert. CPU f /4 1 x CPU Channel Pin1 CH2 CH1 CH0 Bit 2 = AMPSEL Amplifier Selection Bit AIN0 0 0 0 This bit is set and cleared by software. For AIN1 0 0 1 ST7LITES5 devices, this bit must be kept at its re- AIN2 0 1 0 set value (0). 0: Amplifier is not selected AIN3 0 1 1 1: Amplifier is selected AIN4 1 0 0 Note: When AMPSEL=1 it is mandatory that f Notes: ADC be less than or equal to 2 MHz. 1. The number of pins AND the channel selection varies according to the device. Refer to the device pinout. Bits 1:0 = Reserved. Forced by hardware to 0. 2. A write to the ADCCSR register (with ADON set) Note: If ADC settings are changed by writing the aborts the current conversion, resets the EOC bit ADCAMP register while the ADC is running, a and starts a new conversion. dummy conversion is needed before obtaining re- sults with the new settings. 73/124 1

ST7LITE0xY0, ST7LITESxY0 Table 17. ADC Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label ADCCSR EOC SPEED ADON CH2 CH1 CH0 34h Reset Value 0 0 0 0 0 0 0 0 ADCDR D7 D6 D5 D4 D3 D2 D1 D0 35h Reset Value 0 0 0 0 0 0 0 0 ADCAMP SLOW AMPSEL 36h 0 0 0 0 0 0 Reset Value 0 0 74/124 1

ST7LITE0xY0, ST7LITESxY0 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do The ST7 Core features 17 different addressing so, most of the addressing modes may be subdi- modes which can be classified in seven main vided in two submodes called long and short: groups: – Long addressing mode is more powerful be- Addressing Mode Example cause it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cy- Inherent nop cles. Immediate ld A,#$55 – Short addressing mode is less powerful because Direct ld A,$55 it can generally only access page zero (0000h - Indexed ld A,($55,X) 00FFh range), but the instruction size is more compact, and faster. All memory to memory in- Indirect ld A,([$55],X) structions use short addressing modes only Relative jrne loop (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, Bit operation bset byte,#5 INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 18. ST7 Addressing Mode Overview Pointer Pointer Destination/ Length Mode Syntax Address Size Source (Bytes) (Hex.) (Hex.) Inherent nop + 0 Immediate ld A,#$55 + 1 Short Direct ld A,$10 00..FF + 1 Long Direct ld A,$1000 0000..FFFF + 2 + 0 (with X register) No Offset Direct Indexed ld A,(X) 00..FF + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE + 1 Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2 Short Indirect ld A,[$10] 00..FF 00..FF byte + 2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 Relative Direct jrne loop PC-128/PC+1271) + 1 Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte + 2 Bit Direct bset $10,#7 00..FF + 1 Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 Bit Direct Relative btjt $10,#7,skip 00..FF + 2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3 Note: 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 75/124 1

ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent 12.1.3 Direct All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced The opcode fully specifies all the required informa- by their memory address. tion for the CPU to process the operation. The direct addressing mode consists of two sub- modes: Inherent Instruction Function Direct (Short) NOP No operation The address is a byte, thus requires only 1 byte af- TRAP S/W Interrupt ter the opcode, but only allows 00 - FF addressing WFI Wait For Interrupt (Low Power space. Mode) Direct (Long) Halt Oscillator (Lowest Power HALT The address is a word, thus allowing 64 Kbyte ad- Mode) dressing space, but requires 2 bytes after the op- RET Subroutine Return code. IRET Interrupt Subroutine Return 12.1.4 Indexed (No Offset, Short, Long) SIM Set Interrupt Mask In this mode, the operand is referenced by its RIM Reset Interrupt Mask memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. SCF Set Carry Flag The indirect addressing mode consists of three RCF Reset Carry Flag submodes: RSP Reset Stack Pointer Indexed (No Offset) LD Load There is no offset (no extra byte after the opcode), CLR Clear and allows 00 - FF addressing space. PUSH/POP Push/Pop to/from the stack Indexed (Short) INC/DEC Increment/Decrement The offset is a byte, thus requires only 1 byte after TNZ Test Negative or Zero the opcode and allows 00 - 1FE addressing space. CPL, NEG 1 or 2 Complement Indexed (Long) MUL Byte Multiplication The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- SLL, SRL, SRA, RLC, Shift and Rotate Operations code. RRC SWAP Swap Nibbles 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found 12.1.2 Immediate by its memory address, located in memory (point- Immediate instructions have 2 bytes, the first byte er). contains the opcode, the second byte contains the The pointer address follows the opcode. The indi- operand value. rect addressing mode consists of two submodes: Indirect (Short) Immediate Instruction Function The pointer address is a byte, the pointer size is a LD Load byte, thus allowing 00 - FF addressing space, and CP Compare requires 1 byte after the opcode. BCP Bit Compare Indirect (Long) AND, OR, XOR Logical Operations The pointer address is a byte, the pointer size is a ADC, ADD, SUB, SBC Arithmetic Operations word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 76/124 1

ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) 12.1.7 Relative Mode (Direct, Indirect) This is a combination of indirect and short indexed This addressing mode is used to modify the PC addressing modes. The operand is referenced by register value by adding an 8-bit signed offset to it. its memory address, which is defined by the un- signed addition of an index register value (X or Y) Available Relative Direct/ Function with a pointer value located in memory. The point- Indirect Instructions er address follows the opcode. JRxx Conditional Jump The indirect indexed addressing mode consists of CALLR Call Relative two submodes: Indirect Indexed (Short) The relative addressing mode consists of two sub- modes: The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, Relative (Direct) and requires 1 byte after the opcode. The offset follows the opcode. Indirect Indexed (Long) Relative (Indirect) The pointer address is a byte, the pointer size is a The offset is defined in memory, of which the ad- word, thus allowing 64 Kbyte addressing space, dress follows the opcode. and requires 1 byte after the opcode. Table 19. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Long and Short Function Instructions LD Load CP Compare AND, OR, XOR Logical Operations Arithmetic Addition/subtrac- ADC, ADD, SUB, SBC tion operations BCP Bit Compare Short Instructions Only Function CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations Bit Test and Jump Opera- BTJT, BTJF tions SLL, SRL, SRA, RLC, Shift and Rotate Operations RRC SWAP Swap Nibbles CALL, JP Call or Jump subroutine 77/124 1

ST7LITE0xY0, ST7LITESxY0 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in consisting of 63 instructions. The instructions may the following table: Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF Using a prebyte PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent The instructions are described with 1 to 4 bytes. addressing mode by a Y one. In order to extend the number of available op- PIX 92 Replace an instruction using direct, di- codes for an 8-bit CPU (256 opcodes), three differ- rect bit or direct relative addressing ent prebyte opcodes are defined. These prebytes mode to an instruction using the corre- modify the meaning of the instruction they pre- sponding indirect addressing mode. cede. It also changes an instruction using X The whole instruction becomes: indexed addressing mode to an instruc- PC-2 End of previous instruction tion using indirect X indexed addressing mode. PC-1 Prebyte PIY 91 Replace an instruction using X indirect PC Opcode indexed addressing mode by a Y one. PC+1 Additional word (0 to 2) according to the 12.2.1 Illegal Opcode Reset number of bytes required to compute the effective address In order to provide enhanced robustness to the de- vice against unexpected behavior, a system of ille- gal opcode detection is implemented. If a code to These prebytes enable instruction in Y as well as be executed does not correspond to any opcode indirect addressing modes to be implemented. or prebyte value, a reset is generated. This, com- They precede the opcode of the instruction in X or bined with the Watchdog, allows the detection and the instruction using direct addressing mode. The recovery from an unexpected fault or interference. prebytes are: Note: A valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. 78/124 1

ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned > 79/124 1

ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z 80/124 1

ST7LITE0xY0, ST7LITESxY0 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- 13.1.5 Pin input voltage ferred to V . SS The input voltage measurement on a pin of the de- 13.1.1 Minimum and Maximum values vice is described in Figure 47. Unless otherwise specified the minimum and max- Figure 47. Pin input voltage imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T =25°C A ST7PIN and T =T max (given by the selected temperature A A range). Data based on characterization results, design VIN simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 13.1.2 Typical values Unless otherwise specified, typical data are based on T =25°C, V =5V (for the 4.5V≤V ≤5.5V A DD DD voltage range), V =3.3V (for the 3V≤V ≤3.6V DD DD voltage range) and V =2.7V (for the DD 2.4V≤V ≤3V voltage range). They are given only DD as design guidelines and are not tested. 13.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 46. Figure 46. Pin loading conditions ST7PIN C L 81/124 1

ST7LITE0xY0, ST7LITESxY0 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating mum ratings” may cause permanent damage to conditions for extended periods may affect device the device. This is a stress rating only and func- reliability. tional operation of the device under these condi- 13.2.1 Voltage Characteristics Symbol Ratings Maximum value Unit V - V Supply voltage 7.0 DD SS V V Input voltage on any pin 1) & 2) V -0.3 to V +0.3 IN SS DD V Electrostatic discharge voltage (Human Body Model) see section 13.7.2 on page 93 ESD(HBM) 13.2.2 Current Characteristics Symbol Ratings Maximum value Unit I Total current into V power lines (source) 3) 75 VDD DD I Total current out of V ground lines (sink) 3) 150 VSS SS Output current sunk by any standard I/O and control pin 20 I Output current sunk by any high sink I/O pin 40 IO Output current source by any I/Os and control pin - 25 mA Injected current on RESET pin ± 5 I 2) & 4) INJ(PIN) Injected current on PB1 pin 5) +5 Injected current on any other pin 6) ± 5 ΣI 2) Total injected current (sum of all I/O and control pins) 6) ± 20 INJ(PIN) 13.2.3 Thermal Characteristics Symbol Ratings Value Unit T Storage temperature range -65 to +150 °C STG T Maximum junction temperature (see Section 14.2 THERMAL CHARACTERISTICS) J Notes: 1. Directly connecting the I/O pins to V or V could damage the device if an unexpected change of the I/O configura- DD SS tion occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V DD or V according to their reset configuration. For reset pin, please refer to Figure 80. SS 2. I must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be INJ(PIN) IN IN respected, the injection current must be limited externally to the I value. A positive injection is induced by V >V INJ(PIN) IN DD while a negative injection is induced by V <V . IN SS 3. All power (V ) and ground (V ) lines must always be connected to the external supply. DD SS 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB1 pin. 6. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the positive INJ(PIN) and negative injected currents (instantaneous values). These results are based on characterisation with ΣI maxi- INJ(PIN) mum current injection on four I/O port pins of the device. 82/124 1

ST7LITE0xY0, ST7LITESxY0 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices T = -40 to +85°C unless otherwise specified. A Symbol Parameter Conditions Min Max Unit f = 8 MHz. max., 2.4 5.5 OSC V Supply voltage V DD f = 16 MHz. max. 3.3 5.5 OSC External clock frequency on 3.3V≤ VDD≤5.5V up to 16 f MHz CLKIN CLKIN pin 2.4V≤V <3.3V up to 8 DD Figure 48. f Maximum Operating Frequency Versus V Supply Voltage CLKIN DD FUNCTIONALITY GUARANTEED fCLKIN [MHz] IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF 16 PARAMETRIC DATA) FUNCTIONALITY NOTGUARANTEED IN THIS AREA 8 4 1 0 SUPPLYVOLTAGE [V] 2.0 2.4 2.7 3.3 3.5 4.0 4.5 5.0 5.5 Note: For further information on clock management and f description, refer to Figure 14 in section 7 CLKIN on page 24 83/124 1

ST7LITE0xY0, ST7LITESxY0 13.3.2 Operating Conditions with Low Voltage Detector (LVD) T = -40 to 85°C, unless otherwise specified A Symbol Parameter Conditions Min Typ Max Unit High Threshold 4.00 1) 4.25 4.50 Reset release threshold V Med. Threshold 3.40 1) 3.60 3.80 IT+(LVD) (V rise) DD Low Threshold 2.65 1) 2.90 3.15 V High Threshold 3.80 4.05 4.30 1) Reset generation threshold V Med. Threshold 3.20 3.40 3.65 1) IT-(LVD) (V fall) DD Low Threshold 2.40 2.70 2.90 1) V LVD voltage threshold hysteresis V -V 200 mV hys IT+(LVD) IT-(LVD) Vt V rise time rate 2) 20 20000 µs/V POR DD t Filtered glitch delay on V Not detected by the LVD 150 ns g(VDD) DD I ) LVD/AVD current consumption 220 µA DD(LVD Notes: 1. Not tested in production. 2. Not tested in production. The V rise time rate condition is needed to ensure a correct device power-on and LVD reset. DD When the V slope is outside these values, the LVD may not ensure a proper reset of the MCU. DD 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds T = -40 to 85°C, unless otherwise specified A Symbol Parameter Conditions Min Typ Max Unit High Threshold 4.40 4.70 5.00 1=>0 AVDF flag toggle threshold V Med. Threshold 3.90 4.10 4.30 IT+(AVD) (V rise) DD Low Threshold 3.20 3.40 3.60 V High Threshold 4.30 4.60 4.90 0=>1 AVDF flag toggle threshold V Med. Threshold 3.70 3.90 4.10 IT-(AVD) (V fall) DD Low Threshold 2.90 3.20 3.40 V AVD voltage threshold hysteresis V -V 150 mV hys IT+(AVD) IT-(AVD) Voltage drop between AVD flag set ∆V V fall 0.45 V IT- and LVD reset activation DD 84/124 1

ST7LITE0xY0, ST7LITESxY0 13.3.4 Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Min Typ Max Unit V Internal RC Oscillator operating voltage 2.4 5.5 DD(RC) V x4 PLL operating voltage 2.4 3.3 V DD(x4PLL) V x8 PLL operating voltage 3.3 5.5 DD(x8PLL) PLL input clock (f ) t PLL Startup time 60 PLL STARTUP cycles The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables. 13.3.4.1 Devices with “6” order code suffix (tested for T = -40 to +85°C) @ V = 4.5 to 5.5V A DD Symbol Parameter Conditions Min Typ Max Unit f 1) Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD=5V 760 kHz RC quency RCCR = RCCR02 ),T =25°C, V =5V 1000 A DD Accuracy of Internal RC TA=25°C,VDD=4.5 to 5.5V -1 +1 % ACC oscillator with T =-40 to +85°C, V =5V -5 +2 % RC A DD RCCR=RCCR02) T =0 to +85°C, V =4.5 to 5.5V -23) +23) % A DD RC oscillator current con- I T =25°C,V =5V 9703) µA DD(RC) sumption A DD t RC oscillator setup time T =25°C,V =5V 102) µs su(RC) A DD f x8 PLL input clock 13) MHz PLL t PLL Lock time5) 2 ms LOCK t PLL Stabilization time5) 4 ms STAB f = 1MHz@T =25°C, V =4.5 to 5.5V 0.14) % RC A DD ACC x8 PLL Accuracy PLL f = 1MHz@T =-40 to +85°C, V =5V 0.14) % RC A DD t PLL jitter period f = 1MHz 86) kHz w(JIT) RC JIT PLL jitter (∆f /f ) 16) % PLL CPU CPU I PLL current consumption T =25°C 6003) µA DD(PLL) A Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device. DD SS 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page24 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t is required to reach ACC accuracy STAB PLL 5. After the LOCKED bit is set ACC is max. 10% until t has elapsed. See Figure 13 on page 25. PLL STAB 6. Guaranteed by design. 85/124 1

ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) 13.3.4.2 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 2.7 to 3.3V A DD Symbol Parameter Conditions Min Typ Max Unit f 1) Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.0V 560 kHz RC quency RCCR=RCCR12) ,T =25°C, V = 3V 700 A DD Accuracy of Internal RC TA=25°C,VDD=3V -2 +2 % ACC oscillator when calibrated T =25°C,V =2.7 to 3.3V -25 +25 % RC A DD with RCCR=RCCR12)3) T =-40 to +85°C, V =3V -15 15 % A DD RC oscillator current con- I T =25°C,V =3V 7003) µA DD(RC) sumption A DD t RC oscillator setup time T =25°C,V =3V 102) µs su(RC) A DD f x4 PLL input clock 0.73) MHz PLL t PLL Lock time5) 2 ms LOCK t PLL Stabilization time5) 4 ms STAB f = 1MHz@T =25°C, V =2.7 to 3.3V 0.14) % RC A DD ACC x4 PLL Accuracy PLL f = 1MHz@T =40 to +85°C, V = 3V 0.14) % RC A DD t PLL jitter period f = 1MHz 86) kHz w(JIT) RC JIT PLL jitter (∆f /f ) 16) % PLL CPU CPU I PLL current consumption T =25°C 1903) µA DD(PLL) A Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device. DD SS 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page24. 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t is required to reach ACC accuracy STAB PLL 5. After the LOCKED bit is set ACC is max. 10% until t has elapsed. See Figure 13 on page 25. PLL STAB 6. Guaranteed by design. 86/124 1

ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 49. RC Osc Freq vs V @ T =25°C Figure 51. Typical RC oscillator Accuracy vs DD A (Calibrated with RCCR1: 3V @ 25°C) temperature @ V =5V DD (Calibrated with RCCR0: 5V @ 25°C 1.00 0.95 Hz) 00..8950 21 (*) Freq (M 00..7850 C Accuracy -01 (*) ut 0.70 R -2 utp 0.65 -3 O 0.60 -4 0.55 -5 (*) 0.50 -45 0 25 85 125 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 Temperature (°C) VDD (V) (*) tested in production (FCigaulirber a5t0e.d R wCi tOh sRcC FCreRq0 :v 5sV V@DD 2 5°C) Figure 52. RC Osc Freq vs VDD and RCCR Value 1.80 1.10 1.60 MHz) 0001....78900000 -04°5° q. (MHz) 111...024000 rccr=00h Freq. ( 00..5600 2950°° ut Fre 0.80 rccr=64h put 0.40 105° utp 0.60 rccr=80h Out 0.30 130° O 0.40 rccr=C0h 0.20 0.20 rccr=FFh 0.10 0.00 0.00 2.5 3 3.5 4 4.5 5 5.5 6 2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6 Vdd (V) Vdd (V) Figure 53. PLL ∆f /f versus time CPU CPU ∆f /f CPU CPU Max t 0 Min t t w(JIT) w(JIT) 87/124 1

ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 54. PLLx4 Output vs CLKIN frequency Figure 55. PLLx8 Output vs CLKIN frequency 7.00 11.00 Hz) 6.00 Hz) M M 9.00 ency ( 5.00 3.3 ency ( 7.00 5.5 u 4.00 u eq 3 eq 5 ut Fr 3.00 2.7 ut Fr 5.00 4.5 Outp 2.00 Outp 3.00 4 1.00 1.00 1 1.5 2 2.5 3 0.85 0.9 1 1.5 2 2.5 External Input Clock Frequency (MHz) External Input Clock Frequency (MHz) Note: fOSC = fCLKIN/2*PLL4 Note: fOSC = fCLKIN/2*PLL8 88/124 1

ST7LITE0xY0, ST7LITESxY0 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption, the two current values must be the ST7 functional operating modes over tempera- added (except for HALT mode for which the clock ture range does not take into account the clock is stopped). source current consumption. To get the total de- 13.4.1 Supply Current T = -40 to +85°C unless otherwise specified A Symbol Parameter Conditions Typ Max Unit Supply current in RUN mode f =8MHz 1) 4.50 7.00 CPU Supply current in WAIT mode f =8MHz 2) 1.75 2.70 CPU mA Supply current in SLOW mode V f =250kHz 3) 0.75 1.13 5 CPU I Supply current in SLOW WAIT mode 5. f =250kHz 4) 0.65 1 DD = CPU D D -40°C≤T ≤+85°C 0.50 10 V A Supply current in HALT mode 5) -40°C≤T ≤+105°C TBD TBD µA A T = +85°C 5 100 A Notes: 1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals DD SS in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN) DD SS driven by external square wave, LVD disabled. 3. SLOW mode selected with f based on f divided by 32. All I/O pins in input mode with a static value at V or CPU OSC DD V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. SS 4. SLOW-WAIT mode selected with f based on f divided by 32. All I/O pins in input mode with a static value at CPU OSC V or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. DD SS 5. All I/O pins in output mode with a static value at V (no load), LVD disabled. Data based on characterization results, SS tested in production at V max and f max. DD CPU Figure 56. Typical I in RUN vs. f Figure 57. Typical I in SLOW vs. f DD CPU DD CPU 8MHz 5.0 0.80 250kHz 4.0 4MHz 0.70 125kHz Idd (mA)123...000 1MHz Idd (mA) 00000.....2345600000 62.5kHz 0.10 0.0 0.00 2.4 2.7 3.7 4.5 5 5.5 2.4 2.7 3.7 4.5 5 5.5 Vdd (V) Vdd (V) 89/124 1

ST7LITE0xY0, ST7LITESxY0 SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 58. Typical I in WAIT vs. f Figure 60. Typical I vs. Temperature DD CPU DD at V = 5V and f = 8MHz DD CPU 8MHz 2.0 4MHz 1.5 A) 1MHz 5.00 dd (m 1.0 44..0500 RUN I 0.5 3.50 WAIT 0.0 2.4 2.7 3.7 4.5 5 5.5 dd (mA) 223...050000 SSLLOOWW WAIT I Vdd (V) 1.50 1.00 0.50 0.00 -45 25 90 130 Figure 59. Typical I in SLOW-WAIT vs. f Temperature (°C) DD CPU 0.70 250kHz 0.60 125kHz 0.50 62.5kHz mA) 0.40 d ( 0.30 d I 0.20 0.10 0.00 2.4 2.7 3.7 4.5 5 5.5 Vdd (V) 13.4.2 On-chip peripherals Symbol Parameter Conditions Typ Unit f =4MHz V =3.0V 150 I 12-bit Auto-Reload Timer supply current 1) CPU DD DD(AT) f =8MHz V =5.0V 250 CPU DD f =4MHz V =3.0V 50 I SPI supply current 2) CPU DD µA DD(SPI) f =8MHz V =5.0V 300 CPU DD V =3.0V 780 I ADC supply current when converting 3) f =4MHz DD DD(ADC) ADC V =5.0V 1100 DD 1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM DD mode at f =8MHz. cpu 2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica- DD tion (data sent equal to 55h). 3. Data based on a differential I measurement between reset configuration and continuous A/D conversions with am- DD plifier off. 90/124 1

ST7LITE0xY0, ST7LITESxY0 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V , f , and T . DD OSC A 13.5.1 General Timings Symbol Parameter 1) Conditions Min Typ 2) Max Unit 2 3 12 t CPU t Instruction cycle time f =8MHz c(INST) CPU 250 375 1500 ns Interrupt reaction time 3) 10 22 tCPU t f =8MHz v(IT) tv(IT) = ∆tc(INST) + 10 CPU 1.25 2.75 µs 13.5.2 External Clock Source Symbol Parameter Conditions Min Typ Max Unit V CLKIN input pin high level voltage 0.7xV V CLKINH DD DD V V CLKIN input pin low level voltage V 0.3xV CLKINL SS DD t w(CLKINH) CLKIN high or low time 4) see Figure 61 15 t w(CLKINL) ns t r(CLKIN) CLKIN rise or fall time 4) 15 t f(CLKIN) I CLKIN Input leakage current V ≤V ≤V ±1 µA L SS IN DD Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. ∆t is the number of t cycles needed to fin- c(INST) CPU ish the current instruction execution. 4. Data based on design simulation and/or technology characteristics, not tested in production. Figure 61. Typical Application with an External Clock Source 90% V CLKINH 10% V CLKINL tr(CLKIN) tfCLKIN) tw(CLKINH) tw(CLKINL) f OSC EXTERNAL I CLOCKSOURCE L CLKIN ST72XXX 91/124 1

ST7LITE0xY0, ST7LITESxY0 13.6 MEMORY CHARACTERISTICS T = -40°C to 105°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter Conditions Min Typ Max Unit V Data retention mode 1) HALT mode (or RESET) 1.6 V RM 13.6.2 FLASH Program Memory Symbol Parameter Conditions Min Typ Max Unit V Operating voltage for Flash write/erase 2.4 5.5 V DD Programming time for 1~32 bytes 2) T =−40 to +105°C 5 10 ms A t prog Programming time for 1.5 kBytes T =+25°C 0.24 0.48 s A t Data retention 4) T =+55°C3) 20 years RET A N Write erase cycles T =+25°C 10K 7) cycles RW A Read / Write / Erase modes 2.6 6) mA IDD Supply current fCPU = 8MHz, VDD = 5.5V No Read/No Write Mode 100 µA Power down mode / HALT 0 0.1 µA 13.6.3 EEPROM Data Memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage for EEPROM V 2.4 5.5 V DD write/erase t Programming time for 1~32 bytes T =−40 to +105°C 5 10 ms prog A t Data retention 4) T =+55°C 3) 20 years ret A N Write erase cycles T =+25°C 300K 7) cycles RW A Notes: 1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- DD isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the T decreases. A 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. 7. Design target value pending full product characterization. 92/124 1

ST7LITE0xY0, ST7LITESxY0 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS Susceptibility tests are performed on a sample ba- tion environment and simplified MCU software. It sis during product characterization. should be noted that good EMC performance is highly dependent on the user application and the 13.7.1 Functional EMS (Electro Magnetic software in particular. Susceptibility) Therefore it is recommended that the user applies Based on a simple running application on the EMC software optimization and prequalification product (toggling two -+LEDs through I/O ports), tests in relation with the EMC level requested for the product is stressed by two electro magnetic his application. events until a failure occurs (indicated by the LEDs). Software recommendations: ■ ESD: Electro-Static Discharge (positive and The software flowchart must include the manage- negative) is applied on all pins of the device until ment of runaway conditions such as: a functional disturbance occurs. This test – Corrupted program counter conforms with the IEC 1000-4-2 standard. – Unexpected reset ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and V through – Critical Data corruption (control registers...) DD SS a 100pF capacitor, until a functional disturbance Prequalification trials: occurs. This test conforms with the IEC 1000-4- Most of the common failures (unexpected reset 4 standard. and program counter corruption) can be repro- A device reset allows normal operations to be re- duced by manually forcing a low state on the RE- sumed. The test results are given in the table be- SET pin or the Oscillator pins for 1 second. low based on the EMS levels and classes defined To complete these trials, ESD stress can be ap- in application note AN1709. plied directly on the device, over the range of 13.7.1.1 Designing hardened software to avoid specification values. When unexpected behaviour noise problems is detected, the software can be hardened to pre- EMC characterization and optimization are per- vent unrecoverable errors occurring (see applica- formed at component level with a typical applica- tion note AN1015). Level/ Symbol Parameter Conditions Class Voltage limits to be applied on any I/O pin to induce a V =5V, T =+25°C, f =8MHz V DD A OSC 2B FESD functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied V =5V, T =+25°C, f =8MHz V through 100pF on V and V pins to induce a func- DD A OSC 3B FFTB DD DD conforms to IEC 1000-4-4 tional disturbance 13.7.2 EMI (Electromagnetic interference) emission test is in line with the norm SAE J 1752/3 which specifies the board and the Based on a simple application running on the loading of each pin. product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This Table 20: EMI emissions Monitored Max vs. [fOSC/fCPU] Unit Symbol Parameter Conditions Frequency Band 1/4MHz 1/8MHz 0.1MHz to 30MHz 8 14 V =5V, T =+25°C, DD A SO16 package, 30MHz to 130MHz 27 32 dBµV S Peak level EMI conforming to SAE J 1752/3 130MHz to 1GHz 26 28 SAE EMI Level 3.5 4 - Note: 1. Data based on characterization results, not tested in production. 93/124 1

ST7LITE0xY0, ST7LITESxY0 EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical 13.7.3.1 Electro-Static Discharge (ESD) Sensitivity) Electro-Static Discharges (a positive then a nega- Based on two different tests (ESD and LU) using tive pulse separated by 1 second) are applied to specific measurement methods, the product is the pins of each sample according to each pin stressed in order to determine its performance in combination. The sample size depends on the terms of electrical sensitivity. number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22- A114A standard. ESD absolute maximum ratings Symbol Ratings Conditions Maximum value 1) Unit Electro-static discharge voltage T =+25°C V A 4000 V ESD(HBM) (Human Body Model) conforming to JESD22-A114 Notes: 1. Data based on characterization results, not tested in production. 13.7.3.2 Static Latch-Up (applied to each input, output and configurable I/ ■ LU: Two complementary static tests are O pin) are performed on each sample. These required on 10 parts to assess the latch-up test are compliant with the EIA/JESD 78 IC performance. A supply overvoltage (applied to latch-up standard. each power supply pin) and a current injection Electrical Sensitivities Symbol Parameter Conditions Class 1) T =+25°C LU Static latch-up class A II level A conforming to JESD78A Note: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 94/124 1

ST7LITE0xY0, ST7LITESxY0 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.3 Schmitt trigger voltage Vhys hysteresis 1) 400 mV I Input leakage current V ≤V ≤V ±1 L SS IN DD Static current consumption induced by µA IS each floating input pin2) Floating input mode 400 R Weak pull-up equivalent resistor3) VIN=V VDD=5V 50 120 250 kΩ PU SS VDD=3V 160 C I/O pin capacitance 5 pF IO tf(IO)out Output high to low level fall time 1) CL=50pF 25 ns t Output low to high level rise time 1) Between 10% and 90% 25 r(IO)out t External interrupt pulse time 4) 1 t w(IT)in CPU Notes: 1. Data based on characterization results, not tested in production. 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 66). Static peak current value taken at a fixed V value, IN based on design simulation and technology characteristics, not tested in production. This value depends on V and tem- DD perature values. 3. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de- PU PU scribed in Figure 63). 4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. Figure 62. Two typical applications with unused I/O pin configured as input VDD ST7XXX UNUSEDI/OPORT 10kΩ 10kΩ UNUSEDI/OPORT ST7XXX Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost. Figure 63. Typical I vs. V with V =V PU DD IN SS l 90 80 Ta=140°C Ta=95°C 70 Ta=25°C 60 Ta=-45°C A) 50 Ipu(u 40 TO BE CHARACTERIZED 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) 95/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V , f , and T unless otherwise specified. DD CPU A Symbol Parameter Conditions Min Max Unit I =+5mA T ≤85°C 1.0 IO A Output low level voltage for a standard I/O pin T ≥85°C 1.2 A when 8 pins are sunk at same time (see Figure 65) IIO=+2mA TA≤85°C 0.4 T ≥85°C 0.5 V 1) A OL I =+20mA,T ≤85°C 1.3 Owhuetpnu 4t lpoiwn sle avreel svuonltka gaet sfoarm ae h tiigmhe sink I/O pin =5V IO TAA≥85°C 1.5 (see Figure 66) DD IIO=+8mA TA≤85°C 0.75 V T ≥85°C 0.85 A IIO=-5mA, TA≤85°C VDD-1.5 Output high level voltage for an I/O pin T ≥85°C V -1.6 V 2) when 4 pins are sourced at same time A DD OH (see Figure 72) IIO=-2mA TA≤85°C VDD-0.8 T ≥85°C V -1.0 A DD Output low level voltage for a standard I/O pin I =+2mA T ≤85°C 0.5 V when 8 pins are sunk at same time IO A T ≥85°C 0.6 V 1)3) (see Figure 64) A OL Output low level voltage for a high sink I/O pin I =+8mA T ≤85°C 0.5 V IO A when 4 pins are sunk at same time 3 T ≥85°C 0.6 3. A VOH 2)3) Owhuetpnu 4t hpiignhs laervee ls vooulrtcaegde afot rs aanm Ie/O ti mpien V=DD IIO=-2mA TTAA≤≥8855°°CC VVDDDD--01..80 Output low level voltage for a standard I/O pin I =+2mA T ≤85°C 0.6 IO A when 8 pins are sunk at same time T ≥85°C 0.7 V 1)3) A OL Output low level voltage for a high sink I/O pin I =+8mA T ≤85°C 0.6 IO A when 4 pins are sunk at same time T ≥85°C 0.7 V A 7 VOH 2)3) Ow(shueetepn uF 4ti g hpuiigrnehs 6lae9rv)ee ls vooulrtcaegde afot rs aanm Ie/O ti mpien V=2.DD IIO=-2mA TTAA≤≥8855°°CC VVDDDD--01..90 Notes: 1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I IO IO (I/O ports and control pins) must not exceed I . VSS 2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IO I (I/O ports and control pins) must not exceed I . IO VDD 3. Not tested in production, based on characterization results. 96/124 1

ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 64. Typical V at V =3.3V (standard) Figure 66. Typical V at V =5V (high-sink) OL DD OL DD 0.70 2.50 0.60 2.00 VDD=3.3V00..4500 -024°55C°°CC D=5V (HS) 1.50 -024°55C°C VOL at 00..2300 9103°0C°C V) at VD 1.00 9103°0C°C Vol ( 0.50 0.10 0.00 0.00 6 7 8 9 10 15 20 25 30 35 40 0.01 1 2 3 lio (mA) lio (mA) Figure 65. Typical VOL at VDD=5V (standard) Figure 67. Typical VOL at VDD=3V (high-sink) 1.20 0.80 1.00 0.70 S) H VOL at VDD=5V 00000.....2345600000 -02914°5035C°°0°CC°CC ol (V) at VDD=3V ( 000...468000 -02914°5035C°°0CC°C 0.10 V 0.20 0.00 0.01 1 2 3 4 5 0.00 lio (mA) 6 7 8 9 10 15 lio (mA) Figure 68. Typical V -V at V =2.4V DD OH DD 1.60 1.40 4V 1.20 =2. -45°C D 1.00 D 0°C V at 0.80 25°C H 90°C VO 0.60 130°C D- D 0.40 V 0.20 0.00 -0.01 -1 -2 lio (mA) 97/124 1

ST7LITE0xY0, ST7LITESxY0 Figure 69. Typical V -V at V =2.7V Figure 71. Typical V -V at V =4V DD OH DD DD OH DD 1.20 2.50 1.00 2.00 VDD-VOH at VDD=2.7V 000...468000 -02914°5035C°°0°CC°CC VDD-VOH at VDD=4V11..0500 -02914°5035C°°0°CC°CC 0.20 0.50 0.00 0.00 -0.01 -1 -2 -0.01 -1 -2 -3 -4 -5 lio(mA) lio (mA) Figure 70. Typical VDD-VOH at VDD=3V Figure 72. Typical VDD-VOH at VDD=5V 1.60 2.00 1.80 1.40 V 1.60 DD-VOH at VDD=3V 0011....68020000 -02914°5035C°°0°CC°CC VDD-VOH at VDD=5 00111.....6802400000 TO BE CHARACTERIZED -02914°5035C°°0°CC°CC V 0.40 0.40 0.20 0.20 0.00 0.00 -0.01 -1 -2 -3 -4 -5 -0.01 -1 -2 -3 lio (mA) lio (mA) Figure 73. Typical V vs. V (standard I/Os) OL DD 0.70 0.06 0.60 0.05 A Vol (V) at lio=2mA 0000....23450000 -02914°5035C°°0CC°C ol (V) at lio=0.01m 000...000234 -02914°5035C°°0CC°C 0.10 V 0.01 0.00 0.00 2.4 2.7 3.3 5 2.4 2.7 3.3 5 VDD (V) VDD (V) 98/124 1

ST7LITE0xY0, ST7LITESxY0 Figure 74. Typical V vs. V (high-sink I/Os) OL DD 0.70 1.00 HS) at lio=8mA 000...456000 -024°55C°C HS) at lio=20mA 00000.....5678900000 -024°55C°C D ( 0.30 90°C D ( 0.40 90°C D D OL vs V 00..1200 130°C OL vs V 000...123000 130°C V V 0.00 0.00 2.4 3 5 2.4 3 5 VDD (V) VDD (V) Figure 75. Typical V -V vs. V DD OH DD 1.80 1.10 1.70 A 1.00 1.60 m mA1.50 =-2 0.90 -45°C VDD-VOH at lio=-51111....12340000 -02914°5035C°°0°CC°CC D-VOH (V) at lio 000...678000 0291°503C°°0CC°C 1.00 VD 0.50 0.90 0.40 0.80 4 5 2.4 2.7 3 4 5 VDD VDD (V) 99/124 1

ST7LITE0xY0, ST7LITESxY0 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 105°C, unless otherwise specified A Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.3 V Schmitt trigger voltage hysteresis 1) 2 V hys IIO=+5mA TA≤85°C 0.5 1.0 V Output low level voltage 2) V =5V TA≤105°C 1.2 V OL DD IIO=+2mA TA≤85°C 0.2 0.4 TA≤105°C 0.5 R Pull-up equivalent resistor 3) 1) V =5V 20 40 80 kΩ ON DD t Generated reset pulse duration Internal reset sources 30 µs w(RSTL)out t External reset pulse hold time 4) 20 µs h(RSTL)in t Filtered glitch duration 200 ns g(RSTL)in Notes: 1. Data based on characterization results, not tested in production. 2. The I current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 82 and the IO sum of I (I/O ports and control pins) must not exceed I . IO VSS 3. The R pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between ON V and V ILmax DD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below t can be ignored. h(RSTL)in 100/124 1

ST7LITE0xY0, ST7LITESxY0 CONTROL PIN CHARACTERISTICS (Cont’d) Figure 76. RESET pin protection when LVD is enabled.1)2)3)4) VDD ST72XXX Required Optional R ON (note 3) INTERNAL EXTERNAL RESET RESET Filter 0.01µF 1MΩ WATCHDOG PULSE ILLEGAL OPCODE 5) GENERATOR LVDRESET Figure 77. RESET pin protection when LVD is disabled.1) VDD ST72XXX R ON USER INTERNAL EXTERNAL RESET RESET Filter CIRCUIT 0.01µF WATCHDOG PULSE GENERATOR ILLEGAL OPCODE 5) Required Note 1: – The reset network protects the device against parasitic resets. – The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). – Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V max. level specified in section 13.9.1 on page 100. Otherwise the reset will not be taken into account IL internally. – Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en- sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I in INJ(RESET) section 13.2.2 on page 82. Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU). Note 4: Tips when using the LVD: – 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table1 on page7 and notes above) – 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin. – 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.” Note 5: See “Illegal Opcode Reset” on page78. for more details on illegal opcode reset conditions 101/124 1

ST7LITE0xY0, ST7LITESxY0 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Refer to I/O port characteristics for more details on the input/output alternate function characteristics Subject to general operating conditions for V , DD (SS, SCK, MOSI, MISO). f , and T unless otherwise specified. OSC A Symbol Parameter Conditions Min Max Unit Master f /128 = f /4 = CPU CPU fSCK = SPI clock frequency fCPU=8MHz 0.0625 2 MHz 1/tc(SCK) Slave 0 fCPU/2 = f =8MHz 4 CPU t r(SCK) SPI clock rise and fall time see I/O port pin description t f(SCK) t 1) SS setup time 4) Slave T + 50 su(SS) CPU t 1) SS hold time Slave 120 h(SS) t 1) Master 100 w(SCKH) SCK high and low time t 1) Slave 90 w(SCKL) t 1) Master 100 su(MI) Data input setup time t 1) Slave 100 su(SI) t 1) Master 100 th(MI) 1) Data input hold time Slave 100 ns h(SI) t 1) Data output access time Slave 0 120 a(SO) t 1) Data output disable time Slave 240 dis(SO) t 1) Data output valid time 120 v(SO) Slave (after enable edge) t 1) Data output hold time 0 h(SO) t 1) Data output valid time 120 v(MO) Master (after enable edge) t 1) Data output hold time 0 h(MO) Figure 78. SPI Slave Timing Diagram with CPHA=0 3) SS INPUT tsu(SS) tc(SCK) t h(SS) CPHA=0 T U CPOL=0 P N KI CPHA=0 SC CPOL=1 t w(SCKH) t t t t t a(SO) w(SCKL) v(SO) h(SO) t dis(SO) r(SCK) t f(SCK) MISO see OUTPUT seenote2 MSBOUT BIT6OUT LSBOUT note2 t t su(SI) h(SI) MOSI MSBIN BIT1IN LSBIN INPUT Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV . DD DD 4. Depends on f . For example, if f =8MHz, then T = 1/f =125ns and t =175ns CPU CPU CPU CPU su(SS) 102/124 1

ST7LITE0xY0, ST7LITESxY0 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 79. SPI Slave Timing Diagram with CPHA=11) SS INPUT tsu(SS) tc(SCK) t h(SS) CPHA=1 T U CPOL=0 P N KI CPHA=1 SC CPOL=1 t t w(SCKH) t a(SO) t t t dis(SO) w(SCKL) v(SO) h(SO) t r(SCK) t f(SCK) MISO see see OUTPUT note2 HZ MSBOUT BIT6OUT LSBOUT note2 t t su(SI) h(SI) MOSI MSBIN BIT1IN LSBIN INPUT Figure 80. SPI Master Timing Diagram 1) SS INPUT t c(SCK) CPHA=0 CPOL=0 T CPHA=0 PU CPOL=1 N I K C CPHA=1 S CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t t r(SCK) w(SCKL) t f(SCK) tsu(MI) th(MI) MISO INPUT MSBIN BIT6IN LSBIN tv(MO) th(MO) MOSI Seenote2 MSBOUT BIT6OUT LSBOUT Seenote2 OUTPUT Notes: 1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV . DD DD 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. 103/124

ST7LITE0xY0, ST7LITESxY0 13.11 8-BIT ADC CHARACTERISTICS T = -40°C to 85°C, unless otherwise specified A Symbol Parameter Conditions Min Typ Max Unit f ADC clock frequency 4 MHz ADC V Conversion voltage range V V V AIN SS DD R External input resistor 10 1) kΩ AIN C Internal sample and hold capacitor V =5V 3 pF ADC DD t Stabilization time after ADC enable 0 2) STAB µs t Conversion time (t +t ) 3 CONV SAMPLE HOLD f =8MHz, f =4MHz CPU ADC t Sample capacitor loading time 4 SAMPLE 1/f ADC t Hold conversion time 8 HOLD Notes: 1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide- A DD SS lines and are not tested. 2. Data based on characterization results, not tested in production. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first t . The first conversion after the enable is then LOAD always valid. Figure 81. Typical Application with ADC V DD V T 0.6V R 2kΩ(max) AIN AINx 8-Bit A/D VAIN Conversion C V AIN T I C 0.6V L ADC ±1µA 3pF ST7XX 104/124

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Figure 82. R max. vs f with C =0pF1) Figure 83. Recommended C /R values2) AIN ADC AIN AIN AIN 45 1000 40 Cain 10 nF 4 MHz hm) 3305 2 MHz m) 100 CCaaiinn 2 427 n nFF Max. R (KoAIN 11220505 1 MHz Max. R (KohAIN 110 5 0 0.1 0 10 30 70 0.01 0.1 1 10 CPARASITIC (pF) fAIN(KHz) Notes: 1. C represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca- PARASITIC pacitance (3pF). A high C value will downgrade conversion accuracy. To remedy this, f should be reduced. PARASITIC ADC 2. This graph shows that depending on the input signal variation (f ), C can be increased for stabilization and to allow AIN AIN the use of a larger serial resistor (R . It is valid for all f frequencies ≤ 4MHz. AIN) ADC 13.11.1 General PCB Design Guidelines To obtain best results, some general design and alog signals paths should run over the analog layout rules should be followed when designing ground plane and be as short as possible. Isolate the application PCB to shield the noise-sensitive, analog signals from digital signals that may switch analog physical interface from noise-generating while the analog inputs are being sampled by the CMOS logic signals. A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted. Properly place components and route the signal traces on the PCB to shield the analog inputs. An- 105/124

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5.0V DD T = -40°C to 85°C, unless otherwise specified A Symbol Parameter Conditions Typ Max Unit E Total unadjusted error 2) ±1 T E Offset error 2) -0.5 / +1 O E Gain Error 2) f =4MHz, f =2MHz ,V =5.0V ±1 LSB G CPU ADC DD E Differential linearity error 2) ±11) D E Integral linearity error 2) ±11) L E Total unadjusted error 2) ±2 T E Offset error 2) -0.5 / 3.5 O E Gain Error 2) f =8MHz, f =4MHz ,V =5.0V -2 / 0 LSB G CPU ADC DD E Differential linearity error 2) ±11) D E Integral linearity error 2) ±11) L Notes: 1. Data based on characterization results over the whole temperature range, monitored in production. 2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for I and ΣI in Section 13.8 does not affect the ADC INJ(PIN) INJ(PIN) accuracy. – 106/124

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Figure 84. ADC Accuracy Characteristics with Amplifier disabled Digital Result ADCDR E G (1) Example of an actual transfer curve 255 (2) The ideal transfer curve 254 VDDA–VSSA (3) End point correlation line 1LSB =----------------------------------------- 253 IDEAL 256 E =Total Unadjusted Error: maximum deviation (2) beTtween the actual and the ideal transfer curves. E E =Offset Error: deviation between the first actual T O (3) transition and the first ideal one. 7 (1) EG=Gain Error: deviation between the last ideal 6 transition and the last actual one. 5 ED=Differential Linearity Error: maximum deviation EO EL between actual steps and the ideal one. 4 E =Integral Linearity Error: maximum deviation L between any actual transition and the end point 3 E correlation line. D 2 1LSB 1 IDEAL V (LSB ) in IDEAL 0 1 2 3 4 5 6 7 253 254 255 256 V V SSA DDA Figure 85. ADC Accuracy Characteristics with Amplifier enabled Digital Result ADCDR E G (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line E =Total Unadjusted Error: maximum deviation (2) beTtween the actual and the ideal transfer curves. E E =Offset Error: deviation between the first actual T O n+7 (3) transition and the first ideal one. n+6 (1) EtraGn=sGitaioinn aEnrdro trh: ed leavsita atioctnu able otwnee.en the last ideal n+5 ED=Differential Linearity Error: maximum deviation EO EL between actual steps and the ideal one. n+4 E =Integral Linearity Error: maximum deviation L between any actual transition and the end point n+3 E correlation line. D n+2 n=Amplifier Offset 1LSB n+1 IDEAL V (LSB ) in IDEAL 0 1 2 3 4 5 6 7 100 101 102 103 V 250 mV SS Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that f be less than or equal ADC to 2 MHz. (if f =8MHz. then SPEED=0, SLOW=1). CPU 107/124

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Vout (ADC input) Vmax Noise Vmin Vin 0V 0V 250mV (OPAMP input) Symbol Parameter Conditions Min Typ Max Unit V Amplifier operating voltage 4.5 5.5 V DD(AMP) V Amplifier input voltage V =5V 0 250 mV IN DD V Amplifier offset voltage 200 mV OFFSET V Step size for monotonicity3) 5 mV STEP Linearity Output Voltage Response Linear Gain factor Amplified Analog input Gain2) 71) 8 91) Vmax Output Linearity Max Voltage V = 250mV, 2.2 2.4 V INmax Vmin Output Linearity Min Voltage VDD=5V 200 mV Notes: 1. Data based on characterization results over the whole temperature range, not tested in production. 2. For precise conversion results it is recommended to calibrate the amplifier at the following two points: – offset at V = 0V INmin – gain at full scale (for example V =250mV) IN 3. Monotonicity guaranteed if V increases or decreases in steps of min. 5mV. IN 108/124

ST7LITE0xY0, ST7LITESxY0 14 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST JESD97. The maximum ratings related to solder- offers these devices in ECOPACK® packages. ing conditions are also marked on the inner box la- These packages have a Lead-free second level in- bel. terconnect. The category of second Level Inter- ECOPACK is an ST trademark. ECOPACK speci- connect is marked on the package and on the in- fications are available at: www.st.com. ner box label, in compliance with JEDEC Standard 14.1 PACKAGE MECHANICAL DATA Figure 86. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package mm inches1) Dim. Min Typ Max Min Typ Max A 0.800.850.90 0.0315 0.0335 0.0354 A1 0.000.020.05 0.0008 0.0020 A3 0.02 0.0008 b 0.250.300.35 0.0098 0.0118 0.0138 D 5.00 0.1969 D2 3.103.253.35 0.1220 0.1280 0.1319 E 6.00 0.2362 E2 4.104.254.35 0.1614 0.1673 0.1713 e 0.80 0.0315 L 0.450.500.55 0.0177 0.0197 0.0217 ddd 0.08 0.0031 Number of Pins N 20 Note 1. Values in inches are converted from mm and rounded to 4 decimal digits. 109/124

ST7LITE0xY0, ST7LITESxY0 Figure 87. 16-Pin Plastic Dual In-Line Package, 300-mil Width mm inches1) Dim Min Typ Max Min Typ Max E A 5.33 0.2098 A1 0.38 0.0150 A2 A A2 2.92 3.30 4.95 0.1150 0.1299 0.1949 A1 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 L c b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 E1 b3 0.76 0.99 1.14 0.0299 0.0390 0.0449 b2 b eB D1 b3 e c 0.20 0.25 0.36 0.0079 0.0098 0.0142 D 18.67 19.18 19.69 0.7350 0.7551 0.7752 D D1 0.13 0.0051 e 2.54 0.1000 E 7.62 7.87 8.26 0.3000 0.3098 0.3252 E1 6.10 6.35 7.11 0.2402 0.2500 0.2799 L 2.92 3.30 3.81 0.1150 0.1299 0.1500 eB 10.92 0.4299 Number of Pins N 16 Note 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 88. 16-Pin Plastic Small Outline Package, 150-mil Width L mm inches1) Dim. 45× Min Typ Max Min Typ Max A 1.35 1.75 0.0531 0.0689 A1 A A1 0.10 0.25 0.0039 0.0098 B e α A1 C B 0.33 0.51 0.0130 0.0201 H C 0.19 0.25 0.0075 0.0098 10.0 D 9.80 0.3858 0.3937 D 0 E 3.80 4.00 0.1496 0.1575 e 1.27 0.0500 16 9 H 5.80 6.20 0.2283 0.2441 E α 0° 8° 0° 8° L 0.40 1.27 0.0157 0.0500 1 8 Number of Pins N 16 Note 1. Values in inches are converted from mm and rounded to 4 decimal digits. 110/124

ST7LITE0xY0, ST7LITESxY0 14.2 THERMAL CHARACTERISTICS Symbol Ratings Value Unit Package thermal resistance SO16 95 R °C/W thJA (junction to ambient) DIP16 TBD T Maximum junction temperature 1) 150 °C Jmax P Power dissipation 2) 500 mW Dmax Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula P = (T -T ) / R . D J A thJA The power dissipation of an application can be defined by the user with the formula: P =P +P D INT PORT where P is the chip internal power (I xV ) and P is the port power dissipation depending on the INT DD DD PORT ports used in the application. 111/124

ST7LITE0xY0, ST7LITESxY0 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- The FASTROM factory coded parts contain the grammable versions (FLASH) as well as in factory code supplied by the customer. This implies that coded versions (FASTROM). FLASH devices have to be configured by the cus- tomer using the Option Bytes while the FASTROM ST7PLITE0x and ST7PLITES2/S5 devices are devices are factory-configured. Factory Advanced Service Technique ROM (FAS- TROM) versions: they are factory-programmed XFlash devices. ST7FLITE0x and ST7FLITES2/S5 XFlash devices are shipped to customers with a default program memory content (FFh). The OSC option bit is pro- grammed to 0 by default. 15.1 OPTION BYTES The two option bytes allow the hardware configu- Bit 1 = FMP_R Read-out protection ration of the microcontroller to be selected. Readout protection, when selected provides a pro- tection against program memory content extrac- The option bytes can be accessed only in pro- tion and against write access to Flash memory. gramming mode (for example using a standard Erasing the option bytes when the FMP_R option ST7 programming tool). is selected will cause the whole memory to be erased first, and the device can be reprogrammed. OPTION BYTE 0 Refer to Section 4.5 and the ST7 Flash Program- ming Reference Manual for more details. Bits 7:4 = Reserved, must always be 1. 0: Read-out protection off 1: Read-out protection on Bits 3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- Bit 0 = FMP_W FLASH write protection cording to the following table. This option indicates if the FLASH program mem- ory is write protected. Sector 0 Size SEC1 SEC0 Warning: When this option is selected, the pro- 0.5k 0 0 gram memory (and the option bit itself) can never be erased or programmed again. 1k 0 1 0: Write protection off 1.5k 1) 1 x 1: Write protection on Note 1: Configuration available for ST7LITE0x de- vices only. 112/124

ST7LITE0xY0, ST7LITESxY0 OPTION BYTES (Cont’d) OPTION BYTE 1 Bit 7 = PLLx4x8 PLL Factor selection. Bit 4 = OSC RC Oscillator selection 0: PLLx4 0: RC oscillator on 1: PLLx8 1: RC oscillator off Note: If the RC oscillator is selected, then to im- prove clock stability and frequency accuracy, it is Bit 6 = PLLOFF PLL disabled recommended to place a decoupling capacitor, 0: PLL enabled typically 100nF, between the V and V pins as 1: PLL disabled (by-passed) DD SS close as possible to the ST7 device. Bit 5 = Reserved, must always be 1. Table 21. List of valid option combinations Operating conditions Option Bits V range Clock Source PLL Typ f OSC PLLOFF PLLx4x8 DD CPU off 0.7MHz @3V 0 1 1 Internal RC 1% x4 2.8MHz @3V 0 0 0 x8 - - - - 2.4V - 3.3V off 0-4MHz 1 1 1 External clock x4 4MHz 1 0 0 x8 - - - - off 1MHz @5V 0 1 1 Internal RC 1% x4 - - - - x8 8MHz @5V 0 0 1 3.3V - 5.5V off 0-8MHz 1 1 1 External clock x4 - - - - x8 8 MHz 1 0 1 Note: see Clock Management Block diagram in Figure 14 Bits 3:2 = LVD[1:0] Low voltage detection selec- Bit 1 = WDG SW Hardware or software watchdog tion This option bit selects the watchdog type. These option bits enable the LVD block with a se- 0: Hardware (watchdog always enabled) lected threshold as shown in Table 22. 1: Software (watchdog to be enabled by software) Table 22. LVD Threshold Configuration Bit 0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated Configuration LVD1 LVD0 when entering HALT mode while the Watchdog is LVD Off 1 1 active. Highest Voltage Threshold (∼4.1V) 1 0 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Medium Voltage Threshold (∼3.5V) 0 1 Lowest Voltage Threshold (∼2.8V) 0 0 OPTION BYTE 0 OPTION BYTE 1 7 0 7 0 FMP FMP PLL PLL WDG WDG Reserved SEC1 SEC0 OSC LVD1 LVD0 R W x4x8 OFF SW HALT Default 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 Value 113/124

ST7LITE0xY0, ST7LITESxY0 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the FASTROM con- Refer to application note AN1635 for information tents and the list of the selected options (if any). on the counter listing returned by ST after code The FASTROM contents are to be sent on dis- has been transferred. kette, or by electronic means, with the S19 hexa- The STMicroelectronics Sales Organization will be decimal file generated by the development tool. All pleased to provide detailed information on con- unused bytes must be set to FFh. The selected op- tractual points. tions are communicated to STMicroelectronics us- ing the correctly completed OPTION LIST append- ed. 114/124

ST7LITE0xY0, ST7LITESxY0 Figure 89. Ordering information scheme Example: ST7 F LITES5 Y 0 M 6 TR Family ST7 Microcontroller Family Memory type F: Flash P: FASTROM Sub-family LITES2, LITES5, LITE02, LITE05 or LITE09 No. of pins Y = 16 Memory size 0 = 1K (LITESx versions) or 1.5K (LITE0x versions) Package B = DIP M = SO U = QFN Temperature range 6 = -40 °C to 85 °C Shipping Option TR = Tape & Reel packing Blank = Tube (DIP16 or SO16) or Tray (QFN20) For a list of available options (e.g. data EEPROM, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 115/124

ST7LITE0xY0, ST7LITESxY0 ST7LITE0xY0 AND ST7LITESxY0 FASTROM MICROCONTROLLER OPTION LIST (Last update: November 2007) Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference/FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Memory size (check only one option): [ ] 1 K [ ] 1.5 K Device type (check only one option): [ ] ST7PLITES2Y0 [ ] ST7PLITES5Y0 [ ] ST7PLITE02Y0 [ ] ST7PLITE05Y0 [ ] ST7PLITE09Y0 Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and RCCR1 (see section 7.1 on page 24). Conditioning (check only one option): PDIP16 [ ] Tube SO16 [ ] Tape & Reel [ ] Tube QFN20 [ ] Tape & Reel [ ] Tray Special Marking: [ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: PDIP16 (15 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SO16 (11 char. max) : _ _ _ _ _ _ _ _ _ _ _ Sector 0 size: [ ] 0.5K [ ] 1K [ ] 1.5K Readout Protection: [ ] Disabled [ ] Enabled FLASH write Protection: [ ] Disabled [ ] Enabled Clock Source Selection: [ ] Internal RC [ ] External Clock PLL [ ] Disabled [ ] PLLx4 [ ] PLLx8 LVD Reset [ ] Disabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Watchdog Reset on Halt: [ ] Disabled [ ] Enabled Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important note: Not all configurations are available. See Table 21 on page 113 for authorized option byte combinations and “Ordering information scheme” on page115. Please download the latest version of this option list from: www.st.com 116/124

ST7LITE0xY0, ST7LITESxY0 15.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- guage debugger, editor, project manager and inte- clude a complete range of hardware systems and grated programming interface. software tools from STMicroelectronics and third- 15.3.3 Programming tools party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- During the development cycle, the ST7-DVP3 and ripherals, develop and debug your application, and ST7-EMU3 series emulators and the RLink pro- program your microcontrollers. vide in-circuit programming capability for program- ming the Flash microcontroller on your application 15.3.1 Starter kits board. ST offers complete, affordable starter kits. Starter ST also provides a low-cost dedicated in-circuit kits are complete, affordable hardware/software programmer, the ST7-STICK, as well as ST7 tool packages that include features and samples Socket Boards which provide all the sockets re- to help you quickly start developing your applica- quired for programming any of the devices in a tion. specific ST7 sub-family on a platform that can be 15.3.2 Development and debugging tools used with any tool with in-circuit programming ca- pability for ST7. Application development for ST7 is supported by fully optimizing C Compilers and the ST7 Assem- For production programming of ST7 devices, ST’s bler-Linker toolchain, which are all seamlessly in- third-party tool partners also provide a complete tegrated in the ST7 integrated development envi- range of gang and automated programming solu- ronments in order to facilitate the debugging and tions, which are ready to integrate into your pro- fine-tuning of your application. The Cosmic C duction environment. Compiler is available in a free version that outputs 15.3.4 Order Codes for Development and up to 16KBytes of code. Programming Tools The range of hardware tools includes full-featured Table 23 below lists the ordering codes for the ST7-EMU3 series emulators, cost effective ST7- ST7LITE0/ST7LITES development and program- DVP3 series emulators and the low-cost RLink ming tools. For additional ordering codes for spare in-circuit debugger/programmer. These tools are parts and accessories, refer to the online product supported by the ST7 Toolset from STMicroelec- selector at www.st.com/mcu. tronics, which includes the STVD7 integrated de- velopment environment (IDE) with high-level lan- 15.3.5 Order codes for ST7LITE0/ST7LITES development tools Table 23. Development tool order codes for the ST7LITE0/ST7LITES family MCU In-circuit Debugger, RLink Series1) Emulator Programming Tool ST7FLITE02, Starter Kit ST Socket Starter Kit with In-circuit ST7FLITE05, without Demo DVP Series EMU Series Boards and Demo Board Programmer ST7FLITE09, Board EPBs ST7FLITES2, ST7MDT10- ST7MDT10- STX-RLINK STX-RLINK2) ST7FLITE-SK/RAIS2) ST7SB10-SU04) ST7FLITES5 DVP33) EMU3 ST7-STICK4)5) Notes: 1. Available from ST or from Raisonance, www.raisonance.com 2. USB connection to PC 3. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide for connection kit ordering information 4. Add suffix /EU, /UK or /US for the power supply for your region 5. Parallel port connection to PC 117/124

ST7LITE0xY0, ST7LITESxY0 15.4 ST7 APPLICATION NOTES Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN- AN1812 PUT VOLTAGES EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD) AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 EMULATED 16-BIT SLAVE SPI AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS AN1753 SOFTWARE UART USING 12-BIT ART 118/124

ST7LITE0xY0, ST7LITESxY0 Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141 AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264 AN2200 GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB PRODUCT OPTIMIZATION AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA- AN1530 TOR AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC AN1953 PFC FOR ST7MC STARTER KIT AN1971 ST7LITE0 MICROCONTROLLED BALLAST PROGRAMMING AND TOOLS AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN1039 ST7 MATH UTILITY ROUTINES 119/124

ST7LITE0xY0, ST7LITESxY0 Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK) AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY SYSTEM OPTIMIZATION AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09 AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC 120/124

ST7LITE0xY0, ST7LITESxY0 16 KNOWN LIMITATIONS 16.1 Execution of BTJX Instruction Description tings, devices programmed with the Hardware watchdog option cannot be reprogrammed using Executing a BTJx instruction jumps to a random this tool. address in the following conditions: the jump goes to a lower address (jump backward) and the test is performed on a data located at the address 16.3 In-Circuit Debugging with Hardware 00FFh. Watchdog In Circuit Debugging is impacted in the same way 16.2 In-Circuit Programming of devices as In Circuit Programming by the activation of the previously programmed with Hardware hardware watchdog in ICC mode. Please refer to Watchdog option Section 16.2. Description 16.4 Recommendations when LVD is enabled In-Circuit Programming of devices configured with Hardware Watchdog (WDGSW bit in option byte 1 When the LVD is enabled, it is recommended not programmed to 0) requires certain precautions to connect a pull-up resistor or capacitor. A 10nF (see below). pull-down capacitor is required to filter noise on In-Circuit Programming uses ICC mode. In this the reset line. mode, the Hardware Watchdog is not automatical- ly deactivated as one might expect. As a conse- quence, internal resets are generated every 2 ms 16.5 Clearing Active Interrupts Outside by the watchdog, thus preventing programming. Interrupt Routine The device factory configuration is Software Watchdog so this issue is not seen with devices When an active interrupt request occurs at the that are programmed for the first time. For the same time as the related flag or interrupt mask is same reason, devices programmed by the user being cleared, the CC register may be corrupted. with the Software Watchdog option are not impact- Concurrent interrupt context ed. The symptom does not occur when the interrupts The only devices impacted are those that have are handled normally, i.e. when: previously been programmed with the Hardware – The interrupt request is cleared (flag reset or in- Watchdog option. terrupt mask) within its own interrupt routine Workaround – The interrupt request is cleared (flag reset or in- Devices configured with Hardware Watchdog terrupt mask) within any interrupt routine must be programmed using a specific program- – The interrupt request is cleared (flag reset or in- ming mode that ignores the option byte settings. In terrupt mask) in any part of the code while this in- this mode, an external clock, normally provided by terrupt is disabled the programming tool, has to be used. In ST tools, this mode is called "ICP OPTIONS DISABLED". If these conditions are not met, the symptom can be avoided by implementing the following se- Sockets on ST programming tools (such as quence: ST7MDT10-EPB) are controlled using "ICP OP- TIONS DISABLED" mode. Devices can therefore Perform SIM and RIM operation before and after be reprogrammed by plugging them in the ST Pro- resetting an active interrupt request gramming Board socket, whatever the watchdog Ex: configuration. SIM When using third-party tools, please refer the reset flag or interrupt mask manufacturer's documentation to check how to ac- cess specific programming modes. If a tool does RIM not have a mode that ignores the option byte set- 121/124

ST7LITE0xY0, ST7LITESxY0 17 REVISION HISTORY Table 25. Revision History Date Revision Description of changes Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys- tem change Changed all references of ADCDAT to ADCDR Added EMU3 Emulator Programming Capability in Table 23 Clarification of read-out protection Altered note 1 for section 13.2.3 on page 82 removing references to RESET Alteration of f for SLOW and SLOW-WAIT modes in Section 13.4.1 table and Figure 59 CPU on page 90 Removed sentence relating to an effective change only after overflow for CK[1:0], page 56 Added illegal opcode detection to page 1, section 8.4 on page 32, section 12 on page 75 27-Oct-04 3 Clarification of Flash read-out protection, section 4.5.1 on page 15 f value of 1MHz quoted as Typical instead of a Minimum in section 14.3.5.2 on page 92 PLL Updated F in section 13.10.1 on page 102 to F /4 and F /2 SCK CPU CPU section 8.4.4 on page 36: Changed wording in AVDIE and AVDF bit descriptions to “...when the AVDF bit is set” Socket Board development kit details added in Table24 on page115 PWM Signal diagram corrected, Figure 36 on page 55 Corrected count of reserved bits between 003Bh to 007Fh, Table2 on page11 Inserted note that RCCR0 and RCCR1 are erased if read-only flag is reset, section 7.1 on page 24 Added QFN20 package Modified section 2 on page 6 Changed Read operation paragraph in section 5.3 on page 17 Modified note below Figure 9 on page 18 and modified section 5.5 on page 19 Modified note to section 7.1 on page 24 Added note on illegal opcode reset to section 7.4.1 on page 27 Added note 2 to EICR description on page 31 Modified External Interrupt Function in section 10.2.1 on page 42 Changed text on input capture before section 11.1.4 on page 51 Modified text in section 11.1.5 on page 51 Added important note in section 11.3.3.3 on page 62 Changed note 1 in section 13.2 on page 82 Modified values in section 13.2.2 on page 82 Modified note 2 in section 13.3.4.1 on page 85 and section 13.3.4.2 on page 86 Added note on clock stability and frequency accuracy to section 13.3.4.1 on page 85, section 21-July-06 4 13.3.4.2 on page 86, section 7.1 on page 24 and to OSC option bit in Section 15.1 on page 113 Changed I value and note 2 in section 13.8.1 on page 95 S Added note in Figure 62 on page 95 Changed Figure 76 on page 101 and removed EMC protection circuitry in Figure 77 on page 101 (device works correctly without these components) Changed section 13.10.1 on page 102 (t t t ) su(SS), v(MO) and h(MO) Modified Figure 79 (CPHA=1) and Figure 80 on page 103 (t t ) v(MO) , h(MO) Added ECOPACK information to section 14 on page 109 Modified Figure 88 on page 110 (A1 and A swapped in the diagram) Modified Table21 on page112 Modified section 15.2 on page 114 Updated option list on page 116 Changed section 15.3 on page 117 Removed erratasheet section Added Section 16.4 and section 16.5 on page 121 Revision History continued overleaf ... 122/124

ST7LITE0xY0, ST7LITESxY0 Removed QFN20 pinout and mechanical data. Modified text in External Interrupt Function section in section 10.2.1 on page 42 Modified Table24 on page116 (and QFN20 rows in grey). 09-Oct-06 5 Added “External Clock Source” on page91 and Figure 61 on page 91 Modified description of CNTR[11:0] bits in section 11.2.6 on page 56 Updated option list on page 116 Changed section 15.3 on page 117 Title of the document modified Modified LOCKED bit description in section 8.4.4 on page 36 In Table1 on page7 and section 13.2.2 on page 82, note “negative injection not allowed on PB0 and PB1 pins” replaced by “negative injection not allowed on PB1 pin” Added QFN20 package pinout (with new QFN20 mechanical data): Figure 2 on page 6 and Figure 86 on page 109 Modified section 8.4.4 on page 36 19-Nov-07 6 Removed one note in section 11.1.3.1 on page 49 Modified section 13.7 on page 93 Modified “PACKAGE MECHANICAL DATA” on page109 (values in inches rounded to 4 dec- imal digits) Modified section 15.2 on page 114 (“Ordering information scheme” on page115 added and table removed) and option list on page 116 Removed “soldering information” section Modified section 15.3.5 on page 117 123/124

ST7LITE0xY0, ST7LITESxY0 Notes: Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 124/124