ST7260xx Low speed USB 8-bit MCU family with up to 8K Flash and serial communications interface Features ■ Memories – 4 or 8 Kbytes program memory: high density Flash (HDFlash), or FastROM with readout and write protection SO24 QFN40 (6x6) – In-application programming (IAP) and in- circuit programming (ICP) – 2 very high sink true open drain I/Os (25 – 384 bytes RAM memory (128-byte stack) mA at 1.5 V) ■ Clock, reset and supply management – Up to 8 lines with interrupt capability – Run, Wait, Slow and Halt CPU modes ■ 2 timers – 12 or 24 MHz oscillator – Programmable Watchdog – RAM Retention mode – 16-bit Timer with 2 Input Captures, 2 – Optional low voltage detector (LVD) Output Compares, PWM output and clock input ■ USB (Universal Serial Bus) interface – DMA for low speed applications compliant ■ Communications interface with USB 1.5 Mbs (version 2.0) and HID – Asynchronous serial communications specifications (version 1.0) interface (SCI) – Integrated 3.3 V voltage regulator and ■ Instruction set transceivers – 63 basic instructions – Supports USB DFU class specification – 17 main addressing modes – Suspend and Resume operations – 8 x 8 unsigned multiply instruction – 3 Endpoints with programmable In/Out ■ Development tools configuration – Versatile development tools including , ■ Up to 19 I/O ports software library, hardware emulator, – Up to 8 high sink I/Os (10 mA at 1.3 V) programming boards, HID and DFU software layer Table 1. Device summary Features ST7260K2 ST7260K1 ST7260E2 ST7260E1 Flash program memory - 8 K 4 K 8 K 4 K bytes RAM (stack) - bytes 384 (128) Peripherals Watchdog timer, 16-bit timer, USB, SCI Operating supply 4.0V to 5.5V CPU frequency 8MHz (with 24MHz oscillator) or 4MHz (with 12MHz oscillator) Operating temperature 0°C to +70°C Packages QFN40 (6x6) SO24 February 2009 Rev 3 1/139 www.st.com 139

Contents ST7260xx Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/139

ST7260xx Contents 7.3 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.0.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.2.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.5 Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.6 Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3/139

Contents ST7260xx 12.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.2.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.3.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.3.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.3.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4/139

ST7260xx Contents 14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 15.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113 16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5/139

Contents ST7260xx 16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118 16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118 16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119 16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 16.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 16.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 16.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 16.9.2 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.9.3 SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128 17 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17.1.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 18 Device configuration and ordering information . . . . . . . . . . . . . . . . . 131 18.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 18.2 Device ordering information and transfer of customer code . . . . . . . . . . 132 18.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 19 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6/139

ST7260xx Description 1 Description The ST7260xx devices are members of the ST7 microcontroller family designed for USB applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include a low speed USB interface and an asynchronous SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or stand-by state. Typical applications include consumer, home, office and industrial products. 7/139

Block diagram ST7260xx 2 Block diagram Figure 1. General block diagram INTERNAL CLOCK OSCIN OSC/3 OSCILLATOR OSCOUT OSC/4 or OSC/2 for USB1) PORT A VDD POWER PA[7:0] (8 bits) VSS SUPPLY 16-bitTIMER WATCHDOG PB[7:0] A PORT B RESET CONTROL DD (8 bits) R E S 8-BIT CORE S A ALU N D D A LVD TA BU PORT C S USB DMA SCI PC[2:0] VPP/TEST PROGRAM (UART) (3 bits) MEMORY VDDA (8 Kbytes) USB SIE USBDP V USBDM SSA RAM USBVCC (384 bytes) 1) 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock. 8/139

ST7260xx Pin description 3 Pin description Figure 2. 40-lead QFN package pinout A T K A L D C C C C C /IA) /IA) m m 5 5 2 2 1( 2( A C C C C C C C C A P N N N N N N N N P 40 39 38 37 36 35 34 33 32 31 PA0/MCO 1 30 PA3/EXTCLK VSSA 2 29 PA4/ICAP1/IT1 USBDP 3 28 PA5/ICAP2/IT2 USBDM 4 27 PA6/OCMP1/IT3 USBVCC 5 26 PA7/OCMP2/IT4 VDDA 6 25 PB0(10 mA) VDD 7 24 PB1(10 mA) OSCOUT 8 23 PB2(10 mA) OSCIN 9 22 PB3(10 mA) VSS 10 21 PB4(10 mA)/IT5 11 12 13 14 15 16 17 18 19 20 Note: NC=Do not connect USBOE/PC2 TDO/PC1 RDI/PC0 RESET NC NC IT8/PB7(10 mA) IT7/PB6(10 mA) V/TESTPP IT6/PB5(10 mA) Figure 3. 24-pin SO package pinout VDD 1 24 USBVcc OSCOUT 2 23 USBDM OSCIN 3 22 USBDP VSS 4 21 VSSA TDO/PC1 5 20 PA0/MCO RDI/PC0 6 19 PA1(25 mA)/ICCDATA RESET/ 7 18 PA2(25 mA)/ICCCLK IT7/PB6(10mA) 8 17 PA3/EXTCLK VPP/TEST 9 16 PA4/ICAP1/IT1 PB3(10 mA) 10 15 PA5/ICAP2/IT2 PB2(10 mA) 11 14 PA7/OCMP2/IT4 USBOE/PB1(10 mA) 12 13 PB0(10 mA) 9/139

Pin description ST7260xx RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the V is low. It can be used to reset external peripherals. DD OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. V /V (see Note 2): Main power supply and ground voltages. DD SS V /V (see Note 2): Power supply and ground voltages for analog peripherals. DDA SSA Alternate functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. 2 To enhance the reliability of operation, it is recommended that V and V be connected DDA DD together on the application board. This also applies to V and V . SSA SS 3 The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it is mapped on Port B1. 4 The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24 devices it is not available. Legend / abbreviations for Figure2, Figure3 and Table2, Table3: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3 V / 0.7 V with input trigger DD DD Output level: 10 mA = 10 mA high sink (Fn N-buffer only) 25 mA = 25 mA very high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak pull-up, int = interrupt ● Output: OD = open drain, PP = push-pull, T = True open drain The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state. 10/139

ST7260xx Pin description Table 2. D )evice pin description (QFN40) Level Port / control Main e function Pin n° Pin name p t Input Output Alternate function Ty ut pu (after Inp Out float wpu int OD PP reset) 1 PA0/MCO I/O CT X X Port A0 Main Clock Output 2 V S Analog ground SSA 3 USBDP I/O USB bidirectional data (data +) 4 USBDM I/O USB bidirectional data (data -) 5 USBVCC O USB power supply 6 V S Analog supply voltage DDA 7 V S Power supply voltage (4V - 5.5V) DD 8 OSCOUT O Oscillator output 9 OSCIN I Oscillator input 10 V S Digital ground SS 11 PC2/USBOE I/O CT X X Port C2 USB Output Enable SCI Transmit Data 12 PC1/TDO I/O CT X X Port C1 Output SCI Receive Data 13 PC0/RDI I/O CT X X Port C0 Input 14 RESET I/O X X Reset 15 NC -- Not connected 16 NC -- Not connected 17 PB7/IT8 I/O CT 10 mA X X X Port B7 18 PB6/IT7 I/O CT 10 mA X X X Port B6 19 V /TEST S Programming supply PP 20 PB5/IT6 I/O CT 10 mA X X X Port B5 21 PB4/IT5 I/O CT 10 mA X X X Port B4 22 PB3 I/O CT 10 mA X X Port B3 23 PB2 I/O CT 10 mA X X Port B2 24 PB1 I/O CT 10 mA X X Port B1 25 PB0 I/O CT 10 mA X X Port B0 Timer Output Compare 26 PA7/OCMP2/IT4 I/O CT X X X Port A7 2 Timer Output Compare 27 PA6/OCMP1/IT3 I/O CT X X X Port A6 1 28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2 29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1 11/139

Pin description ST7260xx Table 2. Device pin description (QFN40) (continued) Level Port / control Main e function Pin n° Pin name Typ ut put Input Output (after Alternate function Inp Out float wpu int OD PP reset) 30 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock 31 PA2/ICCCLK I/O C 25 mA X T Port A2 ICC Clock T 32 NC -- Do not connect 33 NC -- Do not connect 34 NC -- Do not connect 35 NC -- Do not connect 36 NC -- Do not connect 37 NC -- Do not connect 38 NC -- Do not connect 39 NC -- Do not connect 40 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data 12/139

ST7260xx Pin description Table 3. D evice pin description (SO24) Level Port / control Main e function Pin n° Pin name p t Input Output Alternate function Ty ut pu (after Inp Out float wpu int OD PP reset) Power supply voltage 1 V S DD (4 V - 5.5 V) 2 OSCOUT O Oscillator output 3 OSCIN I Oscillator input 4 V S Digital ground SS SCI Transmit Data 5 PC1/TDO I/O CT X X Port C1 Output SCI Receive Data 6 PC0/RDI I/O CT X X Port C0 Input 7 RESET I/O X X Reset 8 PB6/IT7 I/O CT 10 mA X X X Port B6 9 V /TEST S Programming supply PP 10 PB3 I/O CT 10 mA X X Port B3 11 PB2 I/O CT 10 mA X X Port B2 12 PB1/USBOE I/O CT 10 mA X X Port B1 USB Output Enable 13 PB0 I/O CT 10 mA X X Port B0 Timer Output 14 PA7/OCMP2/IT4 I/O CT X X X Port A7 Compare 2 Timer Input Capture 15 PA5/ICAP2/IT2 I/O CT X X X Port A5 2 Timer Input Capture 16 PA4/ICAP1/IT1 I/O CT X X X Port A4 1 17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock 18 PA2/ICCCLK I/O C 25 mA X T Port A2 ICC Clock T 19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data 20 PA0/MCO I/O CT X X Port A0 Main Clock Output 21 V S Analog ground SSA 22 USBDP I/O USB bidirectional data (data +) 23 USBDM I/O USB bidirectional data (data -) 24 USBVCC O USB power supply 13/139

Register & memory map ST7260xx 4 Register & memory map As shown in Figure4, the MCU is capable of addressing 8Kbytes of memories and I/O registers. The available memory locations consist of up to 384 bytes of RAM including 64 bytes of register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Note: Important: memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 4. Memory map 0040h 0000h Short addressing HW registers RAM (192 bytes) (See Table5) 00FFh 003Fh 0100h 0040h Stack RAM (128 Bytes) (384 Bytes) 017Fh 0180h 01BFh 16-bit addressing 01C0h RAM Reserved 01BFh 7FFFh 8000h Program memory (4 / 8 KBytes) FFDFh FFE0h Interrupt & reset vectors (See Table4) E000h FFFFh 8 KBytes F000h 4 KBytes FFDFh 14/139

ST7260xx Register & memory map Table 4. I n . terrupt vector map Exit from Halt Vector address Description Masked by Remarks mode FFE0h-FFEDh Reserved area FFEEh-FFEFh USB interrupt vector I- bit Internal interrupt No FFF0h-FFF1h SCI interrupt vector I- bit Internal interrupt No FFF2h-FFF3h Reserved area FFF4h-FFF5h TIMER interrupt vector I- bit Internal interrupt No FFF6h-FFF7h IT1 to IT8 interrupt vector I- bit External interrupt Yes FFF8h-FFF9h USB end suspend mode interrupt vector I- bit External interrupts Yes FFFAh-FFFBh Flash start programming interrupt vector I- bit Internal interrupt Yes FFFCh-FFFDh TRAP (software) interrupt vector None CPU interrupt No FFFEh-FFFFh RESET vector None Yes Table 5. H ardware register memory map Reset Address Block Register label Register name Remarks status 0000h PADR Port A Data Register 00h R/W Port A 0001h PADDR Port A Data Direction Register 00h R/W 0002h PBDR Port B Data Register 00h R/W Port B 0003h PBDDR Port B Data Direction Register 00h R/W 0004h PCDR Port C Data Register 1111 x000b R/W Port C 0005h PCDDR Port C Data Direction Register 1111 x000b R/W 0006h to Reserved (2 bytes) 0007h 0008h ITC ITIFRE Interrupt Register 00h R/W 0009h MISC MISCR Miscellaneous Register 00h R/W 000Ah to Reserved (2 bytes) 000Bh 000Ch WDG WDGCR Watchdog Control Register 7Fh R/W 000Dh to Reserved (4 bytes) 0010h 15/139

Register & memory map ST7260xx Table 5. Hardware register memory map (continued) Reset Address Block Register label Register name Remarks status 0011h TCR2 Timer Control Register 2 00h R/W 0012h TCR1 Timer Control Register 1 00h R/W 0013h TCSR Timer Control/Status Register 00h R/W 0014h TIC1HR Timer Input Capture High Register 1 xxh Read only 0015h TIC1LR Timer Input Capture Low Register 1 xxh Read only 0016h TOC1HR Timer Output Compare High Register 1 80h R/W 0017h TOC1LR Timer Output Compare Low Register 1 00h R/W 0018h TIM TCHR Timer Counter High Register FFh Read only 0019h TCLR Timer Counter Low Register FCh R/W 001Ah TACHR Timer Alternate Counter High Register FFh Read only 001Bh TACLR Timer Alternate Counter Low Register FCh R/W 001Ch TIC2HR Timer Input Capture High Register 2 xxh Read only 001Dh TIC2LR Timer Input Capture Low Register 2 xxh Read only 001Eh TOC2HR Timer Output Compare High Register 2 80h R/W 001Fh TOC2LR Timer Output Compare Low Register 2 00h R/W 0020h SCISR SCI Status Register C0h Read only 0021h SCIDR SCI Data Register xxh R/W 0022h SCI SCIBRR SCI Baud Rate Register 00h R/W 0023h SCICR1 SCI Control Register 1 x000 0000b R/W 0024h SCICR2 SCI Control Register 2 00h R/W 0025h USBPIDR USB PID Register x0h Read only 0026h USBDMAR USB DMA address Register xxh R/W 0027h USBIDR USB Interrupt/DMA Register x0h R/W 0028h USBISTR USB Interrupt Status Register 00h R/W 0029h USBIMR USB Interrupt Mask Register 00h R/W 002Ah USBCTLR USB Control Register 06h R/W 002Bh USB USBDADDR USB Device Address Register 00h R/W 002Ch USBEP0RA USB Endpoint 0 Register A 0000 xxxxb R/W 002Dh USBEP0RB USB Endpoint 0 Register B 80h R/W 002Eh USBEP1RA USB Endpoint 1 Register A 0000 xxxxb R/W 002Fh USBEP1RB USB Endpoint 1 Register B 0000 xxxxb R/W 0030h USBEP2RA USB Endpoint 2 Register A 0000 xxxxb R/W 0031h USBEP2RB USB Endpoint 2 Register B 0000 xxxxb R/W 0032h Reserved (5 Bytes) 0036h 0037h Flash FCSR Flash Control /Status Register 00h R/W 0038h to Reserved (8 bytes) 003Fh 16/139

ST7260xx Flash program memory 5 Flash program memory 5.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external V supply. PP The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 5.2 Main features ● 3 Flash programming modes: – Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. – ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. – IAP (in-application programming). In this mode, all sectors, except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ● ICT (in-circuit testing) for downloading and executing user application test patterns in RAM ● Readout protection ● Register Access Security System (RASS) to prevent accidental programming or erasing 5.3 Structure The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTable6). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). T able 6. Sectors available in Flash devices Flash size (bytes) Available sectors 4K Sector 0 8K Sectors 0, 1 >8K Sectors 0, 1, 2 17/139

Flash program memory ST7260xx 5.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Readout protection is enabled and removed through the FMP_R bit in the option byte. Figure 5. Memory map and sector address 8K 16K 32K Flash memorysize 7FFFh Sector2 BFFFh 8Kbytes 24Kbytes DFFFh 4Kbytes Sector1 EFFFh 4Kbytes Sector0 FFFFh 18/139

ST7260xx Flash program memory 5.4 ICC interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure6). These pins are: – RESET: device reset – V : device power supply ground SS – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V : programming voltage PP – OSC1 (or OSCIN): main clock input for external source (optional) – V : application board power supply (see Figure6, Note 3). DD Figure 6. Typical ICC interface Programming tool ICC connector Optional ICC cable (see note 4) Application board (See note 3) ICC connector HE10connectortype 9 7 5 3 1 10 8 6 4 2 Application reset source See note 2 10kΩ Application power supply See note 1 Application VDD OSC2 OSC1 ST7 VSS EL/VPP ESET CCLK DATA I/O S R C C C I C C I I 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. 4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi- oscillator capability need to have OSC2 grounded in this case. 19/139

Flash program memory ST7260xx 5.5 ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure6). For more details on the pin locations, refer to the device pinout description. 5.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SCI, or USB interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 5.7 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 5.7.1 Flash control/status register (FCSR) This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations. FCSR Reset value:0000 0000 (00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W T able 7. Flash control/status register address and reset value Address (Hex) Register label 7 6 5 4 3 2 1 0 0037h FCSR reset value 0 0 0 0 0 0 0 0 20/139

ST7260xx Central processing unit (CPU) 6 Central processing unit (CPU) 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ● Two 8-bit index registers ● 16-bit stack pointer ● Low power modes ● Maskable hardware interrupts ● Non-maskable software interrupt 6.3 CPU registers The six CPU registers shown in Figure7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU registers 7 0 Accumulator Reset value = XXh 7 0 X index register Reset value = XXh 7 0 Y index register Reset value = XXh 15 PCH 8 7 PCL 0 Program counter Reset value = reset vector @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C Condition code register Reset value =1 1 1 X 1 X X X 15 8 7 0 Stack pointer Reset value = stack higher address X = undefined value 21/139

Central processing unit (CPU) ST7260xx 6.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). 6.3.3 Program counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 6.3.4 Condition code register (CC) The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. CC Reset value: 111x1xxx 7 6 5 4 3 2 1 0 1 1 1 H I N Z C R/W R/W R/W R/W R/W T able 8. CC register description BIt Name Function Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 4 H 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. 22/139

ST7260xx Central processing unit (CPU) Table 8. CC register description BIt Name Function Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM 3 I and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 2 N 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1. This bit is accessed by the JRMI and JRPL instructions. Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 1 Z 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0 C 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions. 23/139

Central processing unit (CPU) ST7260xx 6.3.5 Stack pointer register (SP) SP Reset value: 01 7Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure8). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure8. ● When an interrupt is received, the SP is decremented and the context is pushed on the stack. ● On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 8. Stack manipulation example Call Interrupt Push Y Pop Y IRET RET subroutine event or RSP @ 0100h SP SP SP Y CC CC CC A A A X X X PCH PCH PCH SP SP PCL PCL PCL PCH PCH PCH PCH PCH SP @ 01FFh PCL PCL PCL PCL PCL Stack Higher Address = 017Fh Stack Lower Address = 0100h 24/139

ST7260xx Reset and clock management 7 Reset and clock management 7.1 Reset The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active. Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior 7.2 Low voltage detector (LVD) Low voltage reset circuitry generates a reset when V is: DD ● below V when V is rising, IT+ DD ● below V when V is falling. IT- DD During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. It is recommended to make sure that the V supply voltage rises monotonously when the DD device is exiting from Reset, to ensure the application functions properly. 7.2.1 Watchdog reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure9). 7.2.2 External reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure12, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity. 25/139

Reset and clock management ST7260xx Figure 9. Low voltage detector functional diagram RESET LOW VOLTAGE V DD DETECTOR INTERNAL RESET FROM WATCHDOG RESET Figure 10. Low voltage reset signal output V IT+ V IT- V DD RESET Note: Hysteresis (V -V ) = V IT+ IT- hys Figure 11. Temporization timing diagram after an internal reset V IT+ V DD Temporization (4096 CPU clock cycles) $FFFE Addresses 26/139

ST7260xx Reset and clock management Figure 12. Reset timing diagram t DDR V DD OSCIN t OXOV f CPU PC FFFE FFFF RESET 4096 CPU CLOCK CYCLES DELAY WATCHDOG RESET Note: Refer to Electrical Characteristics for values of t , t , V , V and V DDR OXOV IT+ IT- hys 7.3 Clock system 7.3.1 General description The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f ) is derived from the external oscillator CPU frequency (f ), which is divided by 3 (and by 2 or 4 for USB, depending on the external OSC clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure15). The internal clock signal (f ) is also routed to the on-chip peripherals. The CPU clock CPU signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for f . The circuit shown in Figure14 is osc recommended when using a crystal, and Table9 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. 27/139

Reset and clock management ST7260xx T able 9. Recommended values for 24 MHz crystal resonator Symbol Values R (1) 20 Ω 25 Ω 70 Ω SMAX C 56pF 47pF 22pF OSCIN C 56pF 47pF 22pF OSCOUT RP 1-10 MΩ 1-10 MΩ 1-10 MΩ 1. R is the equivalent serial resistor of the crystal (see crystal specification). SMAX 7.3.2 External clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure13. The t specifications do not apply when using an external clock OXOV input. The equivalent specification of the external clock source should be used instead of t (see Section16.5: Clock and timing characteristics). OXOV Figure 13. External clock source connections OSCIN OSCOUT NC EXTERNAL CLOCK Figure 14. Crystal/ceramic resonator OSCIN OSCOUT R P C C OSCIN OSCOUT 28/139

ST7260xx Reset and clock management Figure 15. Clock block diagram 8, 4 or 2 MHz 0 CPU and peripherals) %3 %2 1 SMS 1 6 MHz (USB) %%22 24 or 12 MHz %2 0 Crystal OSC24/12 29/139

Interrupts ST7260xx 8 Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table10: Interrupt mapping and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure16. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: ● Normal processing is suspended at the end of the current instruction execution. ● The PC, X, A and CC registers are saved onto the stack. ● The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table10: Interrupt mapping for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table10: Interrupt mapping). Non-maskable software interrupts This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure16. Interrupts and low power mode All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table10: Interrupt mapping). External interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset. 30/139

ST7260xx Interrupts Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ● The I bit of the CC register is cleared. ● The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by one of the two following operations: ● Writing “0” to the corresponding bit in the status register. ● Accessing the status register while the flag is set followed by a read or write of an associated register. Note: 1 The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2 All interrupts allow the processor to leave the Wait low power mode. 3 Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset. Figure 16. Interrupt processing flowchart FROMRESET N BITISET Y N INTERRUPT FETCHNEXTINSTRUCTION Y N IRET STACKPC,X,A,CC Y SETIBIT LOADPCFROMINTERRUPTVECTOR EXECUTEINSTRUCTION RESTOREPC,X,A,CCFROMSTACK THISCLEARSIBITBYDEFAULT 31/139

Interrupts ST7260xx Table 10. I n terrupt mapping Exit Source Register Priority Vector N° Description from block label order address Halt RESET Reset Highest yes FFFEh-FFFFh N/A Priority TRAP Software Interrupt no FFFCh-FFFDh FLASH Flash Start Programming Interrupt yes FFFAh-FFFBh USB End Suspend Mode ISTR FFF8h-FFF9h yes 1 ITi External Interrupts ITRFRE FFF6h-FFF7h 2 TIMER Timer Peripheral Interrupts TIMSR FFF4h-FFF5h 3 Reserved FFF2h-FFF3h Lowest no 4 SCI SCI Peripheral Interrupts SCISR FFF0h-FFF1h Priority 5 USB USB Peripheral Interrupts ISTR FFEEh-FFEFh 8.0.1 Interrupt register (ITRFRE) ITRFRE Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E R/W R/W R/W R/W R/W R/W R/W R/W T able 11. ITRFRE register description Bit Name Function Interrupt enable control bits If an ITiE bit is set, the corresponding interrupt is generated when: ITiE – a rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6 7:0 (i=1 to or 8) – a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere.. T able 12. Interrupt register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 ITRFRE IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E 0008h reset value 0 0 0 0 0 0 0 0 32/139

ST7260xx Power saving modes 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET, the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f ). CPU From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. 9.2 Halt mode The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering Halt mode, the I bit in the Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. 33/139

Power saving modes ST7260xx Figure 17. Halt mode flowchart HALT INSTRUCTION OSCILLATOR OFF PERIPH. CLOCK OFF CPU CLOCK OFF I-BIT CLEARED N RESET N EXTERNAL Y INTERRUPT* Y OSCILLATOR ON PERIPH. CLOCK ON CPU CLOCK ON I-BIT SET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 9.3 Slow mode In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. 9.4 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. 34/139

ST7260xx Power saving modes The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure18. Related documentation ● AN 980: ST7 keypad decoding techniques, implementing wake-up on keystroke ● AN1014: How to minimize the ST7 power consumption ● AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode Figure 18. Wait mode flowchart WFI INSTRUCTION OSCILLATOR ON PERIPH. CLOCK ON CPU CLOCK OFF I-BIT CLEARED N RESET N Y INTERRUPT Y OSCILLATOR ON PERIPH. CLOCK ON CPU CLOCK ON I-BIT SET IF RESET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 35/139

I/O ports ST7260xx 10 I/O ports 10.1 Introduction The I/O ports offer different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins ● Alternate signal input/output for the on-chip peripherals ● External interrupt generation An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 10.2 Functional description Each port is associated to 2 main registers: ● Data register (DR) ● Data direction register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. T able 13. I/O pin functions DDR Mode 0 Input 1 Output Input modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note: 1 All the inputs are triggered by a Schmitt trigger. 2 When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked. Output mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table13). 36/139

ST7260xx I/O ports In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read. Note: The interrupt function is disabled in this mode. Alternate function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register. Note: 1 Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2 When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Caution: The alternate function must not be activated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. 10.2.1 Port A T a ble 14. Port A0, A3, A4, A5, A6, A7 description I/O Alternate function Port A Input(1) Output Signal Condition MCO (Main Clock PA0 with pull-up push-pull MCO = 1 (MISCR) Output) CC1 =1 PA3 with pull-up push-pull Timer EXTCLK CC0 = 1 (Timer CR2) Timer ICAP1 PA4 with pull-up IT1 Schmitt triggered push-pull IT1E = 1 (ITIFRE) input Timer ICAP2 PA5 with pull-up IT2 Schmitt triggered push-pull IT2E = 1 (ITIFRE) input Timer OCMP1 OC1E = 1 PA6(2) with pull-up IT3 Schmitt triggered push-pull IT3E = 1 (ITIFRE) input Timer OCMP2 OC2E = 1 PA7 with pull-up IT4 Schmitt triggered push-pull IT4E = 1 (ITIFRE) input 1. Reset state 2. Not available on SO24 37/139

I/O ports ST7260xx Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 configuration ALTERNATE ENABLE ALTERNATE 1 VDD OUTPUT 0 P-BUFFER DR VDD PULL-UP D LATCH A T ALTERNATE ENABLE A BU DDR S LATCH PAD DDR SEL N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS ALTERNATE INPUT 0 CMOS SCHMITT TRIGGER T able 15. PA1, PA2 description I/O Alternate function Port A Input(1) Output Signal Condition Very High Current PA1 without pull-up open drain Very High Current PA2 without pull-up open drain 1. Reset state 38/139

ST7260xx I/O ports Figure 20. PA1, PA2 configuration ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH DDR LATCH D PAD A T A B U S DDR SEL N-BUFFER DR SEL 1 ALTERNATE ENABLE 0 VSS CMOS SCHMITT TRIGGER 10.2.2 Port B T a ble 16. Port B description I/O Alternate function Port B Input(1) Output Signal Condition PB0 without pull-up push-pull PB1 without pull-up push-pull USBOE USBOE =1 (USB output enable)(2) (MISCR) PB2 without pull-up push-pull PB3 without pull-up push-pull PB4 without pull-up push-pull IT5 Schmitt triggered IT4E = 1 (ITIFRE) input PB5 without pull-up push-pull IT6 Schmitt triggered IT5E = 1 (ITIFRE) input PB6 without pull-up push-pull IT7 Schmitt triggered IT6E = 1 (ITIFRE) input 39/139

I/O ports ST7260xx Table 16. Port B description (continued) I/O Alternate function Port B Input(1) Output Signal Condition PB7 without pull-up push-pull IT8 Schmitt triggered IT7E = 1 (ITIFRE) input 1. Reset state 2. On SO24 only Figure 21. Port B configuration ALTERNATE ENABLE ALTERNATE 1 VDD OUTPUT 0 VDD DR P-BUFFER LATCH ALTERNATE ENABLE DDR PAD LATCH D A T A B U DDR SEL S DIODES N-BUFFER 1 DR SEL ALTERNATE ENABLE DIGITAL ENABLE 0 VSS ALTERNATE INPUT 10.2.3 Port C T a ble 17. Port C description I/O Alternate function Port C Input(1) Output Signal Condition PC0 with pull-up push-pull RDI (SCI input) PC1 with pull-up push-pull TDO (SCI output) SCI enable USBOE USBOE =1 PC2(2) with pull-up push-pull (USB output enable) (MISCR) 1. Reset state 2. Not available on SO24 40/139

ST7260xx I/O ports Figure 22. Port C configuration ALTERNATE ENABLE ALTERNATE1 VDD OUTPUT 0 P-BUFFER DR VDD PULL-UP LATCH ALTERNATE ENABLE D AT DDR A B LATCH PAD U S DDR SEL N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE 0 VSS ALTERNATE INPUT CMOS SCHMITT TRIGGER 10.2.4 Register description 10.2.5 Data register (PxDR) PADR Reset value: 0000 0000 (00h) PBDR Reset value: 0000 0000 (00h) PCDR Reset value: 1111 x000 (Fxh) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W T able 18. PxDR register description Bit Name Function Data bits The DR register has a specific behavior according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch 7:0 D[7:0] content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). – When using open-drain I/Os in output configuration, the value read in DR is the digital value applied to the I/O pin. – For Port C, unused bits (7-3) are not accessible 41/139

I/O ports ST7260xx 10.2.6 Data direction register (PxDDR) PADDR Reset value: 0000 0000 (00h) PBDDR Reset value: 0000 0000 (00h) PCDDR Reset value: 1111 x000 (Fxh) 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 R/W R/W R/W R/W R/W R/W R/W R/W T able 19. PxDDR register description Bit Name Function Data Direction bits The DDR register gives the input/output direction configuration of the pins. Each bit is DD set and cleared by software. 7:0 [7:0] 0: Input mode 1: Output mode For Port C, unused bits (7-3) are not accessible T able 20. I/O port register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 PADR D7 D6 D5 D4 D3 D2 D1 D0 0000h reset value 0 0 0 0 0 0 0 0 PADDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0001h reset value 0 0 0 0 0 0 0 0 PBDR D7 D6 D5 D4 D3 D2 D1 D0 0002h reset value 0 0 0 0 0 0 0 0 PBDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0003h reset value 0 0 0 0 0 0 0 0 PCDR D7 D6 D5 D4 D3 D2 D1 D0 0004h reset value 0 0 0 0 0 0 0 0 PCDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0005h reset value 0 0 0 0 0 0 0 0 0006h Reserved 0007h Reserved 10.2.7 Related documentation ● AN 970: SPI Communication between ST7 and EEPROM ● AN1048: Software LCD driver 42/139

ST7260xx Miscellaneous register 11 Miscellaneous register MISCR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 - - - - - SMS USBOE MCO R/W R/W R/W T able 21. MISCR register description Bit Name Function 7:3 Reserved Slow mode select This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure15 on page29). 2 SMS The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved USB enable USB 1 If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at OE “1” when the ST7 USB is transmitting data). Unused bits 7-4 are set. Main clock out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared 0 MCO by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (f on I/O port) CPU T able 22. Miscellaneous register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 USB 0009h MISCR SMS OE MCO reset value 0 0 0 43/139

Watchdog timer (WDG) ST7260xx 12 Watchdog timer (WDG) 12.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 12.2 Main features ● Programmable free-running counter (64 increments of 49,152 CPU cycles) ● Programmable reset ● Reset (if watchdog activated) when the T6 bit reaches zero ● Optional reset on HALT instruction (configurable by option byte) ● Hardware Watchdog selectable by option byte. 12.3 Functional description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for a period of t (see Table62: Control timings on page114). DOG The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table23: Watchdog timing (f = 8 MHz) on page45): CPU ● The WDGA bit is set (watchdog enabled) ● The T6 bit is set to prevent generating an immediate reset ● The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. 44/139

ST7260xx Watchdog timer (WDG) Figure 23. Watchdog block diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0 7-BIT DOWNCOUNTER CLOCK DIVIDER f CPU ÷49152 T a ble 23. Watchdog timing (f = 8 MHz) CPU CR register initial value WDG timeout period (ms) Max FFh 393.216 Min C0h 6.144 Note: 1 Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. 2 The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 12.3.1 Software watchdog option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 12.3.2 Hardware watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 45/139

Watchdog timer (WDG) ST7260xx 12.3.3 Low power modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 12.3.4 Using Halt mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. ● For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. ● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant with the value 0x8E. ● As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 12.3.5 Interrupts None. 46/139

ST7260xx Watchdog timer (WDG) 12.3.6 Control register (WDGCR) WDGCR Reset value: 0111 1111 (7Fh) 7 6 5 4 3 2 1 0 WDGA T[6:0] R/W R/W T able 24. WDGCR register description Bit Name Function Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. 7 WDGA 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 7-bit counter (MSB to LSB) 6:0 T[6:0] These bits contain the value of the Watchdog counter. A reset is produced when it rolls over from 40h to 3Fh (T6 is cleared). T able 25. Watchdog timer register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 WDGCR WDGA T6 T5 T4 T3 T2 T1 T0 000Ch reset value 0 1 1 1 1 1 1 1 47/139

Watchdog timer (WDG) ST7260xx 12.4 16-bit timer 12.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 12.4.2 Main features ● Programmable prescaler: f divided by 2, 4 or 8 CPU ● Overflow status flag and maskable interrupt ● External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge ● 1 or 2 output compare functions each with: – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt ● 1 or 2 input capture functions each with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ● Pulse width modulation mode (PWM) ● One pulse mode ● Reduced power mode ● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a) The timer block diagram is shown in Figure24. a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section3: Pin description. When reading an input signal on a non-bonded pin, the value will always be ‘1’. 48/139

ST7260xx Watchdog timer (WDG) 12.4.3 Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. ● Counter Register (CR) – Counter High Register (CHR) is the most significant byte (MSB) – Counter Low Register (CLR) is the least significant byte (LSB) ● Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MSB) – Alternate Counter Low Register (ACLR) is the least significant byte (LSB) These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table32. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f /2, f /4, CPU CPU f /8 or an external frequency. CPU 49/139

Watchdog timer (WDG) ST7260xx Figure 24. Timer block diagram ST7 internal bus fCPU MCU-peripheral interface 8 high 8 low 8-bit 8 8 8 8 8 8 8 8 buffer EXEDG high low high low high low high low 16 1/2 Output Output Input Input Counter 1/4 register Compare Compare Capture Capture 1/8 register register register register 1 2 1 2 EXTCLK Alternate pin Counter register 16 16 16 CC[1:0] Timer internal bus 16 16 ODveertefloctw Output Compare Edge Detect ICAP1 circuit circuit 1 circuit pin 6 Edge Detect ICAP2 circuit 2 pin Latch 1 OCMP1 pin ICF1OCF1TOF ICF2OCF2TIMD 0 0 (Control/Status register) CSR Latch 2 OCMP2 pin ICIE OCIE TOIEFOLV2FOLV1OLVL2IEDG1OLVL1 OC1EOC2EOPM PWM CC1 CC0 IEDG2EXEDG (Control register 1) CR1 (Control register 2) CR2 (See note 1) Timer interrupt 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table10: Interrupt mapping on page32). 50/139

ST7260xx Watchdog timer (WDG) 16-bit read sequence The 16-bit read sequence (from either the Counter register or the Alternate Counter register) is illustrated in the following Figure25. Figure 25. 16-bit read sequence Beginning of the sequence At t0 Read MSB LSB is buffered Other instructions Returns the buffered At t0 +Δt Read LSB LSB value at t0 Sequence completed The user must first read the MSB, afterwhich the LSB value is automatically buffered. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: ● The TOF bit of the SR register is set. ● A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a reset). 51/139

Watchdog timer (WDG) ST7260xx External clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 26. Counter timing diagram, internal clock divided by 2 CPU clock Internal reset Timer clock FFFD FFFE FFFF 0000 0001 0002 0003 Counter register Timer Overflow Flag (TOF) Figure 27. Counter timing diagram, internal clock divided by 4 CPU clock Internal reset Timer clock Counter register FFFC FFFD 0000 0001 Timer Overflow Flag (TOF) Figure 28. Counter timing diagram, internal clock divided by 8 CPU clock Internal reset Timer clock Counter register FFFC FFFD 0000 Timer Overflow Flag (TOF) Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. 52/139

ST7260xx Watchdog timer (WDG) Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure30). T able 26. Input capture byte distribution Register MS byte LS byte ICiR ICiHR ICiLR The ICiR registers are read-only registers. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (f /CC[1:0]). CPU Procedure To use the input capture function select the following in the CR2 register: ● Select the timer clock (CC[1:0]) (see Table32). ● Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). Select the following in the CR1 register: ● Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin ● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: ● ICFi bit is set. ● The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure30). ● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set 2. An access (read or write) to the ICiLR register 53/139

Watchdog timer (WDG) ST7260xx Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3 The two input capture functions can be used together even if the timer also uses the two output compare functions. 4 In One pulse mode and PWM mode only Input Capture 2 can be used. 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note1). 6 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). Figure 29. Input capture block diagram ICAP1 (Control register 1) CR1 pin Edge Detect Edge Detect ICIE IEDG1 circuit 2 circuit 1 ICAP2 pin (Status register) SR IC2R register IC1R register ICF1 ICF2 0 0 0 16-bit (Control register 2) CR2 CC1 CC0 IEDG2 16-bit free running counter Figure 30. Input capture timing diagram Timer clock Counter register FF01 FF02 FF03 ICAPi pin ICAPi flag FF03 ICAPi register Note: The rising edge is the active edge. 54/139

ST7260xx Watchdog timer (WDG) Output compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: – Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. T able 27. Output compare byte distribution Register MS byte LS byte OCiR OCiHR OCiLR These registers are readable and witable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (f /CC[1:0]). CPU Procedure To use the Output Compare function, select the following in the CR2 register: ● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. ● Select the timer clock (CC[1:0]) (see Table32). And select the following in the CR1 register: ● Select the OLVLi bit to applied to the OCMPi pins after the match occurs. ● Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: ● OCFi bit is set ● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset) ● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: Δt f Δ OCiR = * CPU PRESC Where: Δt = Output compare period (in seconds) f = CPU clock frequency (in hertz) CPU PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table32) 55/139

Watchdog timer (WDG) ST7260xx If the timer clock is an external clock, the formula is: Δ OCiR = Δt f * EXT Where: Δt = Output compare period (in seconds) f = External timer clock frequency (in hertz) EXT Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: ● Write to the OCiHR register (further compares are inhibited). ● Read the SR register (first step of the clearance of the OCFi bit, which may be already set). ● Write to the OCiLR register (enables the output compare function and clears the OCFi bit). Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure32 on page57 for an example with f /2 and CPU Figure33 on page57 for an example with f /4). This behavior is the same in OPM or CPU PWM mode. 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5 The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Forced output compare capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode. 56/139

ST7260xx Watchdog timer (WDG) Figure 31. Output compare block diagram 16-bit free running counter OC1EOC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 Output compare circuit OCIE FOLV2FOLV1OLVL2 OLVL1 Latch 1 OCMP1 Pin 16-bit 16-bit Latch OCMP2 2 OC1R register Pin OCF1 OCF2 0 0 0 OC2R register (Status register) SR Figure 32. Output compare timing diagram, f =f /2 TIMER CPU Internal CPU clock Timer clock Counter register 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 Output Compare register i (OCRi) 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi=1) Figure 33. Output compare timing diagram, f =f /4 TIMER CPU Internal CPU clock Timer clock Counter register 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 Output Compare register i (OCRi) 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi=1) 57/139

Watchdog timer (WDG) ST7260xx One pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula below). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table32). Figure 34. One pulse mode cycle When ICR1 = Counter event occurs OCMP1 = OLVL2 on ICAP1 Counter is reset to FFFCh ICF1 bit is set When counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. 58/139

ST7260xx Watchdog timer (WDG) The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR value = t * fCPU - 5 PRESC Where: t = Pulse period (in seconds) f = CPU clock frequnency (in hertz) CPU PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table32) If the timer clock is an external clock the formula is: OCiR = t f - 5 * EXT Where: t = Pulse period (in seconds) f = External timer clock frequency (in hertz) EXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure35). Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. Figure 35. One Pulse mode timing example(1) IC1R 01F8 2ED3 Counter 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 Compare1 1. IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 59/139

Watchdog timer (WDG) ST7260xx Figure 36. Pulse width modulation mode timing example with two output compare functions(1)(2) Counter 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC OCMP1 OLVL2 OLVL1 OLVL2 compare2 compare1 compare2 1. OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. Pulse width modulation mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula below. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table32). 60/139

ST7260xx Watchdog timer (WDG) Figure 37. Pulse width modulation cycle When counter OCMP1 = OLVL1 = OC1R When OCMP1 = OLVL2 counter counter is reset = OC2R to FFFCh ICF1 bit is set If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2, a continuous signal will be seen on the OCMP1 pin. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR value = t * fCPU - 5 PRESC Where: t = Signal or pulse period (in seconds) f = CPU clock frequnency (in hertz) CPU PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table32) If the timer clock is an external clock the formula is: OCiR = t f - 5 * EXT Where: t = Signal or pulse period (in seconds) f = External timer clock frequency (in hertz) EXT The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure36). Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 61/139

Watchdog timer (WDG) ST7260xx 12.4.4 Low power modes T able 28. Effect of low power modes on 16-bit timer Mode Description No effect on 16-bit timer. Wait Timer interrupts cause the device to exit from Wait mode. 16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with Exit from Halt mode capability or from the counter reset value when the MCU is woken up by a reset. Halt If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt mode capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register. 12.4.5 Interrupts T able 29. 16-bit timer interrupt control/wake-up capability(1) Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Input Capture 1 event/counter ICF1 reset in PWM mode ICIE Input Capture 2 event ICF2 Output Compare 1 event OCF1 Yes No (not available in PWM mode) OCIE Output Compare 2 event OCF2 (not available in PWM mode) Timer Overflow event TOF TOIE 1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section8: Interrupts). These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). 62/139

ST7260xx Watchdog timer (WDG) 12.4.6 Summary of timer modes T able 30. Summary of timer modes Timer resources Mode Input Input Output Output capture 1 capture 2 compare 1 compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) One Pulse mode Not recommended(1) Partially(2) No No PWM mode Not recommended(3) No 1. See note 4 in One pulse mode on page58. 2. See note 5 in One pulse mode on page58. 3. See note 4 in Pulse width modulation mode on page60. 12.4.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control Register 1 (CR1) CR1 Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 R/W R/W R/W R/W R/W R/W R/W R/W T aM ble 31. CR1 register description Bit Name Function Input Capture Interrupt Enable 0: Interrupt is inhibited. 7 ICIE 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Output Compare Interrupt Enable 0: Interrupt is inhibited. 6 OCIE 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Timer Overflow Interrupt Enable 5 TOIE 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 63/139

Watchdog timer (WDG) ST7260xx Table 31. CR1 register description (continued) Bit Name Function Forced Output compare 2 This bit is set and cleared by software. 4 FOLV2 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Forced Output compare 1 This bit is set and cleared by software. 3 FOLV1 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with 2 OLVL2 the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width modulation mode. Input Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the 1 IEDG1 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Output Level 1 0 OLVL1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. Control Register 2 (CR2) CR2 Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG R/W R/W R/W R/W R/W R/W R/W T aM ble 32. CR2 register description Bit Name Function Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode). 7 OCIE Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 6 OC2E function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 64/139

ST7260xx Watchdog timer (WDG) Table 32. CR2 register description (continued) Bit Name Function One Pulse Mode 0: One Pulse mode is not active. 5 OPM 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. Pulse Width Modulation 0: PWM mode is not active. 4 PWM 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Clock Control The timer clock mode depends on these bits. 00: Timer clock=f /4 CPU 01: Timer clock=f /2 3:2 CC[1:0] CPU 10: Timer clock=f /8 CPU 11: Timer clock=external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the 1 IEDG2 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK 0 EXEDG will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. Control/Status Register (CSR) CSR Reset value: xxxx x0xx (xxh) 7 6 5 4 3 2 1 0 ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved RO RO RO RO RO R/W - T aM ble 33. CSR register description Bit Name Function Input Capture Flag 1 0: No Input Capture (reset value). 7 ICF1 1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. 65/139

Watchdog timer (WDG) ST7260xx Table 33. CSR register description (continued) Bit Name Function Output Compare Flag 1 0: No match (reset value). 6 OCF1 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Timer Overflow Flag 0: No timer overflow (reset value). 5 TOF 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Input Capture Flag 2 0: No input capture (reset value). 4 ICF2 1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Output Compare Flag 2 0: No match (reset value). 3 OCF2 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Timer Disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce 2 TIMD power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled. 1: Timer prescaler, counter and outputs disabled. 1:0 - Reserved, must be kept cleared. Input capture 1 high register (IC1HR) This is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event). IC1HR Reset value: undefined 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO 66/139

ST7260xx Watchdog timer (WDG) Input capture 1 low register (IC1LR) This is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR Reset value: undefined 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO Output compare 1 high register (OC1HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OC1HR Reset value: 1000 0000 (80h) 7 6 5 4 3 2 1 0 MSB LSB R/W R/W R/W R/W R/W R/W R/W R/W Output compare 1 low register (OC1LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC1LR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 MSB LSB R/W R/W R/W R/W R/W R/W R/W R/W Output compare 2 high register (OC2HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OC2HR Reset value: 1000 0000 (80h) 7 6 5 4 3 2 1 0 MSB LSB R/W R/W R/W R/W R/W R/W R/W R/W 67/139

Watchdog timer (WDG) ST7260xx Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 MSB LSB R/W R/W R/W R/W R/W R/W R/W R/W Counter high register (CHR) This is an 8-bit register that contains the high part of the counter value. CHR Reset value: 1111 1111 (FFh) 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO Counter low register (CLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. CLR Reset value: 1111 1100 (FCh) 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO Alternate counter high register (ACHR) This is an 8-bit register that contains the high part of the counter value. ACHR Reset value: 1111 1111 (FFh) 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO 68/139

ST7260xx Watchdog timer (WDG) Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. ACLR Reset value: 1111 1100 (FCh) 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO Input capture 2 high register (IC2HR) This is an 8-bit register that contains the high part of the counter value (transferred by the Input Capture 2 event). 1C2HR Reset value: undefined 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO Input capture 2 low register (IC2LR) This is an 8-bit register that contains the low part of the counter value (transferred by the Input Capture 2 event). 1C2LR Reset value: undefined 7 6 5 4 3 2 1 0 MSB LSB RO RO RO RO RO RO RO RO 69/139

Watchdog timer (WDG) ST7260xx Table 34. 1 6-bit timer register map and reset values Address Register 7 6 5 4 3 2 1 0 (Hex.) label CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 11 Reset value 0 0 0 0 0 0 0 0 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG 12 Reset value 0 0 0 0 0 0 0 0 CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD - - 13 Reset value x x x x x 0 x x IC1HR MSB LSB 14 Reset value x x x x x x x x IC1LR MSB LSB 15 Reset value x x x x x x x x OC1HR MSB LSB 16 Reset value 1 0 0 0 0 0 0 0 OC1LR MSB LSB 17 Reset value 0 0 0 0 0 0 0 0 CHR MSB LSB 18 Reset value 1 1 1 1 1 1 1 1 CLR MSB LSB 19 Reset value 1 1 1 1 1 1 0 0 ACHR MSB LSB 1A Reset value 1 1 1 1 1 1 1 1 ACLR MSB LSB 1B Reset value 1 1 1 1 1 1 0 0 IC2HR MSB LSB 1C Reset value x x x x x x x x IC2LR MSB LSB 1D Reset value x x x x x x x x OC2HR MSB LSB 1E Reset value 1 0 0 0 0 0 0 0 OC2LR MSB LSB 1F Reset value 0 0 0 0 0 0 0 0 70/139

ST7260xx Serial communications interface (SCI) 13 Serial communications interface (SCI) 13.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 13.2 Main features ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● Independently programmable transmit and receive baud rates up to 250K baud. ● Programmable data word length (8 or 9 bits) ● Receive buffer full, Transmit buffer empty and End of Transmission flags ● Two receiver wake-up modes: – Address bit (MSB) – Idle line ● Muting function for multiprocessor configurations ● Separate enable bits for Transmitter and Receiver ● Four error detection flags: – Overrun error – Noise error – Frame error – Parity error ● Six interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected – Parity error ● Parity control: – Transmits parity bit – Checks parity of received data byte ● Reduced power consumption mode 71/139

Serial communications interface (SCI) ST7260xx 13.2.1 General description The interface is externally connected to another device by two pins (see Figure39): ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. ● RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ● A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: ● A conventional type for commonly-used baud rates. 72/139

ST7260xx Serial communications interface (SCI) Figure 38. SCI block diagram Write Read (DATA REGISTER) DR Transmit Data Register (TDR) Received Data Register (RDR) TDO Transmit Shift Register Received Shift Register RDI CR1 R8 T8 SCID M WAKE PCE PS PIE WAKE TRANSMIT UP RECEIVER RECEIVER CONTROL UNIT CONTROL CLOCK CR2 SR TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRFIDLE OR NF FE PE SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE CONTROL f CPU /16 /PR BRR SCP1SCP0SCT2SCT1SCT0SCR2SCR1SCR0 RECEIVER RATE CONTROL BAUD RATE GENERATOR 13.2.2 Functional description The block diagram of the Serial Control Interface, is shown in Figure38. It contains 6 dedicated registers: ● Two control registers (SCICR1 & SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) Refer to the register descriptions in Section13.3 for the definitions of each bit. 73/139

Serial communications interface (SCI) ST7260xx Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure38). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 39. Word length programming 9-bit Word length (M bit is set) Possible Next Data Frame Parity Data Frame Bit Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Stop Bit Bit Start Idle Frame Bit Break Frame Extra Start ’1’ Bit 8-bit Word length (M bit is reset) Possible Next Data Frame Data Frame Parity Bit Next Start Stop Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Bit Start Idle Frame Bit Break Frame Extra Start ’1’ Bit Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure38). 74/139

ST7260xx Serial communications interface (SCI) Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIETPR registers. ● Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. ● Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: ● The TDR register is empty. ● The data transfer is beginning. ● The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure39). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. 75/139

Serial communications interface (SCI) ST7260xx Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see <Blue HT>Figure 38). Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIERPR registers. ● Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: ● The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. ● The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. 76/139

ST7260xx Serial communications interface (SCI) Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: ● The NF flag is set at the rising edge of the RDRF bit. ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Noise error causes. Framing Error A framing error is detected when: ● The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. ● A break is received. When the framing error is detected: ● The FE bit is set by hardware ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 77/139

Serial communications interface (SCI) ST7260xx Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: fCPU fCPU Tx = Rx = (16*PR)*TR (16*PR)*RR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If f is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and CPU receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. Receiver muting and wake-up feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: ● by Idle Line detection if the WAKE bit is reset, ● by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. 78/139

ST7260xx Serial communications interface (SCI) Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table35. T able 35. Frame formats M bit PCE bit SCI frame 0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB | Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. SCI clock tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs & 36 µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal 79/139

Serial communications interface (SCI) ST7260xx clock occurs just before the pin value changes, the samples would then be out of sync by ~4µs. This means the entire bit length must be at least 40 µs (36µs for the 10th sample + 4µs for synchronization with the internal sampling clock). Clock deviation causes The causes which contribute to the total deviation are: ● D : Deviation due to transmitter error (Local oscillator error of the transmitter or the TRA transmitter is transmitting at a different baud rate). ● D : Error due to the baud rate quantisation of the receiver. QUANT ● D : Deviation of the local oscillator of the receiver: This deviation can occur during REC the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. ● D : Deviation due to the transmission line (generally due to the transceivers) TCL All the deviations of the system should be added and compared to the SCI clock tolerance: D + D + D + D < 3.75% TRA QUANT REC TCL Noise error causes See also description of Noise error in Receiver on page76. Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: Note: 1 A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”. 2 During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a “1”. Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data bits The noise flag (NF) is set during normal data bit reception if the following condition occurs: ● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. 80/139

ST7260xx Serial communications interface (SCI) Figure 40. Bit sampling in reception mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 13.2.3 Low power modes T able 36. Effect of low power modes on SCI Mode Description No effect on SCI. Wait SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. Halt In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 13.2.4 Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). T able 37. SCI interrupt control/wake-up capability Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Transmit data register empty TDRE TIE Yes No Transmission complete TC TCIE Yes No Received data ready to be read RDRF Yes No RIE Overrun error detected OR Yes No Idle line detected IDLE ILIE Yes No Parity error PE PIE Yes No 81/139

Serial communications interface (SCI) ST7260xx 13.3 Register description 13.3.1 Status register (SCISR) SCISR Reset value: 1100 0000 (C0h) 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PE R R R R R R R R T able 38. SCISR register description Bit Name Function Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register 7 TDRE followed by a write to the SCIDR register). 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register. Note: Data will not be transferred to the shift register unless the TDRE bit is cleared. Transmission Complete This bit is set by hardware when transmission of a frame containing data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the 6 TC SCIDR register). 0: Transmission is not complete 1: Transmission is complete Note: TC is not set after the transmission of a Preamble or a Break. Received Data Ready Flag This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2 5 RDRF register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read Idle line detect This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 4 IDLE 0: No idle line is detected 1: Idle line is detected Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new idle line occurs). 82/139

ST7260xx Serial communications interface (SCI) Table 38. SCISR register description (continued) Bit Name Function Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an 3 OR access to the SCISR register followed by a read to the SCIDR register). 0: No overrun error 1: Overrun error is detected Note: When this bit is set RDR register content is not lost but the shift register is overwritten. Noise Flag This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 2 NF 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Framing Error This bit is set by hardware when a desynchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No framing error is detected 1 FE 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both Frame Error and Overrun error, it is transferred and only the OR bit will be set. Parity Error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the 0 PE SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error 83/139

Serial communications interface (SCI) ST7260xx 13.3.2 Control register 1 (SCICR1) SCICR1 Reset value: x000 0000 (x0h) 7 6 5 4 3 2 1 0 R8 T8 SCID M WAKE PCE PS PIE R/W R/W R/W R/W R/W R/W R/W R/W T able 39. SCICR1 register description Bit Name Function Receive data bit 8 7 R8 This bit is used to store the 9th bit of the received word when M = 1. Transmit data bit 8 6 T8 This bit is used to store the 9th bit of the transmitted word when M = 1. Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and 5 SCID cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Word length This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 data bits, 1 Stop bit 4 M 1: 1 Start bit, 9 data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). Wake-Up method This bit determines the SCI Wake-Up method, it is set or cleared by software. 3 WAKE 0: Idle line 1: Address mark Parity Control Enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set 2 PCE and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled 84/139

ST7260xx Serial communications interface (SCI) Table 39. SCICR1 register description (continued) Bit Name Function Parity Selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected 1 PS after the current byte. 0: Even parity 1: Odd parity Parity Interrupt Enable This bit enables the interrupt capability of the hardware parity control when a parity 0 PIE error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled 13.3.3 Control register 2 (SCICR2) SCICR2 Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK R/W R/W R/W R/W R/W R/W R/W R/W T able 40. SCICR2 register description Bit Name Function Transmitter Interrupt Enable This bit is set and cleared by software. 7 TIE 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register. Transmission Complete Interrupt Enable This bit is set and cleared by software. 6 TCIE 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register. Receiver interrupt Enable This bit is set and cleared by software. 5 RIE 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register. Idle Line Interrupt Enable This bit is set and cleared by software. 4 ILIE 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register. 85/139

Serial communications interface (SCI) ST7260xx Table 40. SCICR2 register description (continued) Bit Name Function Transmitter Enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: 3 TE - During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (Idle line) after the current word. - When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). Receiver Enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 2 RE 1: Receiver is enabled and begins searching for a start bit Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line detection. Receiver Wake-Up This bit determines if the SCI is in mute mode or not. It is set and cleared by 1 RWU software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode Send Break This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted. 0 SBK 1: Break characters are transmitted. Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word at the end of the current word. 13.3.4 Data register (SCIDR) SCIDR Reset value: undefined (xxh) 7 6 5 4 3 2 1 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 R/W R/W R/W R/W R/W R/W R/W R/W Contains the Received or Transmitted data character, depending on whether it is read from or written to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure38). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure38). 86/139

ST7260xx Serial communications interface (SCI) 13.3.5 Baud rate register (SCIBRR) SCIBRR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 SCP[1:0] SCT[2:0] SCR[2:0] R/W R/W R/W T able 41. SCIBRR register description Bit Name Function First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges. 00: PR prescaling factor=1 7:6 SCP[1:0] 01: PR prescaling factor=3 10: PR prescaling factor=4 11: PR prescaling factor=13 SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: TR dividing factor=1 001: TR dividing factor=2 5:3 SCT[2:0] 010: TR dividing factor=4 011: TR dividing factor=8 100: TR dividing factor=16 101: TR dividing factor=32 110: TR dividing factor=64 111: TR dividing factor=128 SCI Receiver rate divisor These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: RR dividing factor=1 001: RR dividing factor=2 2:0 SCR[2:0] 010: RR dividing factor=4 011: RR dividing factor=8 100: RR dividing factor=16 101: RR dividing factor=32 110: RR dividing factor=64 111: RR dividing factor=128 T able 42. SCI register map and reset values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label SCISR TDRE TC RDRF IDLE OR NF FE PE 20 Reset Value 1 1 0 0 0 0 0 0 SCIDR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 21 Reset Value x x x x x x x x 87/139

Serial communications interface (SCI) ST7260xx Table 42. SCI register map and reset values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 22 Reset Value 0 0 x x x x x x SCICR1 R8 T8 SCID M WAKE PCE PS PIE 23 Reset Value x x 0 x x 0 0 0 SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK 24 Reset Value 0 0 0 0 0 0 0 0 88/139

ST7260xx USB interface (USB) 14 USB interface (USB) 14.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out. 14.2 Main features ● USB specification version 1.1 compliant ● Supports Low-Speed USB protocol ● Two or three Endpoints (including default one) depending on the device (see device feature list and register map) ● CRC generation/checking, NRZI encoding/decoding and bit-stuffing ● USB Suspend/Resume operations ● DMA data transfers ● On-chip 3.3V regulator ● On-chip USB transceiver 14.3 Functional description The block diagram in Figure41, gives an overview of the USB interface hardware. For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org. Serial interface engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. DMA When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred. 89/139

USB interface (USB) ST7260xx Figure 41. USB block diagram 6 MHz ENDPOINT REGISTERS CPU USBDM Transceiver SIE DMA Address, USBDP data buses and interrupts 3.3V USBVCC Voltage INTERRUPT Regulator REGISTERS MEMORY USBGND 14.4 Register description 14.4.1 DMA address register (DMAR) DMAR Reset value: undefined (xxh) 7 6 5 4 3 2 1 0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure42. 14.4.2 Interrupt/DMA register (IDR) IDR Reset value: xxxx 0000 (x0h) 7 6 5 4 3 2 1 0 DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:6 = DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure42. Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2 90/139

ST7260xx USB interface (USB) When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet. Bits 3:0 = CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception. Note: Not valid for data transmission. Figure 42. DMA buffers 101111 Endpoint 2 TX 101000 100111 Endpoint 2 RX 100000 011111 Endpoint 1 TX 011000 010111 Endpoint 1 RX 010000 001111 Endpoint 0 TX 001000 000111 Endpoint 0 RX DA15-6,000000 000000 14.4.3 PID register (PIDR) PIDR Reset value: xxxx 0000 (x0h) 7 6 5 4 3 2 1 0 RX_ TP3 TP2 0 0 0 RXD 0 SEZ R R R R R R R R Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. Note: PID bits 1 & 0 have a fixed value of 01. When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits as: T able 43. TP bits TP3 TP2 PID name 0 0 OUT 1 0 IN 1 1 SETUP Bits 5:3 Reserved. Forced by hardware to 0. 91/139

USB interface (USB) ST7260xx Bit 2 = RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state Bit 1 = RXD Received data 0: No K-state 1: USB lines are in K-state This bit indicates the status of the RXD transceiver output (differential receiver output). Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wake-up due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1. Bit 0 = Reserved. Forced by hardware to 0. 14.4.4 Interrupt status register (ISTR) ISTR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 SUSP DOVR CTR ERR IOVR ESUSP RESET SOF R/W R/W R/W R/W R/W R/W R/W R/W When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits cannot be set by software. Bit 7 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence. Bit 6 = DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can’t answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 92/139

ST7260xx USB interface (USB) 0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected Bit 2 = ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a USB reset. Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid read-modify-write instructions like AND , XOR.. 14.4.5 Interrupt mask register (IMR) IMR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 SUSPM DOVRM CTRM ERRM IOVRM ESUSPM RESETM SOFM R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the corresponding bit description in ISTR. 93/139

USB interface (USB) ST7260xx 14.4.6 Control register (CTLR) CTLR Reset value: 0000 0110 (06h) 7 6 5 4 3 2 1 0 0 0 0 0 RESUME PDWN FSUSP FRES R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay. Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of the power supply before using the USB interface. Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled. 94/139

ST7260xx USB interface (USB) 14.4.7 Device address register (DADDR) DADDR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. Note: This register is also reset when a USB reset is received from the USB bus or forced through bit FRES in the CTLR register. 14.4.8 Endpoint n register A (EPnRA) EPnRA Reset value: 0000 xxxx (0xh) 7 6 5 4 3 2 1 0 ST_ DTOG STAT STAT TBC3 TBC2 TBC1 TBC0 OUT _TX _TX1 _TX0 R/W R/W R/W R/W R/W R/W R/W R/W These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and register map). Bit 7 = ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed. Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software. Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed below: 95/139

USB interface (USB) ST7260xx T able 44. STAT_TX bits STAT_TX1 STAT_TX0 Meaning DISABLED:transmission transfers cannot be 0 0 executed. STALL: the endpoint is stalled and all transmission 0 1 requests result in a STALL handshake. NAK: the endpoint is naked and all transmission 1 0 requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for transmission. These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 0-8). Caution: Any value outside the range 0-8 willinduce undesired effects (such as continuous data transmission). 14.4.9 Endpoint n register B (EPnRB) EPnRB Reset value: 0000 xxxx (0xh) 7 6 5 4 3 2 1 0 DTOG STAT STAT CTRL EA3 EA2 EA1 EA0 _RX _RX1 _RX0 R/W R/W R/W R/W R/W R/W R/W R/W These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Bit 7 = CTRL Control. This bit should be 0. Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control Endpoint). Bit 6 = DTOG_RX Data toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below: 96/139

ST7260xx USB interface (USB) T able 45. STAT_RX bits STAT_RX1 STAT_RX0 Meaning DISABLED:reception transfers cannot be 0 0 executed. STALL: the endpoint is stalled and all reception 0 1 requests result in a STALL handshake. NAK: the endpoint is naked and all reception 1 0 requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for reception. These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”. 14.4.10 Endpoint 0 register B (EP0RB) EP0RB Reset value: 1000 0000 (80h) 7 6 5 4 3 2 1 0 DTOG STAT STAT 1 0 0 0 0 RX RX1 RX0 R/W R/W R/W R/W R/W R/W R/W R/W This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset. Bit 7 = Forced by hardware to 1. Bits 6:4 = Refer to the EPnRB register for a description of these bits. Bits 3:0 = Forced by hardware to 0. 14.5 Programming considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (ISTR) bits. 14.5.1 Initializing the registers At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests. 97/139

USB interface (USB) ST7260xx 1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers. 2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization. 3. When addresses are received through this channel, update the content of the DADDR. 4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register. 14.5.2 Initializing DMA buffers The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure42. Each buffer is filled starting from the bottom (last 3 address bits=000) up. 14.5.3 Endpoint initialization To be ready to receive: Set STAT_RX to VALID (11b) in EP0RB to enable reception. To be ready to transmit: 1. Write the data in the DMA transmit buffer. 2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field 3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA. Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly. When the operation is completed, they can be accessed again to enable a new operation. 14.5.4 Interrupt handling Start of frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. 98/139

ST7260xx USB interface (USB) End suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates HALT mode. Correct transfer (CTR) 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. 2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. Note: When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register. Table 46. U SB register map and reset values Address Register 7 6 5 4 3 2 1 0 (Hex.) name PIDR TP3 TP2 0 0 0 RX_SEZ RXD 0 25 Reset Value x x 0 0 0 0 0 0 DMAR DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 26 Reset Value x x x x x x x x IDR DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0 27 Reset Value x x x x 0 0 0 0 ISTR SUSP DOVR CTR ERR IOVR ESUSP RESET SOF 28 Reset Value 0 0 0 0 0 0 0 0 ESUSP RESET IMR SUSPM DOVRM CTRM ERRM IOVRM SOFM 29 M M Reset Value 0 0 0 0 0 0 0 0 RESUM CTLR 0 0 0 0 PDWN FSUSP FRES 2A E Reset Value 0 0 0 0 1 1 0 0 DADDR 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 2B Reset Value 0 0 0 0 0 0 0 0 EP0RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0 2C Reset Value 0 0 0 0 x x x x STAT_RX STAT_RX EP0RB 1 DTOG_RX 0 0 0 0 2D 1 0 Reset Value 1 0 0 0 0 0 0 0 99/139

USB interface (USB) ST7260xx Table 46. USB register map and reset values (continued) Address Register 7 6 5 4 3 2 1 0 (Hex.) name EP1RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0 2E Reset Value 0 0 0 0 x x x x STAT_RX STAT_RX EP1RB CTRL DTOG_RX EA3 EA2 EA1 EA0 2F 1 0 Reset Value 0 0 x x x x 0 0 EP2RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0 30 Reset Value 0 0 0 0 x x x x STAT_RX STAT_RX EP2RB CTRL DTOG_RX EA3 EA2 EA1 EA0 31 1 0 Reset Value 0 0 x x x x 0 0 100/139

ST7260xx Instruction set 15 Instruction set 15.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: T able 47. Addressing mode groups Addressing mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two sub-modes called long and short: ● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. ● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 48. S T7 addressing mode overview Destination/ Pointer Pointer Length Mode Syntax source address size (bytes) Inherent nop + 0 Immediate ld A,#$55 + 1 Short Direct ld A,$10 00..FF + 1 Long Direct ld A,$1000 0000..FFFF + 2 + 0 (with X register) No Offset Direct Indexed ld A,(X) 00..FF + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE + 1 Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2 Short Indirect ld A,[$10] 00..FF 00..FF byte + 2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2 101/139

Instruction set ST7260xx Table 48. ST7 addressing mode overview (continued) Destination/ Pointer Pointer Length Mode Syntax source address size (bytes) Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 Relative Direct jrne loop PC-128/PC+127(1) + 1 Relative Indirect jrne [$10] PC-128/PC+127(1) 00..FF byte + 2 Bit Direct bset $10,#7 00..FF + 1 Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 Bit Direct Relative btjt $10,#7,skip 00..FF + 2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 15.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. T able 49. Inherent instructions Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication 102/139

ST7260xx Instruction set Table 49. Inherent instructions Instruction Function SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles 15.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. T able 50. Immediate instructions Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations 15.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub-modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 15.1.4 Indexed (no offset, short, long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (no offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. 103/139

Instruction set ST7260xx Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 15.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub- modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 15.1.6 Indirect indexed (short, long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect indexed (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect indexed (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 104/139

ST7260xx Instruction set T able 51. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Instructions Function LD Load CP Compare AND, OR, XOR Logical Operations Long and short instructions Arithmetic Addition/subtraction ADC, ADD, SUB, SBC operations BCP Bit Compare CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement Short instructions only BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP Call or Jump subroutine 15.1.7 Relative mode (direct, indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. T able 52. Available relative direct/indirect instructions Instructions Function JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two sub-modes: Relative (direct) The offset follows the opcode. Relative (indirect) The offset is defined in memory, of which the address follows the opcode. 15.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: 105/139

Instruction set ST7260xx T able 53. Instruction groups Group Instruction Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 106/139

ST7260xx Instruction set Table 54. I n struction set Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= 107/139

Instruction set ST7260xx Table 54. Instruction set (continued) Mnemo Description Function/Example Dst Src H I N Z C JRUGT Jump if (C + Z = 0) Unsigned > JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C Dst[7..4] <=> SWAP SWAP nibbles reg, M N Z Dst[3..0] TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z 108/139

ST7260xx Electrical characteristics 16 Electrical characteristics 16.1 Parameter conditions Unless otherwise specified, all voltages are referred to V . SS 16.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T =25°C and T =T (given by the A A Amax selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3s). 16.1.2 Typical values Unless otherwise specified, typical data are based on T =25°C, V =5V. They are given A DD only as design guidelines and are not tested. 16.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 16.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure43. Figure 43. Pin loading conditions ST7PIN CL 16.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure44. 109/139

Electrical characteristics ST7260xx Figure 44. Pin input voltage ST7PIN VIN 110/139

ST7260xx Electrical characteristics 16.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. T a ble 55. Voltage characteristics Symbol Ratings Maximum value Unit V - V Supply voltage 6.0 DD SS Input voltage on true open drain pins V -0.3 to 6.0 V V (1) & (2) SS IN Input voltage on any other pin V -0.3 to V +0.3 SS DD See “Absolute maximum Electro-static discharge voltage (Human Body V ratings (electrical sensitivity)” ESD(HBM) Model) on page119. 1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional DD SS internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration. DD SS T a ble 56. Current characteristics Symbol Ratings Maximum value Unit I Total current into V power lines (source) (1) 80 VDD DD I Total current out of V ground lines (sink) (1) 80 VSS SS Output current sunk by any standard I/O and 25 control pin I IO Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 mA Injected current on V pin ± 5 PP Injected current on RESET pin ± 5 I (2) INJ(PIN) Injected current on OSCIN and OSCOUT pins ± 5 Injected current on any other pin (3) & (4) ± 5 Total injected current (sum of all I/O and control ΣI (2) ± 20 INJ(PIN) pins) (3) I (2) Negative injected current to PB0(10mA) pin - 80 µA INJ(PIN) 1. All power (V ) and ground (V ) lines must always be connected to the external supply. DD SS 2. I must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum INJ(PIN) IN IN cannot be respected, the injection current must be limited externally to the I value. A positive INJ(PIN) injection is induced by V >V while a negative injection is induced by V <V . For true open-drain pads, IN DD IN SS there is no positive injection current, and the corresponding V maximum must always be respected IN 3. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the INJ(PIN) positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI maximum current injection on four I/O port pins of the device. INJ(PIN) 4. True open drain I/O port pins do not accept positive injection. 111/139

Electrical characteristics ST7260xx T a ble 57. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range -65 to +150 °C STG T Maximum junction temperature: See Section17.1.1 on page 130 for T J Jmax 16.3 Operating conditions 16.3.1 General operating conditions T able 58. General operating condition Symbol Parameter Conditions Min Typ Max Unit V Operating supply voltage f = 8 MHz 4 5 5.5 DD CPU V Analog supply voltage V V V DDA DD DD V Analog supply voltage V V SSA SS SS f = 24 MHz 8 OSC f Operating frequency MHz CPU f = 12 MHz 4 OSC T Ambient temperature range 0 70 °C A Figure 45. f maximum operating frequency versus V supply voltage CPU DD fCPU [MHz] 8 FUNCTIONALITY GUARANTEED FROM 4 TO 5.5 V 4 FUNCTIONALITY NOTGUARANTEED 2 IN THIS AREA 0 2.5 3.0 3.5 4 4.5 5 5.5 SUPPLYVOLTAGE [V] 112/139

ST7260xx Electrical characteristics 16.3.2 Operating conditions with low voltage detector (LVD) Subject to general operating conditions for V , f , and T . Refer to Figure9 on page26. DD CPU A T able 59. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit Low Voltage Reset Threshold V Max. Variation V DD 3.4 3.7 4.0 V IT+ (V rising) 50V/ms DD Low Voltage Reset Threshold V Max. Variation V DD 3.2 3.5 3.8 V IT- (V falling) 50V/ms DD V Hysteresis (V - V ) (1) 100 175 220 mV hyst IT+ IT- V/m Vt V rise time rate (2) 0.5 50 POR DD s 1. Guaranteed by characterization - not tested in production 2. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested DD in production. 16.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped). Table 60. S upply current consumption Symbol Parameter Conditions Typ Max Unit Supply current variation vs. ΔI Constant V and f 10 (1) % DD(ΔTa) temperature DD CPU f = 4 MHz 7.5 9 (2)(1) CPU CPU RUN mode I/Os in input mode mA f = 8 MHz 10.5 13 (2) CPU f = 4 MHz 6 8 (1) CPU CPU WAIT mode mA I f = 8 MHz 8.5 11 (2) DD CPU CPU HALT mode (3) LVD disabled 25 40 (1) μA LVD disabled 100 120 USB Suspend mode (4) μA LVD enabled 230 1. Not tested in production, guaranteed by characterization. 2. Oscillator and watchdog running. All others peripherals disabled. 3. USB Transceiver is powered down. 4. CPU in Halt mode. Current consumption of external pull-up (1.5 Kohms to USBVCC) and pull-down (15 Kohms to V ) not included. SSA 113/139

Electrical characteristics ST7260xx F igure 46. Typ. I in RUN at 4 and 8 Figure 47. Typ. I in WAIT at 4 and 8 DD DD MHz f MHz f CPU CPU Idd Run (mA) at fcpu=4 and 8MHz Idd WFI (mA) at fcpu=4 and 8MHz 12 10 10 8 A) 8 A) Run (m 6 WFI (m 6 dd dd 4 I 4 I 8MHz 2 8MHz 2 4MHz 4MHz 0 0 4 4.2 4.4 4.6 4.8 5 5.2 5.4 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) Vdd (V) 16.5 Clock and timing characteristics Subject to general operating conditions for V , f , and T . DD CPU A 16.5.1 General timings T a ble 61. CPU timings Symbol Parameter Conditions Min Typ (1) Max Unit 2 3 12 t CPU t Instruction cycle time f =8MHz c(INST) CPU 250 375 1500 ns Interrupt reaction time (2) 10 22 tCPU t f =8MHz v(IT) tv(IT) = Δtc(INST) + 10 tCPU CPU 1.25 2.75 μs 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. Δt is the number of t cycles c(INST) CPU needed to finish the current instruction execution. 16.5.2 Control timing characteristics Table 62. C ontrol timings Value Symbol Parameter Conditions Unit Min Typ Max f Oscillator frequency 24 MHz OSC f Operating frequency 8 MHz CPU External RESET t 2520 ns RL input pulse width t Internal power reset duration 4096 t PORL CPU Watchdog or low voltage reset t 200 300 ns DOGL output pulse width 114/139

ST7260xx Electrical characteristics Table 62. Control timings (continued) Value Symbol Parameter Conditions Unit Min Typ Max 49152 3145728 t t Watchdog time-out CPU DOG f = 8MHz 6.144 393.216 ms CPU Crystal oscillator t 20(1) 30 40(1) ms OXOV start-up time t Power up rise time from V = 0 to 4V 100(1) ms DDR DD 1. Not tested in production, guaranteed by characterization. 115/139

Electrical characteristics ST7260xx 16.5.3 External clock source T able 63. External clock characteristics Symbol Parameter Conditions Min Typ Max Unit OSCIN input pin high level V 0.7xV V OSCINH voltage DD DD V OSCIN input pin low level V V 0.3xV OSCINL voltage SS DD see Figure48 t w(OSCINH) OSCIN high or low time (1) 15 t w(OSCINL) ns t r(OSCIN) OSCIN rise or fall time(1) 15 t f(OSCIN) OSCx Input leakage I V ≤V ≤V ±1 μA L current SS IN DD 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 48. Typical application with an external clock source 90% VOSCINH 10% VOSCINL tr(OSCIN) tf(OSCIN) tw(OSCINH) tw(OSCINL) OSCOUT Not connected internally fOSC EXTERNAL IL CLOCKSOURCE OSCIN ST72XXX Figure 49. Typical application with a crystal resonator i 2 f OSC C L1 OSCIN RESONATOR R F C L2 OSCOUT ST72XXX 116/139

ST7260xx Electrical characteristics 16.6 Memory characteristics Subject to general operating conditions for f , and T unless otherwise specified. CPU A 16.6.1 RAM and hardware registers T a ble 64. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit HALT mode (or V Data retention mode (1) 2.0 V RM RESET) 1. Guaranteed by design. Not tested in production. 16.6.2 Flash memory Operating Conditions: f = 8 MHz. CPU T able 65. Dual voltage Flash memory (1) Symbol Parameter Conditions Min Typ Max Unit Read mode 8 fCPU Operating Frequency Write / Erase MHz 8 mode, T =25°C A V Programming Voltage 4.0V ≤V ≤ 5.5V 11.4 12.6 V PP DD I V Current Write / Erase 30 mA PP PP t Internal V Stabilization Time 10 µs VPP PP t Data Retention T ≤ 55°C 40 years RET A N Write Erase Cycles T =25°C 100 cycles RW A 1. Refer to the Flash Programming Reference Manual for the typical HDFlash programming and erase timing values. Figure 50. Two typical applications with V pin(b) PP VPP PROGRAMMING VPP TOOL ST72XXX 10kΩ ST72XXX b. When the ICP mode is not required by the application, VPP pin must be tied to VSS. 117/139

Electrical characteristics ST7260xx 16.7 EMC characteristics Susceptibility and emission tests are performed on a sample basis during product characterization. 16.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. ● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 16.7.2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 118/139

ST7260xx Electrical characteristics T able 66. EMS data Symbol Parameter Conditions Level/class V =5 V, T =+25 °C, Voltage limits to be applied on any I/O pin DD A V f =8 MHz, 4B FESD to induce a functional disturbance OSC conforms to IEC 1000-4-2 Fast transient voltage burst limits to be V =5 V, T =+25 °C, DD A V applied through 100pF on V and V f =8 MHz, 4A FFTB DD DD OSC pins to induce a functional disturbance conforms to IEC 1000-4-4 16.7.3 Electro magnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 67. E MC data Max vs. Monitored [f /f ] Symbol Parameter Conditions OSC CPU Unit frequency band 16/8 MHz 0.1 MHz to 30 MHz 36 V =5V, T =+25°C, DD A conforming to SAE J 1752/3 30 MHz to 130 MHz 39 dBμV S Peak level (1) EMI Note: Refer to Application Note AN1709 130 MHz to 1 GHz 26 for data on other package types. SAE EMI Level 3.5 - 1. Data based on characterization results, not tested in production. 16.7.4 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 16.7.5 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002 standard. T able 68. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) VESD(HBM) E(Hleucmtraons tbaoticd yd imscohdaerlg)e voltage tToA A=E +C2-5Q°C10, 0co-0n0fo2rming H1C 2000 V 1. Data based on characterization results, not tested in production 119/139

Electrical characteristics ST7260xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance. ● A supply overvoltage (applied to each power supply pin) and ● A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. T able 69. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T = +25 °C conforming to JESD 78 II level A A 120/139

ST7260xx Electrical characteristics 16.8 I/O port pin characteristics 16.8.1 General characteristics Subject to general operating conditions for V , f , and T unless otherwise specified. DD CPU A T able 70. I/O port characteristics Symbol Parameter Conditions Min Typ Max Unit V Input low level voltage 0.3xV IL DD V V Input high level voltage 0.7xV IH DD True open drain I/O 6.0 V Input voltage pins V V IN SS Other I/O pins V DD Schmitt trigger voltage V 400 mV hys hysteresis IL Input leakage current VSS≤VIN≤VDD ±1 Static current μA I consumption induced by Floating input mode 400 S each floating input pin (1) Weak pull-up equivalent RPU resistor (2) VIN=VSS VDD=5 V 50 90 120 kΩ C I/O pin capacitance 5 pF IO Output high to low level tf(IO)out fall time CL=50 pF 25 Between 10% and ns t Output low to high level 90% 25 r(IO)out rise time External interrupt pulse t 1 t w(IT)in time (3) CPU 1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure51). Static peak current value taken at a fixed V value, based on design simulation and technology characteristics, not tested in IN production. This value depends on V and temperature values. DD 2. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current PU PU characteristics described in Figure52). 3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. Figure 51. Two typical applications with unused I/O pin VDD ST72XXX 10kΩ 10kΩ UNUSEDI/OPORT UNUSEDI/OPORT ST72XXX 121/139

Electrical characteristics ST7260xx Figure 52. Typ. I vs. V PU DD Pull-up current (µA) 90 80 70 A)60 µ ent (50 urr c40 p u ull-30 P 20 10 0 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) Figure 53. Typ. R vs. V PU DD Rpu (KOhm) 140 120 100 hm) 80 O K u ( 60 p R 40 20 0 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) 122/139

ST7260xx Electrical characteristics 16.8.2 Output driving current Subject to general operating condition for V , f , and T unless otherwise specified. DD CPU A T able 71. Output current characteristics Symbol Parameter Conditions Min Max Unit Output low level voltage for a standard I/O pin when up to 8 pins are sunk at the I =+1.6 mA 0.4 same time, Port A0, Port A(3:7), Port IO C(0:2) Output low level voltage for a high sink V (1) OL I/O pin when up to 4 pins are sunk at the V IIO=+10 mA 1.3 same time, Port B(0:7) =5 V D D Output low level voltage for a very high V sink I/O pin when up to 2 pins are sunk at I =+25 mA 1.5 IO the same time, Port A1, Port A2 Output high level voltage for an I/O pin I =-10 mA V -1.3 IO DD V (2) when up to 8 pins are sourced at same OH time IIO=-1.6 mA VDD-0.8 1. The IIO current sunk must always respect the absolute maximum rating specified in Section16.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section16.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH. Figure 54. V standard V =5 V Figure 55. V high sink V =5 V OL DD OL DD Vol_2mA (mV) at Vdd=5V Vol_10mA (V) at Vdd=5V 250 1.6 1.4 200 1.2 A (mV)150 mA (V) 1 Vol_2m100 Vol_100.8 0.6 50 0.4 0 0.2 1 1.5 2 2.5 3 3.5 4 5 7 9 11 13 15 17 19 Iio (mA) Iio (mA) Figure 56. V very high sink V =5 V Figure 57. V high sink vs. V OL DD OL DD Vol_25mA (V) at Vdd=5V Vol_10mA (V) at Iio=10mA 0.6 0.95 0.59 0.58 0.85 0.57 A (V)0.75 A (V)0.56 m m0.55 ol_250.65 ol_100.54 V V 0.55 0.53 0.52 0.45 0.51 0.35 0.5 15 20 25 30 35 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Iio (mA) Vdd (V) 123/139

Electrical characteristics ST7260xx F igure 58. V standard vs. V Figure 59. V very high sink vs. V OL DD OL DD Vol_2mA (mV) at Iio=2mA Vol_25mA (V) at Iio=25mA 130 0.8 125 0.75 A (mV)120 mA (V) 0.7 Vol_2m115 Vol_25 0.65 110 105 0.6 4 4.2 4.4 4.6 4.8 5 5.2 5.4 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) Vdd (V) Figure 60. |V -V | @ V =5 V (low Figure 61. |V -V | @ V =5 V (high DD OH DD DD OH DD current) current) |Vdd - Voh| (V) at Vdd=5V |Vdd - Voh| (V) at Vdd=5V 0.3 2 1.8 0.25 1.6 1.4 Voh| (V)0.01.52 Voh| (V)1.12 |Vdd - 0.1 |Vdd - 00..68 0.4 0.05 0.2 0 0 1 1.5 2 2.5 3 3.5 4 2 7 12 17 -Iio (mA) -Iio (mA) Figure 62. |V -V | @I =2 mA (low Figure 63. |V -V | @I =10mA (high DD OH IO DD OH IO current) current) |Vdd - Voh| (V) at Iio=-2mA |Vdd - Voh| (V) at Iio=-10mA 0.165 0.9 0.16 0.8 0.155 0.7 |Vdd - Voh| (V)00..0011..34115545 |Vdd - Voh| (V)0000....3456 0.13 0.2 0.125 0.1 0.12 0 4 4.2 4.4 4.6 4.8 5 5.2 5.4 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) Vdd (V) 124/139

ST7260xx Electrical characteristics 16.9 Control pin characteristics 16.9.1 Asynchronous RESET pin Subject to general operating conditions for V , f , and T unless otherwise specified. DD CPU A Table 72. R ESET pin characteristics Symbol Parameter Conditions Min Typ Max Unit V Input high level voltage 0.7xV V V IH DD DD V Input low voltage V 0.3xV V IL SS DD V Schmitt trigger voltage hysteresis (1) 400 mV hys I =5 mA 0.8 V Output low level voltage (2) V =5V IO V OL DD I =7.5 mA 1.3 IO RON Weak pull-up equivalent resistor (3) VIN=VSS VDD=5 V 50 80 100 kΩ External pin or 6 1/f t Generated reset pulse duration SFOSC w(RSTL)out internal reset sources 30 μs t External reset pulse hold time (4) 5 μs h(RSTL)in 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section16.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production. 4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 125/139

Electrical characteristics ST7260xx RESET pin protection when LVD is enabled When the LVD is enabled, it is recommended to protect the RESET pin as shown in Figure64 and follow these guidelines: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V max. level specified in Section16.9.1. IL Otherwise the reset will not be taken into account internally. 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for I in Section16.2 on page 111. INJ(RESET) 5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull- down capacitor is recommended to filter noise on the reset line. 6. In case a capacitive power supply is used, it is recommended to connect a 1M ohm pull-down resistor to the RESET pin to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of the MCU). Tips when using the LVD: ● Check that all recommendations related to reset circuit have been applied (see section above) ● Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU). Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1M Ohm pull-down on the RESET pin. ● The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace 10nF pull-down on the RESET pin with a 5 µF to 20 µF capacitor. Figure 64. RESET pin protection when LVD is enabled VDD ST72XXX Required Optional R ON (note 6) INTERNAL EXTERNAL RESET RESET Filter 0.01 μF 1 MΩ PULSE WATCHDOG GENERATOR LVDRESET 126/139

ST7260xx Electrical characteristics RESET pin protection when LVD is disabled When the LVD is disabled, it is recommended to protect the RESET pin as shown in Figure65 and follow these guidelines: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V max. level specified in Section16.9.1. IL Otherwise the reset will not be taken into account internally. 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for I in Section16.2 on page 111. INJ(RESET) Figure 65. RESET pin protection when LVD is disabled VDD ST72XXX R ON INTERNAL EXTERNAL RESET RESET Filter CIRCUIT 0.01 μF PULSE WATCHDOG GENERATOR Required 16.9.2 USB - universal bus interface Operating conditions T = 0 to +70 °C, V = 4.0 to 5.25 V unless otherwise specified. A DD T able 73. USB DC electrical characteristics Symbol Parameter Conditions(1) Min. Max. Unit V Differential Input Sensitivity I(D+, D-) 0.2 DI Differential Common Mode V Includes VDI range 0.8 2.5 CM Range Single Ended Receiver V 0.8 2.0 SE Threshold V RL(2) of 1.5 Kohms V Static Output Low 0.3 OL to 3.6v RL (2) of 15 Kohms V Static Output High 2.8 3.6 OH to V SS USBV USBVCC: voltage level (3) V =5 V 3.00 3.60 DD 1. All the voltages are measured from the local ground potential. 2. RL is the load connected on the USB drivers. 3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin. 127/139

Electrical characteristics ST7260xx Figure 66. USB: data signal rise and fall time Differential Data Lines Crossover points VCRS V SS tf tr T able 74. USB: low-speed electrical characteristics Symbol Parameter Conditions Min Max Unit Driver characteristics: CL=50 pF (1) 75 ns t Rise time r CL=600 pF (1) 300 ns CL=50 pF (1) 75 ns t Fall Time f CL=600 pF (1) 300 ns Rise/ Fall Time t tr/tf 80 120 % rfm matching Output signal V 1.3 2.0 V CRS Crossover Voltage 1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1). 16.9.3 SCI - serial communications interface Subject to general operating condition for V , f , and T unless otherwise specified. DD CPU A Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO). Table 75. S CI characteristics Conditions Baud Symbol Parameter Accuracy Standard Unit Rate f vs. Prescaler CPU Standard Conventional Mode TR (or RR)=128, PR=13 300 ~300.48 TR (or RR)= 32, PR=13 1200 ~1201.92 TR (or RR)=16, PR=13 2400 ~2403.84 f Tx Communication frequency 8 MHz ~0.16% TR (or RR)=8, PR=13 4800 ~4807.69 Hz f Rx TR (or RR)=4, PR=13 9600 ~9615.38 TR (or RR)=16, PR= 3 10400 ~10416.67 TR (or RR)=2, PR=13 19200 ~19230.77 TR (or RR)=1, PR=13 38400 ~38461.54 128/139

ST7260xx Package characteristics 17 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 17.1 Package mechanical data Figure 67. 24-pin plastic small outline package, 300-mil width mm inches(1) Dim. D h x 45× Min Typ Max Min Typ Max L A 2.35 2.65 0.0925 0.1043 A1 A C A1 0.10 0.30 0.0039 0.0118 B e a BC 00..3233 00..5312 00..00103901 00..00210216 D 15.20 15.60 0.5984 0.6142 E 7.40 7.60 0.2913 0.2992 e 1.27 0.0500 H 10.00 10.65 0.3937 0.4193 h 0.25 0.75 0.098 0.0295 E H α 0° 8° 0° 8° L 0.40 1.27 0.0157 0.0500 Number of Pins N 24 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 68. 40-lead very thin fine pitch quad flat no-lead package A A2 SEATING A3 mm inches(1) PLANE A1 Dim. Min Typ Max Min Typ Max D A 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A2 0.65 1.00 0.0256 0.0394 A3 0.20 0.0079 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 D 5.85 6.00 6.15 0.2303 0.2362 0.2421 D2 D2 2.75 2.9 3.05 0.1083 0.1142 0.1201 E 5.85 6 6.15 0.2303 0.2362 0.2421 E2 E E2 2.75 2.9 3.05 0.1083 0.1142 0.1201 e 0.50 0.0197 PIN #1 ID TYPE C RADIUS L 0.30 0.40 0.50 0.0118 0.0157 0.0197 2 Number of Pins 1 N 40 L 1.Values in inches are converted from mm and rounded to 4 decimal digits. b e 129/139

Package characteristics ST7260xx 17.1.1 Thermal characteristics T a ble 76. Package thermal characteristics Symbol Ratings Value Unit Package thermal resistance (junction to ambient) R °C/W thJA SO24 70 QFN40 34 P Power dissipation (1) 500 mW D T Maximum junction temperature (2) 150 °C Jmax 1. The maximum power dissipation is obtained from the formula P = (T -T ) / R . The power dissipation D J A thJA of an application can be defined by the user with the formula: P =PI +P where P is the chip D NT PORT INT internal power (I xV ) and P is the port power dissipation depending on the ports used in the DD DD PORT application. 2. The maximum chip-junction temperature is based on technology characteristics. 130/139

ST7260xx Device configuration and ordering information 18 Device configuration and ordering information Each device is available for production in user programmable versions (High Density FLASH) as well as in factory coded versions (FASTROM). ST72P60 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory programmed FLASH devices. ST72F60 FLASH devices are shipped to customers with a default content (FFh). This implies that FLASH devices have to be configured by the customer using the Option Byte while the FASTROM devices are factory-configured. 18.1 Option byte The Option Byte allows the hardware configuration of the microcontroller to be selected. The Option Byte has no address in the memory map and can be accessed only in programming mode using a standard ST7 programming tool. The default contents of the FLASH is fixed to F7h. This means that all the options have “1” as their default value, except LVD. T able 77. Flash option byte 7 0 -- -- WDG SW WD HALT LVD -- OSC 24/12 FMP_R OPT 7:6 = Reserved. OPT 5 = WDGSW Hardware or Software Watchdog This option bit selects the watchdog type. 0: Hardware enabled 1: Software enabled OPT 4 = WDHALT Watchdog and HALT mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPT 3 = LVD Low Voltage Detector selection This option bit selects the LVD. 0: LVD enabled 1: LVD disabled OPT 2 = Reserved. OPT 1 = OSC24/12 Oscillator Selection This option bit selects the clock divider used to drive the USB interface at 6 MHz. 0: 24MHz oscillator 1: 12Mhz oscillator OPT 0 = FMP_R Flash memory readout protection This option indicates if the user flash memory is protected against readout. readout protection, when selected, provides a protection against Program Memory content 131/139

Device configuration and ordering information ST7260xx extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected, causes the whole user memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and Section5.3.1 on page 18 for more details. 0: Readout protection enabled 1: Readout protection disabled 18.2 Device ordering information and transfer of customer code Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. See page 110. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics sales organization will be pleased to provide detailed information on contractual points. T able 78. Supported part numbers Program memory RAM Sales type (1) Package (bytes) (bytes) ST72F60K2U1 384 QFN40 8 K Flash ST72F60E2M1 384 SO24 ST72F60K1U1 384 QFN40 4 K Flash ST72F60E1M1 384 SO24 ST72P60K2U1/xxx 384 QFN40 8 K FASTROM ST72P60E2M1/xxx 384 SO24 ST72P60K1U1/xxx 384 QFN40 4 K FASTROM ST72P60E1M1/xxx 384 SO24 1. /xxx stands for the ROM code name assigned by STMicroelectronics. Contact ST sales office for product availablity of FASTROM types (shaded in table). 18.3 Development tools STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: ➟ http//www.st.com. Tools from these manufacturers include C compliers, emulators and gang programmers. STMicroelectronics Tools 132/139

ST7260xx Device configuration and ordering information Three types of development tool are offered by ST see Table79 and Table80 for more details. T able 79. STMicroelectronics tools features Programming In-Circuit Emulation Software Included capability(1) Yes, powerful ST7 CD ROM with: emulation features ST7 Assembly toolchain ST7 Emulator No including trace/ logic STVD7 powerful Source analyzer Level Debugger for Win 3.1, Win 9x and NT C compiler demo versions ST7 Programming Windows Programming No Yes (All packages) Board Tools for Win 3.1, Win 9x and NT 1. In-Circuit Programming (ICP) interface for FLASH devices. T able 80. Dedicated STMicroelectronics development tools ST7 programming Supported products Evaluation board ST7 emulator board ST7260 ST7MDTULS-EVAL ST7MDTU3-EMU3 ST7MDTU3-EPB (1) 1. Add Suffix /EU or /US for the power supply for your region. 133/139

Device configuration and ordering information ST7260xx ST7260 MICROCONTROLLER OPTION LIST (Last update: January 2009) Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FASTROM code must be sent in .S19 format. Hex extension cannot be processed. STMicroelectronics references: Device Type/Memory Size/Package (check only one option): ------------------------------------------------------------------------------------ FASTROM:| 4K | 8K | ------------------------------------------------------------------------------------ SO24: | [ ] ST72P60E1M1 | [ ] ST72P60E2M1| QFN40: | [ ] ST72P60K1U1 | [ ] ST72P60K2U1| Conditioning (check only one option): Packaged Product ------------------------------------------------------------------------------------ [ ] Tape & Reel (SO package only) [ ] Tube Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _" Authorized characters are letters, digits, '.', '-', '/' and spaces only. For marking, one line is possible with a maximum of 13 characters. Watchdog Selection: [ ] Software activation[ ] Hardware activation Halt when Watchdog on:[ ] Reset [ ] No reset LVD Reset * [ ] Disabled* [ ] Enabled* Oscillator Selection: [ ] 24 MHz. [ ] 12 MHz. Readout Protection: [ ] Disabled [ ] Enabled Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please download the latest version of this option list from: http://www.st.com/ 134/139

ST7260xx Known limitations 19 Known limitations 19.1 PA2 limitation with OCMP1 enabled Description This limitation affects only Rev B Flash devices (with Internal Sales Type 72F60xxxxx$x7); it has been corrected in Rev W Flash devices (with Internal Sales Type 72F60xxxxx$x9). Refer to Figure69 on page137. When Output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in the TCR2 register, pin PA2 is also affected. In particular, the PA2 pin is forced to be floating even if port configuration (PADDR+PADR) has set it as output low. However, it can be still used as an input. 19.2 Unexpected reset fetch If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET vector address to the CPU. Workaround To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 19.3 SCI wrong break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: ● 20 bits instead of 10 bits if M=0 ● 22 bits instead of 11 bits if M=1 In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected. Occurrence The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (f =8 MHz and SCIBRR=0xC9), the wrong break duration CPU occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts. 135/139

Known limitations ST7260xx The exact sequence is: ● Disable interrupts ● Reset and Set TE (IDLE request) ● Set and Reset SBK (Break Request) ● Re-enable interrupts 136/139

ST7260xx Device marking 20 Device marking The silicon revision can be identified either by Rev letter or obtained via a trace code. Follow the procedure below: 1. Identify the silicon revision letter from either the device package or the box label. For example, “B”, etc. Refer to Figure69. 2. If the revision letter is not present, obtain the silicon revision by contacting your local ST office with the trace code information printed on either the box label or the device package. Figure 69. Identifying silicon revision from device marking and box label Silicon Rev Trace code MicroelectronicsBMTTTxxxroYuxxaxtaxxxcaPlxxkxrel Exxxk Q xxcxIDtxxioxynxxxdxxxegxxxxxxxxxxxxXXSXxxxxxxXxxXTXxxxXxX7xxxxXXXxxxxxxxXxXxXxxxxXXxxxxxXXXXxxxxxxxXxXXxXxxxxXxXxxxxX xXxxxxxxxx $XXxxxxxxxxXXxxx7xxXxXBXXX Silicon Rev T S Device package example Example box label 137/139

Revision history ST7260xx 21 Revision history T able 81. Document revision history Date Revision Changes 13-Feb-2006 1 Initial release. 18-Oct-2006 2 Added known limitations section Added caution in Section7.1 on page 25 Added reference to watchdog reset pulse t in Section12.3 on DOG page 44 Removed EMC protective circuitry in Figure65 on page127 (device 05-Feb-2009 3 works correctly without these components) Modified notes below Table76: Package thermal characteristics on page130 Replaced soldering information with ECOPACK reference in Section17 on page 129 138/139

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