ST6208C ST6209C ST6210C ST6220C 8-bit MCUs with A/D converter, two timers, oscillator safeguard & safe reset ■ Memories – 1K, 2K or 4K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out ) protection s ( – 64 bytes RAM t c ■ Clock, Reset and Supply Management PDIP20 u d – Enhanced reset system o – Low Voltage Detector (LVD) for Safe Reset r P – Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator e (LFAO) t e SO20 – Oscillator Safeguard (OSG) l o – 2 Power Saving Modes: Wait and Stop s ■ Interrupt Management b O – 4 interrupt vectors plus NMI and RESET SSOP20 – 12 external interrupt lines (on 2 vectors) - ■ 12 I/O Ports s ) – 12 multifunctional bidirectional I/O (lines t c – 8 alternate function lines u – 4 high sink outputs (20mAd) CDIP20W ■ 2 Timers o r – Configurable watPchdog timer (See Section 11.5 for Ordering Information) – 8-bit timer/cou nter with a 7-bit prescaler e ■ Instruction Set ■ Analog Peetripheral – 8-bit data manipulation – 8-bitl ADC with 4 or 8 input channels (except o – 40 basic instructions on ST6208C) s – 9 addressing modes b O – Bit manipulation ■ Development Tools – Full hardware/software development package Device Summary Features ST6208C ST6209C ST6210C ST6220C Program memory 1K 2K 4K - bytes RAM - bytes 64 Operating Supply 3.0V to 6V Analog Inputs - 4 8 Clock Frequency 8MHz Max Operating -40°C to +125°C Temperature Packages PDIP20/SO20/SSOP20 January 2009 Rev 4 1/104 1

Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9 3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . )11 s 3.1.6 Data ROM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (. . . 13 t 3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c . . . . . 15 u 3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 d 3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o. . . . . . . . . . . . . 15 3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .r . . . . . . . . . . . . . . . 16 P 4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . e. . . . . . . . . . . . . . . . . . . . . 17 t 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e . . . . . . . . . . . . . . . . . . . . . . . . 17 l 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . o. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 s 4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 b O 5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) 5.1.1 Main Oscillator . . . . . . . . . s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ( 5.1.2 Oscillator Safeguard (OtSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 c 5.1.3 Low Frequency Auuxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.4 Register Descridption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 o 5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 r P 5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.1 Inetroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 t 5.3.e2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 l o5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 s 5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 b 5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 O 5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.8 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.9 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.9.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.10 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10.1Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.11 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 104 6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/104 2

Table of Contents 6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . )37 s 7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (. . . 37 t 7.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c . . . . . 37 u 7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 d 7.2.5 Instructions NOT to be used to access Port Data registers (SET, RoES, INC and DEC) 39 7.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .r . . . . . . . . . . . . . . . 39 P 7.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 e 7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t . . . . . . . . . . . . . . . . . . . . . . . 39 e 7.5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . l. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 o s 8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 b 8.1 WATCHDOG TIMER (WDG) . . . . . . . . . . .O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 - 8.1.2 Main Features . . . . . . . . . . .) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 s 8.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ( 8.1.4 Recommendations . c. .t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.5 Low Power Modesu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 d 8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 o 8.1.7 Register rDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 P 8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 e 8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 t 8.2.e2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 l o8.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 s 8.2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 b O 8.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.3.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3/104 3

Table of Contents 9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.1Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.5Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ) 10.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s. 63 ( 10.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t . . . . 63 c 10.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . u. . . . . . . . 63 10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d . . . . . . . . . . 64 o 10.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .r . . . . . . . . . . . . . . . 64 P 10.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 65 10.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . e. . . . . . . . . . . . . . . . . . . . . 66 t 10.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e . . . . . . . . . . . . . . . . . . . . . . . . 66 l 10.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . o. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 s 10.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 b 10.4.4Supply and Clock System . . . . . . . . .O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 - 10.5 CLOCK AND TIMING CHARACTER ISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ) s 10.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ( 10.5.2External Clock Sourcce t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.5.3Crystal and Ceramuic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 d 10.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 o 10.5.5Oscillatorr Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 75 P 10.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 e 10.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 t 10.6e.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 l 10.7o EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 s b 10.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 O 10.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 104 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4/104 1

Table of Contents 11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.3 ECOPACK INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.6.2ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ) 13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s101 ( t 14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c . . . . 103 u 15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d . . . . . . . . . 103 o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 5/104 1

ST6208C/ST6209C/ST6210C/ST6220C 1 INTRODUCTION The ST6208C, 09C, 10C and 20C devices are low mable option bytes of the OTP/EPROM versions cost members of the ST62xx 8-bit HCMOS family in the ROM option list (See Section 11.6 on page of microcontrollers, which is targeted at low to me- 96). dium complexity applications. All ST62xx devices The ST62P08C/P09C/P10C/P20C are the Factory are based on a building block approach: a com- Advanced Service Technique ROM (FASTROM) mon core is surrounded by a number of on-chip versions of ST62T08C, T09C, T10C and T20C peripherals. OTP devices. The ST62E20C is the erasable EPROM version of They offer the same functionality as OTP devices, the ST62T08C, T09C, T10C and T20C devices, but they do not have to be programmed by the which may be used during the development phase ) customer (See Section 11 on page 90). s for the ST62T08C, T09C, T10C and T20C target ( devices, as well as the respective ST6208C, 09C, These compact low-cost devices fecatture a Timer 10C and 20C ROM devices. comprising an 8-bit counter withu a 7-bit program- d mable prescaler, an 8-bit A/D Converter with up to OTP and EPROM devices are functionally identi- o 8 analog inputs (depending on device) and a Dig- cal. OTP devices offer all the advantages of user r ital Watchdog timer, mP aking them well suited for a programmability at low cost, which make them the wide range of auto motive, appliance and industrial ideal choice in a wide range of applications where e applications. frequent code changes, multiple code versions or t e last minute programmability are required. For easyl reference, all parametric data are located o in Sesction 11 on page 90. The ROM based versions offer the same function- b ality, selecting the options defined in the program- O Figure 1. Block Diagram - ) s ( t8-BIT * V A/cD CONVERTER PORT A PA0..PA3 (20mA Sink) PP u d NMI INTERRUPoTS r PORT B PB0..PB7 / Ain* P DATA ROM e P:ROGRAM USER t MEMORY SELECTABLE e ol or (41KK ,B 2yKte s) DATA RAM TIMER TIMER s 64 Bytes b O PC WATCHDOG TIMER STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 8-BIT CORE STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER OSCILLATOR RESET SUPPLY VDDVSS OSCin OSCout RESET * Depending on device. Please refer to I/O Port section. 6/104 4

ST6208C/ST6209C/ST6210C/ST6220C 2 PIN DESCRIPTION Figure 2. 20-Pin Package Pinout VDD 1 20 VSS TIMER 2 19 PA0/20mA Sink OSCin 3 it1 18 PA1/20mA Sink OSCout 4 17 PA2/20mA Sink NMI 5 16 PA3/20mA Sink V 6 15 PB0/Ain* PP RESET 7 14 PB1/Ain* Ain*/PB7 8 it2 13 PB2/Ain* s ) Ain*/PB6 9 it2 12 PB3/Ain* t( c Ain*/PB5 10 11 PB4/Ain* u d itX associatedinterruptvector o * Depending on device. Please refer to I/O Port section. r P Table 1. Device Pin Description e t e Pin n° Pin Name pe Main Functioonl Alternate Function Ty (after Resset) b 1 V S Main power supply O DD 2 TIMER I/O Timer input or -output ) 3 OSCin I Externals clock input or resonator oscillator inverter input ( t 4 OSCout O Rcesonator oscillator inverter output or resistor input for RC oscillator u 5 NMI dI Non maskable interrupt (falling edge sensitive) o Must be held at Vss for normal operation, if a 12.5V level is applied to the pin 6 V r PP P during the reset phase, the device enters EPROM programming mode. 7 RESET e I/O Top priority non maskable interrupt (active low) t 8 PBe7/Ain* I/O Pin B7 (IPU) Analog input l o 9 PB6/Ain* I/O Pin B6 (IPU) Analog input s b 10 PB5/Ain* I/O Pin B5 (IPU) Analog input O 11 PB4/Ain* I/O Pin B4 (IPU) Analog input 12 PB3/Ain* I/O Pin B3 (IPU) Analog input 13 PB2/Ain* I/O Pin B2 (IPU) Analog input 14 PB1/Ain* I/O Pin B1 (IPU) Analog input 15 PB0/Ain* I/O Pin B0 (IPU) Analog input 16 PA3/ 20mA Sink I/O Pin A3 (IPU) 17 PA2/ 20mA Sink I/O Pin A2 (IPU) 18 PA1/ 20mA Sink I/O Pin A1 (IPU) 7/104 5

ST6208C/ST6209C/ST6210C/ST6220C e Main Function Pin n° Pin Name p Alternate Function y (after Reset) T 19 PA0/ 20mA Sink I/O Pin A0 (IPU) 20 V S Ground SS Legend / Abbreviations for Table 1: * Depending on device. Please refer to Section 7 "I/O PORTS" on page 37. I = input, O = output, S = supply, IPU = input with pull-up ) The input with pull-up configuration (reset state) is valid as long as the user software does not chsange it. ( Refer to Section 7 "I/O PORTS" on page 37 for more details on the software configuration ocf tthe I/O ports. u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 8/104 6

ST6208C/ST6209C/ST6210C/ST6220C 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 3.1 MEMORY AND REGISTER MAPS 3.1.1 Introduction Briefly, Program space contains user program code in OTP and user vectors; Data space con- The MCU operates in three separate memory tains user data in RAM and in OTP, and Stack spaces: Program space, Data space, and Stack space accommodates six levels of stack for sub- space. Operation in these three memory spaces is routine and interrupt service routine nesting. described in the following paragraphs. Figure 3. Memory Addressing Diagram ) s ( t c u PROGRAM SPACE DATA SPACdE o 000h 000h r P e RESERVED t e l o s 03Fh b 040h O DATA ROM PROGRAM - WINDOW MEMORY ) 07Fh s (see Figure 4 ( 080h X REGISTER on page10) ct 081h Y REGISTER u 082h V REGISTER d 083h W REGISTER o 084h r P RAM 0BFh e 0C0h HARDWARE e0tFF0h CONTROL l REGISTERS o INTERRUPT & (see Table 2) s RESET VECTORS b 0FFFh 0FFh ACCUMULATOR O 9/104 1

ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) Figure 4. Program Memory Map ST6208C, 09C ST6210C ST6220C 0000h 0000h 0000h RESERVED* 07Fh 080h ) s NOT IMPLEMENTED ( t c u d o NOT IMPLEMENTED r P 07FFh 0800h e RESERVED* t e 087Fh l o 0880h s USER 0AFFh b PROGRAM MEMORY 0B00h O RESERVED* 3872 BYTES 0B9Fh - USER 0BA0h s )PROGRAM MEMORY ( 1824 BYTES USER t c PROGRAM MEMORY u 1024 BYTES d o r 0F9Fh P 0F9Fh 0F9Fh 00FFEAF0hh REeS ERVED* 00FFEAF0hh RESERVED* 00FFEAF0hh RESERVED* 0FF0h INTeEtRRUPT VECTORS 0FF0h INTERRUPT VECTORS 0FF0h INTERRUPT VECTORS 0FF7h l 0FF7h 0FF7h 0FF8ho RESERVED* 0FF8h RESERVED* 0FF8h RESERVED* 0FFsBh 0FFBh 0FFBh b 0FFCh 0FFCh 0FFCh O NMI VECTOR NMI VECTOR NMI VECTOR 0FFDh 0FFDh 0FFDh 0FFEh USER RESET VECTOR 0FFEh USER RESET VECTOR 0FFEh USER RESET VECTOR 0FFFh 0FFFh 0FFFh (*) Reserved areas should be filled with 0FFh 10/104 1

ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) 3.1.2 Program Space such as constants and look-up tables in OTP/ EPROM. Program Space comprises the instructions to be executed, the data required for immediate ad- 3.1.4.1 Data ROM dressing mode instructions, the reserved factory All read-only data is physically stored in program test area and the user vectors. Program Space is memory, which also accommodates the Program addressed via the 12-bit Program Counter register Space. The program memory consequently con- (PC register). Thus, the MCU is capable of ad- tains the program code to be executed, as well as dressing 4K bytes of memory directly. the constants and look-up tables required by the 3.1.3 Readout Protection application. ) The Program Memory in OTP, EPROM or ROM The Data Space locations in which the sdifferent devices can be protected against external readout constants and look-up tables are addres(sed by the t of memory by setting the Readout Protection bit in processor core may be thought ofc as a 64-byte u the option bytes (Section 3.3 on page 16). window through which it is possible to access the d read-only data stored in OTP/EPROM. In the EPROM parts, Readout Protection option o can be desactivated only by U.V. erasure that also 3.1.4.2 Data RAM r P results in the whole EPROM context being erased. The data space in cludes the user RAM area, the e Note: Once the Readout Protection is activated, it accumulator (A), the indirect registers (X), (Y), the t is no longer possible, even for STMicroelectronics, short direct eregisters (V), (W), the I/O port regis- to gain access to the OTP or ROM contents. Re- ters, the lperipheral data and control registers, the o turned parts can therefore not be accepted if the intersrupt option register and the Data ROM Win- Readout Protection bit is set. dobw register (DRWR register). O 3.1.4 Data Space 3.1.5 Stack Space Data Space accommodates all the data necess-ary for processing the user program. This space) com- Stack space consists of six 12-bit registers which s are used to stack subroutine and interrupt return prises the RAM resource, the processo(r core and peripheral registers, as well as rceatd-only data addresses, as well as the current program counter contents. u d o r P e t e l o s b O 11/104 1

ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Reset Address Block Register Name Remarks Label Status 080h X,Y index registers CPU X,Y,V,W xxh R/W to 083h V,W short direct registers 0C0h DRA 1) 2) 3) Port A Data Register 00h R/W I/O Ports 0C1h DRB 1) 2) 3) Port B Data Register 00h R/W ) 0C2h s Reserved (2 Bytes) ( 0C3h t c 0C4h DDRA 2) Port A Direction Register 00hu R/W 0C5h I/O Ports DDRB 2) Port B Direction Register 0d0h R/W o 0C6h r Reserved (2 Bytes) P 0C7h e 0C8h CPU IOR Interrupt Option Register t xxh Write-only e 0C9h ROM DRWR Data ROM Window registoelr xxh Write-only s 0CAh Reservebd (2 Bytes) 0CBh O 0CCh I/O Ports ORA 2) Port A O-pt ion Register 00h R/W 0CDh ORB 2) Port )B Option Register 00h R/W s 0CEh ( t Reserved (2 bytes) 0CFh c u 0D0h ADRd A/D Converter Data Register xxh Read-only ADC 4) 0D1h oADCR A/D Converter Control Register 40h Ro/Wo r P 0D2h PSCR Timer 1 Prescaler Register 7Fh R/W 0D3h Tiem er1 TCR Timer 1 Downcounter Register 0FFh R/W 0D4h t TSCR Timer 1 Status Control Register 00h R/W e l 0D5ho Reserved (3 Bytes) to 0sD7h b O Watchdog 0D8h WDGR Watchdog Register 0FEh R/W Timer 0D9h Reserved (38 Bytes) to 0FEh 0FFh CPU A Accumulator xxh R/W Legend: x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s) in the register. Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always be kept at their reset value. 3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured in input mode (refer to Section 7 "I/O PORTS" on page 37 for more details) 4. Depending on device. See device summary on page 1. 12/104 1

ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) 3.1.6 Data ROM Window 3.1.6.1 Data ROM Window Register (DRWR) The Data read-only memory window is located The DRWR can be addressed like any RAM loca- from address 0040h to address 007Fh in Data tion in the Data Space. space. It allows direct reading of 64 consecutive This register is used to select the 64-byte block of bytes located anywhere in program memory, be- program memory to be read in the Data ROM win- tween address 0000h and 0FFFh. dow (from address 40h to address 7Fh in Data There are 64 blocks of 64 bytes in a 4K device: space). The DRWR register is not cleared on re- set, therefore it must be written to before access- – Block 0 is related to the address range 0000h to ing the Data read-only memory window area for 003Fh. the first time. ) s – Block 1 is related to the address range 0040h to ( 007Fh. t c Address: 0C9h — Write Only and so on... u Reset Value = xxh (undefinedd) All the program memory can therefore be used to o store either instructions or read-only data. The r Data ROM window can be moved in steps of 64 7 P 0 bytes along the program memory by writing the - - DRWR5 DeRWR4 DRWR3 DRWR2 DRWR1 DRWR0 appropriate code in the Data ROM Window Regis- t e ter (DRWR). l o Figure 5. Data ROM Window s Bbits 7:6 = Reserved, must be cleared. PROGRAM O 0000h SPACE 000hDATA SPACE - Bit 5:0 = DRWR[5:0] Data read-only memory Win- ) dow Register Bits. These are the Data read-only s memory Window bits that correspond to the upper ( t bits of the data read-only memory space. c 04u0h Caution: This register is undefined on reset, it is 64-BYTEd DATA ROM write-only, therefore do not read it nor access it us- o rROM 07Fh WINDOW ing Read-Modify-Write instructions (SET, RES, P INC and DEC). e t e l o s b O 0FFFh 0FFh 13/104 1

ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) 3.1.6.2 Data ROM Window memory addressing tion is automatically handled by the ST6 develop- ment tools. In cases where some data (look-up tables for ex- ample) are stored in program memory, reading Please refer to the user manual of the correspod- these data requires the use of the Data ROM win- ing tool. dow mechanism. To do this: 3.1.6.3 Recommendations 1. The DRWR register has to be loaded with the Care is required when handling the DRWR regis- 64-byte block number where the data are located ter as it is write only. For this reason, the DRWR (in program memory). This number also gives the contents should not be changed while executing start address of the block. an interrupt service routine, as the service routine ) 2. Then, the offset address of the byte in the Data cannot save and then restore the registers’s previ- ROM Window (corresponding to the offset in the ous contents. If it is impossible to avoi(d writing to t 64-byte block in program memory) has to be load- the DRWR during the interrupt servcice routine, an u ed in a register (A, X,...). image of the register must be saved in a RAM lo- d cation, and each time the program writes to the When the above two steps are completed, the o DRWR, it must also write to the image register. data can be read. r The image register mPust be written first so that, if To understand how to determine the DRWR and an interrupt occur s between the two instructions, e the content of the register, please refer to the ex- the DRWR is not affected. t ample shown in Figure 6. In any case the calcula- e l o Figure 6. Data ROM Window Memory Addressing s b O DATA SPACE 000h PROGRAM SPACE - 0000h ) s ( t c u d 040h o r OFFSET P 21h e DATA 061h t e 07Fh l o s 0400h b O 64 bytes OFFSET 0421h DATA 10h DRWR 0FFh 07FFh DATA address in Program memory : 421h DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h 64-byte window start address : 10h x 3Fh = 400h Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h 14/104 1

ST6208C/ST6209C/ST6210C/ST6220C 3.2 PROGRAMMING MODES 3.2.1 Program Memory STMicroelectronics (please refer to Section 12 on page 99). EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V pin. The 3.2.2 EPROM Erasing PP programming flow of the ST62T08C,T09C,T10C, The EPROM devices can be erased by exposure T20C and E20C is described in the User Manual of to Ultra Violet light. The characteristics of the MCU the EPROM Programming Board. are such that erasure begins when the memory is exposed to light with a wave lengths shorter than Table 3. ST6208C/09C Program Memory Map approximately 4000Å. It should be noted that sun- Device Address Description light and some types of fluorescent lamps have ) wavelengths in the range 3000-4000Å. s 0000h-0B9Fh Reserved ( 0BA0h-0F9Fh User ROM It is thus recommended that the witndow of the c 0FA0h-0FEFh Reserved MCU packages be covered by anu opaque label to 0FF0h-0FF7h Interrupt Vectors prevent unintentional erasure dproblems when test- 0FF8h-0FFBh Reserved ing the application in such oan environment. 0FFCh-0FFDh NMI Interrupt Vector The recommended erPasrure procedure is exposure 0FFEh-0FFFh Reset Vector to short wave ultraviolet light which have a wave- length 2537Å. Thee integrated dose (i.e. U.V. inten- t sity x exposeure time) for erasure should be a mini- Table 4. ST6210C Program Memory Map mum of l30W-sec/cm2. The erasure time with this o dosage is approximately 30 to 40 minutes using an Device Address Description s ulbtraviolet lamp with 12000µW/cm2 power rating. 0000h-087Fh Reserved O The EPROM device should be placed within 0880h-0F9Fh User ROM 2.5cm (1inch) of the lamp tubes during erasure. 0FA0h-0FEFh Reserved - 0FF0h-0FF7h Interrupt Vector)s s 0FF8h-0FFBh Reserved ( 0FFCh-0FFDh NMI Interrtupt Vector c 0FFEh-0FFFh Rueset Vector d o Table 5. ST6220C Progrram Memory Map P Device Addre ss Description e 0000h-0t07Fh Reserved e 0080h-0F9Fh User ROM l o 0FA0h-0FEFh Reserved s 0FF0h-0FF7h Interrupt Vectors b 0FF8h-0FFBh Reserved O 0FFCh-0FFDh NMI Interrupt Vector 0FFEh-0FFFh Reset Vector Note: OTP/EPROM devices can be programmed with the development tools available from 15/104 1

ST6208C/ST6209C/ST6210C/ST6220C 3.3 OPTION BYTES Each device is available for production in user pro- LSB OPTION BYTE grammable versions (OTP) as well as in factory Bit 7 = PROTECT Readout Protection. coded versions (ROM). OTP devices are shipped This option bit enables or disables external access to customers with a default content (00h), while to the internal program memory. ROM factory coded parts contain the code sup- 0: Program memory not read-out protected plied by the customer. This implies that OTP de- 1: Program memory read-out protected vices have to be configured by the customer using the Option Bytes while the ROM devices are facto- ry-configured. Bit 6 = OSC Oscillator selection. The two option bytes allow the hardware configu- This option bit selects the main oscillator typ)e. ration of the microcontroller to be selected. 0: Quartz crystal, ceramic resonator or exsternal ( The option bytes have no address in the memory clock t c map and can be accessed only in programming 1: RC network u mode (for example using a standard ST6 program- d ming tool). Bit 5 = Reserved, must beo always cleared. In masked ROM devices, the option bytes are r P fixed in hardware by the ROM code (see Section 11.6.2 "ROM VERSION" on page 98). It is there- Bit 4 = Reservede, must be always set. fore impossible to read the option bytes. e t The option bytes can be only programmed once. It Bit 3 = NolMI PULL NMI Pull-Up on/off. is not possible to change the selected options after Thiss option bit enables or disables the internal pull- they have been programmed. upb on the NMI pin. O In order to reach the power consumption value in- 0: Pull-up disabled dicated in Section 10.4, the option byte must -b e 1: Pull-up enabled programmed to its default value. Otherwis)e, an s over-consumption will occur. ( Bit 2 = TIM PULL TIMER Pull-Up on/off. t c This option bit enables or disables the internal pull- u up on the TIMER pin. MSB OPTION BYTE d 0: Pull-up disabled o Bits 15:10 = Reserved, must be always cleared. 1: Pull-up enabled r P Bit 9 = EXTCNTeL External STOP MODE control. Bit 1 = WDACT Hardware or software watchdog. 0: EXTCNTL tmode not available. STOP mode is e This option bit selects the watchdog type. not available with the watchdog active. 1: EXTColNTL mode available. STOP mode is avail- 0: Software (watchdog to be enabled by software) s 1: Hardware (watchdog always enabled) able with the watchdog active by setting NMI pin b to one. O Bit 0 = OSGEN Oscillator Safeguard on/off. This option bit enables or disables the oscillator Bit 8 = LVD Low Voltage Detector on/off. Safeguard (OSG) feature. This option bit enable or disable the Low Voltage 0: Oscillator Safeguard disabled Detector (LVD) feature. 1: Oscillator Safeguard enabled 0: Low Voltage Detector disabled 1: Low Voltage Detector enabled MSB OPTION BYTE LSB OPTION BYTE 15 8 7 0 EXT PRO- NMI TIM WD OSG Reserved LVD OSC Res. Res. CTL TECT PULL PULL ACT EN Default X X X X X X X X X X X X X X X X Value 16/104 1

ST6208C/ST6209C/ST6210C/ST6220C 4 CENTRAL PROCESSING UNIT 4.1 INTRODUCTION tions. The accumulator can be addressed in Data Space as a RAM location at address FFh. Thus The CPU Core of ST6 devices is independent of the the ST6 can manipulate the accumulator just like I/O or Memory configuration. As such, it may be any other register in Data Space. thought of as an independent central processor communicating with on-chip I/O, Memory and Pe- Index Registers (X, Y). These two registers are ripherals via internal address, data, and control used in Indirect addressing mode as pointers to buses. memory locations in Data Space. They can also be accessed in Direct, Short Direct, or Bit Direct addressing modes. They are mapped in) Data 4.2 MAIN FEATURES s Space at addresses 80h (X) and 81h (Y) and can ( be accessed like any other memory lotcation. ■ 40 basic instructions c ■ 9 main addressing modes Short Direct Registers (V, W). uThese two regis- d ters are used in Short Direct addressing mode. ■ Two 8-bit index registers o This means that the data stored in V or W can be ■ Two 8-bit short direct registers accessed with a one-bPyrte instruction (four CPU cy- ■ Low power modes cles). V and W ca n also be accessed using Direct e and Bit Direct addressing modes. They are ■ Maskable hardware interrupts t mapped in De ata Space at addresses 82h (V) and ■ 6-level hardware stack 83h (Wo) land can be accessed like any other mem- ory lsocation. 4.3 CPU REGISTERS b Note: The X and Y registers can also be used as O The ST6 Family CPU core features six registers and Short Direct registers in the same way as V and W. three pairs of flags available to the programm-er. Program Counter (PC). The program counter is a These are described in the following paragr)aphs. 12-bit register which contains the address of the s Accumulator (A). The accumulator (is an 8-bit next instruction to be executed by the core. This t general purpose register used in all carithmetic cal- ROM location may be an opcode, an operand, or culations, logical operations, anud data manipula- the address of an operand. d Figure 7. CPU Registerso r P 7 0 e ACCUMULATOR t e RESET VALUE = xxh SIX LEVEL l STACK o 7 0 s b X INDEX REGISTER O RESET VALUE = xxh 7 0 NORMAL FLAGS CN ZN Y INDEX REGISTER INTERRUPT FLAGS CI ZI RESET VALUE = xxh 7 0 V SHORT INDIRECT NMI FLAGS CNMI ZNMI REGISTER RESET VALUE = xxh 7 0 W SHORT INDIRECT REGISTER RESET VALUE = xxh 11 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh x = Undefined value 17/104 1

ST6208C/ST6209C/ST6210C/ST6220C CPU REGISTERS (Cont’d) The 12-bit length allows the direct addressing of Z : Zero flag 4096 bytes in Program Space. This flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is However, if the program space contains more than cleared. 4096 bytes, the additional memory in program 0: The result of the last operation is different from space can be addressed by using the Program zero ROM Page register. 1: The result of the last operation is zero The PC value is incremented after reading the ad- Switching between the three sets of flags is per- dress of the current instruction. To execute relative formed automatically when an NMI, an interrupt or jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then a RETI instruction occurs. As NMI mode is) auto- matically selected after the reset of the MsCU, the shifted back into the PC. The program counter can ( be changed in the following ways: ST6 core uses the NMI flags first. ct Stack. The ST6 CPU includes a turue LIFO (Last In – JP (Jump) instruction PC = Jump address First Out) hardware stack wdhich eliminates the – CALL instruction PC = Call address need for a stack pointer. Tohe stack consists of six – Relative Branch InstructionPC = PC +/- offset separate 12-bit RAM Plorcations that do not belong to the data space RAM area. When a subroutine – Interrupt PC = Interrupt vector call (or interrupte request) occurs, the contents of – Reset PC = Reset vector each level earte shifted into the next level down, – RET & RETI instructions PC = Pop (stack) while thoel content of the PC is shifted into the first level (the original contents of the sixth stack level – Normal instruction PC = PC + 1 s arbe lost). When a subroutine or interrupt return oc- Flags (C, Z). The ST6 CPU includes three pairs of O curs (RET or RETI instructions), the first level reg- flags (Carry and Zero), each pair being associate d ister is shifted back into the PC and the value of with one of the three normal modes of opera ti-on: each level is popped back into the previous level. Normal mode, Interrupt mode and Non Ma)skable s Interrupt mode. Each pair consists of( a CARRY Figure 8. Stack manipulation t flag and a ZERO flag. One pair (CNc, ZN) is used during Normal operation, anotheru pair is used dur- PROGRAM ing Interrupt mode (CI, ZI), andd a third pair is used COUNTER o in the Non Maskable Interrupt mode (CNMI, ZN- r MI). P The ST6 CPU ues es the pair of flags associated OFRNO RMETURN LEVEL 1 OINNTERRUPT, with the cureretnt mode: as soon as an interrupt (or IONRTERRUPT, LEVEL 2 OSURBROUTINE a Non Mlaskable Interrupt) is generated, the ST6 SUBROUTINE CALL CPU usoes the Interrupt flags (or the NMI flags) in- LEVEL 3 steasd of the Normal flags. When the RETI instruc- tiobn is executed, the previously used set of flags is LEVEL 4 O restored. It should be noted that each flag set can LEVEL 5 only be addressed in its own context (Non Maska- ble Interrupt, Normal Interrupt or Main routine). LEVEL 6 The flags are not cleared during context switching and thus retain their status. Since the accumulator, in common with all other C : Carry flag. data space registers, is not stored in this stack, management of these registers should be per- This bit is set when a carry or a borrow occurs dur- formed within the subroutine. ing arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit Caution: The stack will remain in its “deepest” po- tested in a bit test instruction; it also participates in sition if more than 6 nested calls or interrupts are the rotate left instruction. executed, and consequently the last return ad- 0: No carry has occured dress will be lost. 1: A carry has occured It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. 18/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5 CLOCKS, SUPPLY AND RESET 5.1 CLOCK SYSTEM The main oscillator of the MCU can be driven by Table 6 illustrates various possible oscillator con- any of these clock sources: figurations using an external crystal or ceramic resonator, an external clock input, an external re- – external clock signal sistor (R ), or the lowest cost solution using only NET – external AT-cut parallel-resonant crystal the LFAO. – external ceramic resonator For more details on configuring the clock options, – external RC network (RNET). refer to the Option Bytes section of this docu)ment. s In addition, an on-chip Low Frequency Auxiliary The internal MCU clock frequency (fINT() is divided Oscillator (LFAO) is available as a back-up clock by 12 to drive the Timer, the Watchcdtog timer and system or to reduce power consumption. the A/D converter, by 13 to drive tuhe CPU core and the SPI and by 1 or 3 to drivde the ARTIMER, as An optional Oscillator Safeguard (OSG) filters shown in Figure 9. o spikes from the oscillator lines, and switches to the r LFAO backup oscillator in the event of main oscil- With an 8 MHz oscillaPtor, the fastest CPU cycle is lator failure. It also automatically limits the internal therefore 1.625µs . e clock frequency (fINT) as a function of VDD, in order A CPU cycle tis the smallest unit of time needed to to guarantee correct operation. These functions execute anye operation (for instance, to increment l are illustrated in Figure 10, and Figure 11. the Proogram Counter). An instruction may require s two, four, or five CPU cycles for execution. b O Figure 9. Clock Circuit Block Diagram - ) OSCILLATOsR SAFEGUARD (OSG) ( t c SPI fOSC d u OSG : 13 CORE filtering o r 8-BIT TIMER P 0 MAeIN Oscillator fINT WATCHDOG OeStCILLATOR Divider : 12 1 ol * ADC s b O LFAO OSCOFF BIT : 1 8-BIT ARTIMER * (ADCR REGISTER) : 3 8-BIT ARTIMER OSG ENABLE OPTION BIT (See OPTION BYTE SECTION) * Depending on device. See device summary on page 1. 19/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK SYSTEM (Cont’d) 5.1.1 Main Oscillator Table 6. Oscillator Configurations The oscillator configuration is specified by select- HardwareConfiguration ing the appropriate option in the option bytes (refer to the Option Bytes section of this document). 1) When the CRYSTAL/RESONATOR option is se- on External Clock lected, it must be used with a quartz crystal, a ce- pti O ST6 ramic resonator or an external signal provided on r o OSCin OSCout the OSCin pin. When the RC NETWORK option is at selected, the system clock is generated by an ex- on ternal resistor (the capacitor is implemented inter- es NC ) nally). al/R EXTERNAL ( s The main oscillator can be turned off (when the yst CLOCK ct OSG ENABLED option is selected) by setting the r u C OSCOFF bit of the ADC Control Register (not d available on some devices). This will automatically 1)n Crystal/Reosonator Clock 2) s(LtaFrAt Ot)h.e Low Frequency Auxiliary Oscillator ptio P r ST6 O OSCin OSCout The main oscillator can be turned off by resetting or t e the OSCOFF bit of the A/D Converter Control Reg- at e ister or by resetting the MCU. When the main os- on ol s cillator starts there is a delay made up of the oscil- e s R lsaotfotwr satraer ti-nusptr udcetliaoyn paet raio cdl opcluks f rtehqeu deunrcayt ifoLnF AoOf .th e O rystal/b CL1 CAPALCOIATODRS 3) CL2 Caution: It should be noted that when the RC n-et- C work option is selected, the accuracy of th)e fre- s quency is about 20% so it may not be suitable for RC Network ( some applications (For more detailcs,t please refer 1)n ST6 to the Electrical Characteristics Suection). o OSCin OSCout d pti O o k r r NC P o w e Net RNET t C e R l o s b O 1) LFAO n o pti O ST6 d OSCin OSCout e bl a n E NC G S O Notes: 1. To select the options shown in column 1 of the above table, refer to the Option Byte section. 2.This schematic are given for guidance only and are sub- ject to the schematics given by the crystal or ceramic res- onator manufacturer. 3. For more details, please refer to the Electrical Charac- teristics Section. 20/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK SYSTEM (Cont’d) 5.1.2 Oscillator Safeguard (OSG) imum internal clock frequency, f , is limited to INT f , which is supply voltage dependent. The Oscillator Safeguard (OSG) feature is a OSG means of dramatically improving the operational 5.1.2.2 Management of Supply Voltage integrity of the MCU. It is available when the OSG Variations ENABLED option is selected in the option byte (re- Over-frequency, at a given power supply level, is fer to the Option Bytes section of this document). seen by the OSG as spikes; it therefore filters out The OSG acts as a filter whose cross-over fre- some cycles in order that the internal clock fre- quency is device dependent and provides three quency of the device is kept within the range the basic functions: particular device can stand (depending on V ), DD and below f : the maximum authorised fre)quen- – Filtering spikes on the oscillator lines which OSG s would result in driving the CPU at excessive fre- cy with OSG enabled. ( t quencies 5.1.2.3 LFAO Management c u – Management of the Low Frequency Auxiliary When the OSG is enabled, dthe Low Frequency Oscillator (LFAO), (useable as low cost internal Auxiliary Oscillator can boe used (see Section clock source, backup clock in case of main oscil- 5.1.3). r P lator failure or for low power consumption) e – Automatically limiting the f clock frequency as Note: The OSG should be used wherever possible INT t a function of supply voltage, to ensure correct as it providees maximum security for the applica- operation even if the power supply drops. tion. It slhould be noted however, that it can in- o 5.1.2.1 Spike Filtering creasse power consumption and reduce the maxi- mbum operating frequency to f (see Electrical OSG Spikes on the oscillator lines result in an effectively O Characteristics section). increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over f-re - Caution: Care has to be taken when using the quency for a given power supply voltage). The OSG, as the internal frequency is defined between s a minimum and a maximum value and may vary OSG filters out such spikes (as illustrate(d in Figure 10). In all cases, when the OSG is accttive, the max- depending on both VDD and temperature. For pre- cise timing measurements, it is not recommended u d to use the OSG. o Figure 10. OSG Filterirng Function P f f f f OSC>OSG OSC<OSG e t f e OSC l o s f OSG b O fINT Figure 11. LFAO Oscillator Function MAIN OSCILLATOR MAIN OSCILLATOR STOPS RESTARTS f OSC f LFAO f INT INTERNAL CLOCK DRIVEN BY LFAO 21/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK SYSTEM (Cont’d) 5.1.3 Low Frequency Auxiliary Oscillator The Low Frequency Auxiliary Oscillator is auto- (LFAO) matically switched off as soon as the main oscilla- tor starts. The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. 5.1.4 Register Description Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as ADC CONTROL REGISTER (ADCR) a backup oscillator in case of main oscillator fail- Address: 0D1h — Read/Write ure. Reset value: 0100 0000 (40h) This oscillator is available when the OSG ENA- ) 7 s 0 BLED option is selected in the option byte (refer to ( the Option Bytes section of this document). In this ADCR ADCR ADCR ADCR ADCR OSCc tADCR ADCR 7 6 5 4 3 OFF 1 0 case, it automatically starts one of its periods after u the first missing edge of the main oscillator, what- d Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0] ADC Control ever the reason for the failure (main oscillator de- o fective, no clock circuitry provided, main oscillator RTheegsiset ebri.ts are used toP crontrol the A/D converter (if switched off...). See Figure 11. available on the device) otherwise they are not e User code, normal interrupts, WAIT and STOP in- used. t structions, are processed as normal, at the re- e l duced f frequency. The A/D converter accura- o LFAO cy is decreased, since the internal frequency is be- Bit 2s = OSCOFF Main Oscillator Off. low 1.2 MHz. 0:b Main oscillator enabled O 1: Main oscillator disabled At power on, until the main oscillator starts, the re- set delay counter is driven by the LFAO. If -th e Note: The OSG must be enabled using the OS- main oscillator starts before the 2048 cycle) delay GEN option in the Option Byte, otherwise the OS- s has elapsed, it takes over. COFF setting has no effect. ( t c u d o r P e t e l o s b O 22/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.2 LOW VOLTAGE DETECTOR (LVD) The on-chip Low Voltage Detector is enabled by The LVD Reset circuitry generates a reset when setting a bit in the option bytes (refer to the Option V is below: DD Bytes section of this document). – V when V is rising IT+ DD The LVD allows the device to be used without any – V when V is falling external RESET circuitry. In this case, the RESET IT- DD pin should be left unconnected. The LVD function is illustrated in Figure 12. If the LVD is not used, an external circuit is manda- If the LVD is enabled, the MCU can be in only one tory to ensure correct Power On Reset operation, of two states: see figure in the Reset section. For more details, – Over the input threshold voltage, it is running un- ) please refer to the application note AN669. der full software control s ( The LVD generates a static Reset when the supply – Below the input threshold voltage, itt is in static c voltage is below a reference value. This means safe reset u that it secures the power-up as well as the power- In these conditions, secure odperation is guaran- down keeping the ST6 in reset. o teed without the need for external reset hardware. r The VIT- reference value for a voltage drop is lower During a Low VoltageP Detector Reset, the RESET than the V reference value for power-on in order IT+ pin is held low, th us permitting the MCU to reset to avoid a parasitic reset when the MCU starts run- e other devicest. ning and sinks current on the supply (hysteresis). e l o s Figure 12. Low Voltage Detector Reset b V O DD - V ) hyst s V IT+ ( V t IT- c u d o r P RESET e t e l o s b O 23/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.3 RESET 5.3.1 Introduction The RESET vector fetch phase duration is 2 clock cycles. The MCU can be reset in three ways: ■ A low pulse input on the RESET pin When a reset occurs: ■ Internal Watchdog reset – The stack is cleared ■ Internal Low Voltage Detector (LVD) reset – The PC is loaded with the address of the Reset vector. It is located in program ROM starting at 5.3.2 RESET Sequence address 0FFEh. The basic RESET sequence consists of 3 main A jump to the beginning of the user program must phases: be coded at this address. ) s ■ Internal (watchdog or LVD) or external Reset – The interrupt flag is automatically set, (so that the event t CPU is in Non Maskable Interrupt cmode. This ■ A delay of 2048 clock (fINT) cycles prevents the initialization routinue from being in- d ■ RESET vector fetch terrupted. The initialization routine should there- o The reset delay allows the oscillator to stabilise fore be terminated by ar RETI instruction, in order and ensures that recovery has taken place from to go back to normaPl mode. the Reset state. e t e Figure 13. RESET Sequence l o V s DD b O V IT+ V - IT- ) s ( t c WATCHDOG u RESET d o WATCHDOGUNDERFLOW r P LVD RESET e t e l o s b RESETPIN O INTERNAL RESET RUN RUN RUN RUN RESET RESET RESET 2048 CLOCK CYCLE (fINT) DELAY 24/104 1

ST6208C/ST6209C/ST6210C/ST6220C RESET (Cont’d) 5.3.3 RESET Pin If the RESET pin is grounded while the MCU is in RUN or WAIT modes, processing of the user pro- The RESET pin may be connected to a device on gram is stopped (RUN mode only), the I/O ports the application board in order to reset the MCU if are configured as inputs with pull-up resistors and required. The RESET pin may be pulled low in the main oscillator is restarted. When the level on RUN, WAIT or STOP mode. This input can be the RESET pin then goes high, the initialization se- used to reset the internal state of the MCU and en- quence is executed at the end of the internal delay sure it starts-up correctly. The pin, which is con- period. nected to an internal pull-up, is active low and fea- tures a Schmitt trigger input. A delay (2048 clock If the RESET pin is grounded while the MCU is in cycles) added to the external signal ensures that STOP mode, the oscillator starts up and all t)he I/O even short pulses on the RESET pin are accepted ports are configured as inputs with pull-usp resis- ( as valid, provided VDD has completed its rising tors. When the RESET pin level thcetn goes high, phase and that the oscillator is running correctly the initialization sequence is executed at the end u (normal RUN or WAIT modes). The MCU is kept in of the internal delay period. d the Reset state as long as the RESET pin is held A simple external RESET coircuitry is shown in Fig- low. ure 15. For more detaPilsr, please refer to the appli- cation note AN669. e Figure 14. Reset Block Diagram t e l o s b INTERNAL O RESET f INT VDD - R es RsP)U NTE cycl ct( COU 2048clock u RESET d o RESD1) r P WATCHDOGRESET e t LVDRESET e l o s b1) Resistive ESD protection. O 25/104 1

ST6208C/ST6209C/ST6210C/ST6220C RESET (Cont’d) 5.3.4 Watchdog Reset Figure 16. Reset Processing The MCU provides a Watchdog timer function in order to be able to recover from software hang- ups. If the Watchdog register is not refreshed be- RESET fore an end-of-count condition is reached, a Watchdog reset is generated. 2048 CLOCK CYCLE DELAY After a Watchdog reset, the MCU restarts in the same way as if a Reset was generated by the RE- INTERNAL SET pin. RESET ) s Note: When a watchdog reset occurs, the RESET ( pin is tied low for very short time period, to flag the t c reset phase. This time is not long enough to reset NMI MASK SET u INT LATCH CLEARED external circuits. (IF PRESENTd) o For more details refer to the Watchdog Timer r chapter. P 5.3.5 LVD Reset e SELECT NMI MODE FLAGS Two different RESET sequences caused by the in- e t ternal LVD circuitry can be distinguished: l o ■ Power-On RESET s b PUT FFEh ■ Voltage Drop RESET O ON ADDRESS BUS During an LVD reset, the RESET pin is pulled low when V <V (rising edge) or V <V (fall-ing DD IT+ DD IT- edge). ) s For more details, refer to the LVD chap(ter. YES t IS RE SET STILL c Caution: Do not externally connect directly the PRESENT? u RESET pin to V , this may cdause damage to the DD NO component in case of interonal RESET (Watchdog or LVD). r P LOAD PC Figure 15. Simpele External Reset Circuitry FROM R FEFSEEhT/ FLFOFChATIONS t e l o V V s DD DD b FETCH INSTRUCTION R O RESET C ST62xx Typical: R = 10K C = 10nF R > 4.7 K 26/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.4 INTERRUPTS The ST6 core may be interrupted by four maska- struction to the associated interrupt service rou- ble interrupt sources, in addition to a Non Maska- tine. ble Interrupt (NMI) source. The interrupt process- When an interrupt source generates an interrupt ing flowchart is shown in Figure 18. request, the PC register is loaded with the address Maskable interrupts must be enabled by setting of the interrupt vector, which then causes a Jump the GEN bit in the IOR register. However, even if to the relevant interrupt service routine, thus serv- they are disabled (GEN bit = 0), interrupt events icing the interrupt. are latched and may be processed as soon as the Interrupt are triggered by events either on external GEN bit is set. pins, or from the on-chip peripherals. Several ) Each source is associated with a specific Interrupt events can be ORed on the same interrupst vector. Vector, located in Program space (see Table 8). In On-chip peripherals have flag register(s to deter- t the vector location, the user must write a Jump in- mine which event triggered the intercrupt. u Figure 17. Interrupts Block Diagram d o r VDD P e t NMI LATCH e VECTOR #0 l o s CLEARED BY H/W b AT START OF VECTOR #0 ROUTINE O I/O PORT REGISTER PA0...PA3 “INPUT WITH INTERRUPT” L-A TCH CONFIGURATION ) 0 s VECTOR #1 ( ct ACTL ESATRAERDT BOYF H/W 1 u VECTOR #1 ROUTINE d LES BIT o (IOR REGISTER) r EXIT FROM P STOP/WAIT e t e l o s I/O PORT REGISTER PbB0...PB7 “INPUT WITH INTERRUPT” LATCH VECTOR #2 O CONFIGURATION ESB BIT (IOR REGISTER) CLEARED BY H/W AT START OF VECTOR #2 ROUTINE TMZ BIT VECTOR #3 TIMER ETI BIT (TSCR REGISTER) A/D CONVERTER * EAI BIT VECTOR #4 EOC BIT (ADCR REGISTER) GEN BIT (IOR REGISTER) * Depending on device. See device summary on page 1. 27/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.5 INTERRUPT RULES AND PRIORITY 5.7 NON MASKABLE INTERRUPT MANAGEMENT This interrupt is triggered when a falling edge oc- ■ A Reset can interrupt the NMI and peripheral curs on the NMI pin regardless of the state of the interrupt routines GEN bit in the IOR register. An interrupt request on NMI vector #0 is latched by a flip flop which is ■ The Non Maskable Interrupt request has the automatically reset by the core at the beginning of highest priority and can interrupt any peripheral the NMI service routine. interrupt routine at any time but cannot interrupt another NMI interrupt. 5.8 PERIPHERAL INTERRUPTS ■ No peripheral interrupt can interrupt another. If more than one interrupt request is pending, Different peripheral interrupt flags in the peri)pheral these are processed by the processor core control registers are able to cause an sinterrupt according to their priority level: vector #1 has the ( when they are active if both: t highest priority while vector #4 the lowest. The c priority of each interrupt source is fixed by – The GEN bit of the IOR registeur is set d hardware (see Interrupt Mapping table). – The corresponding enable bit is set in the periph- o eral control register. r P 5.6 INTERRUPTS AND LOW POWER MODES Peripheral interrupts are linked to vectors #3 and #4. Interrupt reqeuests are flagged by a bit in their All interrupts cause the processor to exit from correspondintg control register. This means that a WAIT mode. Only the external and some specific e request cannot be lost, because the flag bit must interrupts from the on-chip peripherals cause the ol be cleared by user software. processor to exit from STOP mode (refer to the s “Exit from STOP“ column in the Interrupt Mapping b O Table). - ) s ( t c u d o r P e t e l o s b O 28/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.9 EXTERNAL INTERRUPTS (I/O Ports) External interrupt vectors can be loaded into the This is due to the vector #2 circuitry.The worka- PC register if the corresponding external interrupt round is to discard this first interrupt request in the occurred and if the GEN bit is set. These interrupts routine (using a flag for example). allow the processor to exit from STOP mode. Masking of One Interrupt by Another on Vector The external interrupt polarity is selected through #2. the IOR register. When two or more port pins (associated with inter- External interrupts are linked to vectors #1 and # rupt vector #2) are configured together as input 2. with interrupt (falling edge sensitive), as long as one pin is stuck at '0', the other pin can never gen- Interrupt requests on vector #1 can be configured ) either as edge or level-sensitive using the LES bit erate an interrupt even if an active edge osccurs at this pin. The same thing occurs when( one pin is in the IOR Register. t stuck at '1' and interrupt vector #2 isc configured as Interrupt requests from vector #2 are always edge rising edge sensitive. u sensitive. The edge polarity can be configured us- d ing the ESB bit in the IOR Register. To avoid this the first pin mo ust input a signal that goes back up to '1' rightr after the falling edge. Oth- In edge-sensitive mode, a latch is set when a edge erwise, in the interrupPt routine for the first pin, de- occurs on the interrupt source line and is cleared activate the “inpeu t with interrupt” mode using the when the associated interrupt routine is started. port control rtegisters (DDR, OR, DR). An active So, an interrupt request can be stored until com- edge on anoether pin can then be latched. l pletion of the currently executing interrupt routine, o I/O port Configuration Spurious Interrupt on before being processed. If several interrupt re- s quests occurs before completion of the current in- bVector #2 O terrupt routine, only the first request is stored. If a pin associated with interrupt vector #2 is in ‘in- put with pull-up’ state, a ‘0’ level is present on the Storing of interrupt requests is not possible in le-vel pin and the ESB bit = 0, when the I/O pin is config- sensitive mode. To be taken into account, t)he low s ured as interrupt with pull-up by writing to the level must be present on the interrupt pin when the ( MCU samples the line after instructiotn execution. DDRx, ORx and DRx register bits, an interrupt is c latched although a falling edge may not have oc- 5.9.1 Notes on using External Iunterrupts curred on the associated pin. d ESB bit Spurious Interrupot on Vector #2 In the opposite case, if the pin is in interrupt with If a pin associated wiPthr interrupt vector #2 is con- pull-up state , a 0 level is present on the pin and figured as interrupt with pull-up, whenever vector the ESB bit =1, when the I/O port is configured as #2 is configured eto be rising edge sensitive (by set- input with pull-up by writing to the DDRx, ORx and ting the ESBe tbit in the IOR register), an interrupt is DRx bits, an interrupt is latched although a rising latched allthough a rising edge may not have oc- edge may not have occurred on the associated o curesd on the associated pin. pin. b O 29/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.10 INTERRUPT HANDLING PROCEDURE The interrupt procedure is very similar to a call pro- Figure 18. Interrupt Processing Flow Chart cedure, in fact the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the INSTRUCTION context and the time at which it occurred. As a re- sult, the user should save all Data space registers which may be used within the interrupt routines. FETCH INSTRUCTION The following list summarizes the interrupt proce- dure: When an interrupt request occurs, the following EXECUTE ) actions are performed by the MCU automatically: INSTRUCTION LOAD PC FsROM INTERRU(PT VECTOR t – The core switches from the normal flags to the c interrupt flags (or the NMI flags). u WAS NO d – sTthaec kP.C contents are stored in the top level of the THE I NAS RTERTUIC?TION o INTERCNLAELA LRA TCH *) r – The normal interrupt lines are inhibited (NMI still YESP active). YES IS TeHE CORE – The internal latch (if any) is cleared. e NtOARLRMEAALD MYO IDN E? MASKABDLISEA IBNLTEERRUPT – The associated interrupt vector is loaded in the PC. l o When an interrupt request occurs, the following s NO actions must be performed by the user software: b ENABLE PUSH THE O MASKABLE INTERRUPTS PC INTO THE STACK – User selected registers have to be saved within the interrupt service routine (normally on a so-ft- ware stack). ) SELECT s NORMAL FLAGS – The source of the interrupt must be d(etermined SELECT t INTERRUPT FLAGS by polling the interrupt flags (if mocre than one source is associated with the saume vector). “POP” d – The RETI (RETurn from Interrupt) instruction THE STACKED PC o must end the interrupt service routine. r P After the RETI instruction is executed, the MCU re- turns to the maine r outine. NO IS THERE AN AN INTERRUPT REQUEST Caution: Wehten a maskable interrupt occurs while AND INTERRUPT MASK? the ST6 lcore is in NORMAL mode and during the o execsution of an “ldi IOR, 00h” instruction (disabling YES abll maskable interrupts): if the interrupt request oc- *) If a latch is present on the interrupt source line O curs during the first 3 cycles of the “ldi” instruction Table 7. Interrupt Response Time (which is a 4-cycle instruction) the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair CI and ZI. Minimum 6 CPU cycles 5.10.1 Interrupt Response Time Maximum 11 CPU cycles This is defined as the time between the moment when the Program Counter is loaded with the in- One CPU cycle is 13 external clock cycles thus 11 terrupt vector and when the program has jump to CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8 the interrupt subroutine and is ready to execute MHz external quartz. the code. It depends on when the interrupt occurs while the core is processing an instruction. 30/104 1

ST6208C/ST6209C/ST6210C/ST6220C 5.11 REGISTER DESCRIPTION INTERRUPT OPTION REGISTER (IOR) 1: Low level sensitive mode is selected for inter- rupt vector #1 Address: 0C8h — Write Only Reset status: 00h Bit 5 = ESB Edge Selection bit. 7 0 0: Falling edge mode on interrupt vector #2 1: Rising edge mode on interrupt vector #2 - LES ESB GEN - - - - Bit 4 = GEN Global Enable Interrupt. Caution: This register is write-only and cannot be 0: Disable all maskable interrupts ) s accessed by single-bit operations (SET, RES, 1: Enable all maskable interrupts ( DEC,...). t Note: When the GEN bit is cleared,c the NMI inter- u rupt is active but cannot be used to exit from STOP d Bit 7 =Reserved, must be cleared. or WAIT modes. o r P Bit 6 = LES Level/Edge Selection bit. Bits 3:0 = Reserve d, must be cleared. e 0: Falling edge sensitive mode is selected for inter- t rupt vector #1 e l o Table 8. Interrupt Mapping s b Vector Source ReOgister Exit Vector Priority Description Flag from number Block Label Address Order - STOP RESET Reset ) N/A N/A yes FFEh-FFFh s Vector #0 NMI Non Maskable (Interrupt N/A N/A yes FFCh-FFDh Highest ct FFAh-FFBh Priority uNOT USED FF8h-FF9h d Vector #1 Port A Eoxt. Interrupt Port A N/A N/A yes FF6h-FF7h Vector #2 Port B r Ext. Interrupt Port B N/A N/A yes FF4h-FF5h P Lowest Vector #3 TIMER Timer underflow TSCR TMZ yes FF2h-FF3h e Priority Vector #4 ADC* End Of Conversion ADCR EOC no FF0h-FF1h t e * Depending on device. See device summary on page 1. l o s b O 31/104 1

ST6208C/ST6209C/ST6210C/ST6220C 6 POWER SAVING MODES 6.1 INTRODUCTION To give a large measure of flexibility to the applica- Figure 19. Power Saving Mode Transitions tion in terms of power consumption, two main pow- er saving modes are implemented in the ST6 (see High Figure 19). In addition, the Low Frequency Auxiliary Oscillator RUN (LFAO) can be used instead of the main oscillator to reduce power consumption in RUN and WAIT LFAO ) modes. s ( After a RESET the normal operating mode is se- WAIT t c lected by default (RUN mode). This mode drives u the device (CPU and embedded peripherals) by d means of a master clock which is based on the o main oscillator frequency. STOP r P From Run mode, the different power saving e Low modes may be selected by calling the specific ST6 t software instruction or for the LFAO by setting the e POWERCONSUMPTION relevant register bit. For more information on the ol LFAO, please refer to the Clock chapter. s b O - ) s ( t c u d o r P e t e l o s b O 32/104 1

ST6208C/ST6209C/ST6210C/ST6220C 6.2 WAIT MODE The MCU goes into WAIT mode as soon as the Figure 20. WAIT Mode Flowchart WAIT instruction is executed. This has the follow- ing effects: OSCILLATOR On – Program execution is stopped, the microcontrol- ler software can be considered as being in a “fro- WAITINSTRUCTION Clock to PERIPHERALS Yes zen” state. Clock to CPU No – RAM contents and peripheral registers are pre- served as long as the power supply voltage is higher than the RAM retention voltage. ) – The oscillator is kept running to provide a clock N s ( to the peripherals; they are still active. t c RESET WAIT mode can be used when the user wants to u reduce the MCU power consumption during idle N d periods, while not losing track of time or the ability o to monitor external events. WAIT mode places the P r Y INTERRUPT MCU in a low power consumption mode by stop- ping the CPU. The active oscillator (main oscillator e t or LFAO) is kept running in order to provide a clock e signal to the peripherals. l o Y OSCILLATOR Restart If the power consumption has to be further re- s duced, the Low Frequency Auxiliary Oscillator b Clock to PERIPHERALS Yes O (LFAO) can be used in place of the main oscillator, Clock to CPU Yes if its operating frequency is lower. If required, th e - LFAO must be switched on before entering W AIT ) mode. s ( Exit from Wait mode t 2048 c CLOCKCYCLE The MCU remains in WAIT modue until one of the DELAY d following events occurs: o – RESET (Watchdog, LrVD or RESET pin) P OSCILLATOR On – A peripheral interrupt (timer, ADC,...), e Clock to PERIPHERALS Yes – An external interrupt (I/O port, NMI) t Clock to CPU Yes e The Program Counter then branches to the start- l ing addoress of the interrupt or RESET service rou- tine.s Refer to Figure 20. b O See also Section 6.4.1. FETCHRESETVECTOR ORSERVICEINTERRUPT 33/104 1

ST6208C/ST6209C/ST6210C/ST6220C 6.3 STOP MODE STOP mode is the lowest power consumption The Program Counter then points to the starting mode of the MCU (see Figure 22). address of the interrupt or RESET service routine (see Figure 21). The MCU goes into STOP mode as soon as the STOP instruction is executed. This has the follow- STOP Mode and Watchdog ing effects: When the Watchdog is active (hardware or soft- – Program execution is stopped, the microcontrol- ware activation), the STOP instruction is disabled ler can be considered as being “frozen”. and a WAIT instruction will be executed in its place unless the EXCTNL option bit is set to 1 in the op- – The contents of RAM and the peripheral regis- tion bytes and a a high level is present on the NMI ters are kept safely as long as the power supply ) voltage is higher than the RAM retention voltage. pin. In this case, the STOP instruction wills be exe- cuted and the Watchdog will be frozen.( – The oscillator is stopped, so peripherals cannot ct work except the those that can be driven by an Figure 21. STOP Mode Timing uOverview external clock. d 204o8 Exit from STOP Mode CLOrCKCYCLE RUN STOP P RUN The MCU remains in STOP mode until one of the DELAY following events occurs: e t – RESET (Watchdog, LVD or RESET pin) e l – A peripheral interrupt (assuming this peripheral SToOP can be driven by an external clock) INSsTRUCTION b – An external interrupt (I/O port, NMI) O In all cases a delay of 2048 clock cycles (f ) is INT- generated to make sure the oscillator has sta rted RESET FETCH properly. s ) OR VECTOR ( INTERRUPT t c u d o r P e t e l o s b O 34/104 1

ST6208C/ST6209C/ST6210C/ST6220C STOP MODE (Cont’d) Figure 22. STOP Mode Flowchart STOPINSTRUCTION ENABLE WATCHDOG DISABLE 1 EXCTNL ) s VALUE 1) ( t c u 0 d LEVEL OSCILLATOoR Off 1 ON Clock to rPERIPHERALS2) No 0 P NMI PIN Clo ck to CPU No e t e l o s b N O OSCILLATOR On RESET Clock to PERIPHERALS Yes - ) N Clock to CPU No s INTERRUPT3) Y ( t c u Y OSCILLATOR Restart d Clock to PERIPHERALS Yes o r Clock to CPU Yes P N Y e RESET t e N ol 2048 CLOCKCYCLE DELAY s INTERRUPT b O OSCILLATOR On Y Clock to PERIPHERALS Yes Clock to CPU Yes FETCHRESETVECTOR ORSERVICEINTERRUPT Notes: 1. EXCTNL is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from STOP mode (such as external interrupt). Refer to the Interrupt Mapping table for more details. 35/104 1

ST6208C/ST6209C/ST6210C/ST6220C 6.4 NOTES RELATED TO WAIT AND STOP MODES 6.4.1 Exit from Wait and Stop Modes as soon as an interrupt occurs. Nevertheless, two cases must be considered: 6.4.1.1 NMI Interrupt – If the interrupt is a normal one, the interrupt rou- It should be noted that when the GEN bit in the tine in which the WAIT or STOP mode was en- IOR register is low (interrupts disabled), the NMI tered will be completed, starting with the interrupt is active but cannot cause a wake up from execution of the instruction which follows the STOP/WAIT modes. STOP or the WAIT instruction, and the MCU is 6.4.1.2 Restart Sequence still in interrupt mode. At the end of this routine When the MCU exits from WAIT or STOP mode, it pending interrupts will be serviced according to should be noted that the restart sequence de- their priority. ) s pends on the original state of the MCU (normal, in- – In the event of a non-maskable interr(upt, the terrupt or non-maskable interrupt mode) prior to non-maskable interrupt service roucttine is proc- entering WAIT or STOP mode, as well as on the essed first, then the routine in wuhich the WAIT or interrupt type. STOP mode was entered widll be completed by o Normal Mode. If the MCU was in the main routine executing the instruction following the STOP or r when the WAIT or STOP instruction was execut- WAIT instruction. ThPe MCU remains in normal in- ed, exit from Stop or Wait mode will occur as soon terrupt mode. e as an interrupt occurs; the related interrupt routine 6.4.2 Recomtmended MCU Configuration is executed and, on completion, the instruction e For lowelst power consumption during RUN or which follows the STOP or WAIT instruction is o WAIT modes, the user software must configure then executed, providing no other interrupts are s pending. thbe MCU as follows: O – Configure unused I/Os as output push-pull low Non Maskable Interrupt Mode. If the STOP or mode WAIT instruction has been executed during exe-cu- tion of the non-maskable interrupt routin)e, the – Place all peripherals in their power down modes s MCU exits from Stop or Wait mode as soon as an before entering STOP mode ( interrupt occurs: the instruction whicth follows the c – Select the Low Frequency Auxiliary Oscillator STOP or WAIT instruction is exuecuted, and the (provided this runs at a lower frequency than the MCU remains in non-maskadble interrupt mode, main oscillator). even if another interrupt haos been generated. r The WAIT and STOP instructions are not execut- Normal Interrupt MoPde. If the MCU was in inter- ed if an enabled interrupt request is pending. rupt mode before the STOP or WAIT instruction e was executed, it exits from STOP or WAIT mode t e l o s b O 36/104 1

ST6208C/ST6209C/ST6210C/ST6220C 7 I/O PORTS 7.1 INTRODUCTION Each I/O port contains up to 8 pins. Each pin can All input lines can be individually connected by be programmed independently as digital input software to the interrupt system by programming (with or without pull-up and interrupt generation), the OR and DR registers accordingly. The inter- digital output (open drain, push-pull) or analog in- rupt trigger modes (falling edge, rising edge and put (when available). low level) can be configured by software for each port as described in the Interrupt section. The I/O pins can be used in either standard or al- ternate function mode. 7.2.2 Analog Inputs ) s Standard I/O mode is used for: Some pins can be configured as analog inputs by ( programming the OR and DR registerts according- – Transfer of data through digital inputs and out- c puts (on specific pins): ly, see Table 9. These analog inpuuts are connect- ed to the on-chip 8-bit Analog dto Digital Converter. – External interrupt generation o Caution: ONLY ONE pin should be programmed Alternate function mode is used for: r as an analog input at Pany time, since by selecting – Alternate signal input/output for the on-chip more than one inp ut simultaneously their pins will e peripherals be effectively shorted. t e The generic I/O block diagram is shown in Figure 7.2.3 Output Modes l 23. o The output configuration is selected by setting the s cobrresponding DDR register bit. In this case, writ- 7.2 FUNCTIONAL DESCRIPTION O ing to the DR register applies this digital value to the I/O pin through the latch. Then, reading the DR Each port is associated with 3 registers located- in register returns the previously stored value. Data space: ) s Two different output modes can be selected by – Data Register (DR) t( software through the OR register: push-pull and c – Data Direction Register (DDR) open-drain. u – Option Register (OR) d DR register value and output pin status: o Each I/O pin may be prorgrammed using the corre- DR Push-pull Open-drain sponding register bits Pin the DDR, DR and OR reg- 0 V V SS SS isters: bit x corresp onding to pin x of the port. Table e 1 V Floating 9 illustrates the various port configurations which DD t can be seleected by user software. l Note: The open drain setting is not a true open o During MCU initialization, all I/O registers are drain. This means it has the same structure as the s cleared and the input mode with pull-up and no in- push-pull setting but the P-buffer is deactivated. b O terrupt generation is selected for all the pins, thus To avoid damaging the device, please respect the avoiding pin conflicts. V absolute maximum rating described in the OUT 7.2.1 Digital Input Modes Electrical Characteristics section. The input configuration is selected by clearing the 7.2.4 Alternate Functions corresponding DDR register bit. When an on-chip peripheral is configured to use a In this case, reading the DR register returns the pin, the alternate function (timer input/output...) is digital value applied to the external I/O pin. not systematically selected but has to be config- ured through the DDR, OR and DR registers. Re- Different input modes can be selected by software fer to the chapter describing the peripheral for through the DR and OR registers, see Table 9. more details. External Interrupt Function 37/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) Figure 23. I/O Port Block Diagram RESET PULL-UP V DD V DD DATA V DD DIRECTION REGISTER ) s ( t cPxx I/O Pin u DATA d REGISTER o r ST6 P INTERNAL BUS e N-tBUFFER e OPTION P-BUFFElR REGISTER o CLAMPING s DIODES b O - ) s ( CMOS t c SCHMITT TO INTERRUPT u d TRIGGER * o TO ADC r P * Depending on device. See device summary on page 1. e t e Table 9.l I/O Port Configurations o s DDR OR DR Mode Option b O 0 0 0 Input With pull-up, no interrupt 0 0 1 Input No pull-up, no interrupt 0 1 0 Input With pull-up and with interrupt 0 1 1 Input Analog input (when available) 1 0 x Output Open-drain output (20mA sink when available) 1 1 x Output Push-pull output (20mA sink when available) Note: x = Don’t care 38/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) 7.2.5 Instructions NOT to be used to access 2. Handling Unused Port Bits Port Data registers (SET, RES, INC and DEC) On ports that have less than 8 external pins con- DO NOT USE READ-MODIFY-WRITE INSTRUC- nected: TIONS (SET, RES, INC and DEC) ON PORT – Leave the unbonded pins in reset state and do DATA REGISTERS IF ANY PIN OF THE PORT IS not change their configuration. CONFIGURED IN INPUT MODE. – Do not use instructions that act on a whole port These instructions make an implicit read and write register (INC, DEC, or read operations). Unavail- back of the entire register. In port input mode, able bits must be masked by software (AND in- however, the data register reads from the input struction). Thus, when a read operation pins directly, and not from the data register latch- ) performed on an incomplete port is followsed by a es. Since data register information in input mode is comparison, use a mask. ( used to set the characteristics of the input pin (in- ct terrupt, pull-up, analog input), these may be unin- 3. High Impedance Input u tentionally reprogrammed depending on the state On any CMOS device, it is ndot recommended to of the input pins. connect high impedance ono input pins. The choice r As a general rule, it is better to only use single bit of these impedance hPas to be done with respect to instructions on data registers when the whole (8- the maximum lea kage current defined in the da- e bit) port is in output mode. In the case of inputs or tasheet. The risk is to be close or out of specifica- t of mixed inputs and outputs, it is advisable to keep tion on the ienput levels applied to the device. l a copy of the data register in RAM. Single bit in- o 7.3 LOW POWER MODES structions may then be used on the RAM copy, af- s ter which the whole copy register can be written to Tbhe WAIT and STOP instructions allow the O the port data register: ST62xx to be used in situations where low power consumption is needed. The lowest power con- SET bit, datacopy - LD a, datacopy ) sumption is achieved by configuring I/Os in output LD DRA, a s push-pull low mode. ( t 7.2.6 Recommendations c Mode Description u 1. Safe I/O State Switching Sdequence No effect on I/O ports. External interrupts WAIT Switching the I/O ports froom one state to another cause the device to exit from WAIT mode. should be done in a sPeqruence which ensures that STOP No effect on I/O ports. External interrupts no unwanted side effects can occur. The recom- cause the device to exit from STOP mode. mended safe traensitions are illustrated in Figure 24 The Interrueptt Pull-up to Input Analog transition 7.4 INTERRUPTS (and vicel-vesra) is potentially risky and should be o The external interrupt event generates an interrupt avoisded when changing the I/O operating mode. if the corresponding configuration is selected with b DDR, DR and OR registers (see Table 9) and the O GEN-bit in the IOR register is set. Figure 24. Diagram showing Safe I/O State Transitions Interrupt Input pull-up 010* 011 Analog Input pull-up (Reset 000 001 Input state) Output Output 100 101 Open Drain Open Drain Output Output 110 111 Push-pull Push-pull Note *. xxx = DDR, OR, DR Bits respectively 39/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) Table 10. I/O Port Option Selections MODE AVAILABLE ON(1) SCHEMATIC V DD V Input DD PA0-PA3 PB0-PB7 Data in DDRx ORx DRx ) s 0 0 1 Interrupt ( t c Reset state VDD u ut Input VDD d Digital Inp DDRxwithO Rpuxll up DRx PPAB00--PPAB37 e P r o Data in 0 0 0 t Interrupt e l o Input s VDD V with pull up bDD with interrupt PA0-PA3 O PB0-PB7 - Data in DDRx ORx DRx ) s 0 1 0 ( Interrupt t c u PB0-PB3 nput Analog Input o d(ST6210C/20C VDD og I P r oPnBl4y)-PB7 ADC nal DDRx ORex DRx (All devices, A 0 e t1 1 except ST6208C) l Oopen drain output (5mA) PB0-PB7 s V DD P-buffer disconnected b O Data out Open drain output (20 mA) PA0-PA3 ut DDRx ORx DRx p ut 1 0 0/1 o al Push-pull output (5mA) PB0-PB7 git Di V DD Push-pull output (20 mA) PA0-PA3 Data out DDRx ORx DRx 1 1 0/1 Note 1. Provided the correct configuration has been selected (see Table 9). 40/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) 7.5 REGISTER DESCRIPTION Bits 7:0 = DD[7:0] Data direction register bits. The DDR register gives the input/output direction DATA REGISTER (DR) configuration of the pins. Each bit is set and Port x Data Register cleared by software. DRx with x = A or B. 0: Input mode Address DRA: 0C0h - Read/Write 1: Output mode Address DRB: 0C1h - Read/Write Reset Value: 0000 0000 (00h) OPTION REGISTER (OR) ) s 7 0 Port x Option Register ( t ORx with x = A or B. c D7 D6 D5 D4 D3 D2 D1 D0 u Address ORA: 0CCh - Read/Wd rite Address ORB: 0CDh - Reaod/Write Bits 7:0 = D[7:0] Data register bits. Reset Value: 0000 00P00r (00h) Reading the DR register returns either the DR reg- 7 e 0 ister latch content (pin configured as output) or the t digital value applied to the I/O pin (pin configured e O7 Ol6 O5 O4 O3 O2 O1 O0 as input). o s Caution: In input mode, modifying this register will b modify the I/O port configuration (see Table 9). O Bits 7:0 = O[7:0] Option register bits. Do not use the Single bit instructions on I/O po rt The OR register allows to distinguish in output - data registers. See (Section 7.2.5). mode if the push-pull or open drain configuration is ) s selected. ( DATA DIRECTION REGISTER (DDcRt) Output mode: u 0: Open drain output(with P-Buffer deactivated) Port x Data Direction Register d 1: Push-pull Output DDRx with x = A or B. o Input mode: See Table 9. Address DDRA: 0C4h -r Read/Write Address DDRB: 0C5hP - Read/Write Each bit is set and cleared by software. Reset Value: 00e00 0000 (00h) Caution: Modifying this register, will also modify t the I/O port configuration in input mode. (see Ta- e 7 l 0 ble 9). o s bDD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O Table 11. I/O Port Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label Reset Value 0 0 0 0 0 0 0 0 of all I/O port registers 0C0h DRA MSB LSB 0C1h DRB 0C4h DDRA MSB LSB 0C5h DDRB 0CCh ORA MSB LSB 0CDh ORB 41/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8 ON-CHIP PERIPHERALS 8.1 WATCHDOG TIMER (WDG) 8.1.1 Introduction 8.1.2 Main Features The Watchdog timer is used to detect the occur- ■ Programmable timer (64 steps of 3072 clock rence of a software fault, usually generated by ex- cycles) ternal interference or by unforeseen logical condi- ■ Software reset tions, which causes the application program to ■ Reset (if watchdog activated) when the SR bit abandon its normal sequence. The Watchdog cir- reaches zero cuit generates an MCU reset on expiry of a pro- ) grammed time period, unless the program refresh- ■ Hardware or software watchdog asctivation es the counter’s contents before the SR bit be- selectable by option bit (Refer tot (the option bytes section) c comes cleared. u d Figure 25. Watchdog Block Diagram o r P e t e l RESET o s b O - ) WATCHDOG sREGISTER (WDGR) ( t c T0 T1 T2 T3 T4 T5 SR C u bit 7 d bit 0 7-BIT DOWNCOUNTER o r P e t e ol fint /12 CLOCK DIVIDER s ÷ 256 b O 42/104 1

ST6208C/ST6209C/ST6210C/ST6220C WATCHDOG TIMER (Cont’d) 8.1.3 Functional Description mode availability (refer to the description of the WDACT and EXTCNTL bits on the Option Bytes). The watchdog activation is selected through an option in the option bytes: When STOP mode is not required, hardware acti- vation without EXTERNAL STOP MODE CON- – HARDWARE Watchdog option TROL should be preferred, as it provides maxi- After reset, the watchdog is permanently active, mum security, especially during power-on. the C bit in the WDGR is forced high and the user When STOP mode is required, hardware activa- can not change it. However, this bit can be read tion and EXTERNAL STOP MODE CONTROL equally as 0 or 1. should be chosen. NMI should be high by default, – SOFTWARE Watchdog option to allow STOP mode to be entered when the) MCU s After reset, the watchdog is deactivated. The func- is idle. ( t tion is activated by setting C bit in the WDGR reg- The NMI pin can be connected to acn I/O line (see ister. Once activated, it cannot be deactivated. Figure 26) to allow its state to be cuontrolled by soft- The counter value stored in the WDGR register ware. The I/O line can then bde used to keep NMI (bits SR:T0), is decremented every 3072 clock cy- low while Watchdog proteoction is required, or to r cles. The length of the timeout period can be pro- avoid noise or keyP bounce. When no more grammed by the user in 64 steps of 3072 clock cy- processing is requ ired, the I/O line is released and e cles. the device placed in STOP mode for lowest power t If the watchdog is activated (by setting the C bit) consumptioen. l and when the SR bit is cleared, the watchdog initi- o ates a reset cycle pulling the reset pin low for typi- Figusre 26. A typical circuit making use of the EbXERNAL STOP MODE CONTROL feature cally 500ns. O The application program must write in the WDGR register at regular intervals during normal ope-ra- tion to prevent an MCU reset. The value) to be s SWITCH stored in the WDGR register must b(e between FEh and 02h (see Table 12). To runc tthe watchdog NMI function the following conditions umust be true: d – The C bit is set (watchdog activated) o I/O – The SR bit is set to prrevent generating an imme- P diate reset e – The T[5:0] bits contain the number of decre- t ments whiech represent the time delay before the watchdlog produces a reset. o s VR02002 Tbable 12. Watchdog Timing (fOSC = 8 MHz) O 2. When software activation is selected (WDACT WDGR Register WDG timeout period initial value (ms) bit in Option byte) and the Watchdog is not activat- ed, the downcounter may be used as a simple 7- Max. FEh 24.576 bit timer (remember that the bits are in reverse or- Min. 02h 0.384 der). 8.1.3.1 Software Reset The software activation option should be chosen The SR bit can be used to generate a software re- only when the Watchdog counter is to be used as set by clearing the SR bit while the C bit is set. a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions 8.1.4 Recommendations should be executed: 1. The Watchdog plays an important supporting jrr 0, WDGR, #+3 ; If C=0,jump to next role in the high noise immunity of ST62xx devices, ldi WDGR, 0FDH ; SR=0 -> reset and should be used wherever possible. Watchdog related options should be selected on the basis of next : a trade-off between application security and STOP 43/104 1

ST6208C/ST6209C/ST6210C/ST6220C WATCHDOG TIMER (Cont’d) These instructions test the C bit and reset the Note: This note applies only when the watchdog is MCU (i.e. disable the Watchdog) if the bit is set used as a standard timer. It is recommended to (i.e. if the Watchdog is active), thus disabling the read the counter twice, as it may sometimes return Watchdog. an invalid value if the read is performed while the counter is decremented (counter bits in transient For more information on the use of the watchdog, state). To validate the return value, both values please read application note AN1015. read must be equal. The counter decrements eve- ry 384µs at 8MHz f . OSC 8.1.5 Low Power Modes ) s ( Mode Description t c WAIT No effect on Watchdog. u d STOP Behaviour depends on the EXTCNTL option in the Option bytes: o 1. Watchdog disabled: r P The MCU will enter Stop mode if a STOP instruction is executed. 2. Watchdog enabled and EXTCNTL option disabled: e t If a STOP instruction is encountered, it is interpreted as a WAIT.e l 3. Watchdog and EXTCNTL option enabled: o s If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the b STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU en- O ters STOP mode. When the MCU exits STOP mode (i.e. whe-n an interrupt is generated), the Watchdog resumes its activity. ) s 8.1.6 Interrupts ( t None. c u d o r P e t e l o s b O 44/104 1

ST6208C/ST6209C/ST6210C/ST6220C WATCHDOG TIMER (Cont’d) 8.1.7 Register Description Bit 0 = C Watchdog Control bit. If the hardware option is selected (WDACT bit in WATCHDOG REGISTER (WDGR) Option byte), this bit is forced high and cannot be Address: 0D8h - Read/Write changed by the user (the Watchdog is always ac- Reset Value: 1111 1110 (FEh) tive). When the software option is selected (WDACT bit in Option byte), the Watchdog func- 7 0 tion is activated by setting the C bit, and cannot then be deactivated (except by resetting the T0 T1 T2 T3 T4 T5 SR C MCU). When C is kept cleared the counter can be) used Bits 7:2 = T[5:0] Downcounter bits as a 7-bit timer. s Caution: These bits are reversed and shifted with 0: Watchdog deactivated t( respect to the physical counter: bit-7 (T0) is the 1: Watchdog activated c u LSB of the Watchdog downcounter and bit-2 (T5) d is the MSB. o Bit 1 = SR: Software Reset bit r P Software can generate a reset by clearing this bit while the C bit is set. When C = 0 (Watchdog de- e activated) the SR bit is the MSB of the 7-bit timer. t e 0: Generate (write) l o 1: No software reset generated, MSB of 7-bit timer s b O - ) s ( t c u d o r P e t e l o s b O 45/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8.2 8-BIT TIMER 8.2.1 Introduction 8.2.2 Main Features The 8-Bit Timer on-chip peripheral is a free run- ■ Time-out downcounting mode with up to 15-bit ning downcounter based on an 8-bit downcounter accuracy with a 7-bit programmable prescaler, giving a max- ■ External counter clock source (valid also in imum count of 215. The peripheral may be config- STOP mode) ured in three different operating modes. ■ Interrupt capability on counter underflow ■ Output signal generation ■ External pulse length measurement ■ Event counter s ) ( The timer can be used in WAIT and StTOP modes c to wake up the MCU. u d Figure 27. Timer Block Diagram o r P TIMER e PIN t e l 7 8-BITDOoWN COUNTER 0 fINT/12 b s fCOUNTER TCR TCR7 TCR6 TCOR5 TCR4 TCR3 TCR2 TCR1 TCR0 REGISTER - ) s f EXT ( LATCH t c 7 0 u d TSCR TMZ ETI TOUT DOUT PSI PS2 PS1 PS0 o REGISTER r P e t e ol INTERRUPT s b O fPRESCALER R E L O A D 7 PSCR REGISTER 0 PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0 /1 /128 /64 /32 /16 /8 /4 /2 PROGRAMMABLEPRESCALER 46/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.3 Counter/Prescaler Description caler and the counter run at the rate of the select- ed clock source. Prescaler Counter and Prescaler Initialization The prescaler input can be the internal frequency f divided by 12 or an external clock applied to After RESET, the counter and the prescaler are in- INT the TIMER pin. The prescaler decrements on the itialized to 0FFh and 7Fh respectively. rising edge, depending on the division factor pro- The 7-bit prescaler can be initialized to 7Fh by grammed by the PS[2:0] bits in the TSCR register. clearing the PSI bit. Direct write access to the The state of the 7-bit prescaler can be read in the prescaler is also possible when PSI =1. Then, any PSCR register. value between 0 and 7Fh can be loaded into) it. s When the prescaler reaches 0, it is automatically The 8-bit counter can be initialized sep(arately by t reloaded with 7Fh. writing to the TCR register. c u 8.2.3.1 8-bit Counting and Interrupt Capability Counter d on Counter Underflow o The free running 8-bit downcounter is fed by the Whatever the division fractor defined for the pres- output of the programmable prescaler, and is dec- P caler, the Timer Counter works as an 8-bit down- remented on every rising edge of the fCOUNTER counter. The inpeut clock frequency is user selecta- clock signal coming from the prescaler. ble using the tPS[2:0] bits. e It is possible to read or write the contents of the counter on the fly, by reading or writing the timer When tohle downcounter decrements to zero, the counter register (TCR). TMZs (Timer Zero) bit in the TSCR is set. If the ETI (Ebnable Timer Interrupt) bit in the TSCR is also When the downcounter reaches 0, it is automati- O set, an interrupt request is generated. cally reloaded with the value 0FFh. - The Timer interrupt can be used to exit the MCU Counter Clock and Prescaler ) from WAIT or STOP mode. s The counter clock frequency is given by(: The TCR can be written at any time by software to t f = f / 2cPS[2:0] define a time period ending with an underflow COUNTER PRESCALERu event, and therefore manage delay or timer func- where fPRESCALER can be: d tions. o – fINT/12 r TMZ is set when the downcounter reaches zero; – f (input on TIMP ER pin) however, it may also be set by writing 00h in the EXT TCR register or by setting bit 7 of the TSCR register. – f /12 gateed by TIMER pin INT t The TMZ bit must be cleared by user software The timer ineput clock feeds the 7-bit programma- ble preoslcaler. The prescaler output can be pro- when servicing the timer interrupt to avoid unde- sired interrupts when leaving the interrupt service gramsmed by selecting one of the 8 available pres- routine. cabler taps using the PS[2:0] bits in the Status/Con- O trol Register (TSCR). Thus the division factor of Note: A write to the TCR register will predominate the prescaler can be set to 2n (where n equals 0, to over the 8-bit counter decrement to 00h function, 7). See Figure 27. i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take prece- The clock input is enabled by the PSI (Prescaler dence, and the TMZ bit is not set until the 8-bit Initialize) bit in the TSCR register. When PSI is re- counter underflows again. set, the counter is frozen and the prescaler is load- ed with the value 7Fh. When PSI is set, the pres- 47/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.4 Functional Description the DDR, OR and DR registers. For more details, please refer to the I/O Ports section. There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR Figure 28. f Clock in Gated Mode register). These three modes correspond to the TIMER two clocks which can be connected to the 7-bit f /12 prescaler (f ÷ 12 or TIMER pin signal), and to INT INT the output mode. f PRESCALER The settings for the different operating modes are TIMER summarized Table 13. fEXT ) s Table 13. Timer Operating Modes ( t c TOUT DOUT Timer Application Figure 29. Gated Mode Operatiuon Function d COUNTER VALUE o Event Counter External counter clock 0 0 (input) source xx1 VALUE 1 P r Gated input External Pulse length e 0 1 (input) measurement t e Output “0” l 1 0 (output) Output signal xx2o VALUE 2 s Output “1” generation b 1 1 (output) O TIMER PIN - PULSE LENGTH 8.2.4.1 Gated Mode ) s 1 (TOUT = “0”, DOUT = “1”) ( t c In this mode, the prescaler is decremented by the u Timer clock input, but only when the signal on the d TIMER pin is held high (f /12 gated by TIMER IoNT pin). See Figure 28 andr Figure 29. TIMER CLOCK P This mode is selected by clearing the TOUT bit in the TSCR regiseter (i.e. as input) and setting the DOUT bit. e t Note: Ionl this mode, if the TIMER pin is multi- plexsed, the corresponding port control bits have to bbe set in input with pull-up configuration through O 48/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.4.2 Event Counter Mode bit transition is used to latch the DOUT bit in the TSCR and, if the TOUT bit is set, DOUT is trans- (TOUT = “0”, DOUT = “0”) ferred to the TIMER pin. This operating mode allows In this mode, the TIMER pin is the input clock of external signal generation on the TIMER pin. See the Timer prescaler which is decremented on eve- Figure 33. ry rising edge of the input clock (allowing event This mode is selected by setting the TOUT bit in count). See Figure 30 and Figure 31. the TSCR register (i.e. as output) and setting the This mode is selected by clearing the TOUT bit in DOUT bit to output a high level or clearing the the TSCR register (i.e. as input) and clearing the DOUT bit to output a low level. DOUT bit. Note: As soon as the TOUT bit is set, The) timer s Note: In this mode, if the TIMER pin is multi- pin is configured as output push-pull re(gardless of plexed, the corresponding port control bits have to the corresponding I/O port control recgtisters setting be set in input with pull-up configuration. (if the TIMER pin is multiplexed).u d Figure 30. fTIMER Clock in Event Counter Mode Figure 32. Output Mode Coontrol r P e f TIMER PRESCALER TIMER t e l o s LATCH b O Figure 31. Event Counter Mode Operation - TMZ TOUT DOUT COUNTER VALUE ) s VALUE 1 ( XX1 t c Figure 33. Output Mode Operation u d o Counter r XX2 P VALUE 2 FFh e TIMER PIN t e l o s b O At each zero event TIMER PIN DOUT has to be copied to the TIMER 8.2.4.3 Output Mode pin 1 (TOUT = “1”, DOUT = “data out”) In Output mode, the TIMER pin is connected to the DOUT latch, hence the Timer prescaler is clocked by the prescaler clock input (f /12). See Figure 32. INT The user can select the prescaler division ratio us- ing the PS[2:0] bits in the TSCR register. When TCR 1st downcount: decrements to zero, it sets the TMZ bit in the TSCR. Default output value is 0 The TMZ bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user. The low-to-high TMZ 49/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.5 Low Power Modes 8.2.6 Interrupts Mode Description Exit Exit No effect on timer. Interrupt Event Event Enable from from WAIT Timer interrupt events cause the device to Flag Bit Wait Stop exit from WAIT mode. Timer Zero Timer registers are frozen except in Event Event TMZ ETI Yes Yes STOP Counter mode (with external clock on TIM- ER pin). ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 50/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.7 Register Description ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. PRESCALER COUNTER REGISTER (PSCR) 0: Interrupt disabled (reset state) Address: 0D2h - Read/Write 1: Interrupt enabled Reset Value: 0111 1111 (7Fh) 7 0 Bit 5 = TOUT Timer Output Control. When low, this bit selects the input mode for the PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR TIMER pin. When high the output mode is select- 7 6 5 4 3 2 1 0 ed. Bit 7 = PSCR7: Not used, always read as “0”. 0: Input mode (reset state) s ) 1: Output mode, the TIMER pin is con(figured as Bits 6:0 = PSCR[6:0] Prescaler LSB. push-pull output ct u d TIMER COUNTER REGISTER (TCR) Bit 4 = DOUT Data Output.o Address: 0D3h - Read / Write Data sent to the timer ourtput when TMZ is set high P Reset Value: 1111 1111 (FFh) (output mode only). Input mode selection (input mode only). e 7 0 t e Bit 3 = PlSI: Prescaler Initialize bit. TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 o Useds to initialize the prescaler and inhibit its count- inbg. When PSI=“0” the prescaler is set to 7Fh and Bits 7:0 = TCR[7:0] Timer counter bits. O the counter is inhibited. When PSI=“1” the prescal- er is enabled to count downwards. As long as - PSE=“1” both counter and prescaler are not run- ) TIMER STATUS CONTROL REGISTER (sTSCR) ning Address: 0D4h - Read/Write ( 0: Counting disabled t Reset Value: 0000 0000 (00h) c 1: Counting enabled u 7 d 0 o Bits 1:0 = PS[2:0] Prescaler Mux. Select. r TMZ ETI TOUT DOPUT PSI PS2 PS1 PS0 These bits select the division ratio of the prescaler register. e Bit 7 = TMZ Ttimer Zero bit. Table 14. Prescaler Division Factors e A low-to-high transition indicates that the timer l count reogister has underflowed. It means that the PS2 PS1 PS0 Divided by TCRs value has changed from 00h to FFh. 0 0 0 1 b This bit must be cleared by user software. 0 0 1 2 O 0: Counter has not underflowed 0 1 0 4 1: Counter underflow occurred 0 1 1 8 1 0 0 16 1 0 1 32 Bit 6 = ETI Enable Timer Interrupt. 1 1 0 64 When set, enables the timer interrupt request. If 1 1 1 128 Table 15. 8-Bit Timer Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 (Hex.) PSCR PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0 0D2h Reset Value 0 1 1 1 1 1 1 1 TCR TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 0D3h Reset Value 1 1 1 1 1 1 1 1 TSCR TMZ ETI TOUT DOUT PSI PS2 PS1 PS0 0D4h Reset Value 0 0 0 0 0 0 0 0 51/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8.3 A/D CONVERTER (ADC) 8.3.1 Introduction 8.3.2 Main Features The on-chip Analog to Digital Converter (ADC) pe- ■ 8-bit conversion ripheral is a 8-bit, successive approximation con- ■ Multiplexed analog input channels verter. This peripheral has multiplexed analog in- ■ Linear successive approximation put channels (refer to device pin out description) that allow the peripheral to convert the analog volt- ■ Data register (DR) which contains the results age levels from different sources. ■ End of Conversion flag The result of the conversion is stored in a 8-bit ■ On/Off bit (to reduce consumption) Data Register. The A/D converter is controlled ■ Typical conversion time 70 µs (with an 8 MHz ) through a Control Register. crystal) s ( The block diagram is shown in Figuret 34. c u Figure 34. ADC Block Diagram d o r P f f INT ADC DIV12 e t e l o s AD OSC AbD AD EAI EOC STA PDS CR3 OFOF CR1 CR0 ADCR - ) s ( t c AIN0 u I/O PORT d o AIN1 r ANALOGTODIGITAL P PORT MUX CONVERTER e t eAINx l o s DDRx ADR b ORx O DRx ADR7ADR6ADR5ADR4ADR3ADR2ADR1ADR0 Note: ADC not present on some devices. See device summary on page 1. 52/104 1

ST6208C/ST6209C/ST6210C/ST6220C A/D CONVERTER (Cont’d) 8.3.3 Functional Description 8.3.3.4 Software Procedure 8.3.3.1 Analog Power Supply Refer to the Control register (ADCR) and Data reg- ister (ADR) in Section 8.3.7 for the bit definitions. The high and low level reference voltage pins are internally connected to the V and V pins. Analog Input Configuration DD SS Conversion accuracy may therefore be impacted The analog input must be configured through the by voltage drops and noise in the event of heavily Port Control registers (DDRx, ORx and DRx). Re- loaded or badly decoupled power supply lines. fer to the I/O port chapter. 8.3.3.2 Digital A/D Conversion Result ADC Configuration The conversion is monotonic, meaning that the re- In the ADCR register: ) s sult never decreases if the analog input does not – Reset the PDS bit to power on the AD(C. This bit t and never increases if the analog input does not. must be set at least one instructiocn before the u If the input voltage (V ) is greater than or equal beginning of the conversion to allow stabilisation AIN d to V (high-level voltage reference) then the of the A/D converter. DDA o conversion result in the DR register is FFh (full – Set the EAI bit to enarble the ADC interrupt if scale) without overflow indication. P needed. If input voltage (V ) is lower than or equal to e AIN ADC Conversion V (low-level voltage reference) then the con- t SSA e version result in the DR register is 00h. In the ADlCR register: o The A/D converter is linear and the digital result of – Sest the STA bit to start a conversion. This auto- the conversion is stored in the ADR register. The bmatically clears (resets to “0”) the End Of Con- accuracy of the conversion is described in the par- O version Bit (EOC). ametric section. When a conversion is complete - RAIN is the maximum recommended impe)dance – The EOC bit is set by hardware to flag that con- s for an analog input signal. If the impedance is too version is complete and that the data in the ADC ( high, this will result in a loss of accturacy due to data conversion register is valid. c leakage and sampling not being ucompleted in the – An interrupt is generated if the EAI bit was set allocated time. Refer to the edlectrical characteris- tics chapter for more detailos. Setting the STA bit will start a new count and will r clear the EOC bit (thus clearing the interrupt con- With an oscillator cP lock frequency less than dition) 1.2MHz, conversio n accuracy is decreased. e Note: 8.3.3.3 Analotg Input Selection e Setting the STA bit must be done by a different in- Selectioonl of the input pin is done by configuring struction from the instruction that powers-on the the related I/O line as an analog input via the Data s ADC (setting the PDS bit) in order to make sure Dbirection, Option and Data registers (refer to I/O the voltage to be converted is present on the pin. O ports description for additional information). Each conversion has to be separately initiated by Caution: Only one I/O line must be configured as writing to the STA bit. an analog input at any time. The user must avoid any situation in which more than one I/O pin is se- The STA bit is continuously scanned so that, if the lected as an analog input simultaneously, because user sets it to “1” while a previous conversion is in they will be shorted internally. progress, a new conversion is started before com- pleting the previous one. The start bit (STA) is a write only bit, any attempt to read it will show a log- ical “0”. 53/104 1

ST6208C/ST6209C/ST6210C/ST6220C A/D CONVERTER (Cont’d) 8.3.4 Recommendations bances and power supply variations due to output switching. Nevertheless, the WAIT instruction The following six notes provide additional informa- should be executed as soon as possible after the tion on using the A/D converter. beginning of the conversion, because execution of 1.The A/D converter does not feature a sample the WAIT instruction may cause a small variation and hold circuit. The analog voltage to be meas- of the V voltage. The negative effect of this var- DD ured should therefore be stable during the entire iation is minimized at the beginning of the conver- conversion cycle. Voltage variation should not ex- sion when the converter is less sensitive, rather ceed ±1/2 LSB for optimum conversion accuracy. than at the end of conversion, when the least sig- A low pass filter may be used at the analog input nificant bits are determined. pins to reduce input voltage variation during con- The best configuration, from an accuracsy )stand- version. point, is WAIT mode with the Timer s(topped. In t 2. When selected as an analog channel, the input this case only the ADC peripheral acnd the oscilla- pin is internally connected to a capacitor C of tor are then still working. The MCuU must be woken ad d typically 9pF. For maximum accuracy, this capaci- up from WAIT mode by the ADC interrupt at the o tor must be fully charged at the beginning of con- end of the conversion. The microcontroller can r version. In the worst case, conversion starts one also be woken up by Pthe Timer interrupt, but this instruction (6.5 µs) after the channel has been se- means the Timer must be running and the result- e lected. The impedance of the analog voltage ing noise could affect conversion accuracy. t source (ASI) in worst case conditions, is calculat- e l ed using the following formula: o Caution: When an I/O pin is used as an analog in- 6.5µs = 9 x C x ASI s (capacitor charged to ovaedr 99.9%), i.e. 30 kΩ in- pubt, A/D conversion accuracy will be impaired if O negative current injections (V < V ) occur from cluding a 50% guardband. INJ SS The ASI can be higher if C has been charged fo r adjacent I/O pins with analog input capability. Re- a longer period by addinga dinstructions before -the fer to Figure 35. To avoid this: ) start of conversion (adding more than 26 sCPU cy- – Use another I/O port located further away from ( cles is pointless). t the analog pin, preferably not multiplexed on the c A/D converter 3. Since the ADC is on the same cuhip as the micro- processor, the user should notd switch heavily load- – Increase the input resistance R (to reduce the IN J ed output signals during coonversion, if high preci- current injections) and reduce R (to preserve ADC sion is required. Such srwitching will affect the sup- conversion accuracy). P ply voltages used as analog references. e Figure 35. Leakage from Digital Inputs 4. Conversion accuracy depends on the quality of t the power seupplies (V and V ). The user must DD SS take spoelcial care to ensure a well regulated refer- ences voltage is present on the V and V pins DD SS (pbower supply voltage variations must be less than O 0.1V/ms). This implies, in particular, that a suitable Digital decoupling capacitor is used at the V pin. DD Input The converter resolution is given by: RINJ PBy/AINy I/O Port V –V (Digital I/O) DD SS -------------------------------- 256 V INJ Leakage Current if V < V The Input voltage (Ain) which is to be converted INJ SS must be constant for 1µs before conversion and Analog remain constant during conversion. Input 5. Conversion resolution can be improved if the RADC PBx/AINx A/D power supply voltage (V ) to the microcontroller Converter DD is lowered. V 6. In order to optimize the conversion resolution, AIN the user can configure the microcontroller in WAIT mode, because this mode minimises noise distur- 54/104 1

ST6208C/ST6209C/ST6210C/ST6220C A/D CONVERTER (Cont’d) 8.3.5 Low Power Modes cally cleared when the STA bit is set. Data in the data conversion register are valid only when this Mode Description bit is set to “1”. 0: Conversion is not complete No effect on A/D Converter. ADC interrupts WAIT 1: Conversion can be read from the ADR register cause the device to exit from Wait mode. STOP A/D Converter disabled. Bit 5 = STA: Start of Conversion. Write Only. Note: The A/D converter may be disabled by clear- 0: No effect ing the PDS bit. This feature allows reduced power 1: Start conversion consumption when no conversion is needed. ) Note: Setting this bit automatically clears tshe EOC bit. If the bit is set again when a conv(ersion is in 8.3.6 Interrupts progress, the present conversion is csttopped and a u new one will take place. This bit is write only, any Interrupt Event Event Enable fEroxmit fEroxmit attempt to read it will showo a ldogical zero. Flag Bit r Wait Stop P End of Conver- Bit 4 = PDS Powe r Down Selection. EOC EAI Yes No e sion 0: A/D convertter is switched off e 1: A/D converter is switched on Note: The EOC bit is cleared only when a new l o conversion is started (it cannot be cleared by writ- s ing 0). To avoid generating further EOC interrupt, Bbit 3 = ADCR3 Reserved, must be cleared. the EAI bit has to be cleared within the ADC inter- O rupt subroutine. 8.3.7 Register Description - Bit 2 = OSCOFF Main Oscillator off. ) A/D CONVERTER CONTROL REGISTEsR (AD- 0: Main Oscillator enabled CR) t( 1: Main Oscillator disabled c Address: 0D1h - Read/Write (Bitu 6 Read Only, Bit Note: This bit does not apply to the ADC peripher- 5 Write Only) d al but to the main clock system. Refer to the Clock o System section. Reset value: 0100 0000 (40h) r P 7 e 0 Bits 1:0 = ADCR[1:0] Reserved, must be cleared. t ADCR OSC ADCR ADCR EAI EOCe STA PDS 3 OFF 1 0 ol A/D CONVERTER DATA REGISTER (ADR) Bit 7s = EAI Enable A/D Interrupt. Address: 0D0h - Read only b 0: ADC interrupt disabled O Reset value: xxxx xxxx (xxh) 1: ADC interrupt enabled 7 0 Bit 6 = EOC End of conversion. Read Only ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 When a conversion has been completed, this bit is set by hardware and an interrupt request is gener- ated if the EAI bit is set. The EOC bit is automati- Bits 7:0 = ADR[7:0]: 8 Bit A/D Conversion Result. Table 16. ADC Register Map and Reset Values Address Register 7 6 5 4 3 2 1 0 (Hex.) Label ADR ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0D0h Reset Value 0 0 0 0 0 0 0 0 ADCR EAI EOC STA PDS ADCR3 OSCOFF ADCR1 ADCR0 0D1h Reset Value 0 1 0 0 0 0 0 0 55/104 1

ST6208C/ST6209C/ST6210C/ST6220C 9 INSTRUCTION SET 9.1 ST6 ARCHITECTURE The ST6 architecture has been designed for max- tended addressing mode are able to branch to any imum efficiency while keeping byte usage to a address in the 4 Kbyte Program space. minimum; in short, to provide byte-efficient pro- gramming. The ST6 core has the ability to set or Extended addressing mode instructions are two clear any register or RAM location bit in Data bytes long. space using a single instruction. Furthermore, pro- Program Counter Relative. Relative addressing grams can branch to a selected address depend- mode is only used in conditional branch instruc- ing on the status of any bit in Data space. ) tions. The instruction is used to perform a tsest and, if the condition is true, a branch with a s(pan of -15 t 9.2 ADDRESSING MODES to +16 locations next to the addressc of the relative instruction. If the condition is notu true, the instruc- The ST6 has nine addressing modes, which are tion which follows the relative dinstruction is execut- o described in the following paragraphs. Three dif- ed. Relative addressing mode instructions are one r ferent address spaces are available: Program byte long. The opcodPe is obtained by adding the space, Data space, and Stack space. Program three most significant bits which characterize the space contains the instructions which are to be ex- test condition, onee bit which determines whether it ecuted, plus the data for immediate mode instruc- is a forwarde tbranch (when it is 0) or backward tions. Data space contains the Accumulator, the X, branch (wlhen it is 1) and the four least significant o Y, V and W registers, peripheral and Input/Output bits which give the span of the branch (0h to Fh) s registers, the RAM locations and Data ROM loca- which must be added or subtracted from the ad- b tions (for storage of tables and constants). Stack dress of the relative instruction to obtain the O space contains six 12-bit RAM cells used to stack branch destination address. the return addresses for subroutines and int-e r- rupts. ) Bit Direct. In bit direct addressing mode, the bit to s be set or cleared is part of the opcode, and the Immediate. In immediate addressing (mode, the byte following the opcode points to the address of t operand of the instruction follows thec opcode loca- the byte in which the specified bit must be set or tion. As the operand is a ROM byute, the immediate cleared. Thus, any bit in the 256 locations of Data addressing mode is used tod access constants space memory can be set or cleared. which do not change duroing program execution (e.g., a constant usedP tor initialize a loop counter). Bit Test & Branch. Bit test and branch addressing mode is a combination of direct addressing and Direct. In direct eaddressing mode, the address of relative addressing. Bit test and branch instruc- the byte whicth is processed by the instruction is tions are three bytes long. The bit identification e stored in the location which follows the opcode. Di- and the test condition are included in the opcode l rect addoressing allows the user to directly address byte. The address of the byte to be tested is given the 2s56 bytes in Data Space memory with a single in the next byte. The third byte is the jump dis- twbo-byte instruction. placement, which is in the range of -127 to +128. O This displacement can be determined using a la- Short Direct. The core can address the four RAM bel, which is converted by the assembler. registers X, Y, V, W (locations 80h, 81h, 82h, 83h) in short-direct addressing mode. In this case, the Indirect. In indirect addressing mode, the byte instruction is only one byte and the selection of the processed by the register-indirect instruction is at location to be processed is contained in the op- the address pointed to by the content of one of the code. Short direct addressing is a subset of direct indirect registers, X or Y (80h, 81h). The indirect addressing mode. (Note that 80h and 81h are also register is selected by bit 4 of the opcode. Register indirect registers). indirect instructions are one byte long. Extended. In extended addressing mode, the 12- Inherent. In inherent addressing mode, all the in- bit address needed to define the instruction is ob- formation necessary for executing the instruction tained by concatenating the four least significant is contained in the opcode. These instructions are bits of the opcode with the byte following the op- one byte long. code. The instructions (JP, CALL) which use ex- 56/104 1

ST6208C/ST6209C/ST6210C/ST6220C 9.3 INSTRUCTION SET The ST6 offers a set of 40 basic instructions Load & Store. These instructions use one, two or which, when combined with nine addressing three bytes depending on the addressing mode. modes, yield 244 usable opcodes. They can be di- For LOAD, one operand is the Accumulator and vided into six different types: load/store, arithme- the other operand is obtained from data memory tic/logic, conditional branch, control instructions, using one of the addressing modes. jump/call, and bit manipulation. The following par- agraphs describe the different types. For Load Immediate, one operand can be any of the 256 data space bytes while the other is always All the instructions belonging to a given type are immediate data. presented in individual tables. ) s Table 17. Load & Store Instructions ( t cFlags Instruction Addressing Mode Bytes Cycles u Z C d LD A, X Short Direct 1 4 o Δ * LD A, Y Short Direct 1 4 r Δ * P LD A, V Short Direct 1 4 Δ * e LD A, W Short Direct 1 4 Δ * t e LD X, A Short Direct 1 4 Δ * l LD Y, A Short Direct 1o 4 Δ * s LD V, A Short Direct b 1 4 Δ * LD W, A Short Direct O 1 4 Δ * LD A, rr Direct 2 4 Δ * - LD rr, A Direct 2 4 Δ * ) s LD A, (X) Indirect 1 4 Δ * ( LD A, (Y) Indirect t 1 4 Δ * c LD (X), A Indirectu 1 4 Δ * d LD (Y), A Indirect 1 4 Δ * o LDI A, #N Immediate 2 4 Δ * r P LDI rr, #N Immediate 3 4 * * e Legend: t X, Y Index Reegisters, l V, W Shoort Direct Registers # sImmediate data (stored in ROM memory) rrb Data space register O Δ Affected * Not Affected 57/104 1

ST6208C/ST6209C/ST6210C/ST6220C INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are either a data space memory location or an imme- used to perform arithmetic calculations and logic diate value. In CLR, DEC, INC instructions the op- operations. In AND, ADD, CP, SUB instructions erand can be any of the 256 data space address- one operand is always the accumulator while, de- es. In COM, RLC, SLA the operand is always the pending on the addressing mode, the other can be accumulator. Table 18. Arithmetic & Logic Instructions Flags Instruction Addressing Mode Bytes Cycles Z C ADD A, (X) Indirect 1 4 Δ sΔ) ADD A, (Y) Indirect 1 4 Δ ( Δ t ADD A, rr Direct 2 4 Δ c Δ u ADDI A, #N Immediate 2 4 Δ d Δ AND A, (X) Indirect 1 4 oΔ Δ r AND A, (Y) Indirect 1 4 P Δ Δ AND A, rr Direct 2 4 Δ Δ e ANDI A, #N Immediate 2 4 Δ Δ t e CLR A Short Direct 2 4 Δ Δ l o CLR r Direct 3 4 * * s COM A Inherent 1 b 4 Δ Δ CP A, (X) Indirect 1O 4 Δ Δ CP A, (Y) Indirect 1 4 Δ Δ - CP A, rr Direct ) 2 4 Δ Δ s CPI A, #N Immediate 2 4 Δ Δ ( DEC X Short Direct ct 1 4 Δ * DEC Y Short Directu 1 4 Δ * d DEC V Short Direct 1 4 Δ * o DEC W Srhort Direct 1 4 Δ * P DEC A Direct 2 4 Δ * DEC rr e Direct 2 4 Δ * t DEC (X) e Indirect 1 4 Δ * DEC (Yo)l Indirect 1 4 Δ * INCs X Short Direct 1 4 Δ * b INC Y Short Direct 1 4 Δ * O INC V Short Direct 1 4 Δ * INC W Short Direct 1 4 Δ * INC A Direct 2 4 Δ * INC rr Direct 2 4 Δ * INC (X) Indirect 1 4 Δ * INC (Y) Indirect 1 4 Δ * RLC A Inherent 1 4 Δ Δ SLA A Inherent 2 4 Δ Δ SUB A, (X) Indirect 1 4 Δ Δ SUB A, (Y) Indirect 1 4 Δ Δ SUB A, rr Direct 2 4 Δ Δ SUBI A, #N Immediate 2 4 Δ Δ Notes: X,Y Index Registers # Immediate data (stored in ROM memory) V, W Short Direct Registers * Not Affected Δ Affected rr Data space register 58/104 1

ST6208C/ST6209C/ST6210C/ST6220C INSTRUCTION SET (Cont’d) Conditional Branch. Branch instructions perform Control Instructions. Control instructions control a branch in the program when the selected condi- microcontroller operations during program execu- tion is met. tion. Bit Manipulation Instructions. These instruc- Jump and Call. These two instructions are used tions can handle any bit in Data space memory. to perform long (12-bit) jumps or subroutine calls One group either sets or clears. The other group to any location in the whole program space. (see Conditional Branch) performs the bit test branch operations. Table 19. Conditional Branch Instructions ) s Flags Instruction Branch If Bytes Cycles ( Z t C c JRC e C = 1 1 2 * u * d JRNC e C = 0 1 2 * * o JRZ e Z = 1 1 2 * * r P JRNZ e Z = 0 1 2 * * JRR b, rr, ee Bit = 0 3 5 e * Δ JRS b, rr, ee Bit = 1 3 5 e t * Δ Notes: ol b 3-bit address rr Dsata space register e 5 bit signed displacement in the range -15 to +16 Δ bAffected. The tested bit is shifted into carry. ee 8 bit signed displacement in the range -126 to +129 * Not Affected O Table 20. Bit Manipulation Instructions - Flags ) Instruction Addressing Mode s Bytes Cycles Z C ( SET b,rr Bit Direct ct 2 4 * * RES b,rr Bit Direct u 2 4 * * d Notes: o b 3-bit address * Not Affected r rr Data space register P Bit Manipulation Instructions should not be used on Port Data Registers and any registers with read only and/or write only bits (see I/O port chapter) e t Table 21. Ceontrol Instructions l o Flags sInstruction Addressing Mode Bytes Cycles Z C b O NOP Inherent 1 2 * * RET Inherent 1 2 * * RETI Inherent 1 2 Δ Δ STOP (1) Inherent 1 2 * * WAIT Inherent 1 2 * * Notes: 1. This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected. Δ Affected *Not Affected Table 22. Jump & Call Instructions Flags Instruction Addressing Mode Bytes Cycles Z C CALL abc Extended 2 4 * * JP abc Extended 2 4 * * Notes: abc 12-bit address * Not Affected 59/104 1

ST6208C/ST6209C/ST6210C/ST6220C Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW LOW 0 1 2 3 4 5 6 7 0000 0001 0010 0011 0100 0101 0110 0111 HI HI 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 0 0 e abc e b0,rr,ee e NOP # e a,(x) 0000 0000 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI 1 1 e abc e b0,rr,ee e x e a,nn 0001 0001 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2 2 e abc e b4,rr,ee e # e a,(x) 0010 0)010 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind s 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI( 3 e abc e b4,rr,ee e a,x e a,nnct 3 0011 0011 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 u imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC d4 ADD 4 o 4 e abc e b2,rr,ee e # e a,(x) 0100 r 0100 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 P prc 1 ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 5 e abc e b2,rr,ee e y e e a,nn 5 0101 0101 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 e t sd 1 prc 2 imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZl 2 JRC 4 INC 6 o 6 e abc e b6,rr,ee e # e (x) 0110 s 0110 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 7 O 7 e abc e b6,rr,ee e a,y e # 0111 0111 1 pcr 2 ext 1 pcr 3 - bt 1 pcr 1 sd 1 prc 2 JRNZ 4 CALL 2 JRNC 5) JRR 2 JRZ 2 JRC 4 LD 8 e abc e s b1,rr,ee e # e (x),a 8 1000 ( 1000 1 pcr 2 ext 1 tpcr 3 bt 1 pcr 1 prc 1 ind 2 JRNZ 4 CALL 2 cJRNC 5 JRS 2 JRZ 4 INC 2 JRC 9 u 9 e abc e b1,rr,ee e v e # 1001 d 1001 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc o 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND A r A e P abc e b5,rr,ee e # e a,(x) 1010 1010 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind e 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI B t B 1011 e e abc e b5,rr,ee e a,v e a,nn 1011 l1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm o 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB sC C b 1100 e abc e b3,rr,ee e # e a,(x) 1100 O 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI D D e abc e b3,rr,ee e w e a,nn 1101 1101 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC E E e abc e b7,rr,ee e # e (x) 1110 1110 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC F F e abc e b7,rr,ee e a,w e # 1111 1111 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc Abbreviations for Addressing Modes: Legend: dir Direct # Indicates Illegal Instructions Mnemonic sd Short Direct e 5-bit Displacement Cycles 2 JRC imm Immediate b 3-bit Address Operands e inh Inherent rr 1-byte Data space address Bytes 1 prc ext Extended nn 1-byte immediate data b.d Bit Direct abc 12-bit address Addressing Mode bt Bit Test ee 8-bit displacement pcr Program Counter Relative ind Indirect 60/104 1

ST6208C/ST6209C/ST6210C/ST6220C Opcode Map Summary (Continued) LOW LOW 8 9 A B C D E F 1000 1001 1010 1011 1100 1101 1110 1111 HI HI 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD 0 0 e abc e b0,rr e rr,nn e a,(y) 0000 0000 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 1 1 e abc e b0,rr e x e a,rr 0001 0001 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP 2 2 e abc e b4,rr e a e a,(y) 0010 0)010 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind s 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP( 3 e abc e b4,rr e x,a e a,rrct 3 0011 0011 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 u dir 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC d4 ADD 4 o 4 e abc e b2,rr e e a,(y) 0100 r 0100 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 P prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD 5 e abc e b2,rr e y e e a,rr 5 0101 0101 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 e t sd 1 prc 2 dir 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZl2 STOP 2 JRC 4 INC 6 o 6 e abc e b6,rr e e (y) 0110 s 0110 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC 7 O 7 e abc e b6,rr e y,a e rr 0111 0111 1 pcr 2 ext 1 pcr 2 - b.d 1 pcr 1 sd 1 prc 2 dir 2 JRNZ 4 JP 2 JRNC 4) RES 2 JRZ 2 JRC 4 LD 8 e abc e s b1,rr e # e (y),a 8 1000 ( 1000 1 pcr 2 ext 1 tpcr 2 b.d 1 pcr 1 prc 1 ind 2 JRNZ 4 JP 2 cJRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 9 u 9 e abc e b1,rr e v e rr,a 1001 d 1001 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir o 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND A r A e P abc e b5,rr e a e a,(y) 1010 1010 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind e 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND B t B 1011 e e abc e b5,rr e v,a e a,rr 1011 l1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir o 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB sC C b 1100 e abc e b3,rr e e a,(y) 1100 O 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB D D e abc e b3,rr e w e a,rr 1101 1101 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC E E e abc e b7,rr e e (y) 1110 1110 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC F F e abc e b7,rr e w,a e rr 1111 1111 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir Abbreviations for Addressing Modes: Legend: dir Direct # Indicates Illegal Instructions sd Short Direct e 5-bit Displacement Cycles 2 JRC Mnemonic imm Immediate b 3-bit Address Operands e inh Inherent rr 1-byte Data space address Bytes 1 prc ext Extended nn 1-byte immediate data b.d Bit Direct abc 12-bit address Addressing Mode bt Bit Test ee 8-bit Displacement pcr Program Counter Relative ind Indirect 61/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10 ELECTRICAL CHARACTERISTICS 10.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- Figure 36. Pin Loading Conditions ferred to V . SS 10.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- ST6PIN imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ) C s devices with an ambient temperature at T =25°C L A ( and T =T max (given by the selected temperature t A A c range). u d Data based on characterization results, design o simulation and/or technology characteristics are 10.1.5 Pin Input Voltagre indicated in the table footnotes and are not tested P in production. Based on characterization, the min- The input voltage measurement on a pin of the de- imum and maximum values refer to sample tests vice is describede in Figure 37. t and represent the mean value plus or minus three e times the standard deviation (mean±3Σ). Figure o3l7. Pin Input Voltage s 10.1.2 Typical Values b Unless otherwise specified, typical data are based O on T =25°C, V =5V (for the 4.5V≤V ≤6.0V ST6PIN A DD DD voltage range) and V =3.3V (for -the DD 3V≤VDD≤3.6V voltage range). They are gisve)n only as design guidelines and are not tested(. VIN t c 10.1.3 Typical Curves u Unless otherwise specified, adll typical curves are given only as design guideloines and are not tested. r 10.1.4 Loading CapaPcitor The loading coend itions used for pin parameter measurementt is shown in Figure 36. e l o s b O 62/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating mum ratings” may cause permanent damage to conditions for extended periods may affect device the device. This is a stress rating only and func- reliability. tional operation of the device under these condi- 10.2.1 Voltage Characteristics Symbol Ratings Maximum value Unit V - V Supply voltage 7 DD SS V Input voltage on any pin 1) & 2) V -0.3 to V +0.3 IN SS DD )V V Output voltage on any pin 1) & 2) V -0.3 to V +0.3 s OUT SS DD ( V Electro-static discharge voltage (Human Body Model) 3500 t ESD(HBM) c u 10.2.2 Current Characteristics d o Symbol Ratings Maximum value Unit r I Total current into V power lines (source) 3) P 80 VDD DD I Total current out of V ground lines (sink) 3) e 100 VSS SS t Output current sunk by any standard I/O and conterol pin 20 l I Output current sunk by any high sink I/O pino 40 mA IO s Output current source by any I/Os and control pin 15 b Injected current on RESET pin O ±5 I 2) & 4) INJ(PIN) Injected current on any other pin ±5 - ) 10.2.3 Thermal Characteristics s ( Symbol t Ratings Value Unit c T Storage temuperature range -60 to +150 °C STG d Maximum junction temperature T o J (rsee THERMAL CHARACTERISTICS section) P e Notes: t 1. Directly coennecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset DD SS is genoelrated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program coun- ter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ s for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset con- b DD SS figuration. O 2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induceIdN by VIN>VDD while a negative injection is induced by VIN<VSS. 3. Power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage is lower than the specified limits). - Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 63/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.3 OPERATING CONDITIONS 10.3.1 General Operating Conditions Symbol Parameter Conditions Min Max Unit V Supply voltage see Figure 38 3.0 6 V DD V =3.0V, 1 & 6 Suffix 0 1) 4 DD V =3.0V, 3 Suffix 0 1) 4 DD f Oscillator frequency MHz OSC V =3.6V, 1 & 6Suffix 0 1) 8 DD V =3.6V, 3 Suffix 0 1) 4 DD ) fOSC=4MHz, 1 & 6 Suffix 3.0 6.0 s ( fOSC=4MHz, 3 Suffix 3.0 6t.0 V Operating Supply Voltage c V DD fOSC=8MHz, 1 & 6 Suffix 3.6 u 6.0 f =8MHz, 3 Suffix 4.5d 6.0 OSC o 1 Suffix Version 0 70 r P T Ambient temperature range 6 Suffix Version -40 85 °C A 3 Suffix Version e -40 125 t e Notes: l o 1. An oscillator frequency above 1.2MHz is recommended for reliable A/D results. s 2. Operating conditions with T =-40 to +125°C. b A O Figure 38. f Maximum Operating Frequency Versus V Supply Voltage for OTP & ROM devices OSC DD - ) fOSC [MHz] s 1 & 6 (suffix version t 8 c u D 7 YEE d 3 suffix version TT o 6 NALIRANPREAr 3 f OAA OSG 5 eCTI GUHIS l4e t FUNNOTIN T 2 fOSG Min o s 3 b 1 O 2 SUPPLY 1 2.5 3 3.6 4 4.5 5 5.5 6 VOLTAGE (VDD) 1. In this area, operation is guaranteed at the quartz crystal frequency. 2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least f Min. OSG 3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f . OSG 64/104 1

ST6208C/ST6209C/ST6210C/ST6220C OPERATING CONDITIONS (Cont’d) 10.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V , f , and T . DD OSC A Symbol Parameter Conditions Min Typ 1) Max Unit Reset release threshold V 3.9 4.1 4.3 IT+ (V rise) DD V Reset generation threshold V 3.6 3.8 4 IT- (V fall) DD V LVD voltage threshold hysteresis V -V 50 300 700 mV hys IT+ IT- ) Vt V rise time rate 2) s mV/s POR DD tg(VDD) Filtered glitch delay on VDD 3) Not detected by the LVD 30 ct( ns Notes: u 1. LVD typical data are based on T =25°C. They are given only as design guidelines and are nodt tested. A o 2. The minimum V rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production. DD r 3. Data based on characterization results, not tested in production. P Figure 39. LVD Threshold Versus V and f 3) e DD OSC t e l FUNCTIONALITY fOSC [MHz] o NOT GUARANTEED s IN THIS AREA b DEVICEUNDER8 O RESET IN THIS AREA4 - FUNCTIONAL AREA ) s SUPPLY 02.5 3 3c.5tV(IT-≥3.6 4 4.5 5 5.5 6 VOLTAGE [V] u d Figure 40. Typical LVD Thresholds Versus Figure 41. Typical LVD thresholds vs. o Temperature for OTP devices Temperature for ROM devices r P e t e l o Thresholds [V] Thresholds [V] s 4b.2 4.2 O 4 4 VVIdTd+ up VVITd+d up 3.8 VVIdTd- down 3.8 VVITd-d down 3.6 3.6 -40°C 25°C 95°C 125°C -40°C 25°C 95°C 125°C T [°C] T [°C] 65/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption, the two current values must be the ST6 functional operating modes over tempera- added (except for STOP mode for which the clock ture range does not take into account the clock is stopped). source current consumption. To get the total de- 10.4.1 RUN Modes Symbol Parameter Conditions Typ 1) Max 2) Unit V 0 f =32kHz 0.5 0.7 Supply current in RUN mode 3) 6.≤D fOOSSCC=1MHz 1.3 1.7 ) (see Figure 42 & Figure 43) 5VV≤D fffOOOSSSCCC===248MMMHHHzzz 123...623 c234t...438( s IDD 4. u mA Supply current in RUN mode 3) 3.6V≤ ffOOSSCC==13M2kHHzz r o 00d..36 00..48 (see Figure 42 & Figure 43) DD fOSC=2MHz P 0.9 1.2 V fOSC=4MHz 1.0 1.5 V≤ fOSC=8MHz e 1.8 2.3 3 t e Notes: ol 1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤6.0V rasnge) and V =3.3V (3V≤V ≤3.6V range). A DD DD DD DD 2. Data based on characterization results, tested in production abt V max. and f max. DD OSC O 3. CPU running with memory access, all I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSCIN) driven by external square wave, OSG- a nd LVD disabled, option bytes not programmed. Figure 42. Typical I in RUN vs. f ) Figure 43. Typical I in RUN vs. Temperature DD CPU s DD (V = 5V) ( DD t IDD [mA] c IDD [mA] u 5 d 3.5 8MHz 1MHzo 4MHz 32rKHz P 3 4 2MHz e e t 2.5 8MHz 1MHz 4MHz 32KHz l o 3 2MHz s 2 b O 2 1.5 1 1 0.5 0 0 3 4 5 6 -40 25 95 125 VDD [V] T[°C] 66/104 1

ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.2 WAIT Modes Symbol Parameter Conditions Typ 1) Max 2) Unit f =32kHz 330 550 Supply current in WAIT mode 3) fOSC=1MHz 350 600 OSC Option bytes not programmed f =2MHz 370 650 OSC (see Figure 44) es fOSC=4MHz 410 700 vic fOSC=8MHz 480 800 SOupptipolny bcyutreresn pt riong WraAmImT emdo tdoe 0 30)H 6.0V≤DD OTP de fffOOOSSSCCC===123MM2kHHHzzz 124861 1682000 s ) (see Figure 45) V≤ fOSC=4MHz 57 1t80( 5V fOSC=8MHz 70 c200 4. u es fOSC=32kHz 19d0 300 Supply current in WAIT mode3) vic fOSC=1MHz o 210 350 e f =2MHz r 240 400 (see Figure 46) M d fOOSSCC=4MHz P 280 500 RO fOSC=8MHz e 350 600 I µA DD t f =32kHze 80 120 Supply current in WAIT mode 3) fOSC=1MlHz 90 140 OSC o Option bytes not programmed f =2MHz 100 150 OSCs (see Figure 44) es fbOSC=4MHz 120 200 vicO fOSC=8MHz 150 250 e Supply current in WAIT mode 3) ) 3.6V≤- OTP d ffOOSSCC==13M2kHHzz 58 3400 Option bytes programmed to 00H s DD fOSC=2MHz 16 50 (see Figure 45) ct( VV≤ ffOOSSCC==48MMHHzz 1280 16000 u 3 Supply current in WAoIT dmode 3) vices ffOOSSCC==13M2kHHzz 6605 110100 Option bytes notr programmed de fOSC=2MHz 80 120 (see Figure 46P) M fOSC=4MHz 100 150 e RO fOSC=8MHz 130 210 t e Notes: l 1. Typicaol data are based on T =25°C, V =5V (4.5V≤V ≤6.0V range) and V =3.3V (3V≤V ≤3.6V range). A DD DD DD DD s 2. Data based on characterization results, tested in production at V max. and f max. b DD OSC 3. All I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSC ) driven by external O IN square wave, OSG and LVD disabled. 67/104 1

ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 44. Typical I in WAIT vs f and Temperature for OTP devices with option bytes not DD CPU programmed IDD [µA] IDD [µA] 800 700 8MHz 1M 8MHz 1MHz 700 4MHz 32KHz 4MHz 32KHz 2MHz 600 2MHz 600 ) s 500 ( 500 t c u 400 d o 400 300 r P 200 e 300 t e 100 ol s b 0 200 O 3 4 5 6 -40 25 95 125 - VDD [V] T[°C] ) s Figure 45. Typical IDD in WAIT vs (fCPU and Temperature for OTP devices with option bytes programmed to 00H ct u IDD [µA] IDD [µA] d 120 o 90 8MHz 1rM 8MHz 1MHz P 4MHz 32KHz 80 4MHz 32KHz 100 e 2MHz 2MHz t e 70 l o 80 s 60 b O 60 50 40 40 30 20 20 0 10 3 4 5 6 -20 25 95 VDD [V] T[°C] 68/104 1

ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 46. Typical I in WAIT vs f and Temperature for ROM devices DD CPU IDD [µA] IDD [µA] 600 450 8MHz 1M 8MHz 1MHz 4MHz 32KHz 4MHz 32KHz 400 500 2MHz 2MHz 350 400 ) s 300 ( t c 300 u 250 d o 200 r 200 P e 100 t 150 e l o 0 100s b 3 4 5 6 -20 25 95 125 O VDD [V] T[°C] - ) s ( t c u d o r P e t e l o s b O 69/104 1

ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.3 STOP Mode Symbol Parameter Conditions Typ 1) Max Unit 10 3) Supply current in STOP mode 2) OTP devices 0.3 20 4) I μA DD (see Figure 47 & Figure 48) 2 3) ROM devices 0.1 20 4) Notes: 1. Typical data are based on V =5.0V at T =25°C. DD A ) 2. All I/O pins in input with pull-up mode (no load), all peripherals in reset state, OSG and LVD disabled, optsion bytes programmed to 00H. Data based on characterization results, tested in production at V max. and f m(ax. DD CPtU 3. Maximum STOP consumption for -40°C<Ta<90°C c u 4. Maximum STOP consumption for -40°C<Ta<125°C d Figure 47. Typical I in STOP vs Temperature Figure 48. Typical I in SoTOP vs Temperature DD DD for OTP devices for ROM devices r P IDD [nA] IDD [nA] e 1200 e t Ta=-40°C Ta=95°C l Ta=-40°C Ta=95°C o Ta=25°C Ta=125°C 15s00 Ta=25°C Ta=125°C 1000 b O 800 - ) s 1000 ( 600 ct u d 400 o r 500 P 200 e t e l o 0 0 s b 3 4 5 6 3 4 5 6 O VDD [V] VDD [V] 70/104 1

ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.4 Supply and Clock System The previous current consumption specified for source current consumption. To get the total de- the ST6 functional operating modes over tempera- vice consumption, the two current values must be ture range does not take into account the clock added (except for STOP mode). Symbol Parameter Conditions Typ 1) Max 2) Unit f =32kHz, OSC f =1MHz 230 OSC f =2MHz V =5.0V 260 OSC DD fOSC=4MHz 340 ) s f =8MHz 480 Supply current of RC oscillator OSC ( t fOSC=32kHz, c f =1MHz 80 u OSC f =2MHz V =3.3V 11d0 OSC DD f =4MHz o 180 OSC r fOSC=8MHz P 320 I DD(CK) f =32kHz, 900 OSC e f =1MHz 280 OSC t μA f =2MHz e V =5.0V 240 OSC DD fOSC=4MHzol 140 f =8MHsz 40 OSC Supply current of resonator oscillator b f =32kHz, 120 OSOC f =1MHz 70 OSC - fOSC=2MHz VDD=3.3V 50 ) fOSC=4MHz 20 s f =8MHz 10 ( OSC IDD(LFAO) LFAO supply current 3) ct VDD=5.0V 102 I OSG supply current 4) u V =5.0V 40 DD(OSG) d DD IDD(LVD) LVD supply curreont 5) VDD=5.0V 170 r P 10.4.5 On-Chip Peripherals e Symbol Parameter Conditions Typ 1) Unit t e V =5.0V 170 IDD(TIMo)l8-bit Timer supply current 6) fOSC=8MHz VDD=3.3V 100 s DD µA bI ADC supply current when converting 7) f =8MHz VDD=5.0V 80 O DD(ADC) OSC V =3.3V 50 DD Notes: 1. Typical data are based on T =25°C. A 2. Data based on characterization results, not tested in production. 3. Data based on a differential I measurement between reset configuration (OSG and LFAO disabled) and LFAO run- DD ning (also includes the OSG stand alone consumption). 4. Data based on a differential I measurement between reset configuration with OSG disabled and OSG enabled. DD 5. Data based on a differential I measurement between reset configuration with LVD disabled and LVD enabled. DD 6. Data based on a differential I measurement between reset configuration (timer disabled) and timer running. DD 7. Data based on a differential I measurement between reset configuration and continuous A/D conversions. DD 71/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V , f , and T . DD OSC A 10.5.1 General Timings Symbol Parameter Conditions Min Typ 1) Max Unit 2 4 5 t CPU t Instruction cycle time c(INST) f =8MHz 3.25 6.5 8.125 μs CPU Interrupt reaction time 2) 6 11 tCPU t v(IT) tv(IT) = Δtc(INST) + 6 fCPU=8MHz 9.75 17.875 μs ) s 10.5.2 External Clock Source ( t c Symbol Parameter Conditions Min Typ u Max Unit V OSC input pin high level voltage 0.7xV d V OSCINH IN See Figure 49 DD o DD V VOSCINL OSCIN input pin low level voltage VSS r 0.3xVDD P I OSCx Input leakage current V ≤V ≤V ± 2 μA L SS IN DD e Notes: t e 1. Data based on typical application software. l 2. Time measured between interrupt event and interrupt vector fetch. Δto is the number of t cycles needed to finish the current instruction execution. s c(INST) CPU b O Figure 49. Typical Application with an Exter-na l Clock Source ) s ( 90% t c V OSCINH u 10% d o V OSCINL r P e t e l o s OSCOUT b Not connected O f OSC EXTERNAL I CLOCKSOURCE L OSCIN ST62XX 72/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 10.5.3 Crystal and Ceramic Resonator Oscillators The ST6 internal clock can be supplied with sever- characterization results with specified typical ex- al different Crystal/Ceramic resonator oscillators. ternal components. Refer to the crystal/ceramic Only parallel resonant crystals can be used. All the resonator manufacturer for more details (frequen- information given in this paragraph are based on cy, package, accuracy...). Symbol Parameter Conditions Typ Unit R Feedback resistor 3 MΩ F f =32kHz, 120 OSC CL1 Recommended load capacitances versus equiva- fOSC=1MHz 47 s ) f =2MHz 33 pF CL2 lent crystal or ceramic resonator frequency fOOSSCC=4MHz c33t( fOSC=8MHz u 22 d o r Oscillator Typical Crystal or Ceramic Resonators P CL1 CL2 tSU(osc) Reference Freq. Characteristic 1) [pF] [pF] [ms] 1) e CSB455E 455KHz Δf =[±0.5KHz ,±0.3%t ,±0.5% ] 220 220 OSC tolerance e ΔTa aging amic RATA CCSSTBC10C020.J00MG0H6 12MMHHzz ΔΔffOOSSCC==[[±±00..55K%Htozletoralensrcaen,c±oe0l,±.50%.3Δ%TaΔ,T±a0,±.30%.5a%gianggi]ng] 14070 14070 er U b C M CSTCC4.00MG0H6 4MHz ΔfOSC=[±0.5O%tolerance,±0.3%ΔTa,±0.3%aging] 47 47 CSTCC8.00MG 8MHz Δf =[±0.5% ,±0.3% ,±0.3% ] 15 15 OSC tolerance ΔTa aging - Notes: ) s 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. ( 2. t is the typical oscillator start-up ttime measured between V =2.8V and the fetch of the first instruction (with a SU(OSC) c DD quick V ramp-up from 0 to 5V (<50μs). DD u 3. The oscillator selection can be odptimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resoonator manufacturer for more details. r P Figure 50. Typicea l Application with a Crystal or Ceramic Resonator t e l V o DD s CL1 OSC b IN O RESONATOR RF FOSC OSCOUT C L2 ST62XX 73/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 10.5.4 RC Oscillator The ST6 internal clock can be supplied with an external RC oscillator. Depending on the R value, the NET accuracy of the frequency is about 20%, so it may not be suitable for some applications. Symbol Parameter Conditions Min Typ Max Unit V 6.0≤ RRNNEETT==2427kkΩΩ 75..21 85..67 61.05 D D RNET=100kΩ 3.2 3.4 3.8 V ≤ RNET=220kΩ 1.8 1.9 2 fOSC RC oscillator frequency 1) 4.5V RNET=470kΩ 0.9 0.95 1.1( s )MHz V R =22kΩ 3.7 4.3 4t.9 6 NET c 3.≤ RNET=47kΩ 2.8 3 u 3.3 D R =100kΩ 1.8 1d.9 2 D NET V R =220kΩ 1 o 1.1 1.2 ≤ NET V R =470kΩ 0.5r 0.55 0.6 3 NET P RNET RC Oscillator external resistor 2) see Figure 52 & Figure 53e 22 870 kΩ t Notes: e 1. Data based on characterization results, not tested in production. Theosle measurements were done with the OSCin pin unconnected (only soldered on the PCB). s 2. R must have a positive temperature coefficient (ppm/°C), cbarbon resistors should therefore not be used. NET O - Figure 51. Typical Application with RC Osc illator ) s ( t c u V V EXTERNAL RC d DD DD o r OSCOUPT e MIRROR t CURRENT e R l NET o V DD s b O f OSC OSC IN NC C ~9pF DISCHARGE EX ST62XX 74/104 1

ST6208C/ST6209C/ST6210C/ST6220C CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 52. Typical RC Oscillator frequency vs. Figure 53. Typical RC Oscillator frequency vs. V Temperature (V = 5V) DD DD fosc [MHz] Rnet=22KOhm fosc [MHz] Rnet=22KOhm 12 Rnet=47KOhm Rnet=47KOhm Rnet=100KOhm 10 Rnet=100KOhm 10 Rnet=220KOhm Rnet=220KOhm 8 8 Rnet=470KOhm Rnet=470KOhm ) 6 6 s ( 4 4 ct u 2 2 d o 0 0 r P 3 4 5 6 -40 25 95 125 VDD [V] e Ta [°C] t e l 10.5.5 Oscillator Safeguard (OSG) and Low Frequency Auoxiliary Oscillator (LFAO) s Symbol Parameter Condibtions Min Typ Max Unit O fLFAO LForewq uFerenqcuye 1n)cy Auxiliary Oscillator TTA==-22 55°°CC,, VVDD==53..30VV 28060 315500 834000 kHz A DD f Internal Frequency with OSG ena-s )TA=25°C, VDD=4.5V 4 MHz OSG bled ( T =25°C, V =3.3V 2 t A DD c Figure 54. Typical LFAO Frequuencies d o fosc [kHz] r P 600 e Ta=-40°C 500 e t Ta=25°C ol 400 Ta=125°C s b 300 O 200 100 0 3 4 5 6 VDD [V] Note: 1. Data based on characterization results. 75/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A 10.6.1 RAM and Hardware Registers Symbol Parameter Conditions Min Typ Max Unit V Data retention1) 0.7 V RM 10.6.2 EPROM Program Memory Symbol Parameter Conditions Min Typ Max Unit tret Data retention 2) TA=+55°C 3) 10 sy)ears ( t Figure 55. EPROM Retention Time vs. Temperature c u d Retention time [Years] o 100000 r P 10000 e t 1000 e l o 100 s b 10 O 1 - ) 0.1 s ( -40 -30 -20 -10 0t 10 20 30 40 50 60 70 80 90 100 110 120 c u Temperature [°C] d o r Notes: P 1. iMstienrims (uomn lyV DinD S sTueOp pPly m voodltea)g.e G wuiathraonutte leodsi nbgy dcoantas tsrtuocrteiodn i,n n RoAt tMes (tiend S iTnO pPro mduocdtieo no.r under RESET) or in hardware reg- t 2. Data basede on reliability test results and monitored in production. For OTP devices, data retention and programmability must bel guaranteed by a screening procedure. Refer to Application Note AN886. o 3. The data retention time increases when the T decreases, see Figure 55. s A b O 76/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- ■ ESD: Electro-Static Discharge (positive and sis during product characterization. negative) is applied on all pins of the device until a functional disturbance occurs. This test 10.7.1 Functional EMS conforms with the IEC 1000-4-2 standard. (Electro Magnetic Susceptibility) ■ FTB: A Burst of Fast Transient voltage (positive Based on a simple running application on the and negative) is applied to V and V through DD SS product (toggling 2 LEDs through I/O ports), the a 100pF capacitor, until a functional disturbance product is stressed by two electro magnetic events occurs. This test conforms with the IEC 1000-4- until a failure occurs (indicated by the LEDs). 4 standard. ) A device reset allows normal operations tso be re- sumed. ( t c Symbol Parameter Conditions Neg 1)u Pos 1) Unit d Voltage limits to be applied on any I/O pin V =5V, T =+25°C, f =8MHz VFESD to induce a functional disturbance coDnDforms toA IEC 1000O-4S-C2 o -2 2 r Fast transient voltage burst limits to be ap- P kV V =5V, T =+25°C, f =8MHz V plied through 100pF on V and V pins DD A OSC -2.5 3 FFTB DD DD conforms to IEC 1000-4e-4 to induce a functional disturbance t e l Notes: o 1. Data based on characterization results, not tested in production.s b 2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close aOs possible to the device power supply pins. Other EMC rec- ommendations are given in other sections (I/Os, RES ET, OSCx pin characteristics). - ) s Figure 56. EMC Recommended Star (Network Power Supply Connection 2) t c u ST62XX dVDD 10µF 0.1µF o VDD r POWERP ST6 DIGITALNOISE SUPPLY FILTERING eSOURCE (close to the MCU) VSS t e l o s b O 77/104 1

ST6208C/ST6209C/ST6210C/ST6220C EMC CHARACTERISTICS (Cont’d) 10.7.2 Absolute Electrical Sensitivity – S1 switches position from generator to R. Based on three different tests (ESD, LU and DLU) – A discharge from C through R (body resistance) L using specific measurement methods, the product to the ST6 occurs. is stressed in order to determine its performance in – S2 must be closed 10 to 100ms after the pulse terms of electrical sensitivity. For more details, re- delivery period to ensure the ST6 is not left in fer to the AN1181 application note. charge state. S2 must be opened at least 10ms 10.7.2.1 Electro-Static Discharge (ESD) prior to the delivery of the next pulse. Electro-Static Discharges (3 positive then 3 nega- Machine Model Test Sequence tive pulses separated by 1 second) are applied to – C is loaded through S1 by the HV pulse g)ener- the pins of each sample according to each pin L s combination. The sample size depends of the ator. ( t number of supply pins of the device (3 parts*(n+1) – S1 switches position from generatcor to ST6. u supply pin). Two models are usually simulated: Human Body Model and Machine Model. This test – A discharge from CL to the SdT6 occurs. o conforms to the JESD22-A114A/A115A standard. – S2 must be closed 10 to 100ms after the pulse r See Figure 57 and the following test sequences. delivery period to enPsure the ST6 is not left in charge state. S2 must be opened at least 10ms Human Body Model Test Sequence prior to the delievery of the next pulse. t e – C is loaded through S1 by the HV pulse gener- – R (machine resistance), in series with S2, en- L l ator. sureso a slow discharge of the ST6. s Absolute Maximum Ratings b O Symbol Ratings Conditions Maximum value 1) Unit - VESD(HBM) E(Hleucmtraon-s Btaotdicy d Misocdhealr)ge voltages ) TA=+25°C 2000 ( V V Electro-static discharge vcotltage T =+25°C 200 ESD(MM) (Machine Model) u A d Notes: o 1. Data based on characterrization results, not tested in production. P e Figure 57. Tytpical Equivalent ESD Circuits e l o s S1 R=1500Ω S1 b O R = 10k~ HIGHVOLTAGE HIGHVOLTAGE 1 PULSE ST6 PULSE ST6 0M GENERATOR CL=100pF S2 GENERATOR Ω CL=200pF S2 HUMANBODYMODEL MACHINEMODEL 78/104 1

ST6208C/ST6209C/ST6210C/ST6220C EMC CHARACTERISTICS (Cont’d) 10.7.2.2 Static and Dynamic Latch-Up ■ DLU: Electro-Static Discharges (one positive ■ LU: 3 complementary static tests are required then one negative test) are applied to each pin on 10 parts to assess the latch-up performance. of 3 samples when the micro is running to A supply overvoltage (applied to each power assess the latch-up performance in dynamic supply pin), a current injection (applied to each mode. Power supplies are set to the typical input, output and configurable I/O pin) and a values, the oscillator is connected as near as power supply switch sequence are performed possible to the pins of the micro and the on each sample. This test conforms to the EIA/ component is put in reset mode. This test JESD 78 IC latch-up standard. For more details, conforms to the IEC1000-4-2 and SAEJ1752/3 refer to the AN1181 application note. standards and is described in Figure 58. For ) more details, refer to the AN1181 apsplication note. ( t c Electrical Sensitivities u d Symbol Parameter Conditions o Class 1) r T =+25°C P A LU Static latch-up class A TA=+85°C e A DLU Dynamic latch-up class VDD=5V, fOSC=4MeHtz, TA=+25°C A l Notes: o 1. Class description: A Class is an STMicroelectronics internal specisfication. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it excebeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). O 2. Schaffner NSG435 with a pointed test finger. - ) s Figure 58. Simplified Diagram of the (ESD Generator for DLU t c u d RCoH=50MΩ RD=330Ω DISCHARGETIP VDD r P V SS e CS=150pF HVRELAY ST6 t e ESD ol GENERATOR2) DISCHARGE RETURNCONNECTION s b O 79/104 1

ST6208C/ST6209C/ST6210C/ST6220C EMC CHARACTERISTICS (Cont’d) 10.7.3 ESD Pin Protection Strategy Standard Pin Protection To protect an integrated circuit against Electro- To protect the output structure the following ele- Static Discharge the stress must be controlled to ments are added: prevent degradation or destruction of the circuit el- – A diode to V (3a) and a diode from V (3b) ements. The stress generally affects the circuit el- DD SS ements which are connected to the pads but can – A protection device between VDD and VSS (4) also affect the internal devices when the supply To protect the input structure the following ele- pads receive the stress. The elements to be pro- ments are added: tected must not receive excessive current, voltage – A resistor in series with the pad (1) or heating within their structure. ) – A diode to V (2a) and a diode from Vs (2b) An ESD network combines the different input and DD (SS output ESD protections. This network works, by al- – A protection device between VDD catnd VSS (4) lowing safe discharge paths for the pins subjected u to ESD stress. Two critical ESD stress cases are d presented in Figure 59 and Figure 60 for standard o pins. P r Figure 59. Positive Stress on a Standard Pad vs. V e SS t e V V DD l DD o s b (3a) (2a) O - (1) ) OUT (4) IN s ( Mainpath t c u (3b) (2b) Pathtoavoid d o r VSS P VSS Figure 60. Negaetive Stress on a Standard Pad vs. V DD t e V V l DD DD o s b (3a) (2a) O (1) OUT (4) IN Mainpath (3b) (2b) V V SS SS 80/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.8 I/O PORT PIN CHARACTERISTICS 10.8.1 General Characteristics Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A Symbol Parameter Conditions Min Typ 1) Max Unit V Input low level voltage 2) 0.3xV IL DD V V Input high level voltage 2) 0.7xV IH DD V =5V 200 400 V Schmitt trigger voltage hysteresis 3) DD mV hys V =3.3V 200 400 DD I Input leakage current VSS≤VIN≤VDD 0.1 1 s )μA L (no pull-up configured) ( t V =5V 40 110 3c50 R Weak pull-up equivalent resistor 4) V =V DD u kΩ PU IN SS VDD=3.3V 80 230 d 700 C I/O input pin capacitance 5o 10 pF IN r C I/O output pin capacitance P 5 10 pF OUT tf(IO)out Output high to low level fall time 5) CL=50pF e 30 ns tr(IO)out Output low to high level rise time 5) Between 10% and 90% e t 35 tw(IT)in External interrupt pulse time 6) ol 1 tCPU s Figure 61. Typical RPU vs. VDD with VIN = VSS b O Rpu [Khom] 350 - Ta=-4)0°C s 300 (Ta=25°C t 250 c Ta=95°C u Ta=125°C d 200 o r 150 P 100 e t e 50 l o 3 4 5 6 s b VDD [V] O Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The R pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, PU not tested in production. 5. Data based on characterization results, not tested in production. 6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. Figure 62. Two typical Applications with unused I/O Pin VDD ST62XX UNUSEDI/OPORT 10kΩ 10kΩ UNUSEDI/OPORT ST62XX 81/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORT PIN CHARACTERISTICS (Cont’d) 10.8.2 Output Driving Current Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A Symbol Parameter Conditions Min Max Unit IIO=+10µA, TA≤125°C 0.1 Output low level voltage for a standard I/O pin IIO=+3mA, TA≤125°C 0.8 (see Figure 63 and Figure 66) IIO=+5mA, TA≤85°C 0.8 IIO=+10mA, TA≤85°C 1.2 V 1) IIO=+10µA, TA≤125°C 0.1 s ) OL Output low level voltage for a high sink I/O pin =5VD IIIIOO==++71m0mAA, T, TA≤A1≤8255°°CC u c00t..88( V (see Figure 64 and Figure 67) VD IIO=+15mA, TA≤125°C d 1.3 IIO=+20mA, TA≤85°C o 1.3 r IIO=+30mA, TA≤85°CP 2 IIO=-10μA, TA≤1e25°C VDD-0.1 VOH 2) O(suetep uFti ghuigreh 6le5v aenl vdo Fltiagguere f o6r8 a)n I/O pin IIO=-3mA, eTAt≤125°C VDD-1.5 IIO=-5omlA, TA≤85°C VDD-1.5 s Notes: b 1. The I current sunk must always respect the absolute maOximum rating specified in Section 10.2.2 and the sum of I IO IO (I/O ports and control pins) must not exceed IVSS. - 2. ITIOh e(I /IOIO pcourrtrse natn sdo cuorncetr oml puisnts a) lwmauysst nreost peexccte teshde) IaV bDsDo. lTurteu em oapxeimn udmra irna tIi/nOg psinpse cdifoieeds inno St heacvtieo nV 1O0H..2.2 and the sum of ( t c Figure 63. Typical V at V =u 5V (standard) Figure 64. Typical V at V = 5V (high-sink) OL DD OL DD d o Vol [mV] at Vdd=5V r Vol [V] at Vdd=5V P 1 1000 Ta=-40°Ce Ta=95°C Ta=-40°C Ta=95°C t 0.8 e 800 Tla=25°C Ta=125°C Ta=25°C Ta=125°C o 0.6 60s0 b 0.4 O 400 0.2 200 0 0 0 2 4 6 8 10 0 4 8 12 16 20 Iio [mA] Iio [mA] 82/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 65. Typical V at V = 5V OH DD Voh [V] at Vdd=5V 5 4.5 ) Ta=-40°C Ta=95°C s 4 ( t c Ta=25°C Ta=125°C u d 3.5 o -8 -6 -4 -2 0 r P Iio [mA] e t e Figure 66. Typical V vs V (standard I/Os) OL DD l o s Vol [mV] at Iio=2mA Ta=-40°C Ta=95°C Vobl [mV] at Iio=5mA Ta=-40°C Ta=95°C O 350 700 Ta=25°C Ta=125°C Ta=25°C Ta=125°C - 300 s ) 600 ( t c 250 500 u d 200 o 400 r P 150 e 300 3 t 4 5 6 3 4 5 6 e l VDD [V] VDD [V] o s Fbigure 67. Typical V vs V (high-sink I/Os) OL DD O Vol [V] at Iio=8mA Vol [V] at Iio=20mA 0.55 Ta=-40°C Ta=95°C 1.8 Ta=-40°C Ta=95°C 0.5 1.6 Ta=25°C Ta=125°C 0.45 1.4 Ta=25°C Ta=125°C 0.4 1.2 0.35 1 0.3 0.8 0.25 0.6 0.2 0.4 3 4 5 6 3 4 5 6 VDD [V] VDD [V] 83/104 1

ST6208C/ST6209C/ST6210C/ST6220C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 68. Typical V vs V OH DD Voh [V] at Iio=-2mA Voh [V] at Iio=-5mA 6 6 5 5 4 4 ) Ta=-40°C Ta=95°C 3 Ta=-40°C Ta=9s5°C ( 3 t Ta=25°C Ta=125°C 2 Ta=25°C c Ta=125°C u d 2 1 o 3 4 5 6 3 4 5 6 r P VDD [V] VDD [V] e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 84/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.9 CONTROL PIN CHARACTERISTICS 10.9.1 Asynchronous RESET Pin Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A Symbol Parameter Conditions Min Typ 1) Max Unit V Input low level voltage 2) 0.3xV IL DD V V Input high level voltage 2) 0.7xV IH DD V Schmitt trigger voltage hysteresis 3) 200 400 mV hys V =5V 150 350 900 R Weak pull-up equivalent resistor 4) V =V DD kΩ ON IN SS VDD=3.3V 300 730 1900 s ) V =5V 2.8 ( RESD ESD resistor protection VIN=VSS DD ct kΩ V =3.3V DD u External pin or d t t Generated reset pulse duration CPU w(RSTL)out internal reset sources o μs r t External reset pulse hold time 5) P μs h(RSTL)in tg(RSTL)in Filtered glitch duration 6) e ns t e Notes: l 1. Unless otherwise specified, typical data are based on T =25°C and oV =5V. A DD s 2. Data based on characterization results, not tested in production. b 3. Hysteresis voltage between Schmitt trigger switching leveOls. Based on characterization results, not tested. 4. The R pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, ON not tested in production. - 5. All short pulse applied on RESET pin with a dur)ation below t can be ignored. s h(RSTL)in 6. The reset network protects the device aga(inst parasitic resets, especially in a noisy environment. 7. The output of the external reset circuit mcutst have an open-drain output to drive the ST6 reset pad. Otherwise the device can be damaged when the ST6 genuerates an internal reset (LVD or watchdog). d Figure 69. Typical R vs V with V =V ON o DD IN SS r P Ron [Kohm] e 1000 t e 900 Ta=-40°C Ta=95°C l o 800 Ta=25°C Ta=125°C s 700 b 600 O 500 400 300 200 100 3 4 5 6 VDD [V] 85/104 1

ST6208C/ST6209C/ST6210C/ST6220C CONTROL PIN CHARACTERISTICS (Cont’d) Figure 70. Typical Application with RESET pin 8) L A OPTIOECNXIRRTECESUREINTTA7L) VDD0.1μFVDD4.7kΩ RESET RESD1) RVPDUD fINT STOP MODE COUNTER2048 external clock cycles (IRNETsSEER)TNAL 0.1μF t WATCcHDOGRESET u LVDRESET d o r P e t e 10.9.2 NMI Pin l o Subject to general operating conditions for V , f , and sT unless otherwise specified. DD OSC A b Symbol Parameter COonditions Min Typ 1) Max Unit VVIL IInnppuutt hloigwh l elevveel lv vooltlataggee 2 2)) ) - 0.7xV 0.3xVDD V IH s DD V Schmitt trigger voltage hysteresi(s 3) 200 400 mV hys t c V =5V 40 100 350 R Weak pull-up equivalent ruesistor 4) V =V DD kΩ pull-up IN SS d VDD=3.3V 80 200 700 o Notes: r P 1. Unless otherwise specified, typical data are based on T =25°C and V =5V. A DD 2. Data based on ceharacterization results, not tested in production. 3. Hysteresis evotltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The Rl equivalent resistor is based on a resistive transistor. This data is based on characterization results, not opull-up tested in production. s b Figure 71. Typical R vs. V with V =V O pull-up DD IN SS Rpull-up [Kohm] 300 Ta=-40°C Ta=95°C 250 Ta=25°C Ta=125°C 200 150 100 50 3 4 5 6 VDD [V] 86/104 1

ST6208C/ST6209C/ST6210C/ST6220C CONTROL PIN CHARACTERISTICS (Cont’d) 10.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V , Refer to I/O port characteristics for more details on DD f , and T unless otherwise specified. the input/output alternate function characteristics OSC A (TIMER). 10.10.1 Watchdog Timer Symbol Parameter Conditions Min Typ Max Unit 3,072 196,608 )tINT s tw(WDG) Watchdog time-out duration fCPU=4MHz 0.768 49.152( ms t f =8MHz 0.384 24c.576 ms CPU u d 10.10.2 8-Bit Timer o r Symbol Parameter Conditions Min P Typ Max Unit fEXT Timer external clock frequency e0 fINT/4 MHz t VDD>4.5V e 125 ns tw Pulse width at TIMER pin VDD=3V ol 1 µs s b O - ) s ( t c u d o r P e t e l o s b O 87/104 1

ST6208C/ST6209C/ST6210C/ST6220C 10.11 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V , f , and T unless otherwise specified. DD OSC A Symbol Parameter Conditions Min Typ 1) Max Unit f Clock frequency 1.2 f MHz OSC OSC V Conversion range voltage 2) V V V AIN SS DD R External input resistor 10 3) kΩ AIN f =8MHz 70 t Total convertion time OSC μs ADC f =4MHz 140 OSC 2 4 )t t Stabilization time 4) s CPU STAB f =8MHz 3.25 6.5 ( µs OSC t c AD Analog input current during conver- u 1.0 µA I sion d o AC Analog input capacitance 2 5 pF IN r P Notes: e 1. Unless otherwise specified, typical data are based on T =25°C and V =5V. A DD t 2. The ADC refers to V and V . e DD SS 3. Any added external serial resistor will downgrade the ADC accuracy (eoslpecially for resistance greater than 10kΩ). Data based on characterization results, not tested in production. s 4. As a stabilization time for the AD converter is required, the firsbt conversion after the enable can be wrong. O Figure 72. Typical Application with ADC - ) s RAIN (AINx r≈150Ω t VAIN c u ADC d 10pF 10MΩ o r P e t e ST62XX l o s b O Note: ADC not present on some devices. See device summary on page 1. 88/104 1

ST6208C/ST6209C/ST6210C/ST6220C 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Conditions Min Typ. Max Unit ±2, fosc>1.2MHz |E | Total unadjusted error 1) 1.2 T ±4, fosc>32KHz EO Offset error 1) V =5V 2) 0.72 E Gain Error 1) f DD=8MHz -0.31 LSB G OSC |E | Differential linearity error 1) 0.54 D |EL| Integral linearity error 1) s ) ( Notes: t c 1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout u the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: d - Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage is lower than the specified limits). o - Pure digital pins must have a negative injection less than 1mA. In addition, it is recommrended to inject the current as P far as possible from the analog input pins. 2. Data based on characterization results over the whole temperature range, moneitored in production. t e l o Figure 73. ADC Accuracy Characteristics s b O 255 Digital Result ADCDR - EG (1) Example of an actual transfer curve ) (2) The ideal transfer curve 254 VDDA–VSSA s (3) End point correlation line 253 1LSBIDEAL=----------------2---5----6------------------ t( c u (2) E =Total Unadjusted Error: maximum deviation dET beTtween the actual and the ideal transfer curves. 7 o (3) E =Offset Error: deviation between the first actual O r (1) transition and the first ideal one. 6 P E =Gain Error: deviation between the last ideal G 5 e transition and the last actual one. 4 EeOt EL EbeDt=wDeieffne raecnttuiaall Lsitneepasr iatyn dE rtrhoer :i dmeaaxl iomnuem. deviation 3 ol ED EbeLt=wIneteeng raanl yL iancetauraitl yt raEnrrsoitri:o nm aanxdim tuhme ednedv ipaotioinnt 2s correlation line. b 1LSB 1 IDEAL O V (LSB ) in IDEAL 0 1 2 3 4 5 6 7 253 254 255 256 V V SSA DDA Note: ADC not present on some devices. See device summary on page 1. 89/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11 GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 74. 20-Pin Plastic Dual In-Line Package, 300-mil Width mm inches Dim. A2 A Min Typ Max Min Typ Max A 5.33 0.210 ) A1 L c A1 0.38 0.015 s ( A2 2.92 3.30 4.95 0.11t5 0.130 0.195 c b eB D1 b2 e b 0.36 0.46 0.56u 0.014 0.018 0.022 b2 1.14 1.52 d1.78 0.045 0.060 0.070 o c 0.20 0.25 0.36 0.008 0.010 0.014 r D D 24.P89 26.16 26.92 0.980 1.030 1.060 De1 0.13 0.005 e te 2.54 0.100 20 11 l eB 10.92 0.430 o E1 s E1 6.10 6.35 7.11 0.240 0.250 0.280 1 10 b L 2.92 3.30 3.81 0.115 0.130 0.150 O Number of Pins - N 20 ) s ( t Figure 75. 20-Pin Ceramic Side-Bcrazed Dual In-Line Package u d o mm inches r Dim. P Min Typ Max Min Typ Max A 3.63 0.143 e t A1 0.38 0.015 e B 3.56 0.46 0.56 0.1400.0180.022 l o B1 1.14 12.70 1.78 0.0450.5000.070 s b C 0.20 0.25 0.36 0.0080.0100.014 O D 24.8925.4025.910.9801.0001.020 D1 22.86 0.900 E1 6.99 7.49 8.00 0.2750.2950.315 e 2.54 0.100 G 6.35 6.60 6.86 0.2500.2600.270 G1 9.47 9.73 9.98 0.3730.3830.393 G2 1.14 0.045 L 2.92 3.30 3.81 0.1150.1300.150 S 12.70 0.500 Ø 4.22 0.166 CDIP20W Number of Pins N 20 90/104 1

ST6208C/ST6209C/ST6210C/ST6220C PACKAGE MECHANICAL DATA (Cont’d) Figure 76. 20-Pin Plastic Small Outline Package, 300-mil Width mm inches D h x 45× Dim. Min Typ Max Min Typ Max L A A 2.35 2.65 0.093 0.104 A1 c A1 0.10 0.30 0.004 0.012 a B e B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 )0.013 s D 12.60 13.00 0.496( 0.512 t E 7.40 7.60 0c.291 0.299 u e 1.27 0.050 d H 10.00 o 10.65 0.394 0.419 h 0.25r 0.75 0.010 0.030 E H P α 0° 8° 0° 8° e L 0.40 1.27 0.016 0.050 t e Number of Pins l o N 20 s b O - ) s Figure 77. 20-Pin Plastic Shrink Sma(ll Outline Package t c u d o mm inches D r Dim. P L Min Typ Max Min Typ Max e A2 A c A 2.00 0.079 A1 t A1 0.05 0.002 e lb h A2 1.65 1.75 1.85 0.065 0.069 0.073 o e s b 0.22 0.38 0.009 0.015 b c 0.09 0.25 0.004 0.010 O D 6.90 7.20 7.50 0.272 0.283 0.295 E 7.40 7.80 8.20 0.291 0.307 0.323 E1 5.00 5.30 5.60 0.197 0.209 0.220 e 0.65 0.026 E1 E θ 0° 4° 8° 0° 4° 8° L 0.55 0.75 0.95 0.022 0.030 0.037 Number of Pins N 20 91/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.2 THERMAL CHARACTERISTICS Symbol Ratings Value Unit Package thermal resistance (junction to ambient) DIP20 60 R °C/W thJA SO20 80 SSOP20 115 P Power dissipation 1) 500 mW D T Maximum junction temperature 2) 150 °C Jmax Notes: ) s 1. The power dissipation is obtained from the formula PD = PINT + PPORT where PINT is the chip internal pow(er (IDDxVDD) and P is the port power dissipation determined by the user. t PORT c 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA. u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 92/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.3 ECOPACK INFORMATION In order to meet environmental requirements, ST offers these devices in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. ECOPACK® specifica- tions, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 93/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 23. Suggested List of DIP20 Socket Types Same Package / Probe Adaptor / Socket Reference Socket Type Footprint DIP20 TEXTOOL 220-33-42 X Textool Table 24. Suggested List of SO20 Socket Types Same Package / Probe Adaptor / Socket Reference Socket Type Footprint ) s ENPLAS OTS-20-1.27-04 Open (Top SO20 t YAMAICHI IC51-0202-714 Clcamshell u Adapter from SO20 to DIP20 footprint EMU PROBE X d SMD to DIP (delivered with emulator) o Programming r Logical Systems PA20SO1-08H-6 P X Open Top Adapter e Table 25. Suggested List of SSOP20 Socket Types e t l o Same Package / Probe Adaptor / Socket Referensce Socket Type Footprint b SSOP20 ENPLAS OTS-20-0.65-01O X Open Top Programming Logical Systems PA20SS--OT-6 X Open Top Adapter ) s ( t c u d o r P e t e l o s b O 94/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.5 ORDERING INFORMATION The following section deals with the procedure for and also details the ST6 factory coded device transfer of customer codes to STMicroelectronics type. Figure 78. ST6 Factory Coded Device Types ST62T20CB6/CCC ROM code ) s ( t Temperature code: c 1: Standard 0 to +70 °C u 3: Automotive -40 to +125 °dC 6: Industrial -40 to +85 °oC r P Package type: B: Plastic DIP e D: Ceramic DIP (EPROM devices only) t M: Plasetic SOP N: Pllastic SSOP o T: Plastic TQFP s b Revision index: O B,C: Product Definition change L: Low Voltage Device - ) s ST6 Sub family ( t c Version Code: u No char: ROM d E: EPROM o P: FASTROM r T: OTP P e t Family e l o s b O 95/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.6 TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents 11.6.1 FASTROM version and the list of the selected FASTROM options. The ST62P08C/P09C/P10C and P20C are the The ROM contents are to be sent on diskette, or Factory Advanced Service Technique ROM (FAS- by electronic means, with the hexadecimal file TROM) versions of ST62T08C, T09C, T10C and generated by the development tool. All unused T20C OTP devices. bytes must be set to FFh. They offer the same functionality as OTP devices, The selected options are communicated to but they do not have to be programmed by the STMicroelectronics using the correctly filled OP- customer. The customer code must be sent to TION LIST appended. See page 97. STMicroelectronics in the same way as for ROM ) The STMicroelectronics Sales Organization will be devices. The FASTROM option list has thse same pleased to provide detailed information on con- options as defined in the programma(ble option t tractual points. byte of the OTP version. It also offecrs an identifier option. If this option is enabled, ueach FASTROM Listing Generation and Verification. When d device is programmed with a unique 5-byte STMicroelectronics receives the user’s ROM con- o number which is mapped at addresses 0F9Bh- tents, a computer listing is generated from it. This r 0F9Fh. The user musPt therefore leave these bytes listing refers exactly to the ROM contents and op- blanked. tions which will be used to produce the specified e MCU. The listing is then returned to the customer The identificattion number is structured as follows: e who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing ol0F9Bh T0 forms a part of the contractual agreement for the s 0F9Ch T1 b production of the specific customer MCU. 0F9Dh T2 O 0F9Eh T3 - 0F9Fh Test ID ) s ( with T0, T1, T2, T3 = time in seconds since 01/01/ t c 1970 and Test ID = Tester Identifier. u d o r P e t e l o s b O 96/104 1

ST6208C/ST6209C/ST6210C/ST6220C TRANSFER OF CUSTOMER CODE (Cont’d) ST6208C/09C/10C/20C/P08C/P09C/P10C/P20C MICROCONTROLLER OPTION LIST Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references: ) s Device: [ ] ST6208C (1 KB) [ ] ST6209C (1 KB) ( [ ] ST6210C (2 KB) [ ] ST6220C (4 KB) t c [ ] ST62P08C (1 KB) [ ] ST62P09C (1 KB) u [ ] ST62P10C (2 KB) [ ] ST62P20C (4 KB) d o Package: [ ] Dual in Line Plastic r [ ] Small Outline Plastic with conditioningP [ ] Shrink Small Outline Plastic with conditioning Conditioning option: [ ] Standard (Tube) [ ] Teape & Reel t Temperature Range: [ ] 0°C to + 70°C e [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C l o s Marking: [ ] Standard marking b [ ] Special marking (ROM only): O PDIP20 (10 char. max): _ _ _ _ _ _ _ _ _ _ SO20 (8 char. max): _ _ _ _ _ _ _ _ - S SOP20 (11 char. max): _ _ _ _ _ _ _ _ _ _ _ Authorized characters are letters, digits, '.', '-)', '/' and spaces only. s ( t Oscillator Safeguard: c [ ] Enabled [ ] Disabled Watchdog Selection: u [ ] Software Activation [ ] Hardware Activation d Timer pull-up: [ ] Enabled [ ] Disabled o NMI pull-up: [ ] Enabled [ ] Disabled r Oscillator SelectionP: [ ] Quartz crystal / Ceramic resonator [ ] RC network e t Readouet Protection: FASTROM: l o [ ] Enabled [ ] Disabled s ROM: b [ ] Enabled: O [ ] Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled Low Voltage Detector: [ ] Enabled [ ] Disabled External STOP Mode Control: [ ] Enabled [ ] Disabled Identifier (FASTROM only): [ ] Enabled [ ] Disabled Comments: Oscillator Frequency in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97/104 1

ST6208C/ST6209C/ST6210C/ST6220C 11.6.2 ROM VERSION ROM Readout Protection. If the ROM READOUT PROTECTION option is selected, a protection The ST6208C, 09C, 10C and 20C are mask pro- fuse can be blown to prevent any access to the grammed ROM version of ST62T08C, T09C, program memory content. T10C and T20C OTP devices. In case the user wants to blow this fuse, high volt- They offer the same functionality as OTP devices, selecting as ROM options the options defined in age must be applied on the VPP pin. the programmable option byte of the OTP version. Figure 80. Programming wave form Figure 79. Programming Circuit V 0 .5s min ) PP s ( 100 µs max t 5 V 4 .7 µF c u 15 d 14V typ o 1 00nF 10 r P 5 e V DD t e V SS ol s V b PP 150 µs typ O PROTECT VPP 14 V- 400mA ) s max 100nF ZPD15( t 15Vc u d 4mA typ o t r P VR02001 VR02003 e t e l Note: ZPoD15 is used for overvoltage protection s b O 98/104 1

ST6208C/ST6209C/ST6210C/ST6220C 12 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware the ST6 from third party manufacturers can be ob- and software development tools for the ST6 micro- tain from the STMicroelectronics Internet site: controller family. Full details of tools available for ➟ http://www.st.com. Table 26. Dedicated Third Parties Development Tools Third Party 1) Designation ST Sales Type Web site address ST-REALIZER II: Graphical Schematic ACTUM based Development available from STREALIZER-II http://www.actum.com/ STMicroelectronics. ) Low cost emulator available from CEI- s CEIBO http://www.cei(bo.com/ BO. t c This tool includes in the same environ- u ment: an assembler, linker, C compiler, d debugger and simulator. The assembler o package (plus limited C compiler) is free ST6RAIS-SWC/ r RAISONANCE P http://www.raisonance.com/ and can be downloaded from raisonance PC web site. The full version is available e both from STMicroelectronics and Raiso- t e nance. l o High end emulator available from s SOFTEC. b SOFTEC O http://www.softecmicro.com/ Gang programmer available from SOFTEC. - ADVANCED EQUIPMENT ) http://www.aec.com.tw/ s ADVANCED TRANSDATA ( http://www.adv-transdata.com/ t BP MICROSYSTEMS c http://www.bpmicro.com/ u DATA I/O d http://www.data-io.com/ DATAMAN o http://www.dataman.com/ r EE TOOLS P http://www.eetools.com/ ELNECe http://www.elnec.com/ HI-LO SeYtSTEMS http://www.hilosystems.com.tw/ ICE oTlECHNOLOGY http://www.icetech.com/ s LEAP http://www.leap.com.tw/ Single and gang programmers b O LLOYD RESEARCH http://www.lloyd-research.com/ http://www.chipprogram- LOGICAL DEVICES mers.com/ MQP ELECTRONICS http://www.mqp.com/ NEEDHAMS http://www.needhams.com/ ELECTRONICS STAG PROGRAMMERS http://www.stag.co.uk/ SYSTEM GENERAL CORP http://www.sg.com.tw TRIBAL MICROSYSTEMS http://www.tribalmicro.com/ XELTEK http://www.xeltek.com/ Note 1: For latest information on third party tools, please visit our Internet site: ➟ http://www.st.com. 99/104 1

ST6208C/ST6209C/ST6210C/ST6220C DEVELOPMENT TOOLS (Cont’d) STMicroelectronics Tools Four types of development tool are offered by ST, all of them connect to a PC via a parallel or serial port: see Table 27 and Table 28 for more details. Table 27. STMicroelectronics Tool Features Emulation Type Programming Capability Software Included Device simulation (limited MCU CD ROM with: ST6 Starter Kit emulation as interrupts are Yes (DIP packages only) – Rkit-ST6 from Raisonance not supported) – ST6 Assembly toolchain) s In-circuit powerful emula- – WGDB6 powerful Source Level ( ST6 HDS2 Emulator tion features including No Debugger for Wint 3.1, Win 95 trace/ logic analyzer and NT c u – Various software demo ver- d ST6 EPROM No Yes sionso. Programmer Board – Wrindows Programming Tools Pfor Win 3.1, Win 95 and NT e Table 28. Dedicated STMicroelectronics Development Tools t e Supported Products ST6 Starter Kit ST6 HDSl2 Emulator ST6 Programming Board o sComplete: ST6208C, ST6209C, ST6210C b ST62GP-EMU2 ST622XC-KIT ST62E2XC-EPB and ST6220C O Dedication board: ST62GP-DBE - ) s ( t c u d o r P e t e l o s b O 100/104 1

ST6208C/ST6209C/ST6210C/ST6220C 13 ST6 APPLICATION NOTES IDENTIFICATION DESCRIPTION MOTOR CONTROL AN392 MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS AN414 CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU AN416 SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC AN422 IMPROVES UNIVERSAL MOTOR DRIVE AN863 IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR BATTERY MANAGEMENT ) s AN417 FROM NICD TO NIMH FAST BATTERY CHARGING ( t c AN433 ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER u AN859 AN INTELLIGENT ONE HOUR MULTICHARGER FOR Li-Ion, NiMH andd NiCd BATTERIES o HOME APPLIANCE r AN674 MICROCONTROLLERS IN HOME APPLIANCES: A SOFT REVP OLUTION AN885 ST62 MICROCONTROLLERS DRIVE HOME APPLIANCeE MOTOR TECHNOLOGY t GRAPHICAL DESIGN e l AN676 BATTERY CHARGER USING THE ST6-REALIoZER s AN677 PAINLESS MICROCONTROLLER CODE BY GRAPHICAL APPLICATION DESCRIPTION b AN839 ANALOG MULTIPLE KEY DECODINOG USING THE ST6-REALIZER AN840 CODED LOCK USING THE ST6 -REALIZER - AN841 A CLOCK DESIGN USING) THE ST6-REALIZER s AN842 7 SEGMENT DISPLA(Y DRIVE USING THE ST6-REALIZER t COST REDUCTION c u AN431 USING STd6 ANALOG INPUTS FOR MULTIPLE KEY DECODING AN594 DIRECoT SOFTWARE LCD DRIVE WITH ST621X AND ST626X r AN672 OPPTIMIZING THE ST6 A/D CONVERTER ACCURACY AN673 e REDUCING CURRENT CONSUMPTION AT 32KHZ WITH ST62 DESIGN IMPRtOVEMENTS e AN420 l EXPANDING A/D RESOLUTION OF THE ST6 A/D CONVERTER o AN4s32 USING ST62XX I/O PORTS SAFELY b AN434 MOVEMENT DETECTOR CONCEPTS FOR NOISY ENVIRONMENTS O AN435 DESIGNING WITH MICROCONTROLLERS IN NOISY ENVIRONMENTS AN669 SIMPLE RESET CIRCUITS FOR THE ST6 AN670 OSCILLATOR SELECTION FOR ST62 AN671 PREVENTION OF DATA CORRUPTION IN ST6 ON-CHIP EEPROM AN911 ST6 MICRO IS EMC CHAMPION AN975 UPGRADING FROM ST625X/6XB TO ST625X/6XC AN1015 SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE PERIPHERAL OPERATIONS AN590 PWM GENERATION WITH ST62 AUTO-RELOAD TIMER AN591 INPUT CAPTURE WITH ST62 AUTO-RELOAD TIMER AN592 PLL GENERATION USING THE ST62 AUTO-RELOAD TIMER AN593 ST62 IN-CIRCUIT PROGRAMMING AN678 LCD DRIVING WITH ST6240 101/104 1

ST6208C/ST6209C/ST6210C/ST6220C IDENTIFICATION DESCRIPTION AN913 PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER AN914 USING ST626X SPI AS UART AN1016 ST6 USING THE ST623XB/ST628XB UART AN1050 ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER AN1127 USING THE ST62T6XC/5XC SPI IN MASTER MODE GENERAL MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY AN683 TOPICS ) s AN886 SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER ( t AN887 MAKING IT EASY WITH MICROCONTROLLERS c u AN898 EMC GENERAL INFORMATION d AN899 SOLDERING RECOMMENDATIONS AND PACKAGING INFORMAToION r AN900 INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY P AN901 EMC GUIDE-LINES FOR MICROCONTROLLER - BASED APPLICATIONS e AN902 QUALITY AND RELIABILITY INFORMATION t e AN912 A SIMPLE GUIDE TO DEVELOPMENT TOOLSol AN1181 ELECTROSTATIC DISHARGE SENSITIVITsY MEASUREMENT b O - ) s ( t c u d o r P e t e l o s b O 102/104 1

ST6208C/ST6209C/ST6210C/ST6220C 14 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Main Changes Date Removed references to 32768 clock cycle delay in Section 5 and Section 6 3.3 Changed note 2 in Section 10.6.2 on page 76: added text on data retention and program- October 03 mability. Updated device summary on page 1 4 Replaced soldering information by ECOPACK® information in Section 11.3 on page 93 January 2009 Updated disclaimer on last page ) s ( t c 15 TO GET MORE INFORMATION u d To get the latest information on this product please use the STMicroelectronics web server. o ➟ http://www.st.com/ r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 103/104 1

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