ST1S32 4 A DC step-down switching regulator Datasheet — production data Features ■ 4 A DC output current ■ 2.8 V to 5.5 V input voltage ■ Output voltage adjustable from 0.8 V ■ 1.5 MHz switching frequency ■ Internal soft-start and enable VFDFPN 8 4x4x1.0 ■ Integrated 60 mΩ and 45 mΩ Power MOSFETs ■ All ceramic capacitor Description ■ Power Good (POR) The ST1S32 is an internally compensated 1.5 ■ Cycle-by-cycle current limiting MHz fixed-frequency PWM synchronous step- ■ Current foldback short-circuit protection down regulator. The ST1S32 operates from 2.8 V ■ VFDFPN 8 4x4x1.0 package to 5.5 V input, while it regulates an output voltage as low as 0.8 V and up to V . IN Applications The ST1S32 integrates a 60 mΩ high-side switch and a 45 mΩ synchronous rectifier, allowing very ■ µP/ASIC/DSP/FPGA core and I/O supplies high efficiency with very low output voltages. ■ Point of Load for: STB, TV, DVD The peak current mode control with internal ■ Optical storage, hard disk drives, printers, compensation delivers a very compact solution audio/graphic cards with a minimum component count. The ST1S32 is available in 4 mm x 4 mm, 8-lead VFDFPN package. Figure 1. Application circuit L VIN VOUT VINSW SW VINA Cin_a R3 R1 ST1S32 EN VFB PG Cout Cin_sw R2 GND AM12608V1 May 2012 Doc ID 023246 Rev 1 1/29 This is information on a product in full production. www.st.com 29

Contents ST1S32 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 Doc ID 023246 Rev 1

ST1S32 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) 1.2 Pin description Table 1. Pin description No. Type Description 1 VINA Unregulated DC input voltage. Enable input. With EN higher than 1.5 V the device in ON and with EN 2 EN lower than 0.5 V the device is OFF. Feedback input. Connecting the output voltage directly to this pin the 3 FB output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from V to the FB pin. OUT 4 AGND Ground. Open drain Power Good (POR) pin. It is released (open drain) when the output voltage is higher than 0.92 * V with a delay of 170 us. If the OUT 5 PG output voltage is below 0.92 * VOUT, the POR pin goes to low impedance immediately. If not used, it can be left floating or to GND. 6 VINSW Power input voltage. 7 SW Regulator output switching pin. 8 PGND Power Ground. Doc ID 023246 Rev 1 3/29

Maximum ratings ST1S32 2 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Input voltage -0.3 to 7 IN V Enable voltage -0.3 to V EN IN V Output switching voltage -1 to V V SW IN V Power-on reset voltage (Power Good) -0.3 to V PG IN V Feedback voltage -0.3 to 1.5 FB P Power dissipation at T < 60 °C 2.25 W TOT A T Operating junction temperature range -40 to 150 °C OP T Storage temperature range -55 to 150 °C stg 2.1 Thermal data Table 3. Thermal data Symbol Parameter Value Unit Maximum thermal resistance junction- R 40 °C/W thJA ambient (1) 1. Package mounted on demonstration board. 4/29 Doc ID 023246 Rev 1

ST1S32 Electrical characteristics 3 Electrical characteristics T =25 °C, V =5 V, unless otherwise specified. J IN Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. Max. Operating input voltage V (1) 2.8 5.5 IN range V V Turn-on V threshold (1) 2.4 INON CC V Turn-off V threshold (1) 2.0 INOFF CC High-side switch on- R -P I =300 mA 60 mΩ DSON resistance SW Low-side switch on- R -N I =300 mA 45 mΩ DSON resistance SW I Maximum limiting current (2) 5.0 A LIM Oscillator F Switching frequency 1.2 1.5 1.9 MHz SW D Maximum duty cycle (2) 95 100 % MAX Dynamic characteristics 0.792 0.8 0.808 V Feedback voltage V FB Io=10 mA to 4 A(1) 0.776 0.8 0.824 %V / OUT Reference load regulation Io=10 mA to 4 A(2) 0.2 0.6 % ΔI OUT %V / OUT Reference line regulation V = 2.8 V to 5.5 V (2) 0.2 0.3 % ΔV IN IN DC characteristics Duty cycle=0, no load I Quiescent current 630 1200 μA Q V =1.2 V FB Total standby quiescent I OFF 10 μA QST-BY current Enable Device ON level 1.5 V EN threshold voltage V EN Device OFF level 0.5 I EN current 0.1 μA EN Doc ID 023246 Rev 1 5/29

Electrical characteristics ST1S32 Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Power Good PG threshold 92 %V FB PG hystereris 30 50 PG mV PG output voltage low Isink= 6 mA open drain 400 PG rise delay 170 μs Soft-start T Soft-start duration 400 μs SS Protection Thermal shutdown 150 T °C SHDN Hystereris 20 1. Specifications referred to T from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range J are assured by design, characterization and statistical correlation. 2. Guaranteed by design. 6/29 Doc ID 023246 Rev 1

ST1S32 Functional description 4 Functional description The ST1S32 is based on a “peak current mode”, constant frequency control. The output voltage V is sensed by the Feedback pin (FB) compared to an internal reference (0.8 V) OUT providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure3. They are: ● A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability ● The soft-start circuitry to limit inrush current during the startup phase ● The transconductance error amplifier ● The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches ● The drivers for embedded P-channel and N-channel Power MOSFET switches ● The high-side current sensing block ● The low-side current sense to implement diode emulation ● A voltage monitor circuitry (UVLO) that checks the input and internal voltages ● A thermal shutdown block, to prevent thermal run-away. Figure 3. Block diagram Doc ID 023246 Rev 1 7/29

Functional description ST1S32 4.1 Soft-start The soft-start is essential to assure the correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage rise monothonically. The soft-start is managed by ramping the reference of the error amplifier from 0 V to 0.8 V. The internal soft-start capacitor is charged with a resistor to 0.8 V, then the FB pin follows the reference so that the output voltage is regulated to rise to the set value monothonically. 4.2 Error amplifier and control loop stability The error amplifier provides the error signal to be compared with the high-side switch current through the current sense circuitry. The non-inverting input is connected with the internal 0.8 V reference, whilst the inverting input is the FB pin. The compensation network is internal and connected between the E/A output and GND. The error amplifier of the ST1S32 is a transconductance operational amplifier, with high bandwidth and high output impedance. The characteristics of the uncompensated error amplifier are: Table 5. Characteristics of the uncompensated error amplifier Description Value DC gain 94 dB gm 238 μA/V Ro 96 MΩ The ST1S32 embeds the compensation network that assures the stability of the loop in the whole operating range. Here below are all the tools needed to check the loop stability. In Figure 4. the simple small signal model for the peak current mode control loop is shown. 8/29 Doc ID 023246 Rev 1

ST1S32 Functional description Figure 4. Block diagram of the loop for the small signal analysis VIN Slope GCO(s) Compensation High side Switch G (s) L DIV Current sense VOUT Logic Cout And Low side Driver Switch PWM comparator 0.8V R1 V C V FB Rc Error Amp R2 Cc G (s) EA AM12609V1 Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, G (s); CO 2. from output (V ) to the FB pin, G (s); OUT DIV 3. from the FB pin to control (output of E/A), G (s). EA The transfer function from control to output G (s) results: CO Equation 1 ⎛ s⎞ G (s) = R-----L---O----A----D--⋅ --------------------------------------------------1---------------------------------------------------⋅ -⎝--1-----+-----ω-------z----⎠--⋅ F (s) CO R R ⋅ T ⎛ s⎞ H i 1+-----o---u---t---L---------S----W---⋅ [mC⋅ (1–D)–0.5] ⎝1+ω----p-⎠ where R represents the load resistance, R the equivalent sensing resistor of the LOAD i current sense circuitry (0.369 Ω), ω the single pole introduced by the LC filter and ω the p z zero given by the ESR of the output capacitor. F (s) accounts for the sampling effect performed by the PWM comparator on the output of H the error amplifier that introduces a double pole at one half of the switching frequency. Equation 2 ω = ----------------1------------------ Z ESR⋅ C OUT Doc ID 023246 Rev 1 9/29

Functional description ST1S32 Equation 3 ω = -------------------1---------------------+m------C-----⋅-----(---1-----–----D-----)---–-----0---.--5-- p R ⋅ C L⋅ C ⋅ f LOAD OUT OUT SW where: Equation 4 ⎛ S ⎜m = 1+-----e- ⎜ C Sn ⎜ ⎜Se = Vpp⋅ fSW ⎜ ⎝⎜Sn = V-----I--N----–---L--V----O----U----T--⋅ Ri S represents the ON-time slope of the sensed inductor current, S the slope of the external n e ramp (V peak-to-peak amplitude - 0.535 V) that implements the slope compensation to PP avoid sub-harmonic oscillations at duty cycle over 50%. The sampling effect contribution F (s) is: H Equation 5 F (s) = ---------------------1---------------------- H 2 s s 1+---------------------+----- ωn⋅ QP ω2 n where: Equation 6 1 Q = ---------------------------------------------------------------- P π⋅ [m ⋅ (1–D)–0.5] C and Equation 7 ω = π⋅ f n SW The transfer function G (s) from V to FB results: DIV OUT R G (s) = ------------2-------- DIV R +R 1 2 The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. In Figure5, the small signal model of the error amplifier with the internal compensation network is shown. 10/29 Doc ID 023246 Rev 1

ST1S32 Functional description Figure 5. Small signal model for the error amplifier V FB Ro Co CRcc Cp Vd Gm*Vd Cc V REF AM11419v1 R and C introduce a pole and a zero in the open loop gain. C does not significantly affect C C P system stability and can be neglected. So, G (s) results: EA Equation 8 G ⋅ (1+s⋅ R ⋅ C ) G (s) = ----------------------------------------------------------------------------E---A----0------------------------------------c---------------c------------------------------------------------------------------------- EA s2⋅ R ⋅ (C +C )⋅ R ⋅ C +s⋅ (R ⋅ C +R ⋅ (C +C )+R ⋅ C )+1 0 0 p c c 0 c 0 0 p c c where G = G · R EA m o The poles of this transfer function are (if C >> C +C ): c 0 P Equation 9 1 f = ------------------------------------------ P LF 2⋅ π⋅ R ⋅ C 0 c Equation 10 1 f = ------------------------------------------------------------ P HF 2⋅ π⋅ R ⋅ (C +C ) c 0 p whereas the zero is defined as: Equation 11 1 f = ------------------------------------------ Z 2⋅ π⋅ R ⋅ C c c The embedded compensation network is R =80 kΩ, C =55 pF while C and C can be C C P O Ω, considered as negligible. The error amplifier output resistance is 212 M so the relevant singularities are: Doc ID 023246 Rev 1 11/29

Functional description ST1S32 Equation 12 f = 36, 2 kHz f = 30 Hz Z P LF So, closing the loop, the loop gain G (s) is: LOOP Equation 13 G (s) = G (s)⋅ G (s)⋅ G (s) LOOP CO DIV EA Example: VIN=5 V, VOUT=1.2 V, Iomax=4 A, L=1.0 uH, Cout=47 uF (MLCC), R1=10 kΩ, R2=20 kΩ (see Section5.2 and Section5.3 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure6. The bandwidth is 117 kHz and the phase margin is 63 degrees. Figure 6. Module Bode plot 120 102 84 66 B] 48 d e [ ul 30 d o M 12 6 24 42 60 0.1 1 10 100 1.103 1.104 1.105 1.106 1.107 Frequency [Hz] AM11420v1 12/29 Doc ID 023246 Rev 1

ST1S32 Functional description Figure 7. Phase Bode plot 10 17.5 45 72.5 e s ha 100 P 127.5 155 182.5 210 0.1 1 10 100 1.103 1.104 1.105 1.106 1.107 Frequency [Hz] AM11421v1 4.3 Overcurrent protection The ST1S32 implements overcurrent protection sensing the current flowing through the high-side current switch. If the current exceeds the overcurrent threshold, the high-side is turned off, implementing a cycle-by-cycle current limitation. Since the regulation loop is no longer fixing the duty cycle, the output voltage is unregulated and the FB pin falls accordingly to the new duty cycle. If the FB pin falls below 0.2 V, the peak current limit is reduced to around 2.3 A and the switching frequency is reduced to assure that the inductor current is properly limited below the above mentioned value and above 1.2 A. This strategy is called “current foldback”. The mechanism to adjust the switching undercurrent foldback condition exploits the low-side current sense circuitry. If FB is lower than 0.2 V, the high-side Power MOSFET is turned off when the current reaches the current foldback threshold (2.3 A), then, after a proper dead time that avoids the cross conduction, the low-side is turned on until the low-side current is lower than a valley threshold (1.2 A). Once the low-side is turned off, the high-side is immediately turned on. In this way the frequency is adjusted to keep the inductor current ripple between the current foldback value (2.3 A) and valley threshold (1.2 A), therefore properly limiting the output current in case of overcurrent or short-circuit. It should be noted that in some cases, mainly with very low output voltages, the hard overcurrent can make the FB find the new equilibrium just over the current foldback threshold (0.2 V). In this case no frequency reduction is enabled, then the inductor current may diverge. That is, the ripple current during the minimum ON-time is higher than the ripple current during the OFF-time (the switching period minus the minimum ON-time), so pulse- by-pulse the average current is rising, exceeding the current limit. In order to avoid too high current, a further protection is activated when the high-side current exceeds a further current threshold (OCP2) slightly over the current limit (OCP1). If the current triggers the second threshold, the converter stops switching, the reference of the error amplifier is pulled down and then it restarts with a soft-start procedure. If the overcurrent condition is still active, the current foldback with frequency reduction properly limits the output current to 2.3 A. Doc ID 023246 Rev 1 13/29

Functional description ST1S32 4.4 Enable function The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 10 uA. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V compatible. IN 4.5 Light load operation With peak current mode control loop the output of the error amplifier is proportional to the load current. In the ST1S32, to increase light load efficiency, when the output of the error amplifier falls below a certain threshold, the high-side turn-on is prevented. This mechanism reduces the switching frequency at light load in order to save the switching losses. 4.6 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 oC. Once the junction temperature goes back to about 130 oC, the device restarts in normal operation. 14/29 Doc ID 023246 Rev 1

ST1S32 Application information 5 Application information 5.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 14 I = I ⋅ D–2-----⋅------D-----2-+-D----2-- RMS O η η2 where Io is the maximum DC output current, D is the duty cycle, and η is the efficiency. Considering η=1, this function has a maximum at D=0.5 and is equal to Io/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 15 VPP = C------------⋅I--O---F-----------⋅ ⎝⎛1–D--η--⎠⎞ ⋅ D+D--η--⋅ (1–D) +ESR⋅ IO IN SW where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case, the equation of C as a function of the target peak-to-peak voltage ripple (V ) can IN PP be written as follows: Equation 16 CIN = V-------------I⋅--O----F----------⋅ ⎝⎛1–D--η--⎠⎞ ⋅ D+D--η--⋅ (1–D) PP SW neglecting the small ESR of ceramic capacitors. Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum peak-to-peak input voltage (V ), the minimum input capacitor (C ) value is: PP_MAX IN_MIN Equation 17 I C = --------------------------O--------------------------- IN_MIN 2⋅ V ⋅ F PP_MAX SW Doc ID 023246 Rev 1 15/29

Application information ST1S32 Typically, C is dimensioned to keep the maximum peak-to-peak voltage ripple in the order IN of 1% of V . INMAX The placement of the input capacitor is very important in order to avoid noise injection and voltage spikes on the input voltage pin. So the C must be placed as close as possible to IN the VIN_SW pin. In Table6 some multi-layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Series Cap value (µF) Rated voltage (V) Murata GRM21 10 10 C3225 10 25 TDK C3216 10 16 Taiyo Yuden LMK212 22 10 A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1µF. 5.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by the following equation: Equation 18 V –V V ΔI = -----I-N--------------O----U----T--⋅ T = -----O----U---T--⋅ T L L ON L OFF where T is the conduction time of the high-side switch and T is the conduction time of ON OFF the low-side switch (in CCM, F =1/(T + T )). The maximum current ripple, given the SW ON OFF V , is obtained at maximum T , that is at minimum duty cycle (see previous section to OUT OFF calculate minimum duty). So by fixing ΔI =20% to 30% of the maximum output current, the L minimum inductance value can be calculated as: Equation 19 V 1–D L = ------O----U----T--⋅ --------------M-----I-N--- MIN ΔI F MAX SWMIN where F is the minimum switching frequency, according to Table4. SWMIN 16/29 Doc ID 023246 Rev 1

ST1S32 Application information The slope compensation, to prevent the sub-harmonic instability in peak current control loop, is internally managed and so fixed. This implies a further lower limit for the inductor value. To assure the sub-harmonic stability: Equation 20 L>V ⁄ (2• V •f ) out pp sw where V is the peak-to-peak value of the slope compensation ramp. pp The inductor value selected, based on Equation 19, must satisfy Equation 20. The peak current through the inductor is given by: Equation 21 ΔI IL, PK = IO+---2---L-- So if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (µH) Saturation current (A) XAL50xx 1.2 to 3.3 6.3 to 9 Coilcraft XAL60xx 2.2 to 5.6 7.4 to 11 MSS1048 1.0 to 3.8 6.5 to 11 WE-HCI 7030 1.5 to 4.7 7 to 14 Wurth WE-PD type L 1.5 to 3.5 6.4 to 10 DR73 1.0 to 2.2 5.5 to 7.9 Coiltronics DR74 1.5 to 3.3 5.4 to 8.35 5.3 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Doc ID 023246 Rev 1 17/29

Application information ST1S32 Equation 22 ΔI ΔV = ESR⋅ ΔI +--------------------M----A---X--------------- OUT MAX 8⋅ C ⋅ f OUT SW For the ceramic (MLCC) capacitor the capacitive component of the ripple dominates the resistive one. While for the electrolythic capacitor the opposite is true. As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Section4.2 help to check loop stability, given the application conditions, the value of the inductor and the output capacitor. In Table8 some capacitor series are listed. Table 8. Output capacitors Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) GRM32 22 to 100 6.3 to 25 < 5 Murata GRM31 10 to 47 6.3 to 25 < 5 ECJ 10 to 22 6.3 < 5 Panasonic EEFCD 10 to 68 6.3 15 to 55 Sanyo TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 < 5 5.4 Thermal dissipation The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of loss within the device are: a) conduction losses due to the on-resistance of the high-side switch (R ) and low- HS side switch (R ); these are equal to: LS Equation 23 P = R ⋅ I 2⋅ D+R ⋅ I 2⋅ (1–D) COND HS OUT LS OUT where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V and V , but actually it is slightly higher to compensate the losses of OUT IN the regulator. b) switching losses due to high-side Power MOSFET turn-on and off; these can be calculated as: 18/29 Doc ID 023246 Rev 1

ST1S32 Application information Equation 24 (T +T ) P = V ⋅ I ⋅ -------R----I-S----E-------------F---A----L---L----⋅ Fsw = V ⋅ I ⋅ T ⋅ F SW IN OUT 2 IN OUT SW SW where T and T are the overlap times of the voltage across the high-side power RISE FALL switch (V ) and the current flowing into it during turn-on and turn-off phases, as shown in DS Figure8. T is the equivalent switching time. For this device the typical value for the SW equivalent switching time is 20 ns. c) Quiescent current losses, calculated as: Equation 25 P = V ⋅ I Q IN Q where I is the quiescent current (I =1.2 mA maximum). Q Q The junction temperature T can be calculated as: J Equation 26 T = T +Rth ⋅ P J A JA TOT where T is the ambient temperature and P is the sum of the power losses just seen. A TOT Rth is the equivalent thermal resistance junction-to-ambient of the device; it can be JA calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth measured on the demonstration board described in Section5.5 is about JA 40 °C/W for the VFDFPN package. Doc ID 023246 Rev 1 19/29

Application information ST1S32 Figure 8. Switching losses V IN V SW I SW,HS V DS,HS P SW P P COND,HS COND,LS T T FALL RISE AM11422v1 5.5 Layout considerations The PC board layout of the switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes, to reduce interference generated by the high switching current loops and to optimize the reliability of the device. In order to avoid EMC problems, the high switching current loops must be as short as possible. In the buck converter there are two high switching current loops: during the ON- time, the pulsed current flows through the input capacitor, the high-side power switch, the inductor and the output capacitor; during the OFF-time, through the low-side power switch, the inductor and the output capacitor. The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current. In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the VINA pin to the input must be derived from VINSW. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so interference can be minimized by routing the feedback node with a very short trace and as far as possible from the high current paths. A single point connection from signal ground to power ground is suggested. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction-to-ambient; so a large ground plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. 20/29 Doc ID 023246 Rev 1

ST1S32 Application information Figure 9. PCB layout example Via to connect the thermal pad to bottom or inner ground plane Star center for common ground Short high switching current loop Input cap as close as possible to VINSW pin Short FB trace VINA derived from Cin to avoid dynamic voltage drop between VINA and VINSW AM11423v1 Doc ID 023246 Rev 1 21/29

Demonstration board ST1S32 6 Demonstration board Figure 10. Demonstration board schematic 5V VIN UU11 SSTT11SS3321 1 8 LL11 3.3V VIN_A PGND CC33 2 EN SW 7 Vout 11uu 3 6 22..22uuHH FB VIN_SW 4 5 CC11 CC22 AGND ePAD PGOOD 1100uu 2222uu RR33 RR11 1100kk RR22 6622..55kk CC44 2200kk NNCC 0 0 AM12610V1 Table 9. Component list Reference Part number Description Manufacturer U1 ST1S32PUR ST L1 DR74 2R2 2.2 µH, Isat=7 A Coiltronics C1 C3225X7RE106K 10 µF 25 V X7R TDK C2 C3225X7R1C226M 22 µF 16 V X7R TDK C3 1 µF 25 V X7R C4 NC R1 62.5 kΩ R2 20 kΩ R3 10 kΩ 22/29 Doc ID 023246 Rev 1

ST1S32 Demonstration board Figure 11. Demonstration board PCB top and bottom Doc ID 023246 Rev 1 23/29

Typical characteristics ST1S32 7 Typical characteristics Figure 12. Efficiency vs. I @ V = 5 V Figure 13. Zero load operation OUT IN VIN=5V VIN=5V, VOUT=1.2V, IO=0A Green: IL (100mA/div) Timescale 2us/div Yellow: SW (1V/div) Red: VOUT (20mV/div) Figure 14. 100 mA operation Figure 15. Efficiency vs. I @ V = 3.3 V OUT IN V =5V, V =1.2V, I =100mA IN OUT O VIN=3.3V Green: IL (100mA/div) Timescale 2us/div Yellow: SW (1V/div) Red: VOUT (20mV/div) 24/29 Doc ID 023246 Rev 1

ST1S32 Typical characteristics Figure 16. Overcurrent protection Figure 17. Short-circuit protection VIN=5V, VOUT=1.2V, ILOAD=0.5A -> 5.8A VIN=5.5V, VOUT=1.2V Green: IL (1A/div) Timescale 200us/div Green: IL (1A/div) Timescale 100us/div Yellow: SW (1V/div) Yellow: SW (1V/div) Red: VOUT (200mV/div) Red: VOUT (200mV/div) Doc ID 023246 Rev 1 25/29

Package mechanical data ST1S32 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 26/29 Doc ID 023246 Rev 1

ST1S32 Package mechanical data Table 10. VFQFPN8 (4x4x1.0 mm) mechanical data mm inch Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A3 0.20 0.0079 b 0.23 0.30 0.38 0.009 0.0117 0.0149 D 3.90 4.00 4.10 0.153 0.157 0.161 D2 2.82 3.00 3.23 0.111 0.118 0.127 E 3.90 4.00 4.10 0.153 0.157 0.161 E2 2.05 2.20 2.30 0.081 0.087 0.091 e 0.80 0.031 L 0.40 0.50 0.60 0.016 0.020 0.024 Figure 18. Package dimensions (cid:23)(cid:24)(cid:22)(cid:25)(cid:22)(cid:21)(cid:19)(cid:34) Doc ID 023246 Rev 1 27/29

Order codes ST1S32 Figure 19. Recommended footprint(a) AM12611V1 9 Order codes Table 11. Ordering information Order codes Package ST1S32PUR VFDFPN 4x4 8L 10 Revision history Table 12. Document revision history Date Revision Changes 31-May-2012 1 First release. a. Dimensions are in mm. 28/29 Doc ID 023246 Rev 1

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