32 Mbit (x16) Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet The SST39VF320xB devices are 2M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high-performance CMOS Super- Flash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF320xB write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Features (cid:129) Organizedas2Mx16 (cid:129) Security-IDFeature –SST:128bits;User:128words (cid:129) SingleVoltageReadandWriteOperations –2.7-3.6V (cid:129) FastReadAccessTime: –70ns (cid:129) SuperiorReliability –Endurance:100,000Cycles(Typical) (cid:129) LatchedAddressandData –Greaterthan100yearsDataRetention (cid:129) FastEraseandWord-Program: (cid:129) LowPowerConsumption(typicalvaluesat5MHz) –Sector-EraseTime:18ms(typical) –ActiveCurrent:6mA(typical) –Block-EraseTime:18ms(typical) –StandbyCurrent:4µA(typical) –Chip-EraseTime:35ms(typical) –AutoLowPowerMode:4µA(typical) –Word-ProgramTime:7µs(typical) (cid:129) HardwareBlock-Protection/WP#InputPin (cid:129) AutomaticWriteTiming –TopBlock-Protection(top32KWord) –InternalV Generation PP forSST39VF3202B –BottomBlock-Protection(bottom32KWord) (cid:129) End-of-WriteDetection forSST39VF3201B –ToggleBits –Data#Polling (cid:129) Sector-EraseCapability –Uniform2KWordsectors (cid:129) CMOSI/OCompatibility (cid:129) Block-EraseCapability (cid:129) JEDECStandard –Uniform32KWordblocks –FlashEEPROMPinAssignments (cid:129) Chip-EraseCapability (cid:129) PackagesAvailable –48-leadTSOP(12mmx20mm) (cid:129) Erase-Suspend/Erase-ResumeCapabilities –48-ballTFBGA(6mmx8mm) (cid:129) HardwareResetPin(RST#) (cid:129) Allnon-Pb(lead-free)devicesareRoHScompliant www.microchip.com ©2011SiliconStorageTechnology,Inc. DS25111A 12/11

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Product Description The SST39VF320xB devices are 2M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alter- nate approaches. The SST39VF320xB write (Program or Erase) with a 2.7-3.6V power supply. ThesedevicesconformtoJEDECstandardpinassignmentsforx16memories. Featuring high performance Word-Program, the SST39VF320xB devices provide a typical Word- Program time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Soft- ware Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of appli- cations, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retentionisratedatgreaterthan100years. The SST39VF320xB devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash tech- nologies. These devices also improve flexibility while lowering the cost for program, data, and con- figurationstorageapplications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro- gramtimesincreasewithaccumulatedErase/Programcycles. Tomeethigh-density,surfacemountrequirements,theSST39VF320xBdevicesareofferedin48-lead TSOPand48-ballTFBGApackages.SeeFigure2andFigure3forpinassignments. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 2

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Block Diagram SuperFlash X-Decoder Memory MemoryAddress AddressBuffer Latches Y-Decoder CE# OE# WE# ControlLogic WP# RESET# I/OBuffersandDataLatches DQ15-DQ0 1384B1.0 Figure 1: Functional Block Diagram A15 1 48 A16 A14 2 47 NC A13 3 46 VSS A12 4 45 DQ15 A11 5 44 DQ7 A10 6 43 DQ14 A9 7 42 DQ6 A8 8 41 DQ13 A19 9 StandardPinout 40 DQ5 A20 10 39 DQ12 WE# 11 TopView 38 DQ4 RST# 12 37 VDD DieUp NC 13 36 DQ11 WP# 14 35 DQ3 NC 15 34 DQ10 A18 16 33 DQ2 A17 17 32 DQ9 A7 18 31 DQ1 A6 19 30 DQ8 A5 20 29 DQ0 A4 21 28 OE# A3 22 27 VSS A2 23 26 CE# A1 24 25 A0 138448-tsopEKP1.0 Figure 2: Pin Assignments for 48-lead TSOP ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 3

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet TOPVIEW (ballsfacingdown) 6 A13 A12 A14 A15 A16 NC DQ15VSS 5 A9 A8 A10 A11 DQ7DQ14DQ13DQ6 4 WE# RST# NC A19 DQ5DQ12 VDD DQ4 3 NC WP# A18 A20 DQ2DQ10DQ11DQ3 2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 13844-tfbgaB1KP2.0 Figure 3: pin assignments for 48-ball TFBGA Table 1: Pin Description Symbol PinName Functions A 1-A AddressInputs Toprovidememoryaddresses. MS 0 DuringSector-EraseA -A addresslineswillselectthesector. MS 11 DuringBlock-EraseA -A addresslineswillselecttheblock. MS 15 DQ -DQ DataInput/output TooutputdataduringReadcyclesandreceiveinputdataduringWritecycles. 15 0 DataisinternallylatchedduringaWritecycle. Theoutputsareintri-statewhenOE#orCE#ishigh. WP# WriteProtect Toprotectthetop/bottombootblockfromErase/Programoperationwhen grounded. RST# Reset ToresetandreturnthedevicetoReadmode. CE# ChipEnable ToactivatethedevicewhenCE#islow. OE# OutputEnable Togatethedataoutputbuffers. WE# WriteEnable TocontroltheWriteoperations. V PowerSupply Toprovidepowersupplyvoltage:2.7-3.6V DD V Ground SS NC NoConnection Unconnectedpins. T1.025111 1. AMS=Mostsignificantaddress AMS=A20forSST39VF320xB ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 4

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written tothedeviceusingstandardmicroprocessorwritesequences.AcommandiswrittenbyassertingWE# lowwhilekeepingCE#low.TheaddressbusislatchedonthefallingedgeofWE#orCE#,whichever occurslast.ThedatabusislatchedontherisingedgeofWE#orCE#,whicheveroccursfirst. The SST39VF320xB also have the Auto Low Power mode which puts the device in a near standby modeafterdatahasbeenaccessedwithavalidReadoperation.ThisreducestheI activereadcur- DD rent from typically 9 mA to typically 4 µA. The Auto Low Power mode reduces the typical I active DD readcurrenttotherangeof2mA/MHzofReadcycletime.ThedeviceexitstheAutoLowPowermode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE#heldsteadilylow,untilthefirstaddresstransitionorCE#isdrivenhigh. Read TheReadoperationoftheSST39VF320xBiscontrolledbyCE#andOE#,bothhavetobelowforthe systemtoobtaindatafromtheoutputs.CE#isusedfordeviceselection.WhenCE#ishigh,thechipis deselected and only standby power is consumed. OE# is the output control and is used to gate data fromtheoutputpins.ThedatabusisinhighimpedancestatewheneitherCE#orOE#ishigh.Referto theReadcycletimingdiagramforfurtherdetails(Figure5). Word-Program Operation The SST39VF320xB are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. Thefirststepisthethree-byteloadsequenceforSoftwareDataProtection.Thesecondstepistoload word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of eitherCE#orWE#,whicheveroccursfirst.ThethirdstepistheinternalProgramoperationwhichisini- tiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figure 6 and Figure 7 for WE# and CE# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.Duringthecommandsequence,WP#shouldbestaticallyheldhighorlow. Sector/Block-Erase Operation TheSector-(orBlock-)Eraseoperationallowsthesystemtoerasethedeviceonasector-by-sector(or block-by-block)basis.TheSST39VF320xBofferbothSector-EraseandBlock-Erasemode.Thesector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequencewithSector-Erasecommand(50H)andsectoraddress(SA)inthelastbuscycle.TheBlock- Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H)andblockaddress(BA)inthelastbuscycle.Thesectororblockaddressislatchedonthefalling edgeofthesixthWE#pulse,whilethecommand(50Hor30H)islatchedontherisingedgeofthesixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera- tioncanbedeterminedusingeitherData#PollingorToggleBitmethods.SeeFigure11andFigure12 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 5

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet for timing waveforms and Figure 25 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the pro- tectedblockwillbeignored.Duringthecommandsequence,WP#shouldbestaticallyheldhighorlow. Erase-Suspend/Erase-Resume Commands TheErase-SuspendoperationtemporarilysuspendsaSector-orBlock-Eraseoperationthusallowing datatobereadfromanymemorylocation,orprogramdataintoanysector/blockthatisnotsuspended foranEraseoperation.TheoperationisexecutedbyissuingonebytecommandsequencewithErase- Suspend command (B0H). The device automatically enters read mode typically within 10 µs after the Erase-Suspendcommandhadbeenissued.Validdatacanbereadfromanysectororblockthatisnot suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blockswilloutputDQ togglingandDQ at‘1’.WhileinErase-Suspendmode,aWord-Programopera- 2 6 tionisallowedexceptforthesectororblockselectedforErase-Suspend. ToresumeSector-EraseorBlock-Eraseoperationwhichhasbeensuspendedthesystemmustissue Erase Resume command. The operation is executed by issuing one byte command sequence with EraseResumecommand(30H)atanyaddressinthelastBytesequence. Chip-Erase Operation The SST39VF320xB provide a Chip-Erase operation, which allows the user to erase the entire mem- oryarraytothe“1”state.Thisisusefulwhentheentiredevicemustbequicklyerased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command(10H)ataddress555Hinthelastbytesequence.TheEraseoperationbeginswiththerising edgeofthesixthWE#orCE#,whicheveroccursfirst.DuringtheEraseoperation,theonlyvalidreadis ToggleBitorData#Polling.SeeTable6forthecommandsequence,Figure10fortimingdiagram,and Figure25fortheflowchart.AnycommandsissuedduringtheChip-Eraseoperationareignored.When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should bestaticallyheldhighorlow. Write Operation Status Detection The SST39VF320xB provide two software means to detect the completion of a Write (Program or Erase)cycle,inordertooptimizethesystemwritecycletime.Thesoftwaredetectionincludestwosta- tus bits: Data# Polling (DQ ) and Toggle Bit (DQ ). The End-of-Write detection mode is enabled after 7 6 therisingedgeofWE#,whichinitiatestheinternalProgramorEraseoperation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ . In order to prevent spurious rejection, if an erroneous result occurs, the software 7 6 routine should include a loop to read the accessed location an additional two (2) times. If both reads arevalid,thenthedevicehascompletedtheWritecycle,otherwisetherejectionisvalid. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 6

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Data# Polling (DQ ) 7 WhentheSST39VF320xBareintheinternalProgramoperation,anyattempttoreadDQ willproduce 7 the complement of the true data. Once the Program operation is completed, DQ will produce true 7 data.NotethateventhoughDQ mayhavevaliddataimmediatelyfollowingthecompletionofaninternalWrite 7 operation,theremainingdataoutputsmaystillbeinvalid:validdataontheentiredatabuswillappearinsubse- quentsuccessiveReadcyclesafteranintervalof1µs.DuringinternalEraseoperation,anyattempttoread DQ will produce a ‘0’. Once the internal Erase operation is completed, DQ will produce a ‘1’. The 7 7 Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse.SeeFigure8forData#PollingtimingdiagramandFigure22foraflowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ will produce 6 alternating“1”sand“0”s,i.e.,togglingbetween1and0.WhentheinternalProgramorEraseoperation iscompleted,theDQ bitwillstoptoggling.Thedeviceisthenreadyforthenextoperation.ForSector- 6 , Block-, or Chip-Erase, the toggle bit (DQ ) is valid after the rising edge of sixth WE# (or CE#) pulse. 6 DQ will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro- 6 gramoperationisinitiatedinasector/blocknotselectedinErase-Suspendmode,DQ willtoggle. 6 An additional Toggle Bit is available on DQ , which can be used in conjunction with DQ to check 2 6 whetheraparticularsectorisbeingactivelyerasedorerase-suspended.Table2showsdetailedstatus bits information. The Toggle Bit (DQ ) is valid after the rising edge of the last WE# (or CE#) pulse of 2 Writeoperation.SeeFigure9forToggleBittimingdiagramandFigure22foraflowchart. Table 2: Write Operation Status Status DQ DQ DQ 7 6 2 NormalOperation StandardProgram DQ7# Toggle NoToggle StandardErase 0 Toggle Toggle Erase-Suspend ReadfromErase-SuspendedSector/Block 1 1 Toggle Mode ReadfromNon-Erase-SuspendedSector/ Data Data Data Block Program DQ7# Toggle N/A T2.0 25111 Note: DQ7,DQ6andDQ2requireavalidaddresswhenreadingstatusinformation. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 7

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Data Protection The SST39VF320xB provide both hardware and software features to protect nonvolatile data from inadvertentwrites. Hardware Data Protection Noise/GlitchProtection:AWE#orCE#pulseoflessthan5nswillnotinitiateawritecycle. V PowerUp/DownDetection:TheWriteoperationisinhibitedwhenV islessthan1.5V. DD DD Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre- ventsinadvertentwritesduringpower-uporpower-down. Hardware Block Protection TheSST39VF3202Bsupporttophardwareblockprotection,whichprotectsthetop32KWordblockof thedevice.TheSST39VF3201Bsupportbottomhardwareblockprotection,whichprotectsthebottom 32KWordblockofthedevice.TheBootBlockaddressrangesaredescribedinTable3.Programand Eraseoperationsarepreventedonthe32KWordwhenWP#islow.IfWP#isleftfloating,itisinternally heldhighviaapull-upresistor,andtheBootBlockisunprotected,enablingProgramandEraseopera- tionsonthatblock. Table 3: Boot Block Address Ranges Product AddressRange BottomBootBlock SST39VF3201B 000000H-007FFFH TopBootBlock SST39VF3202B 1F8000H-1FFFFFH T3.0 25111 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 8

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Hardware Reset (RST#) TheRST#pinprovidesahardwaremethodofresettingthedevicetoreadarraydata.WhentheRST# pinisheldlowforatleastT anyin-progressoperationwillterminateandreturntoReadmode.When RP, no internal Program/Erase operation is in progress, a minimum period of T is required after RST# RHR isdrivenhighbeforeavalidReadcantakeplace.SeeFigure17. The Erase or Program operation that has been interrupted needs to be re-initiated after the device resumesnormaloperationmodetoensuredataintegrity. Software Data Protection (SDP) TheSST39VF320xBprovidetheJEDECapprovedSoftwareDataProtectionschemeforalldataalter- ation operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three- bytesequence.Thethree-byteloadsequenceisusedtoinitiatetheProgramoperation,providingopti- mal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the SoftwareDataProtectionpermanentlyenabled.SeeTable6forthespecificsoftwarecommandcodes. DuringSDPcommandsequence,invalidcommandswillabortthedevicetoreadmodewithinT The RC. contentsofDQ -DQ canbeV orV ,butnoothervalue,duringanySDPcommandsequence. 15 8 IL IH Common Flash Memory Interface (CFI) The SST39VF320xB also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence. The systemcanalsoentertheCFIQuerymode,byusingtheone-bytesequencewith55HonAddressand 98H on Data Bus. Once the device enters the CFI Query mode, the system can read CFI data at the addressesgiveninTables7through9.ThesystemmustwritetheCFIExitcommandtoreturntoRead modefromtheCFIQuerymode. Product Identification The Product Identification mode identifies the devices as the SST39VF3201B and SST39VF3202B, and the manufacturer as SST. This mode may be accessed through software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when usingmultiplemanufacturersinthesamesocket.Fordetails,seeTable6forsoftwareoperation,Figure 13 for the Software ID Entry and Read timing diagram and Figure 23 for the Software ID Entry com- mandsequenceflowchart. Table 4: Product Identification Address Data Manufacturer’sID 0000H BFH DeviceID SST39VF3201B 0001H 235DH SST39VF3202B 0001H 235CH T4.0 25111 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 9

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Product Identification Mode Exit/CFI Mode Exit InordertoreturntothestandardReadmode,theSoftwareProductIdentificationmodemustbeexited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to theReadmode.ThiscommandmayalsobeusedtoresetthedevicetotheReadmodeafteranyinad- vertenttransientconditionthatapparentlycausesthedevicetobehaveabnormally,e.g.,notreadcor- rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program orEraseoperation.SeeTable6forsoftwarecommandcodes,Figure15fortimingwaveform,andFig- ure23andFigure24forflowcharts. Security ID TheSST39VF320xBdevicesoffera136wordSecurityIDspace.TheSecureIDspaceisdividedinto two segments - one factory programmed segment and one user programmed segment. The first seg- mentisprogrammedandlockedatSSTwitharandom128-bitnumber.The128-wordusersegmentis leftun-programmedforthecustomertoprogramasdesired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command.Todetectend-of-writefortheSECID,readthetogglebits.DonotuseData#Polling.Once thisiscomplete,theSecIDshouldbelockedusingtheUserSecIDProgramLock-Out.Thisdisables anyfuturecorruptionofthisspace.NotethatregardlessofwhetherornottheSecIDislocked,neither SecIDsegmentcanbeerased. TheSecureIDspacecanbequeriedbyexecutingathree-bytecommandsequencewithEnterSecID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com- mandshouldbeexecuted.RefertoTable6formoredetails. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 10

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Operations Table 5: Operation Modes Selection Mode CE# OE# WE# DQ Address Read V V V D A IL IL IH OUT IN Program V V V D A IL IH IL IN IN Erase V V V X1 Sectororblockaddress, IL IH IL XXHforChip-Erase Standby V X X HighZ X IH WriteInhibit X V X HighZ/D X IL OUT X X V HighZ/D X IH OUT ProductIdentification SoftwareMode V V V SeeTable6 IL IL IH T5.025111 1. XcanbeVILorVIH,butnoothervalue. Table 6: Software Command Sequence Command 1stBus 2ndBus 3rdBus 4thBus 5thBus 6thBus Sequence WriteCycle WriteCycle WriteCycle WriteCycle WriteCycle WriteCycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Data Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 4 50H X Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BA 4 30H X Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H QuerySecID5 555H AAH 2AAH 55H 555H 88H UserSecurityID 555H AAH 2AAH 55H 555H A5H WA6 Data Word-Program UserSecurityID 555H AAH 2AAH 55H 555H 85H XXH6 0000H ProgramLock-Out SoftwareID 555H AAH 2AAH 55H 555H 90H Entry7,8 CFIQueryEntry 555H AAH 2AAH 55H 555H 98H CFIQueryEntry 55H 98H SoftwareIDExit9,10 555H AAH 2AAH 55H 555H F0H /CFIExit/SecIDExit SoftwareIDExit9,10 XXH F0H /CFIExit/SecIDExit T6.025111 1. AddressformatA10-A0(Hex). AddressesA11-A20canbeVILorVIH,butnoothervalue,forCommandsequenceforSST39VF320xB. 2. DQ15-DQ8canbeVILorVIH,butnoothervalue,forCommandsequence 3. WA=ProgramWordaddress 4. SAXforSector-Erase;usesAMS-A11addresslines BAX,forBlock-Erase;usesAMS-A15addresslines AMS=Mostsignificantaddress AMS=A20forSST39VF320xB ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 11

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet 5. WithAMS-A4=0;SecIDisreadwithA3-A0, SSTIDisreadwithA3=0(Addressrange=000000Hto000007H), UserIDisreadwithA3=1(Addressrange=000008Hto000087H). LockStatusisreadwithA7-A0=0000FFH.Unlocked:DQ3=1/Locked:DQ3=0. 6. ValidWord-AddressesforSecIDarefrom000000H-000007Hand000008Hto000087H. 7. ThedevicedoesnotremaininSoftwareProductIDModeifpowereddown. 8. WithAMS-A1=0; SSTManufacturerID=00BFH,isreadwithA0=0, SST39VF3201BDeviceID=235DH,isreadwithA0=1, SST39VF3202BDeviceID=235CH,isreadwithA0=1. AMS=Mostsignificantaddress AMS=A20forSST39VF320xB 9. BothSoftwareIDExitoperationsareequivalent 10. Ifusersneverlockafterprogramming,SecIDcanbeprogrammedoverthepreviouslyunprogrammedbits(data=1) usingtheSecIDmodeagain(theprogrammed“0”bitscannotbereversedto“1”).ValidWord-AddressesforSecIDare from000000H-000007Hand000008Hto000087H. Table 7: CFI Query Identification String1 for SST39VF320xB Address Data Data 10H 0051H QueryUniqueASCIIstring“QRY” 11H 0052H 12H 0059H 13H 0002H PrimaryOEMcommandset 14H 0000H 15H 0000H AddressforPrimaryExtendedTable 16H 0000H 17H 0000H AlternateOEMcommandset(00H=noneexists) 18H 0000H 19H 0000H AddressforAlternateOEMextendedTable(00H=noneexits) 1AH 0000H T7.025111 1. RefertoCFIpublication100formoredetails. Table 8: System Interface Information for SST39VF320xB Address Data Data 1BH 0027H V Min(Program/Erase) DD DQ -DQ :Volts,DQ -DQ :100millivolts 7 4 3 0 1CH 0036H V Max(Program/Erase)DQ -DQ :Volts,DQ -DQ :100millivolts DD 7 4 3 0 1DH 0000H V min.(00H=noV pin) PP PP 1EH 0000H V max.(00H=noV pin) PP PP 1FH 0003H TypicaltimeoutforWord-Program2Nµs(23=8µs) 20H 0000H Typicaltimeoutformin.sizebufferprogram2Nµs(00H=notsupported) 21H 0004H TypicaltimeoutforindividualSector/Block-Erase2Nms(24=16ms) 22H 0005H TypicaltimeoutforChip-Erase2Nms(25=32ms) 23H 0001H MaximumtimeoutforWord-Program2Ntimestypical(21x23=16µs) 24H 0000H Maximumtimeoutforbufferprogram2Ntimestypical 25H 0001H MaximumtimeoutforindividualSector/Block-Erase2Ntimestypical(21x24=32ms) 26H 0001H MaximumtimeoutforChip-Erase2Ntimestypical(21x25=64ms) T8.0 25111 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 12

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Table 9: Device Geometry Information for SST39VF320xB Address Data Data 27H 0016H Devicesize=2NBytes(16H=22;222=4MByte) 28H 0001H FlashDeviceInterfacedescription;0001H=x16-onlyasynchronousinterface 29H 0000H 2AH 0000H Maximumnumberofbytesinmulti-bytewrite=2N(00H=notsupported) 2BH 0000H 2CH 0002H NumberofEraseSector/Blocksizessupportedbydevice 2DH 00FFH SectorInformation(y+1=Numberofsectors;zx256B=sectorsize) 2EH 0003H y=1023+1=1024sectors(03FFH=1023) 2FH 0010H 30H 0000H z=16x256Bytes=4KBytes/sector(0010H=16) 31H 003FH BlockInformation(y+1=Numberofblocks;zx256B=blocksize) 32H 0000H y=63+1=64blocks(003FH=63) 33H 0000H 34H 0001H z=256x256Bytes=64KBytes/block(0100H=256) T9.0 25111 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 13

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Electrical Specifications AbsoluteMaximumStressRatings (Applied conditions greater than those listed under “Absolute MaximumStressRatings”maycausepermanentdamagetothedevice.Thisisastressratingonlyand functional operation of the device at these conditions or conditions greater than those defined in the operationalsectionsofthisdatasheetisnotimplied.Exposuretoabsolutemaximumstressratingcon- ditionsmayaffectdevicereliability.) TemperatureUnderBias ............................................. -55°Cto+125°C StorageTemperature ................................................ -65°Cto+150°C D.C.VoltageonAnyPintoGroundPotential ............................-0.5VtoV +0.5V DD TransientVoltage(<20ns)onAnyPintoGroundPotential ..................-2.0VtoV +2.0V DD VoltageonA PintoGroundPotential .....................................-0.5Vto13.2V 9 PackagePowerDissipationCapability(T =25°C) .................................. 1.0W A SurfaceMountSolderReflowTemperature ........................... 260°Cfor10seconds OutputShortCircuitCurrent1 .................................................. 50mA 1. Outputsshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime. Table 10:Operating Range Range AmbientTemp V DD Commercial 0°Cto+70°C 2.7-3.6V Industrial -40°Cto+85°C 2.7-3.6V T10.125111 Table 11:AC Conditions of Test1 InputRise/FallTime OutputLoad 5ns C =30pF L T11.125111 1. SeeFigures19and20 ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 14

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Power Up Specifications All functionalities and DC specifications are specified for a V ramp rate of greater than 1V per 100 DD ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recommended V power-up to RESET# high time should be greater than 100 DD µstoensureaproperreset. TPU-READ 100µs VDD VDDmin 0V VIH RESET# TRHR 50ns CE# 1384F24.0 Figure 4: Power-Up Diagram ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 15

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Table 12:DC Operating Characteristics V = 2.7-3.6V1 DD Limits Symbol Parameter Min Max Units TestConditions I PowerSupplyCurrent Addressinput=V /V 2,atf=5MHz, DD ILT IHT V =V Max DD DD Read3 15 mA CE#=V ,OE#=WE#=V ,allI/Osopen IL IH ProgramandErase 45 mA CE#=WE#=V ,OE#=V IL IH I StandbyV Current 20 µA CE#=V ,V =V Max SB DD IHC DD DD I AutoLowPower 20 µA CE#=V ,V =V Max ALP ILC DD DD Allinputs=V orV WE#=V SS DD, IHC I InputLeakageCurrent 1 µA V =GNDtoV ,V =V Max LI IN DD DD DD I InputLeakageCurrent 10 µA WP#=GNDtoV orRST#=GNDto LIW DD onWP#pinandRST# V DD I OutputLeakageCurrent 1 µA V =GNDtoV ,V =V Max LO OUT DD DD DD V InputLowVoltage 0.8 V V =V Min IL DD DD V InputLowVoltage(CMOS) 0.3 V V =V Max ILC DD DD V InputHighVoltage 0.7V V V =V Max IH DD DD DD V InputHighVoltage(CMOS) V -0.3 V V =V Max IHC DD DD DD V OutputLowVoltage 0.2 V I =100µA,V =V Min OL OL DD DD V OutputHighVoltage V -0.2 V I =-100µA,V =V Min OH DD OH DD DD T12.025111 1. TypicalconditionsfortheActiveCurrentshownonthefrontpageofthedatasheetareaveragevaluesat25°C (roomtemperature),andVDD=3V.Not100%tested. 2. SeeFigure19 3. TheIDDcurrentlistedistypicallylessthan2mA/MHz,withOE#atVIH.TypicalVDDis3V. Table 13:Recommended System Power-up Timings Symbol Parameter Minimum Units T 1 Power-uptoReadOperation 100 µs PU-READ T 1 Power-uptoProgram/EraseOperation 100 µs PU-WRITE T13.025111 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameter. Table 14:Capacitance (TA = 25°C, f=1 Mhz, other pins open) Parameter Description TestCondition Maximum C 1 I/OPinCapacitance V =0V 10pF I/O I/O C 1 InputCapacitance V =0V 10pF IN IN T14.025111 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameter. Table 15:Reliability Characteristics Symbol Parameter MinimumSpecification Units TestMethod N 1,2 Endurance 10,000 Cycles JEDECStandardA117 END T 1 DataRetention 100 Years JEDECStandardA103 DR I 1 LatchUp 100+I mA JEDECStandard78 LTH DD T15.025111 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameter. 2. NENDenduranceratingisqualifiedasa10,000cycleminimumforthewholedevice.Asector-orblock-levelratingwould resultinahigherminimumspecification. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 16

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet AC Characteristics Table 16:Read Cycle Timing Parameters V = 2.7-3.6V DD Symbol Parameter Min Max Units T ReadCycleTime 70 ns RC T ChipEnableAccessTime 70 ns CE T AddressAccessTime 70 ns AA T OutputEnableAccessTime 35 ns OE T 1 CE#LowtoActiveOutput 0 ns CLZ T 1 OE#LowtoActiveOutput 0 ns OLZ T 1 CE#HightoHigh-ZOutput 16 ns CHZ T 1 OE#HightoHigh-ZOutput 16 ns OHZ T 1 OutputHoldfromAddressChange 0 ns OH T 1 RST#PulseWidth 500 ns RP T 1 RST#HighbeforeRead 50 ns RHR T 1,2 RST#PinLowtoReadMode 20 µs RY T16.025111 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthis parameter. 2. ThisparameterappliestoSector-Erase,Block-Erase,andProgramoperations. ThisparameterdoesnotapplytoChip-Eraseoperations. Table 17:Program/Erase Cycle Timing Parameters Symbol Parameter Min Max Units T Word-ProgramTime 10 µs BP T AddressSetupTime 0 ns AS T AddressHoldTime 30 ns AH T WE#andCE#SetupTime 0 ns CS T WE#andCE#HoldTime 0 ns CH T OE#HighSetupTime 0 ns OES T OE#HighHoldTime 10 ns OEH T CE#PulseWidth 40 ns CP T WE#PulseWidth 40 ns WP T 1 WE#PulseWidthHigh 30 ns WPH T 1 CE#PulseWidthHigh 30 ns CPH T DataSetupTime 30 ns DS T 1 DataHoldTime 0 ns DH T 1 SoftwareIDAccessandExitTime 150 ns IDA T Sector-Erase 25 ms SE T Block-Erase 25 ms BE T Chip-Erase 50 ms SCE T17.025111 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthis parameter. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 17

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet TRC TAA ADDRESSAMS-0 TCE CE# TOE OE# TOLZ TOHZ VIH WE# TCLZ TOH TCHZ HIGH-Z HIGH-Z DQ15-0 DATAVALID DATAVALID 1384F03.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB Figure 5: Read Cycle Timing Diagram INTERNALPROGRAMOPERATIONSTARTS TBP ADDRESSAMS-0 555 2AA 555 ADDR TAH TDH TWP WE# TAS TWPH TDS OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1384F04.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 6: WE# Controlled Program Cycle Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 18

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet INTERNALPROGRAMOPERATIONSTARTS TBP ADDRESSAMS-0 555 2AA 555 ADDR TAH TDH TCP CE# TAS TCPH TDS OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1384F05.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 7: CE# Controlled Program Cycle Timing Diagram ADDRESSAMS-0 TCE CE# TOEH TOES OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1384F06.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB Figure 8: Data# Polling Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 19

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet ADDRESSAMS-0 TCE CE# TOEH TOE TOES OE# WE# DQ6andDQ2 TWOREADCYCLES WITHSAMEOUTPUTS 1384F07.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB Figure 9: Toggle Bits Timing Diagram SIX-BYTECODEFORCHIP-ERASE TSCE ADDRESSAMS-0 555 2AA 555 555 2AA 555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1384F08.0 Note: ThisdevicealsosupportsCE#controlledChip-EraseoperationTheWE#andCE#signalsare interchangeableaslongasminimumtimingsaremet.(SeeTable17) AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 10:WE# Controlled Chip-Erase Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 20

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet SIX-BYTECODEFORBLOCK-ERASE TBE ADDRESSAMS-0 555 2AA 555 555 2AA BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1384F09.0 Note: ThisdevicealsosupportsCE#controlledBlock-EraseoperationTheWE#andCE#signalsare interchangeableaslongasminimumtimingsaremet.(SeeTable17) BAX=BlockAddress AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 11:WE# Controlled Block-Erase Timing Diagram SIX-BYTECODEFORSECTOR-ERASE TSE ADDRESSAMS-0 555 2AA 555 555 2AA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 1384F10.0 Note: ThisdevicealsosupportsCE#controlledSector-EraseoperationTheWE#andCE#signalsare interchangeableaslongasminimumtimingsaremet.(SeeTable17) SAX=SectorAddress AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 12:WE# Controlled Sector-Erase Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 21

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Three-ByteSequenceforSoftwareIDEntry ADDRESSA14-0 555 2AA 555 0000 0001 CE# OE# TWP TIDA WE# TWPH TAA DQ15-0 XXAA XX55 XX90 00BF DeviceID SW0 SW1 SW2 1384F11.0 Note: DeviceID=235DHforSST39VF3201Band235CHforSST39VF3202B WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 13:Software ID Entry and Read Three-ByteSequenceforCFIQueryEntry ADDRESSA14-0 555 2AA 555 CE# OE# TWP TIDA WE# TWPH TAA DQ15-0 XXAA XX55 XX98 SW0 SW1 SW2 1384F12.0 Note: WP#mustbeheld inproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 14:CFI Query Entry and Read ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 22

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet THREE-BYTESEQUENCEFOR SOFTWAREIDEXITANDRESET ADDRESSA14-0 555 2AA 555 DQ15-0 XXAA XX55 XXF0 TIDA CE# OE# TWP WE# TWHP 1384F13.0 SW0 SW1 SW2 Note: WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 15:Software ID Exit/CFI Exit THREE-BYTESEQUENCEFOR CFIQUERYENTRY ADDRESSAMS-0 555 2AA 555 CE# OE# TWP TIDA WE# TWPH TAA DQ15-0 XXAA XX55 XX88 SW0 SW1 SW2 1384F14.0 Note: AMS=Mostsignificantaddress AMS=A20forSST39VF320xB WP#mustbeheldinproperlogicstate(VILorVIH)1µspriortoand1µsafterthecommandsequence. XcanbeVILorVIH,butnoothervalue. Figure 16:Sec ID Entry ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 23

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet TRP RST# CE#/OE# TRHR 1384F15.0 Figure 17:RST# Timing Diagram (When no internal operation is in progress) TRP RST# TRY CE#/OE# End-of-WriteDetection (Toggle-Bit) 1384F16.0 Figure 18:RST# Timing Diagram (During Program or Erase operation) ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 24

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet VIHT INPUT VIT REFERENCEPOINTS VOT OUTPUT VILT 1384F17.0 AC test inputs are driven at V (0.9 V ) for a logic “1” and V (0.1 V ) for a logic “0”. Mea- IHT DD ILT DD surement reference points for inputs and outputs are V (0.5 V ) and V (0.5 V ). Input rise IT DD OT DD andfalltimes(10%90%)are<5ns. Note: VIT-VINPUTTest VOT-VOUTPUTTest VIHT-VINPUTHIGHTest VILT-VINPUTLOWTest Figure 19:AC Input/Output Reference Waveforms TOTESTER TODUT CL 1384F18.0 Figure 20:A Test Load Example ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 25

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Start Loaddata:XXAAH Address:555H Loaddata:XX55H Address:2AAH Loaddata:XXA0H Address:555H LoadWord Address/Word Data Waitforendof Program(TBP, Data#Polling bit,orTogglebit operation) Program Completed XcanbeVILorVIH,butnoothervalue 1384F19.0 Figure 21:Word-Program Algorithm ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 26

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet InternalTimer ToggleBit Data# Polling Program/Erase Program/Erase Program/Erase Initiated Initiated Initiated WaitTBP, Readword ReadDQ7 TSCE,TSE orTBE Readsame No IsDQ7= word truedata Program/Erase Completed Yes No DoesDQ6 Program/Erase match Completed Yes Program/Erase Completed 1384F20.0 Figure 22:Wait Options ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 27

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet CFIQueryEntry SecIDQueryEntry SoftwareProductIDEntry CommandSequence CommandSequence CommandSequence Loaddata:XXAAH Loaddata:XX98H Loaddata:XXAAH Loaddata:XXAAH Address:555H Address:55H Address:555H Address:555H Loaddata:XX55H Loaddata:XX55H Loaddata:XX55H WaitTIDA Address:2AAH Address:2AAH Address:2AAH Loaddata:XX98H Loaddata:XX88H Loaddata:XX90H ReadCFIdata Address:555H Address:555H Address:555H WaitTIDA WaitTIDA WaitTIDA ReadCFIdata ReadSecID ReadSoftwareID XcanbeVILorVIH,butnoothervalue 1384F21.0 Figure 23:Software ID/CFI Entry Command Flowcharts ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 28

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet SoftwareIDExit/CFIExit/SecIDExit CommandSequence Loaddata:XXAAH Loaddata:XXF0H Address:555H Address:XXH Loaddata:XX55H WaitTIDA Address:2AAH Loaddata:XXF0H Returntonormal Address:555H operation WaitTIDA Returntonormal operation XcanbeVILorVIH,butnoothervalue 1384F22.0 Figure 24:Software ID/CFI Exit Command Flowcharts ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 29

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Chip-Erase Sector-Erase Block-Erase CommandSequence CommandSequence CommandSequence Loaddata:XXAAH Loaddata:XXAAH Loaddata:XXAAH Address:555H Address:555H Address:555H Loaddata:XX55H Loaddata:XX55H Loaddata:XX55H Address:2AAH Address:2AAH Address:2AAH Loaddata:XX80H Loaddata:XX80H Loaddata:XX80H Address:555H Address:555H Address:555H Loaddata:XXAAH Loaddata:XXAAH Loaddata:XXAAH Address:555H Address:555H Address:555H Loaddata:XX55H Loaddata:XX55H Loaddata:XX55H Address:2AAH Address:2AAH Address:2AAH Loaddata:XX10H Loaddata:XX50H Loaddata:XX30H Address:555H Address:SAX Address:BAX WaitTSCE WaitTSE WaitTBE Chiperased Sectorerased Blockerased toFFFFH toFFFFH toFFFFH XcanbeVILorVIH,butnoothervalue 1384F23.0 Figure 25:Erase Command Sequence ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 30

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Product Ordering Information SST 39 VF 3201B - 70 - 4I - EKE XX XX XXXXX - XX - XX - XXX EnvironmentalAttribute E1=non-Pb PackageModifier K=48ballsorleads PackageType E=TSOP(type1,dieup,12mmx20mm) B3=TFBGA(6mmx8mm,0.8mmpitch) TemperatureRange C=Commercial=0°Cto+70°C I=Industrial=-40°Cto+85°C MinimumEndurance 4=10,000cycles ReadAccessSpeed 70=70ns HardwareBlockProtection 1=BottomBoot-Block 2=TopBoot-Block DeviceDensity 320=32Mbit Voltage V=2.7-3.6V ProductSeries 39=Multi-PurposeFlashPlus 1. Environmentalsuffix“E”denotesnon-Pbsolder. SSTnon-Pbsolderdevicesare“RoHSCompli- ant”. Valid Combinations for SST39VF3201B SST39VF3201B-70-4C-EKE SST39VF3201B-70-4C-B3KE SST39VF3201B-70-4I-EKE SST39VF3201B-70-4I-B3KE Valid Combinations for SST39VF3202B SST39VF3202B-70-4C-EKE SST39VF3202B-70-4C-B3KE SST39VF3202B-70-4I-EKE SST39VF3202B-70-4I-B3KE Note:Validcombinationsarethoseproductsinmassproductionorwillbeinmassproduction.ConsultyourSST salesrepresentativetoconfirmavailabilityofvalidcombinationsandtodetermineavailabilityofnewcombi- nations. ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 31

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Packaging Diagrams 1.05 0.95 Pin#1Identifier 0.50 BSC 0.27 12.20 0.17 11.80 0.15 18.50 0.05 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 0°-5° 19.80 0.70 Note: 1. ComplieswithJEDECpublication95MO-142DDdimensions, 0.50 althoughsomedimensionsmaybemorestringent. 2. Alllineardimensionsareinmillimeters(max/min). 1mm 3. Coplanarity:0.1mm 4. Maximumallowablemoldflashis0.15mmatthepackageends,and0.25mmbetweenleads. 48-tsop-EK-8 Figure 26:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm, SST Package Code: EK ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 32

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet TOPVIEW BOTTOMVIEW 8.00 0.10 5.60 0.80 0.45 0.05 (48X) 6 6 5 5 4 4.00 4 6.00 0.10 3 3 2 2 1 1 0.80 A B C D E F G H H G F E D C B A A1CORNER A1CORNER SIDEVIEW 1.10 0.10 0.12 SEATINGPLANE 1mm 0.35 0.05 Note: 1.ComplieswithJEDECPublication95,MO-210,variant AB-1,althoughsomedimensionsmaybemorestringent. 2.Alllineardimensionsareinmillimeters. 3.Coplanarity:0.12mm 4.Ballopeningsizeis0.38mm( 0.05mm) 48-tfbga-B3K-6x8-450mic-5 Figure 27:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm, SST Package Code: B3K ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 33

32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B A Microchip Technology Company DataSheet Table 18:Revision History Revision Description Date 00 (cid:129) Initialrelease Mar2008 01 (cid:129) Changed1Vper100µsto1Vper100msinPowerUpSpecifications Jan2009 onpage11 (cid:129) ChangedstatusfromPreliminarySpecificationstoDataSheet A (cid:129) Appliednewdocumentformat Dec2011 (cid:129) Releaseddocumentunderletterrevisionsystem (cid:129) UpdatedSpecnumberfromS71384toDS25111 ISBN:978-1-61341-888-8 ©2011SiliconStorageTechnology,Inc–aMicrochipTechnologyCompany.Allrightsreserved. SST,SiliconStorageTechnology,theSSTlogo,SuperFlash,MTP,andFlashFlexareregisteredtrademarksofSiliconStorageTech- nology,Inc.MPF,SQI,SerialQuadI/O,andZ-ScalearetrademarksofSiliconStorageTechnology,Inc.Allothertrademarksand registeredtrademarksmentionedhereinarethepropertyoftheirrespectiveowners. Specificationsaresubjecttochangewithoutnotice.Refertowww.microchip.comforthemostrecentdocumentation.Forthemostcurrent packagedrawings,pleaseseethePackagingSpecificationlocatedathttp://www.microchip.com/packaging. Memorysizesdenoterawstoragecapacity;actualusablecapacitymaybeless. SSTmakesnowarrantyfortheuseofitsproductsotherthanthoseexpresslycontainedintheStandardTermsandConditionsof Sale. Forsalesofficelocationsandinformation,pleaseseewww.microchip.com. SiliconStorageTechnology,Inc. AMicrochipTechnologyCompany www.microchip.com ©2011SiliconStorageTechnology,Inc. DS25111A 12/11 34