Obsolete Device Please contact Microchip Sales for replacement information. 32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF032B devices are enhanced with improved operating frequency which lowers power consumption. SST25VF032B SPI serial flash memories are manufactured with SST's propri- etary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufactur- ability compared with alternate approaches. Features • Single Voltage Read and Write Operations (cid:129) End-of-Write Detection –2.7-3.6V –Software polling the BUSY bit in Status Register –Busy Status readout on SO pin (cid:129) Serial Interface Architecture (cid:129) Hold Pin (HOLD#) –SPI Compatible: Mode 0 and Mode 3 –Suspends a serial sequence to the memory (cid:129) High Speed Clock Frequency without deselecting the device –Up to 80 MHz (cid:129) Write Protection (WP#) (cid:129) Superior Reliability –Enables/Disables the Lock-Down function of the status –Endurance: 100,000 Cycles register –Greater than 100 years Data Retention (cid:129) Software Write Protection (cid:129) Low Power Consumption: –Write protection through Block-Protection bits in status –Active Read Current: 10 mA (typical) register –Standby Current: 5 µA (typical) (cid:129) Temperature Range (cid:129) Flexible Erase Capability –Industrial: -40°C to +85°C –Uniform 4 KByte sectors (cid:129) Packages Available –Uniform 32 KByte overlay blocks –Uniform 64 KByte overlay blocks –8-lead SOIC (200 mils) –8-contact WSON (5 X 6 mm) (cid:129) Fast Erase and Byte-Program: (cid:129) All devices are RoHS compliant –Chip-Erase Time: 35 ms (typical) –Sector-/Block-Erase Time: 18 ms (typical) –Byte-Program Time: 7 µs (typical) (cid:129) Auto Address Increment (AAI) Word Programming –Decrease total chip programming time over Byte-Pro- gram operations www.microchip.com ©2015 DS20005071B 04/15

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Product Description The SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25VF032B SPI serial flash memories are manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain bet- ter reliability and manufacturability compared with alternate approaches. The SST25VF032B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF032B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF032B device is offered in 8-lead SOIC (200 mils) and 8-contact WSON packages. See Figure 2 for pin assignments. ©2015 DS20005071B 04/15 2

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Block Diagram SuperFlash X - Decoder Address Memory Buffers and Latches Y - Decoder I/O Buffers Control Logic and Data Latches Serial Interface CE# SCK SI SO WP# HOLD# 1327 B1.0 Note: In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page12. for details Figure 1: Functional Block Diagram ©2015 DS20005071B 04/15 3

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Pin Description CE# 1 8 VDD CE# 1 8 VDD SO 2 7 HOLD# SO 2 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 1327 8-SOIC P1.0 1327 8-WSON P1.0 Note: In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page12. for details. Figure 2: Pin Assignments for 8-Lead SOIC Table 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. RY/BY# Ready / Busy pin Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg- ister. HOLD# Hold To temporarily stop serial communication with SPI flash memory without reset- ting the device. V Power Supply To provide power supply voltage: 2.7-3.6V DD V Ground SS T1.0 20005071 ©2015 DS20005071B 04/15 4

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Memory Organization The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks. Device Operation The SST25VF032B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. CE# MODE 3 MODE 3 SCK MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE MSB HIGH IMPEDANCE SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 1327 F04.0 Figure 3: SPI Protocol ©2015 DS20005071B 04/15 5

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Hold Operation The HOLD# pin is used to pause a serial sequence using the SPI flash memory, but without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits from Hold mode when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V or IL V IH. If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1327 F05.0 Figure 4: Hold Condition Waveform Write Protection SST25VF032B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for the Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled. Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction WP# BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed T2.0 20005071 ©2015 DS20005071B 04/15 6

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write pro- tection. During an internal Erase or Program operation, the status register may be read only to deter- mine the completion of an operation in progress. Table 3 describes the function of each bit in the software status register. Table 3: Software Status Register Default at Bit Name Function Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 R 0 = No internal Write operation is in progress 1 WEL 1 = Device is memory Write enabled 0 R 0 = Device is not memory Write enabled 2 BP0 Indicate current level of block write protection (See Table 4) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 4) 1 R/W 4 BP2 Indicate current level of block write protection (See Table 4) 1 R/W 5 BP3 Indicate current level of block write protection (See Table 4) 0 R/W 6 AAI Auto Address Increment Programming status 0 R 1 = AAI programming mode 0 = Byte-Program mode 7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 R/W 0 = BP3, BP2, BP1, BP0 are readable/writable T3.0 20005071 Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: (cid:129) Power-up (cid:129) Write-Disable (WRDI) instruction completion (cid:129) Byte-Program instruction completion (cid:129) Auto Address Increment (AAI) programming is completed or reached its highest unpro- tected memory address (cid:129) Sector-Erase instruction completion (cid:129) Block-Erase instruction completion (cid:129) Chip-Erase instruction completion (cid:129) Write-Status-Register instructions ©2015 DS20005071B 04/15 7

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. Block Protection (BP3,BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as shown in Table 4, to be software protected against any memory Write (Program or Erase) operation. The Write-Status- Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to the defaults specified in Table 4. Block Protection Lock-Down (BPL) WP# pin driven low (V ), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it IL prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V ), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to IH 0. Table 4: Software Status Register Block Protection FOR SST25VF032B1 Status Register Bit2 Protected Memory Address Protection Level BP3 BP2 BP1 BP0 32 Mbit None X 0 0 0 None Upper 1/64 X 0 0 1 3F0000H-3FFFFFH Upper 1/32 X 0 1 0 3E0000H-3FFFFFH Upper 1/16 X 0 1 1 3C0000H-3FFFFFH Upper 1/8 X 1 0 0 380000H-3FFFFFH Upper 1/4 X 1 0 1 300000H-3FFFFFH Upper 1/2 X 1 1 0 200000H-3FFFFFH All Blocks X 1 1 1 000000H-3FFFFFH T4.0 20005071 1. X = Don’t Care (RESERVED) default is “0 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected) ©2015 DS20005071B 04/15 8

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF032B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write- Enable (WREN) instruction must be executed prior any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The com- plete list of instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the ris- ing edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions (1 of 2) Address Dummy Data Maximum Instruction Description Op Code Cycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency Read Read Memory 0000 0011b (03H) 3 0 1 to  25 MHz High-Speed Read Read Memory at 0000 1011b (0BH) 3 1 1 to  80 MHz higher speed 4 KByte Sector-Erase3 Erase 4 KByte of 0010 0000b (20H) 3 0 0 80 MHz memory array 32 KByte Block-Erase4 Erase 32KByte block 0101 0010b (52H) 3 0 0 80 MHz of memory array 64 KByte Block-Erase5 Erase 64 KByte block 1101 1000b (D8H) 3 0 0 80 MHz of memory array Chip-Erase Erase Full Memory 0110 0000b (60H) 0 0 0 80 MHz Array or 1100 0111b (C7H) Byte-Program To Program One 0000 0010b (02H) 3 0 1 80 MHz Data Byte AAI-Word-Program6 Auto Address Incre- 1010 1101b (ADH) 3 0 2 to  80 MHz ment Programming RDSR7 Read-Status-Regis- 0000 0101b (05H) 0 0 1 to  80 MHz ter EWSR Enable-Write-Status- 0101 0000b (50H) 0 0 0 80 MHz Register WRSR Write-Status-Regis- 0000 0001b (01H) 0 0 1 80 MHz ter WREN Write-Enable 0000 0110b (06H) 0 0 0 80 MHz WRDI Write-Disable 0000 0100b (04H) 0 0 0 80 MHz RDID8 Read-ID 1001 0000b (90H) 3 0 1 to  80 MHz or 1010 1011b (ABH) JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to  80 MHz ©2015 DS20005071B 04/15 9

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Table 5: Device Operation Instructions (Continued) (2 of 2) Address Dummy Data Maximum Instruction Description Op Code Cycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency EBSY Enable SO as an out- 0111 0000b (70H) 0 0 0 80 MHz put RY/BY# status during AAI program- ming DBSY Disable SO as RY/BY# 1000 0000b (80H) 0 0 0 80 MHz status during AAI pro- gramming T5.0 20005071 1. One bus cycle is eight clock periods. 2. Address bits above the most significant bit can be either VIL or VIH. 3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. 4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. 5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. 6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufac- turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. Read (25 MHz) The Read instruction, 03H, supports up to 25 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until termi- nated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For example, once the data from address location 3FFFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A - 23 A ]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read 0 sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 47 48 5556 6364 70 SCK MODE 0 03 ADD. ADD. ADD. SI MSB MSB N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1327 F06.0 Figure 5: Read Sequence ©2015 DS20005071B 04/15 10

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet High-Speed-Read (80 MHz) The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com- mand, 0BH, followed by address bits [A -A ] and a dummy byte. CE# must remain active low for the 23 0 duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For example, once the data from address location 3FFFFFH has been read, the next output will be from address location 000000H. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 23 24 3132 3940 4748 55 56 6364 7172 78 SCK MODE 0 SI 0B ADD. ADD. ADD. X N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1327 F07.1 Figure 6: High-Speed-Read Sequence Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A -A ]. Following the address, the data is 23 0 input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe- cuted. The user may poll the Busy bit in the software status register or wait T for the completion of BP the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 SCK MODE 0 SI 02 ADD. ADD. ADD. DIN MSB LSB SO HIGH IMPEDANCE 1327 F08.0 Figure 7: Byte-Program Sequence ©2015 DS20005071B 04/15 11

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when ini- tiating an AAI Word Program operation. While within AAI Word Programming sequence, only the fol- lowing instructions are valid: for software end-of-write detection—AAI Word (ADH), WRDI (04H), and RDSR (05H); for hardware end-of-write detection—AAI Word (ADH) and WRDI (04H). There are three options to determine the completion of each AAI Word program cycle: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register, or wait T BP. Refer to“End-of-Write Detection” for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. Initiate the AAI Word Program instruction by executing an 8-bit command, ADH, followed by address bits [A -A ]. Fol- 23 0 lowing the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) is programmed into the initial address [A -A ] with A =0, the second 23 1 0 byte of Data (D1) is programmed into the initial address [A -A ] with A =1. CE# must be driven high 23 1 0 before executing the AAI Word Program instruction. Check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed, followed by the next two, and so on. When programming the last desired word, or the highest unprotected memory address, check the busy status using either the hardware or software (RDSR instruction) method to check for program comple- tion. Once programming is complete, use the applicable method to terminate AAI. If the device is in Software End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the device is in AAI Hardware End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H, followed by the 8-bit DBSY command, 80H. There is no wrap mode during AAI programming once the highest unprotected memory address is reached. See Figures 10 and 11 for the AAI Word programming sequence. End-of-Write Detection There are three methods to determine completion of a program cycle during AAI Word programming: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Soft- ware Status Register, or wait T The Hardware End-of-Write detection method is described in the BP. section below. Hardware End-of-Write Detection The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming. (see Figure 8) The 8-bit command, 70H, must be executed prior to initiating an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status of the inter- nal flash status on the SO pin. A ‘0’ indicates the device is busy and a ‘1’ indicates the device is ready for the next instruction. De-asserting CE# will return the SO pin to tri-state. While in AAI and Hardware End-of-Write detection mode, the only valid instructions are AAI Word (ADH) and WRDI (04H). To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the Write- Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY# status during the AAI command. See Figures 9 and 10. ©2015 DS20005071B 04/15 12

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 SI 70 MSB SO HIGH IMPEDANCE 1327 F09.0 Figure 8: Enable SO as Hardware RY/BY# During AAI Programming CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 SI 80 MSB SO HIGH IMPEDANCE 1327 F10.0 Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2015 DS20005071B 04/15 13

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet CE# MODE 3 0 7 0 7 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 SCKMODE 0 SI EBSY WREN AD A A A D0 D1 AD D2 D3 Load AAI command, Address, 2 bytes data SO Check for Flash Busy Status to load next valid1 command CE# cont. 0 7 8 1516 23 0 7 0 7 0 7 8 15 SCK cont. SI cont. AD Dn-1 Dn WRDI DBSY RDSR Last 2 WRDI followed by DBSY Data Bytes to exit AAI Mode SO cont. DOUT Check for Flash Busy Status to load next valid1 command 1327 AAI.HW.3 Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming Figure 10:Auto Address Increment (AAI) Word-Program Sequence with Hardware End-of- Write Detection Wait TBP or poll Software Status register to load next valid1 command CE# MODE 3 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 0 7 8 1516 23 0 7 0 7 8 15 SCK MODE 0 SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR Load AAI command, Address, 2 bytes data Last 2 WRDI to exit Data Bytes AAI Mode SO DOUT 1327 AAI.SW.2 Note: 1. Valid commands during AAI programming: AAI command or WRDI command Figure 11:Auto Address Increment (AAI) Word-Program Sequence with Software End-of-Write Detection ©2015 DS20005071B 04/15 14

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write- Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com- mand sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol- lowed by address bits [A -A ]. Address bits [A -A ] (A = Most Significant address) are used to 23 0 MS 12 MS determine the sector address (SA ), remaining address bits can be V or V CE# must be driven high X IL IH. before the instruction is executed. Poll the Busy bit in the software status register or wait T for the SE completion of the internal self-timed Sector-Erase cycle. See Figure 12 for the Sector-Erase sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 SCK MODE 0 SI 20 ADD. ADD. ADD. SO HIGH IMPEDANCE 1327 F13.0 Figure 12:Sector-Erase Sequence ©2015 DS20005071B 04/15 15

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block- Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruc- tion clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected mem- ory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A -A ]. Address 23 0 bits [A -A ] (A = Most Significant Address) are used to determine block address (BA ), remain- MS 15 MS X ing address bits can be V or V CE# must be driven high before the instruction is executed. The 64-KByte IL IH. Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A -A ]. 23 0 Address bits [A -A ] are used to determine block address (BA ), remaining address bits can be V or V MS 16 X IL IH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait T for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase BE cycles. See Figure 13 for the 32-KByte Block-Erase sequence and Figure 14 for the 64-KByte Block- Erase sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 52 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1327 32KBklEr.0 Figure 13:32-KByte Block-Erase Sequence CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 D8 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1327 63KBlkEr.0 Figure 14:64-KByte Block-Erase Sequence ©2015 DS20005071B 04/15 16

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. Initiate the Chip-Erase instruction by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait T for the comple- CE tion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 SI 60 or C7 MSB SO HIGH IMPEDANCE 1327 F16.0 Figure 15:Chip-Erase Sequence Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR instruction sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE 0 SI 05 MSB HIGH IMPEDANCE SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1327 F17.0 Figure 16:Read-Status-Register (RDSR) Sequence ©2015 DS20005071B 04/15 17

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to ‘1’ allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Pro- gram/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Sta- tus-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 SI 06 MSB SO HIGH IMPEDANCE 1327 F18.0 Figure 17:Write Enable (WREN) Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to ‘0,’ therefore, preventing any new Write operations. The WRDI instruction will not terminate any programming opera- tion in progress. Any program operation in progress may continue up to T after executing the WRDI BP instruction. CE# must be driven high before the WRDI instruction is executed. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 SI 04 MSB SO HIGH IMPEDANCE 1327 F19.0 Figure 18:Write Disable (WRDI) Sequence ©2015 DS20005071B 04/15 18

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two- step instruction sequence of the EWSR instruction followed by the WRSR instruction works like soft- ware data protection (SDP) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to ‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or WP# pin is driven high (V ) prior to the low-to-high transition of the CE# pin at the end of IH the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL functions. CE# MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 101112131415 SCK MODE 0 MODE 0 STATUS REGISTER IN SI 50 or 06 01 7 6 5 4 3 2 1 0 MSB MSB MSB HIGH IMPEDANCE SO 1327 F20.0 Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta- tus-Register (WRSR) Sequence ©2015 DS20005071B 04/15 19

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the device as SST25VF032B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A -A ]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H 23 0 and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufac- turer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. Refer to Tables 6 and 7 for device identification data. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 4748 5556 63 SCK MODE 0 SI 90 or AB 00 00 ADD1 MSB MSB HIGH HIGH IMPEDANCE IMPEDANCE SO BF Device ID BF Device ID MSB Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1327 F21.0 Figure 20:Read-ID Sequence Table 6: Product Identification Address Data Manufacturer’s ID 00000H BFH Device ID SST25VF032B 00001H 4AH T6.020005071 ©2015 DS20005071B 04/15 20

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF032B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 24-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 4AH, identifies the device as SST25VF032B. The instruction sequence is shown in Figure 21. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334 SCK MODE 0 SI 9F HIGH IMPEDANCE SO BF 25 4A MSB MSB 1327 F22.0 Figure 21:JEDEC Read-ID Sequence Table 7: JEDEC Read-ID Data Device ID Manufacturer’s ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 BFH 25H 4AH T7.0 20005071 ©2015 DS20005071B 04/15 21

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Electrical Specifications Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con- ditions may affect device reliability. Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Package Power Dissipation Capability (T = 25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W A Surface Mount Solder Reflow Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. Table 8: Operating Range Range Ambient Temp V DD Industrial -40°C to +85°C 2.7-3.6V T8.1 20005071 Table 9: AC Conditions of Test1 Input Rise/Fall Time Output Load 5ns C = 30 pF L T9.1 20005071 1. See Figure 26 Table 10:DC Operating Characteristics (VDD = 2.7-3.6V) Limits Symbol Parameter Min Max Units Test Conditions I Read Current 10 mA CE# = 0.1 V /0.9 V @25 MHz, SO = open DDR DD DD I Read Current 20 mA CE# = 0.1 V /0.9 V @66 MHz, SO = open DDR2 DD DD I Read Current 25 mA CE# = 0.1 V /0.9 V @80 MHz, SO = open DDR3 DD DD I Program and Erase Current 30 mA CE# = V DDW DD I Standby Current 20 µA CE# = V , V = V or V SB DD IN DD SS I Input Leakage Current 1 µA V = GND to V , V = V Max LI IN DD DD DD I Output Leakage Current 1 µA V = GND to V , V = V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V = V Min IL DD DD V Input High Voltage 0.7 V V V = V Max IH DD DD DD V Output Low Voltage 0.2 V I = 100 µA, V = V Min OL OL DD DD V Output Low Voltage 0.4 V I = 1.6 mA, V = V Min OL2 OL DD DD V Output High Voltage V -0.2 V I = -100 µA, V = V Min OH DD OH DD DD T10.0 20005071 ©2015 DS20005071B 04/15 22

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Table 11:Capacitance (TA = 25°C, f = 1 MHz, other pins open) Parameter Description Test Condition Maximum C 1 Output Pin Capacitance V = 0V 12 pF OUT OUT C 1 Input Capacitance V = 0V 6 pF IN IN T11.0 20005071 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 12:Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method N 1 Endurance 100,000 Cycles JEDEC Standard A117 END T 1 Data Retention 100 Years JEDEC Standard A103 DR I 1 Latch Up 100 + I mA JEDEC Standard 78 LTH DD T12.0 20005071 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2015 DS20005071B 04/15 23

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Table 13:AC Operating Characteristics 25 MHz 66 MHz 80 MHz Symbol Parameter Min Max Min Max Min Max Units F 1 Serial Clock Frequency 25 66 80 MHz CLK T Serial Clock High Time 18 6.5 6 ns SCKH T Serial Clock Low Time 18 6.5 6 ns SCKL T 2 Serial Clock Rise Time (Slew 0.1 0.1 0.1 V/ns SCKR Rate) T Serial Clock Fall Time (Slew 0.1 0.1 0.1 V/ns SCKF Rate) T 3 CE# Active Setup Time 10 5 5 ns CES T 3 CE# Active Hold Time 10 5 5 ns CEH T 3 CE# Not Active Setup Time 10 5 5 ns CHS T 3 CE# Not Active Hold Time 10 5 5 ns CHH T CE# High Time 100 50 50 ns CPH T CE# High to High-Z Output 15 7 7 ns CHZ T SCK Low to Low-Z Output 0 0 0 ns CLZ T Data In Setup Time 5 2 2 ns DS T Data In Hold Time 5 4 4 ns DH T HOLD# Low Setup Time 10 5 5 ns HLS T HOLD# High Setup Time 10 5 5 ns HHS T HOLD# Low Hold Time 10 5 5 ns HLH T HOLD# High Hold Time 10 5 5 ns HHH T HOLD# Low to High-Z Output 20 7 7 ns HZ T HOLD# High to Low-Z Output 15 7 7 ns LZ T Output Hold from SCK Change 0 0 0 ns OH T Output Valid from SCK 15 6 6 ns V T Sector-Erase 25 25 25 ms SE T Block-Erase 25 25 25 ms BE T Chip-Erase 50 50 50 ms SCE T 4 Byte-Program 10 10 10 µs BP T13.0 20005071 1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz 2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements 3. Relative to SCK. 4. TBP of AAI-Word Programming is also 10 µs maximum time. ©2015 DS20005071B 04/15 24

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet TCPH CE# TCHH TCES TCEH TCHS SCK TDS TDH TSCKR TSCKF SI MSB LSB HIGH-Z HIGH-Z SO 1327 F23.0 Figure 22:Serial Input Timing Diagram CE# TSCKH TSCKL SCK TOH TCLZ TCHZ SO MSB LSB TV SI 1327 F24.0 Figure 23:Serial Output Timing Diagram ©2015 DS20005071B 04/15 25

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet CE# THHH THLS THHS SCK THLH THZ TLZ SO SI HOLD# 1327 F25.0 Figure 24:Hold Timing Diagram ©2015 DS20005071B 04/15 26

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Power-Up Specifications All functionalities and DC specifications are specified for a V ramp rate of greater than 1V per 100 DD ms (0v - 3.0V in less than 300 ms). See Table 14 and Figure 25 for more information. Table 14:Recommended System Power-up Timings Symbol Parameter Minimum Units T 1 V Min to Read Operation 100 µs PU-READ DD T 1 V Min to Write Operation 100 µs PU-WRITE DD T14.020005071 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VDD VDD Max Chip selection is not allowed. All commands are rejected by the device. VDD Min TPU-READ Device fully accessible TPU-WRITE Time 1327 F26.0 Figure 25:Power-up Timing Diagram ©2015 DS20005071B 04/15 27

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet VIHT VHT VHT INPUT REFERENCE POINTS OUTPUT VLT VLT VILT 1327 IORef.0 AC test inputs are driven at V (0.9V ) for a logic “1” and V (0.1V ) for a logic “0”. Measure- IHT DD ILT DD ment reference points for inputs and outputs are V (0.6V ) and V (0.4V ). Input rise and fall HT DD LT DD times (10%  90%) are <5 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test Figure 26:AC Input/Output Reference Waveforms TO TESTER TO DUT CL 25071 TstLd.0 Figure 27:A Test Load Example ©2015 DS20005071B 04/15 28

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Product Ordering Information SST 25 VF 032B - 80 - 4I - S2AF XX XX XXXX - XX - XX - XXXX Environmental Attribute F1 = non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer E = non-Pb Package Modifier A = 8 leads or contacts Package Type S2 = SOIC 200 mil body width Q = WSON (5 x 6 mm) Temperature Range I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles2 Operating Frequency 66 = 66 MHz 80 = 80 MHz Device Density 032 = 32 Mbit Voltage V = 2.7-3.6V Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “F” denotes non-Pb/non-SN solder; “E” denotes non-Pb solder. SST non-Pb/ non-Sn solder devices are “RoHS Compliant”. 2. Meets 100K Minimum Endurance cycles. Valid combinations for SST25VF032B SST25VF032B-66-4I-S2AF SST25VF032B-80-4I-S2AF SST25VF032B-80-4I-QAE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. ©2015 DS20005071B 04/15 29

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Packaging Diagrams Pin #1 TOP VIEW SIDE VIEW Identifier 0.50 0.35 5.40 5.15 1.27 BSC 0.25 END VIEW 0.05 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0° 0.19 8° Note: 1. All linear dimensions are in millimeters (max/min). 0.80 2. Coplanarity: 0.1 mm 08-soic-EIAJ-S2A-3 0.50 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 1mm Figure 28:8-lead Small-outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm) SST Package Code: S2A ©2015 DS20005071B 04/15 30

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet TOP VIEW SIDE VIEW BOTTOM VIEW Pin #1 0.2 Pin #1 Corner 1.27 BSC 5.00 ± 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.05 Max 0.50 6.00 ± 0.10 0.80 0.70 CROSS SECTION Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 0.80 3. The external paddle is electrically connected to the 0.70 die back-side and possibly to certain VSS leads. 1mm This paddle can be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. 8-wson-5x6-QA-9.0 Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. Figure 29:8-Contact Very-very-thin, Small-outline, No-lead (WSON) SST Package Code: QA ©2015 DS20005071B 04/15 31

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet Table 15:Revision History Revision Description Date 00 (cid:129) Initial release of data sheet Oct 2006 01 (cid:129) Changed clock frequency from 50 MHz to 66 MHz globally Mar 2008 (cid:129) Revised Table 13 AC Operating Characteristics (cid:129) Revised Product Ordering Information and Valid Combinations on page29 (cid:129) Revised Figure 10 and Figure 11 (cid:129) Changed IDDR2 from Max 15 mA to Max 20 mA in Table 10 (cid:129) Changed TDH from Min 5 ns to Min 4 ns (66MHz) in Table 13 02 (cid:129) Removed SC package Jul 2008 (cid:129) Removed Commercial Temperature. 03 (cid:129) Added new valid combination with 80 MHz Clock Frequency May 2009 (cid:129) Added QA package (cid:129) Edited Features, page 1 (cid:129) Edited Product Description, page 1 (cid:129) Edited Table5 on page9 (cid:129) Edited Figure 6 on page 9 (cid:129) Edited Table10 on page22 (cid:129) Edited Table13 on page24 04 (cid:129) Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write Feb 2011 Detection”, and “Hardware End-of-Write Detection” on page12. (cid:129) Revised Figures 10 and 11 on page14. (cid:129) Updated document to new format. A (cid:129) Updated Endurance information on page23 and page29 Dec 2011 (cid:129) Released document under letter revision system (cid:129) Updated Spec number from S71327 to DS25071 (cid:129) Added heading “Power-Up Specifications” on page27 B (cid:129) EOL of all SST25VF032B devices. Apr 2015 (cid:129) Document marked obsolete. ©2015 DS20005071B 04/15 32

32 Mbit SPI Serial Flash SST25VF032B EOL Data Sheet ISBN:978-1-63277-311-1 © 2015 Microchip Technology Inc. SST, Silicon Storage Technology, the SST logo, SuperFlash, and MTP are registered trademarks of Microchip Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Microchip Technology, Inc. All other trademarks and registered trade- marks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. Microchip makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. www.microchip.com ©2015 DS20005071B 04/15 33