2 Mbit SPI Serial Flash SST25VF020 SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory Data Sheet FEATURES: • Single 2.7-3.6V Read and Write Operations (cid:129) End-of-Write Detection (cid:129) Serial Interface Architecture – Software Status – SPI Compatible: Mode 0 and Mode 3 (cid:129) Hold Pin (HOLD#) (cid:129) 20 MHz Max Clock Frequency – Suspends a serial sequence to the memory without deselecting the device (cid:129) Superior Reliability (cid:129) Write Protection (WP#) – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention – Enables/Disables the Lock-Down function of the status register (cid:129) Low Power Consumption: (cid:129) Software Write Protection – Active Read Current: 7 mA (typical) – Standby Current: 8 µA (typical) – Write protection through Block-Protection bits in status register (cid:129) Flexible Erase Capability (cid:129) Temperature Range – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C (cid:129) Fast Erase and Byte-Program: – Extended: -20°C to +85°C – Chip-Erase Time: 70 ms (typical) (cid:129) Packages Available – Sector- or Block-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) – 8-lead SOIC 150 mil body width – 8-contact WSON (5mm x 6mm) (cid:129) Auto Address Increment (AAI) Programming (cid:129) All non-Pb (lead-free) devices are RoHS compliant – Decrease total chip programming time over Byte-Program operations PRODUCT DESCRIPTION The SST serial flash family features a four-wire, SPI- rent, and time of application. Since for any given voltage compatible interface that allows for a low pin-count pack- range, the SuperFlash technology uses less current to age occupying less board space and ultimately lowering program and has a shorter erase time, the total energy total system costs. SST25VF020 SPI serial flash memo- consumed during any Erase or Program operation is less ries are manufactured with SST’s proprietary, high perfor- than alternative flash memory technologies. The mance CMOS SuperFlash Technology. The split-gate SST25VF020 device operates with a single 2.7-3.6V cell design and thick-oxide tunneling injector attain better power supply. reliability and manufacturability compared with alternate The SST25VF020 device is offered in an 8-lead SOIC 150 approaches. mil body width (SA) package, and in an 8-contact WSON The SST25VF020 device significantly improves perfor- package. See Figure 2 for the pin assignments. mance, while lowering power consumption. The total energy consumed is a function of the applied voltage, cur- ©2006 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. S71231-07-000 10/06 These specifications are subject to change without notice. 1

2 Mbit SPI Serial Flash SST25VF020 Data Sheet SuperFlash X - Decoder Address Memory Buffers and Latches Y - Decoder I/O Buffers Control Logic and Data Latches Serial Interface 1231 B1.0 CE# SCK SI SO WP# HOLD# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 2

2 Mbit SPI Serial Flash SST25VF020 Data Sheet PIN DESCRIPTION CE# 1 8 VDD CE# 1 8 VDD SO 2 7 HOLD# SO 2 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 1231 08-soic P1.0 123108-wson P2.0 8-LEAD SOIC 8-CONTACT WSON FIGURE 2: Pin Assignments TABLE 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data To transfer commands, addresses, or data serially into the device. Input Inputs are latched on the rising edge of the serial clock. SO Serial Data To transfer data serially out of the device. Output Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply (2.7-3.6V). DD V Ground SS T1.0 1231 ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 3

2 Mbit SPI Serial Flash SST25VF020 Data Sheet PRODUCT IDENTIFICATION DEVICE OPERATION The SST25VF020 is accessed through the SPI (Serial TABLE 2: Product Identification Peripheral Interface) bus compatible protocol. The SPI bus Address Data consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Manufacturer’s ID 00000H BFH Data Input (SI), Serial Data Output (SO), and Serial Clock Device ID (SCK). SST25VF020 00001H 43H The SST25VF020 supports both Mode 0 (0,0) and Mode 3 T2.01231 (1,1) of SPI bus operations. The difference between the MEMORY ORGANIZATION two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no The SST25VF020 SuperFlash memory array is organized data is being transferred. The SCK signal is low for Mode 0 in 4 KByte sectors with 32 KByte overlay blocks. and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. CE# MODE 3 MODE 3 SCK MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB 1231 F02.1 FIGURE 3: SPI Protocol ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 4

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Hold Operation HOLD# pin is used to pause a serial sequence underway coincide with the SCK active low state, then the device with the SPI flash memory without resetting the clocking exits in Hold mode when the SCK next reaches the active sequence. To activate the HOLD# mode, CE# must be in low state. See Figure 4 for Hold Condition waveform. active low state. The HOLD# mode begins when the SCK Once the device enters Hold mode, SO will be in high- active low state coincides with the falling edge of the impedance state while SI and SCK can be V or V . HOLD# signal. The HOLD mode ends when the HOLD# IL IH signal’s rising edge coincides with the SCK active low state. If CE# is driven active high during a Hold condition, it returns the device to standby mode. As long as HOLD# If the falling edge of the HOLD# signal does not coincide signal is low, the memory remains in the Hold condition. To with the SCK active low state, then the device enters Hold resume communication with the device, HOLD# must be mode when the SCK next reaches the active low state. driven active high, and CE# must be driven active low. See Similarly, if the rising edge of the HOLD# signal does not Figure 18 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1231 F03.0 FIGURE 4: Hold Condition Waveform Write Protection TABLE 3: Conditions to execute Write-Status- Register (WRSR) Instruction SST25VF020 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down WP# BPL Execute WRSR Instruction function of the status register. The Block-Protection bits L 1 Not Allowed (BP1, BP0, and BPL) in the status register provide Write L 0 Allowed protection to the memory array and the status register. See H X Allowed Table 5 for Block-Protection description. T3.0 1231 Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down func- tion of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down func- tion of the BPL bit is disabled. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 5

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Status Register The software status register provides status on whether the Program operation, the status register may be read only to flash memory array is available for any Read or Write oper- determine the completion of an operation in progress. ation, whether the device is Write enabled, and the state of Table 4 describes the function of each bit in the software the memory Write protection. During an internal Erase or status register. TABLE 4: Software Status Register Default at Bit Name Function Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 R 0 = No internal Write operation is in progress 1 WEL 1 = Device is memory Write enabled 0 R 0 = Device is not memory Write enabled 2 BP0 Indicate current level of block write protection (See Table 5) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 5) 1 R/W 4:5 RES Reserved for future use 0 N/A 6 AAI Auto Address Increment Programming status 0 R 1 = AAI programming mode 0 = Byte-Program mode 7 BPL 1 = BP1, BP0 are read-only bits 0 R/W 0 = BP1, BP0 are read/writable T4.0 1231 Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indi- cates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the inter- nal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automati- cally reset under the following conditions: (cid:129) Power-up (cid:129) Write-Disable (WRDI) instruction completion (cid:129) Byte-Program instruction completion (cid:129) Auto Address Increment (AAI) programming reached its highest memory address (cid:129) Sector-Erase instruction completion (cid:129) Block-Erase instruction completion (cid:129) Chip-Erase instruction completion ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 6

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Block Protection (BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP1, BP0) bits define the size of the WP# pin driven low (V ), enables the Block-Protection- IL memory area, as defined in Table 5, to be software pro- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any tected against any memory Write (Program or Erase) further alteration of the BPL, BP1, and BP0 bits. When the operations. The Write-Status-Register (WRSR) instruction WP# pin is driven high (V ), the BPL bit has no effect and IH is used to program the BP1 and BP0 bits as long as WP# its value is “Don’t Care”. After power-up, the BPL bit is is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase reset to 0. can only be executed if Block-Protection bits are both 0. After power-up, BP1 and BP0 are set to 1. TABLE 5: Software Status Register Block Protection1 Status Register Protected Memory Area Bit Protection Level BP1 BP0 2 Mbit 0 0 0 None 1 (1/4 Memory Array) 0 1 030000H-03FFFFH 2 (1/2 Memory Array) 1 0 020000H-03FFFFH 3 (Full Memory Array) 1 1 000000H-03FFFFH T5.0 1231 1. Default at power-up for BP1 and BP0 is ‘11’. Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 7

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), most significant bit. CE# must be driven low before an and configure the SST25VF020. The instruction bus cycles instruction is entered and must be driven high after the last are 8 bits each for commands (Op Code), data, and bit of the instruction has been shifted in (except for Read, addresses. Prior to executing any Byte-Program, Auto Read-ID and Read-Status-Register instructions). Any low Address Increment (AAI) programming, Sector-Erase, to high transition on CE#, before receiving the last bit of an Block-Erase, or Chip-Erase instructions, the Write-Enable instruction bus cycle, will terminate the instruction in (WREN) instruction must be executed first. The complete progress and return the device to the standby mode. list of the instructions is provided in Table 6. All instructions Instruction commands (Op Code), addresses, and data are are synchronized off a high to low transition of CE#. Inputs all input from the most significant bit (MSB) first. will be accepted on the rising edge of SCK starting with the TABLE 6: Device Operation Instructions1 Bus Cycle2 1 2 3 4 5 Cycle Type/Operation3,4 S S S S S S S S S S IN OUT IN OUT IN OUT IN OUT IN OUT Read 03H Hi-Z A -A Hi-Z A -A Hi-Z A -A Hi-Z X D 23 16 15 8 7 0 OUT Sector-Erase5,6 20H Hi-Z A -A Hi-Z A -A Hi-Z A -A Hi-Z - - 23 16 15 8 7 0 Block-Erase5,7 52H Hi-Z A -A Hi-Z A -A Hi-Z A -A Hi-Z - - 23 16 15 8 7 0 Chip-Erase6 60H Hi-Z - - - - - - - - Byte-Program6 02H Hi-Z A -A Hi-Z A -A Hi-Z A -A Hi-Z D Hi-Z 23 16 15 8 7 0 IN Auto Address Increment (AAI) Program6,8 AFH Hi-Z A -A Hi-Z A -A Hi-Z A -A Hi-Z D Hi-Z 23 16 15 8 7 0 IN Read-Status-Register (RDSR) 05H Hi-Z X D - Note9 - Note9 - Note9 OUT Enable-Write-Status-Register (EWSR)10 50H Hi-Z - - - - - - - - Write-Status-Register (WRSR)10 01H Hi-Z Data Hi-Z - - -. - - - Write-Enable (WREN) 06H Hi-Z - - - - - - - - Write-Disable (WRDI) 04H Hi-Z - - - - - - - - Read-ID 90H or Hi-Z 00H Hi-Z 00H Hi-Z ID Addr11 Hi-Z X D 12 OUT ABH T6.0 1231 1. AMS = Most Significant Address AMS = A17 for SST25VF020 Address bits above the most significant bit of each density can be VIL or VIH 2. One bus cycle is eight clock periods. 3. Operation: SIN = Serial In, SOUT = Serial Out 4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) 5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH 6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. 7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH 8. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be programmed. 9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and Device ID output stream is continuous until terminated by a low to high transition on CE# 12. Device ID = 43H for SST25VF020 ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 8

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Read The Read instruction outputs the data starting from the 2Mbit density, once the data from address location specified address location. The data output stream is con- 3FFFFH had been read, the next output will be from tinuous through all addresses until terminated by a low to address location 00000H. high transition on CE#. The internal address pointer will The Read instruction is initiated by executing an 8-bit com- automatically increment until the highest memory address mand, 03H, followed by address bits [A -A ]. CE# must is reached. Once the highest memory address is reached, 23 0 remain active low for the duration of the Read cycle. See the address pointer will automatically increment to the Figure 5 for the Read sequence. beginning (wrap-around) of the address space, i.e. for CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 47 48 5556 6364 70 SCK MODE 0 03 ADD. ADD. ADD. SI MSB MSB N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1231 F04.1 FIGURE 5: READ SEQUENCE Byte-Program The Byte-Program instruction programs the bits in the Program instruction is initiated by executing an 8-bit com- selected byte to the desired data. The selected byte must mand, 02H, followed by address bits [A -A ]. Following the 23 0 be in the erased state (FFH) when initiating a Program address, the data is input in order from MSB (bit 7) to LSB operation. A Byte-Program instruction applied to a pro- (bit 0). CE# must be driven high before the instruction is tected memory area will be ignored. executed. The user may poll the Busy bit in the software status register or wait T for the completion of the internal Prior to any Write operation, the Write-Enable (WREN) BP self-timed Byte-Program operation. See Figure 6 for the instruction must be executed. CE# must remain active low Byte-Program sequence. for the duration of the Byte-Program instruction. The Byte- CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 SCK MODE 0 SI 02 ADD. ADD. ADD. DIN MSB MSB MSB LSB SO HIGH IMPEDANCE 1231 F05.1 FIGURE 6: Byte-Program Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 9

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to status register or wait T for the completion of each inter- BP be programmed without re-issuing the next sequential nal self-timed Byte-Program cycle. Once the device com- address location. This feature decreases total program- pletes programming byte, the next sequential address may ming time when the entire memory array is to be pro- be program, enter the 8-bit command, AFH, followed by the grammed. An AAI program instruction pointing to a data to be programmed. When the last desired byte had protected memory area will be ignored. The selected been programmed, execute the Write-Disable (WRDI) address range must be in the erased state (FFH) when ini- instruction, 04H, to terminate AAI. After execution of the tiating an AAI program instruction. WRDI command, the user must poll the Status register to ensure the device completes programming. See Figure 7 Prior to any write operation, the Write-Enable (WREN) for AAI programming sequence. instruction must be executed. The AAI program instruction is initiated by executing an 8-bit command, AFH, followed There is no wrap mode during AAI programming; once the by address bits [A -A ]. Following the addresses, the data highest unprotected memory address is reached, the 23 0 is input sequentially from MSB (bit 7) to LSB (bit 0). CE# device will exit AAI operation and reset the Write-Enable- must be driven high before the AAI program instruction is Latch bit (WEL=0). executed. The user must poll the BUSY bit in the software TBP TBP CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 313233343536373839 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 SCK MODE 0 SI AF A[23:16] A[15:8] A[7:0] Data Byte 1 AF Data Byte 2 TBP CE# 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 101112131415 SCK AF Last Data Byte 04 05 SI Write Disable (WRDI) Read Status Register (RDSR) Instruction to terminate Instruction to verify end of AAI Operation AAI Operation SO DOUT 1231 F06.1 FIGURE 7: Auto Address Increment (AAI) Program Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 10

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 (A =Most Significant address) are used to determine the MS KByte sector to FFH. A Sector-Erase instruction applied to sector address (SA ), remaining address bits can be V or X IL a protected memory area will be ignored. Prior to any Write V CE# must be driven high before the instruction is exe- IH. operation, the Write-Enable (WREN) instruction must be cuted. The user may poll the Busy bit in the software status executed. CE# must remain active low for the duration of register or wait T for the completion of the internal self- SE the any command sequence. The Sector-Erase instruction timed Sector-Erase cycle. See Figure 8 for the Sector- is initiated by executing an 8-bit command, 20H, followed Erase sequence. by address bits [A -A ]. Address bits [A -A ] 23 0 MS 12 CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 20 ADD. ADD. ADD. SI MSB MSB SO HIGH IMPEDANCE 1231 F07.1 FIGURE 8: Sector-Erase Sequence Block-Erase The Block-Erase instruction clears all bits in the selected 32 address bits [A -A ]. Address bits [A -A ] (A = Most 23 0 MS 15 MS KByte block to FFH. A Block-Erase instruction applied to a significant address) are used to determine block address protected memory area will be ignored. Prior to any Write (BA ), remaining address bits can be V or V . CE# must X IL IH operation, the Write-Enable (WREN) instruction must be be driven high before the instruction is executed. The user executed. CE# must remain active low for the duration of may poll the Busy bit in the software status register or wait any command sequence. The Block-Erase instruction is T for the completion of the internal self-timed Block- BE initiated by executing an 8-bit command, 52H, followed by Erase cycle. See Figure 9 for the Block-Erase sequence. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 52 ADD. ADD. ADD. SI MSB MSB SO HIGH IMPEDANCE 1231 F08.1 FIGURE 9: Block-Erase Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 11

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to by executing an 8-bit command, 60H. CE# must be driven FFH. A Chip-Erase instruction will be ignored if any of the high before the instruction is executed. The user may poll memory area is protected. Prior to any Write operation, the the Busy bit in the software status register or wait T for CE Write-Enable (WREN) instruction must be executed. CE# the completion of the internal self-timed Chip-Erase cycle. must remain active low for the duration of the Chip-Erase See Figure 10 for the Chip-Erase sequence. instruction sequence. The Chip-Erase instruction is initiated CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 60 SI MSB SO HIGH IMPEDANCE 1231 F09.1 FIGURE10: Chip-Erase Sequence Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows read- CE# must be driven low before the RDSR instruction is ing of the status register. The status register may be read at entered and remain low until the status data is read. Read- any time even during a Write (Program/Erase) operation. Status-Register is continuous with ongoing clock cycles When a Write operation is in progress, the Busy bit may be until it is terminated by a low to high transition of the CE#. checked before sending any new commands to assure that See Figure 11 for the RDSR instruction sequence. the new commands are properly received by the device. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE 0 05 SI MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB Status 1231 F10.1 Register Out FIGURE11: Read-Status-Register (RDSR) Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 12

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 06 SI MSB SO HIGH IMPEDANCE 1231 F11.1 FIGURE12: Write Enable (WREN) Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write- Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE# must be driven high before the WRDI instruction is executed. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 04 SI MSB SO HIGH IMPEDANCE 1231 F12.1 FIGURE13: Write Disable (WRDI) Sequence Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write- Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write- Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 13

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Write-Status-Register (WRSR) When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status reg- The Write-Status-Register instruction works in conjunction ister can all be changed. As long as BPL bit is set to 0 or with the Enable-Write-Status-Register (EWSR) instruction WP# pin is driven high (V ) prior to the low-to-high transi- to write new values to the BP1, BP0, and BPL bits of the IH tion of the CE# pin at the end of the WRSR instruction, the status register. The Write-Status-Register instruction must BP0, BP1, and BPL bit in the status register can all be be executed immediately after the execution of the Enable- altered by the WRSR instruction. In this case, a single Write-Status-Register instruction (very next instruction bus WRSR instruction can set the BPL bit to “1” to lock down cycle). This two-step instruction sequence of the EWSR the status register as well as altering the BP0 and BP1 bit instruction followed by the WRSR instruction works like at the same time. See Table 3 for a summary description of SDP (software data protection) command structure which WP# and BPL functions. CE# must be driven low before prevents any accidental alteration of the status register val- the command sequence of the WRSR instruction is ues. The Write-Status-Register instruction will be ignored entered and driven high before the WRSR instruction is when WP# is low and BPL bit is set to “1”. When the WP# executed. See Figure 14 for EWSR and WRSR instruction is low, the BPL bit can only be set from “0” to “1” to lock- sequences. down the status register, but cannot be reset from “1” to “0”. CE# MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 101112131415 SCK MODE 0 MODE 0 STATUS REGISTER IN 50 01 7 6 5 4 3 2 1 0 SI MSB MSB MSB HIGH IMPEDANCE SO 1231 F13.1 FIGURE14: Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR) Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 14

2 Mbit SPI Serial Flash SST25VF020 Data Sheet Read-ID The Read-ID instruction identifies the device as address 00000H and the device ID is located in address SST25VF020 and manufacturer as SST. The device infor- 00001H. Once the device is in Read-ID mode, the manu- mation can be read from executing an 8-bit command, 90H facturer’s and device ID output data toggles between or ABH, followed by address bits [A -A ]. Following the address 00000H and 00001H until terminated by a low to 23 0 Read-ID instruction, the manufacturer’s ID is located in high transition on CE#. CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 4748 5556 63 SCK MODE 0 90 or AB 00 00 ADD1 SI MSB MSB HIGH HIGH IMPEDANCE IMPEDANCE SO BF Device ID BF Device ID MSB Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1231 F14.1 FIGURE15: Read-ID Sequence ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 15

2 Mbit SPI Serial Flash SST25VF020 Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE AC CONDITIONS OF TEST Range Ambient Temp V Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns DD Commercial 0°C to +70°C 2.7-3.6V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF Industrial -40°C to +85°C 2.7-3.6V See Figures 20 and 21 Extended -20°C to +85°C 2.7-3.6V TABLE 7: DC Operating Characteristics V = 2.7-3.6V DD Limits Symbol Parameter Min Max Units Test Conditions I Read Current 10 mA CE#=0.1 V /0.9 V @20 MHz, SO=open DDR DD DD I Program and Erase Current 30 mA CE#=V DDW DD I Standby Current 15 µA CE#=V , V =V or V SB DD IN DD SS I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 1 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 0.7 V V V =V Max IH DD DD DD V Output Low Voltage 0.2 V I =100 µA, V =V Min OL OL DD DD V Output High Voltage V -0.2 V I =-100 µA, V =V Min OH DD OH DD DD T7.0 1231 TABLE 8: Recommended System Power-up Timings Symbol Parameter Minimum Units T 1 V Min to Read Operation 10 µs PU-READ DD T 1 V Min to Write Operation 10 µs PU-WRITE DD T8.0 1231 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: Capacitance (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C 1 Output Pin Capacitance V = 0V 12 pF OUT OUT C 1 Input Capacitance V = 0V 6 pF IN IN T9.0 1231 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 16

2 Mbit SPI Serial Flash SST25VF020 Data Sheet TABLE 10: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method N 1 Endurance 10,000 Cycles JEDEC Standard A117 END T 1 Data Retention 100 Years JEDEC Standard A103 DR I 1 Latch Up 100 + I mA JEDEC Standard 78 LTH DD T10.0 1231 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: AC Operating Characteristics V = 2.7-3.6V DD Limits Symbol Parameter Min Max Units F Serial Clock Frequency 20 MHz CLK T Serial Clock High Time 20 ns SCKH T Serial Clock Low Time 20 ns SCKL T Serial Clock Rise Time 5 ns SCKR T Serial Clock Fall Time 5 ns SCKF T 1 CE# Active Setup Time 20 ns CES T 1 CE# Active Hold Time 20 ns CEH T 1 CE# Not Active Setup Time 10 ns CHS T 1 CE# Not Active Hold Time 10 ns CHH T CE# High Time 100 ns CPH T CE# High to High-Z Output 20 ns CHZ T SCK Low to Low-Z Output 0 ns CLZ T Data In Setup Time 4 ns DS T Data In Hold Time 5 ns DH T HOLD# Low Setup Time 10 ns HLS T HOLD# High Setup Time 10 ns HHS T HOLD# Low Hold Time 15 ns HLH T HOLD# High Hold Time 10 ns HHH T HOLD# Low to High-Z Output 20 ns HZ T HOLD# High to Low-Z Output 20 ns LZ T Output Hold from SCK Change 0 ns OH T Output Valid from SCK 23 ns V T Sector-Erase 25 ms SE T Block-Erase 25 ms BE T Chip-Erase 100 ms SCE T Byte-Program 20 µs BP T11.21231 1. Relative to SCK. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 17

2 Mbit SPI Serial Flash SST25VF020 Data Sheet TCPH CE# TCHH TCES TSCKF TCEH TCHS SCK TDS TDH TSCKR MSB LSB SI HIGH-Z HIGH-Z SO 1231 F15.0 FIGURE16: Serial Input Timing Diagram CE# TSCKH TSCKL SCK TOH TCLZ TCHZ SO MSB LSB TV SI 1231 F16.0 FIGURE17: Serial Output Timing Diagram ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 18

2 Mbit SPI Serial Flash SST25VF020 Data Sheet CE# THHH THLS THHS SCK THLH THZ TLZ SO SI HOLD# 1231 F17.0 FIGURE18: Hold Timing Diagram VDD VDD Max Chip selection is not allowed. All commands are rejected by the device. VDD Min TPU-READ Device fully accessible TPU-WRITE Time 1231 F18.0 FIGURE19: Power-up Timing Diagram ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 19

2 Mbit SPI Serial Flash SST25VF020 Data Sheet VIHT VHT VHT INPUT? REFERENCE POINTS OUTPUT VLT VLT VILT 1231 F19.1 AC test inputs are driven at V (0.9V ) for a logic “1” and V (0.1V ) for a logic “0”. Measurement reference points IHT DD ILT DD for inputs and outputs are V (0.7V ) and V (0.3V ). Input rise and fall times (10% ↔ 90%) are <5 ns. HT DD LT DD Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE20: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1231 F20.0 FIGURE21: A Test Load Example ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 20

2 Mbit SPI Serial Flash SST25VF020 Data Sheet PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST25VFXXX - XXX - XX - XXX Environmental Attribute E1 = non-Pb Package Modifier A = 8 leads or contacts Package Type S = SOIC 150 mil body width Q = WSON Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 20 = 20 MHz Device Density 020 = 2 Mbit Voltage V = 2.7-3.6V Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. Valid combinations for SST25VF020 SST25VF020-20-4C-SAE SST25VF020-20-4C-QAE SST25VF020-20-4I-SAE SST25VF020-20-4I-QAE SST25VF020-20-4E-SAE SST25VF020-20-4E-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 21

2 Mbit SPI Serial Flash SST25VF020 Data Sheet PACKAGING DIAGRAMS Pin #1 Identifier TOP VIEW SIDE VIEW 7° 4 places 0.51 5.0 0.33 4.8 1.27 BSC END VIEW 45° 7° 0.25 4 places 0.10 4.00 3.80 1.75 6.20 1.35 0.25 0° 5.80 0.19 8° 1.27 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, 0.40 although some dimensions may be more stringent. 08-soic-5x6-SA-8 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 1mm FIGURE22: 8-lead Small Outline Integrated Circuit (SOIC) 150 mil body width (4.9mm x 6mm) SST Package Code: SA ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 22

2 Mbit SPI Serial Flash SST25VF020 Data Sheet TOP VIEW SIDE VIEW BOTTOM VIEW Pin #1 0.2 Pin #1 Corner 1.27 BSC 5.00 ± 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.05 Max 0.50 6.00 ± 0.10 0.80 0.70 CROSS SECTION Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 0.80 3. The external paddle is electrically connected to the 0.70 die back-side and possibly to certain VSS leads. 1mm This paddle can be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. 8-wson-5x6-QA-9.0 Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. FIGURE23: 8-contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: QA TABLE 12: Revision History Number Description Date 00 (cid:129) Initial release of S71231 Apr 2003 (2 Mbit and 4 Mbit parts were originally described in data sheet S71192) 01 (cid:129) Updated Figures 3, 5 - 15: Aligned SI waveform with rising edge of clock Aug 2003 02 (cid:129) Added new 8-SOIC (S2A) package and associated MPNs Oct 2003 03 (cid:129) 2004 Data Book Dec 2003 (cid:129) Updated the Package Outline for S2A 04 (cid:129) Added Extended temperature and associated MPNs Jun 2004 05 (cid:129) Revised Absolute Max. Stress Ratings for Surface Mount Solder Reflow Temp. Nov 2005 06 (cid:129) Updated QA package drawing to revision 9. Jan 2006 (cid:129) Removed leaded parts. (cid:129) Added footnote to product ordering section. 07 (cid:129) Removed all references to SST25VF040 due to end of life. New SST25VF040 EOL Oct 2006 data sheet is S71231(04). (cid:129) Revised Hold Operation, page5 paragraph 4, to indicate that device returns to standby mode when CE# is driven active high during a Hold Condition. Silicon Storage Technology, Inc. (cid:129) 1171 Sonora Court (cid:129) Sunnyvale, CA 94086 (cid:129) Telephone 408-735-9110 (cid:129) Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2006 Silicon Storage Technology, Inc. S71231-07-000 10/06 23

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: SST25VF020-20-4C-SAE SST25VF020-20-4C-QAE SST25VF020-20-4I-SAE SST25VF020-20-4C-SAE-T SST25VF020-20-4C-QAE-T SST25VF020-20-4I-QAE SST25VF020-20-4I-QAE-T SST25VF020-20-4I-SAE-T SST25VF020-20-4C-QA SST25VF020-20-4C-SA SST25VF020-20-4E-QA SST25VF020-20-4E-QAE SST25VF020- 20-4E-SA SST25VF020-20-4E-SAE SST25VF020-20-4I-QA SST25VF020-20-4I-SA