16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet SST's 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ulti- mately lowers total system costs. The SST25VF016B devices are enhanced with improved operating frequency and lower power consumption. SST25VF016B SPI serial flash memories are manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunnel- ing injector attain better reliability and manufacturability compared with alternate approaches. Features (cid:129) SingleVoltageReadandWriteOperations (cid:129) AutoAddressIncrement(AAI)Programming –2.7-3.6V –DecreasetotalchipprogrammingtimeoverByte-Pro- gramoperations (cid:129) SerialInterfaceArchitecture (cid:129) End-of-WriteDetection –SPICompatible:Mode0andMode3 –SoftwarepollingtheBUSYbitinStatusRegister (cid:129) HighSpeedClockFrequency –BusyStatusreadoutonSOpininAAIMode –Upto80MHz (cid:129) HoldPin(HOLD#) (cid:129) SuperiorReliability –Suspendsaserialsequencetothememory –Endurance:100,000Cycles(typical) withoutdeselectingthedevice –Greaterthan100yearsDataRetention (cid:129) WriteProtection(WP#) (cid:129) LowPowerConsumption: –Enables/DisablestheLock-Downfunctionofthestatus –ActiveReadCurrent:10mA(typical) register –StandbyCurrent:5µA(typical) (cid:129) SoftwareWriteProtection (cid:129) FlexibleEraseCapability –WriteprotectionthroughBlock-Protectionbitsinstatus –Uniform4KBytesectors register –Uniform32KByteoverlayblocks (cid:129) TemperatureRange –Uniform64KByteoverlayblocks –Commercial:0°Cto+70°C (cid:129) FastEraseandByte-Program: –Industrial:-40°Cto+85°C –Chip-EraseTime:35ms(typical) (cid:129) PackagesAvailable –Sector-/Block-EraseTime:18ms(typical) –Byte-ProgramTime:7µs(typical) –8-leadSOIC(200mils) –8-contactWSON(6mmx5mm) (cid:129) AlldevicesareRoHScompliant www.microchip.com ©2011SiliconStorageTechnology,Inc. DS25044A 08/11

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Product Description SST’s25seriesSerialFlashfamilyfeaturesafour-wire,SPI-compatibleinterfacethatallowsforalow pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF016B devices are enhanced with improved operating frequency and even lower power con- sumptionthantheoriginalSST25VFxxxAdevices.SST25VF016BSPIserialflashmemoriesareman- ufacturedwithSST’sproprietary,high-performanceCMOSSuperFlashtechnology.Thesplit-gatecell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternateapproaches. The SST25VF016B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF016B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gramandhasashortererasetime,thetotalenergyconsumedduringanyEraseorProgramoperation islessthanalternativeflashmemorytechnologies. The SST25VF016B device is offered in both 8-lead SOIC (200 mils) and 8-contact WSON (6mm x 5mm)packages.SeeFigure2forpinassignments. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 2

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Block Diagram SuperFlash X - Decoder Address Memory Buffers and Latches Y - Decoder I/O Buffers Control Logic and Data Latches Serial Interface CE# SCK SI SO WP# HOLD# 1271B1.0 Figure 1: Functional Block Diagram ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 3

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Pin Description CE# 1 8 VDD CE# 1 8 VDD SO 2 7 HOLD# SO 2 7 HOLD# TopView TopView WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 127108-wsonQAP2.0 127108-soicS2AP1.0 8-LeadSOIC 8-ContactWSON Figure 2: Pin Assignments Table 1: Pin Description Symbol PinName Functions SCK SerialClock Toprovidethetimingoftheserialinterface. Commands,addresses,orinputdataarelatchedontherisingedgeoftheclock input,whileoutputdataisshiftedoutonthefallingedgeoftheclockinput. SI SerialDataInput Totransfercommands,addresses,ordataseriallyintothedevice. Inputsarelatchedontherisingedgeoftheserialclock. SO SerialDataOutput Totransferdataseriallyoutofthedevice. Dataisshiftedoutonthefallingedgeoftheserialclock. OutputsFlashbusystatusduringAAIProgrammingwhenreconfiguredasRY/ BY#pin.See“HardwareEnd-of-WriteDetection”onpage12fordetails. CE# ChipEnable ThedeviceisenabledbyahightolowtransitiononCE#.CE#mustremainlowfor thedurationofanycommandsequence. WP# WriteProtect TheWriteProtect(WP#)pinisusedtoenable/disableBPLbitinthestatusregis- ter. HOLD# Hold TotemporarilystopserialcommunicationwithSPIflashmemorywithoutresetting thedevice. V PowerSupply Toprovidepowersupplyvoltage: 2.7-3.6VforSST25VF016B DD V Ground SS T1.025044 ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 4

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Memory Organization The SST25VF016B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32KByteoverlayblocksand64KByteoverlayerasableblocks. Device Operation TheSST25VF016BisaccessedthroughtheSPI(SerialPeripheralInterface)buscompatibleprotocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessedthroughtheSerialDataInput(SI),SerialDataOutput(SO),andSerialClock(SCK). TheSST25VF016BsupportsbothMode0(0,0)andMode3(1,1)ofSPIbusoperations.Thedifference betweenthetwomodes,asshowninFigure3,isthestateoftheSCKsignalwhenthebusmasterisin Stand-bymodeandnodataisbeingtransferred.TheSCKsignalislowforMode0andSCKsignalis highforMode3.Forbothmodes,theSerialDataIn(SI)issampledattherisingedgeoftheSCKclock signalandtheSerialDataOutput(SO)isdrivenafterthefallingedgeoftheSCKclocksignal. CE# MODE3 MODE3 SCK MODE0 MODE0 SI Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DONTCARE MSB HIGHIMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SO MSB 1271SPIprot.0 Figure 3: SPI Protocol ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 5

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Hold Operation TheHOLD#pinisusedtopauseaserialsequenceunderwaywiththeSPIflashmemorywithoutreset- tingtheclockingsequence.ToactivatetheHOLD#mode,CE#mustbeinactivelowstate.TheHOLD# modebeginswhentheSCKactivelowstatecoincideswiththefallingedgeoftheHOLD#signal.The HOLDmodeendswhentheHOLD#signal’srisingedgecoincideswiththeSCKactivelowstate. IfthefallingedgeoftheHOLD#signaldoesnotcoincidewiththeSCKactivelowstate,thenthedevice enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode whentheSCKnextreachestheactivelowstate.SeeFigure4forHoldConditionwaveform. OncethedeviceentersHoldmode,SOwillbeinhigh-impedancestatewhileSIandSCKcanbeV orV IL IH. IfCE#isdrivenactivehighduringaHoldcondition,itresetstheinternallogicofthedevice.Aslongas HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device,HOLD#mustbedrivenactivehigh,andCE#mustbedrivenactivelow.SeeFigure24forHold timing. SCK HOLD# Active Hold Active Hold Active 1271HoldCond.0 Figure 4: Hold Condition Waveform Write Protection SST25VF016B provides software Write protection. The Write Protect pin (WP#) enables or disables thelock-downfunctionofthestatusregister.TheBlock-Protectionbits(BP3,BP2,BP1,BP0,andBPL) inthestatusregisterprovideWriteprotectiontothememoryarrayandthestatusregister.SeeTable4 fortheBlock-Protectiondescription. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. WhenWP#isdrivenlow,theexecutionoftheWrite-Status-Register(WRSR)instructionisdeterminedby thevalueoftheBPLbit(seeTable2).WhenWP#ishigh,thelock-downfunctionoftheBPLbitisdisabled. Table 2: Conditions to Execute Write-Status-Register (WRSR) Instruction WP# BPL ExecuteWRSRInstruction L 1 NotAllowed L 0 Allowed H X Allowed T2.025044 ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 6

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Status Register The software status register provides status on whether the flash memory array is available for any ReadorWriteoperation,whetherthedeviceisWriteenabled,andthestateoftheMemoryWritepro- tection. During an internal Erase or Program operation, the status register may be read only to deter- mine the completion of an operation in progress. Table 3 describes the function of each bit in the softwarestatusregister. Table 3: Software Status Register Defaultat Bit Name Function Power-up Read/Write 0 BUSY 1=InternalWriteoperationisinprogress 0 R 0=NointernalWriteoperationisinprogress 1 WEL 1=DeviceismemoryWriteenabled 0 R 0=DeviceisnotmemoryWriteenabled 2 BP0 Indicatecurrentlevelofblockwriteprotection(SeeTable4) 1 R/W 3 BP1 Indicatecurrentlevelofblockwriteprotection(SeeTable4) 1 R/W 4 BP2 Indicatecurrentlevelofblockwriteprotection(SeeTable4) 1 R/W 5 BP3 Indicatecurrentlevelofblockwriteprotection(SeeTable4) 0 R/W 6 AAI AutoAddressIncrementProgrammingstatus 0 R 1=AAIprogrammingmode 0=Byte-Programmode 7 BPL 1=BP3,BP2,BP1,BP0areread-onlybits 0 R/W 0=BP3,BP2,BP1,BP0areread/writable T3.0 25044 Busy TheBusybitdetermineswhetherthereisaninternalEraseorProgramoperationinprogress.A“1”for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is readyforthenextvalidoperation. Write Enable Latch (WEL) The Write-Enable-Latch (WEL) bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase)commands.TheWrite-Enable-Latchbitisautomaticallyresetunderthefollowingconditions: (cid:129) Power-up (cid:129) Write-Disable(WRDI)instructioncompletion (cid:129) Byte-Programinstructioncompletion (cid:129) AutoAddressIncrement(AAI)programmingiscompletedorreacheditshighestunpro- tectedmemoryaddress (cid:129) Sector-Eraseinstructioncompletion (cid:129) Block-Eraseinstructioncompletion (cid:129) Chip-Eraseinstructioncompletion (cid:129) Write-Status-Registerinstructions ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 7

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Auto Address Increment (AAI) TheAutoAddressIncrementProgramming-StatusbitprovidesstatusonwhetherthedeviceisinAuto AddressIncrement(AAI)programmingmodeorByte-Programmode.ThedefaultatpowerupisByte- Programmode. Block Protection (BP3,BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as defined in Table4,tobesoftwareprotectedagainstanymemoryWrite(ProgramorErase)operation.TheWrite- Status-Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP#ishighortheBlock-Protect-Lock(BPL)bitis0.Chip-ErasecanonlybeexecutedifBlock-Protec- tionbitsareall0.Afterpower-up,BP3,BP2,BP1andBP0aresetto1. Block Protection Lock-Down (BPL) WP# pin driven low (V ), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it IL preventsanyfurtheralterationoftheBPL,BP3,BP2,BP1,andBP0bits.WhentheWP#pinisdriven high(V ),theBPLbithasnoeffectanditsvalueis“Don’tCare”.Afterpower-up,theBPLbitisresetto IH 0. Table 4: Software Status Register Block Protection for SST25VF016B1 StatusRegisterBit2 ProtectedMemoryAddress ProtectionLevel BP3 BP2 BP1 BP0 16Mbit None X 0 0 0 None Upper1/32 X 0 0 1 1F0000H-1FFFFFH Upper1/16 X 0 1 0 1E0000H-1FFFFFH Upper1/8 X 0 1 1 1C0000H-1FFFFFH Upper1/4 X 1 0 0 180000H-1FFFFFH Upper1/2 X 1 0 1 100000H-1FFFFFH AllBlocks X 1 1 0 000000H-1FFFFFH AllBlocks X 1 1 1 000000H-1FFFFFH T4.025044 1. X=Don’tCare(RESERVED)defaultis“0 2. Defaultatpower-upforBP2,BP1,andBP0is‘111’.(AllBlocksProtected) ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 8

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The instructionbuscyclesare8bitseachforcommands(OpCode),data,andaddresses.Priortoexecut- inganyByte-Program,AutoAddressIncrement(AAI)programming,Sector-Erase,Block-Erase,Write- Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first.ThecompletelistofinstructionsisprovidedinTable5.Allinstructionsaresynchronizedoffahigh tolowtransitionofCE#.InputswillbeacceptedontherisingedgeofSCKstartingwiththemostsignif- icantbit.CE#mustbedrivenlowbeforeaninstructionisenteredandmustbedrivenhighafterthelast bitoftheinstructionhasbeenshiftedin(exceptforRead,Read-ID,andRead-Status-Registerinstruc- tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (OpCode),addresses,anddataareallinputfromthemostsignificantbit(MSB)first. Table 5: Device Operation Instructions Address Dummy Data Maximum Instruction Description OpCodeCycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency Read ReadMemoryat25MHz 00000011b(03H) 3 0 1to 25MHz High-Speed ReadMemoryat80MHz 00001011b(0BH) 3 1 1to 80MHz Read 4KByteSec- Erase4KByteof 00100000b(20H) 3 0 0 80MHz tor-Erase3 memoryarray 32KByte Erase32KByteblock 01010010b(52H) 3 0 0 80MHz Block-Erase4 ofmemoryarray 64KByte Erase64KByteblock 11011000b(D8H) 3 0 0 80MHz Block-Erase5 ofmemoryarray Chip-Erase EraseFullMemoryArray 01100000b(60H) 0 0 0 80MHz or 11000111b(C7H) Byte-Program ToProgramOneDataByte 00000010b(02H) 3 0 1 80MHz AAI-Word-Pro- AutoAddressIncrement 10101101b(ADH) 3 0 2to 80MHz gram6 Programming RDSR7 Read-Status-Register 00000101b(05H) 0 0 1to 80MHz EWSR Enable-Write-Status-Reg- 0101b0000b 0 0 0 80MHz ister (50H) WRSR Write-Status-Register 00000001b(01H) 0 0 1 80MHz WREN Write-Enable 00000110b(06H) 0 0 0 80MHz WRDI Write-Disable 00000100b(04H) 0 0 0 80MHz RDID8 Read-ID 10010000b(90H) 3 0 1to 80MHz or 10101011b(ABH) JEDEC-ID JEDECIDread 10011111b(9FH) 0 0 3to 80MHz EBSY EnableSOtooutputRY/BY# 01110000b(70H) 0 0 0 80MHz statusduringAAIprogram- ming DBSY DisableSOasRY/BY# 10000000b(80H) 0 0 0 80MHz statusduringAAIprogram- ming T5.0 25044 1. Onebuscycleiseightclockperiods. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 9

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet 2. AddressbitsabovethemostsignificantbitofeachdensitycanbeVILorVIH. 3. 4KByteSectorEraseaddresses:useAMS-A12,remainingaddressesaredon’tcarebutmustbeseteitheratVILorVIH. 4. 32KByteBlockEraseaddresses:useAMS-A15,remainingaddressesaredon’tcarebutmustbeseteitheratVILorVIH. 5. 64KByteBlockEraseaddresses:useAMS-A16,remainingaddressesaredon’tcarebutmustbeseteitheratVILorVIH. 6. Tocontinueprogrammingtothenextsequentialaddresslocation,enterthe8-bitcommand,ADH,followedby2bytesof datatobeprogrammed.DataByte0willbeprogrammedintotheinitialaddress[A23-A1]withA0=0,DataByte1willbe programmedintothe initialaddress[A23-A1]withA0=1. 7. TheRead-Status-RegisteriscontinuouswithongoingclockcyclesuntilterminatedbyalowtohightransitiononCE#. 8. Manufacturer’sIDisreadwithA0=0,andDeviceIDisreadwithA0=1.Allotheraddressbitsare00H.TheManufac- turer’sIDanddeviceIDoutputstreamiscontinuousuntilterminatedbyalow-to-hightransitiononCE#. Read (25 MHz) TheReadinstruction,03H,supportsupto25MHzRead.Thedeviceoutputsthedatastartingfromthe specified address location. The data output stream is continuous through all addresses until termi- natedbyalowtohightransitiononCE#.Theinternaladdresspointerwillautomaticallyincrementuntil the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A - 23 A ]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read 0 sequence. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 47 48 5556 6364 70 SCK MODE0 03 ADD. ADD. ADD. SI MSB MSB N N+1 N+2 N+3 N+4 HIGHIMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1271ReadSeq.0 Figure 5: Read Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 10

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet High-Speed-Read (80 MHz) TheHigh-Speed-Readinstructionsupportingupto80MHzReadisinitiatedbyexecutingan8-bitcom- mand, 0BH, followed by address bits [A -A ] and a dummy byte. CE# must remain active low for the 23 0 durationoftheHigh-Speed-Readcycle.SeeFigure6fortheHigh-Speed-Readsequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci- fiedaddresslocation.Thedataoutputstreamiscontinuousthroughalladdressesuntilterminatedbya low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached. Once the highest memory address is reached, the address pointer willautomaticallyincrementtothebeginning(wrap-around)oftheaddressspace.Oncethedatafrom addresslocation1FFFFFHhasbeenread,thenextoutputwillbefromaddresslocation000000H. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 23 24 3132 3940 4748 55 56 6364 7172 80 SCKMODE0 SI 0B ADD. ADD. ADD. X MSB MSB N N+1 N+2 N+3 N+4 SO HIGHIMPEDANCE DOUT DOUT DOUT DOUT DOUT MSB Note: X=DummyByte:8ClocksInputDummyCycle(VILorVIH) 1271HSRdSeq.0 Figure 6: High-Speed-Read Sequence Byte-Program TheByte-Programinstructionprogramsthebitsintheselectedbytetothedesireddata.Theselected bytemust beinthe erasedstate(FFH) wheninitiatinga Program operation. AByte-Programinstruction appliedtoaprotectedmemoryareawillbeignored. PriortoanyWriteoperation,theWrite-Enable(WREN)instructionmustbeexecuted.CE#mustremain activelowforthedurationoftheByte-Programinstruction.TheByte-Programinstructionisinitiatedby executingan8-bitcommand,02H,followedbyaddressbits[A -A ].Followingtheaddress,thedatais 23 0 input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe- cuted. The user may poll the Busy bit in the software status register or wait T for the completion of BP theinternalself-timedByte-Programoperation.SeeFigure7fortheByte-Programsequence. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 SCK MODE0 SI 02 ADD. ADD. ADD. DIN MSB MSB MSB LSB SO HIGHIMPEDANCE 1271ByteProg.0 Figure 7: Byte-Program Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 11

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes orentirememoryarrayistobeprogrammed.AnAAIWordprograminstructionpointingtoaprotected memoryareawillbeignored.Theselectedaddressrangemustbeintheerasedstate(FFH)whenini- tiating an AAI Word Program operation. While within AAI Word Programming sequence, only the fol- lowing instructions are valid: for software end-of-write detection—AAI Word (ADH), WRDI (04H), and RDSR(05H);forhardwareend-of-writedetection—AAIWord(ADH)andWRDI(04H).Therearethree options to determine the completion of each AAI Word program cycle: hardware detection by reading theSerialOutput,softwaredetectionbypollingtheBUSYbitinthesoftwarestatusregister,orwaitT BP. Referto“End-of-WriteDetection”fordetails. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. Initiate the AAI WordPrograminstructionbyexecutingan8-bitcommand,ADH,followedbyaddressbits[A -A ].Fol- 23 0 lowingtheaddresses,twobytesofdataareinputsequentially,eachonefromMSB(Bit7)toLSB(Bit 0). The first byte of data (D0) is programmed into the initial address [A -A ] with A =0, the second 23 1 0 byte of Data (D1) is programmed into the initial address [A -A ] with A =1. CE# must be driven high 23 1 0 before executing the AAI Word Program instruction. Check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the next two sequential addressesmaybeprogrammed,followedbythenexttwo,andsoon. Whenprogrammingthelastdesiredword,orthehighestunprotectedmemoryaddress,checkthebusy statususingeitherthehardwareorsoftware(RDSRinstruction)methodtocheckforprogramcomple- tion. Once programming is complete, use the applicable method to terminate AAI. If the device is in Software End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the deviceisinAAIHardwareEnd-of-WriteDetectionmode,executetheWrite-Disable(WRDI)instruction, 04H, followed by the 8-bit DBSY command, 80H. There is no wrap mode during AAI programming once the highest unprotected memory address is reached. See Figures 10 and 11 for the AAI Word programmingsequence. End-of-Write Detection There are three methods to determine completion of a program cycle during AAI Word programming: hardwaredetectionbyreadingtheSerialOutput,softwaredetectionbypollingtheBUSYbitintheSoft- ware Status Register, or wait T The Hardware End-of-Write detection method is described in the BP. sectionbelow. Hardware End-of-Write Detection The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the SoftwareStatusRegisterduringanAAIWordprogramoperation.The8-bitcommand,70H,configures theSerialOutput(SO)pintoindicateFlashBusystatusduringAAIWordprogramming.(seeFigure8) The8-bit command, 70H,must be executed prior toinitiating an AAIWord-Program instruction.Once aninternalprogrammingoperationbegins,assertingCE#willimmediatelydrivethestatusoftheinter- nalflashstatusontheSOpin.A‘0’indicatesthedeviceisbusyanda‘1’indicatesthedeviceisready forthenextinstruction.De-assertingCE#willreturntheSOpintotri-state.WhileinAAIandHardware End-of-Writedetectionmode,theonlyvalidinstructionsareAAIWord(ADH)andWRDI(04H). To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the Write- Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY#statusduringtheAAIcommand.SeeFigures9and10. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 12

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet CE# MODE3 0 1 2 3 4 5 6 7 SCK MODE0 70 SI MSB SO HIGHIMPEDANCE 1271EnableSO.0 Figure 8: Enable SO as Hardware RY/BY# During AAI Programming CE# MODE3 0 1 2 3 4 5 6 7 SCK MODE0 80 SI MSB SO HIGHIMPEDANCE 1271DisableSO.0 Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 13

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet CE# MODE3 0 7 0 7 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 SCKMODE0 SI EBSY WREN AD A A A D0 D1 AD D2 D3 LoadAAIcommand,Address,2bytesdata SO CheckforFlashBusyStatustoloadnextvalid1command CE#cont. 0 7 8 1516 23 0 7 0 7 0 7 8 15 SCKcont. SIcont. AD Dn-1 Dn WRDI DBSY RDSR Last2 WRDI followedbyDBSY DataBytes toexitAAIMode SOcont. DOUT CheckforFlashBusyStatustoloadnextvalid1command Note: 1.ValidcommandsduringAAIprogramming:AAIcommandorWRDIcommand 2.UsermustconfiguretheSOpintooutputFlashBusystatusduringAAIprogramming 1271AAI.HW.3 Figure 10:Auto Address Increment (AAI) Word-Program Sequence with Hardware End-of-Write Detection WaitTBPorpollSoftwareStatus registertoloadnextvalid1command CE# MODE3 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 0 7 8 1516 23 0 7 0 7 8 15 SCK MODE0 SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR LoadAAIcommand,Address,2bytesdata Last2 WRDItoexit DataBytes AAIMode SO DOUT Note: 1.ValidcommandsduringAAIprogramming:AAIcommand,RDSRcommand,orWRDIcommand 1271AAI.SW.1 Figure 11:Auto Address Increment (AAI) Word-Program Sequence with Software End-of-Write Detection ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 14

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet 4-KByte Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instructionappliedtoaprotectedmemoryareawillbeignored.PriortoanyWriteoperation,theWrite- Enable(WREN)instructionmustbeexecuted.CE#mustremainactivelowforthedurationofanycom- mand sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol- lowed by address bits [A -A ]. Address bits [A -A ] (A =Most Significant address) are used to 23 0 MS 12 MS determinethesectoraddress(SA ),remainingaddressbitscanbeV orV CE#mustbedrivenhigh X IL IH. beforetheinstructionisexecuted.TheusermaypolltheBusybitinthesoftwarestatusregisterorwait T for the completion of the internal self-timed Sector-Erase cycle. See Figure 12 for the Sector- SE Erasesequence. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE0 20 ADD. ADD. ADD. SI MSB MSB SO HIGHIMPEDANCE 1271SecErase.0 Figure 12:Sector-Erase Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 15

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block- Eraseinstructionappliedtoaprotectedmemoryareawillbeignored.The64-KByteBlock-Eraseinstruc- tionclearsallbitsintheselected64KByteblocktoFFH.ABlock-Eraseinstructionappliedtoaprotectedmem- oryareawillbeignored.PriortoanyWriteoperation,theWrite-Enable(WREN)instructionmustbeexecuted. CE# must remain active low for the duration of any command sequence. The 32-Kbyte Block-Erase instructionisinitiatedbyexecutingan8-bitcommand,52H,followedbyaddressbits[A -A ].Address 23 0 bits[A -A ](A =MostSignificantAddress)areusedtodetermineblockaddress(BA ),remaining MS 15 MS X addressbitscanbeV orV CE#mustbedrivenhighbeforetheinstructionisexecuted.The64-KbyteBlock- IL IH. Eraseinstructionisinitiatedbyexecutingan8-bitcommandD8H,followedbyaddressbits[A -A ].Addressbits 23 0 [A -A ]areusedtodetermineblockaddress(BA ),remainingaddressbitscanbeV orV CE#mustbe MS 15 X IL IH. drivenhighbeforetheinstructionisexecuted.TheusermaypolltheBusybitinthesoftwarestatusregisteror wait T for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase BE cycles.SeeFigures13and14forthe32-KByteBlock-Eraseand64-KByteBlock-Erasesequences. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE0 52 ADDR ADDR ADDR SI MSB MSB SO HIGHIMPEDANCE 127132KBklEr.0 Figure 13:32-KByte Block-Erase Sequence CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE0 D8 ADDR ADDR ADDR SI MSB MSB SO HIGHIMPEDANCE 127163KBlkEr.0 Figure 14:64-KByte Block-Erase Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 16

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Chip-Erase TheChip-EraseinstructionclearsallbitsinthedevicetoFFH.AChip-Eraseinstructionwillbeignored if any of the memory area is protected. PriortoanyWriteoperation,theWrite-Enable(WREN)instruction mustbeexecuted.CE#mustremainactivelowforthedurationoftheChip-Eraseinstructionsequence. TheChip-Eraseinstructionisinitiatedbyexecutingan8-bitcommand,60HorC7H.CE#mustbedriven highbeforetheinstructionisexecuted.TheusermaypolltheBusybitinthesoftware status register or wait T for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase CE sequence. CE# MODE3 0 1 2 3 4 5 6 7 SCK MODE0 60orC7 SI MSB SO HIGHIMPEDANCE 1271ChEr.0 Figure 15:Chip-Erase Sequence Read-Status-Register (RDSR) TheRead-Status-Register(RDSR)instructionallowsreadingofthestatusregister.Thestatusregister maybereadatanytimeevenduringaWrite(Program/Erase)operation.WhenaWriteoperationisin progress, the Busy bit may be checked before sending any new commands to assure that the new commandsareproperlyreceivedbythedevice.CE#mustbedrivenlowbeforetheRDSRinstructionis enteredandremainlowuntilthestatusdataisread.Read-Status-Registeriscontinuouswithongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR instructionsequence. CE# MODE3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE0 05 SI MSB HIGHIMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SO MSB Status RegisterOut 1271RDSRseq.0 Figure 16:Read-Status-Register (RDSR) Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 17

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Write-Enable (WREN) TheWrite-Enable(WREN)instructionsetstheWrite-Enable-LatchbitintheStatusRegisterto1allow- ing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/ Erase)operation.TheWRENinstructionmayalsobeusedtoallowexecutionoftheWrite-Status-Reg- ister (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upontherisingedgeCE#oftheWRSRinstruction.CE#mustbedrivenhighbeforetheWRENinstruc- tionisexecuted. CE# MODE3 0 1 2 3 4 5 6 7 SCK MODE0 06 SI MSB SO HIGHIMPEDANCE 1271WREN.0 Figure 17:Write Enable (WREN) Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any newWriteoperationsfromoccurring.TheWRDIinstructionwillnotterminateanyprogrammingopera- tioninprogress.AnyprogramoperationinprogressmaycontinueuptoT afterexecutingtheWRDI BP instruction.CE#mustbedrivenhighbeforetheWRDIinstructionisexecuted. CE# MODE3 0 1 2 3 4 5 6 7 SCK MODE0 04 SI MSB SO HIGHIMPEDANCE 1271WRDI.0 Figure 18:Write Disable (WRDI) Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 18

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two- step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven highbeforetheEWSRinstructionisexecuted. Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of thestatusregister.CE#mustbedrivenlowbeforethecommandsequenceoftheWRSRinstructionis enteredanddrivenhighbeforetheWRSRinstructionisexecuted.SeeFigure19forEWSRorWREN andWRSRinstructionsequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”.When theWP# is low, the BPL bit can only be set from “0” to“1” to lock-down the status register, butcannotberesetfrom“1”to“0”.WhenWP#ishigh,thelock-downfunctionoftheBPLbitisdisabled andtheBPL,BP0,andBP1andBP2bitsinthestatusregistercanallbechanged.AslongasBPLbit issetto0orWP#pinisdrivenhigh(V )priortothelow-to-hightransitionoftheCE#pinattheendof IH theWRSRinstruction,thebitsinthestatusregistercanallbealteredbytheWRSRinstruction.Inthis case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as alteringtheBP0,BP1,andBP2bitsatthesametime.SeeTable2forasummarydescriptionofWP# andBPLfunctions. CE# MODE3 0 1 2 3 4 5 6 7 MODE3 0 1 2 3 4 5 6 7 8 9 101112131415 SCK MODE0 MODE0 STATUS REGISTERIN 50or06 01 7 6 5 4 3 2 1 0 SI MSB MSB MSB HIGHIMPEDANCE SO 1271EWSR.0 Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 19

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet JEDEC Read-ID TheJEDECRead-IDinstructionidentifiesthedeviceasSST25VF016BandthemanufacturerasSST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 41H, identifies the device as SST25VF016B. TheinstructionsequenceisshowninFigure20.TheJEDECReadIDinstructionisterminatedbyalow tohightransitiononCE#atanytimeduringdataoutput.Ifnoothercommandisissuedafterexecuting the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode (CE#=V ). IH CE# MODE3 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334 SCK MODE0 SI 9F HIGHIMPEDANCE BF 25 41 SO MSB MSB 1271JEDECID.1 Figure 20:JEDEC Read-ID Sequence Table 6: JEDEC Read-ID Data DeviceID Manufacturer’sID MemoryType MemoryCapacity Byte1 Byte2 Byte3 BFH 25H 41H T6.0 25044 ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 20

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF016B and manufacturer as SST. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A -A ]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H 23 0 and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufac- turer’s and device ID output data toggles between address 00000H and 00001H until terminated by a lowtohightransitiononCE#. RefertoTables6and7fordeviceidentificationdata. CE# MODE3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 4748 5556 63 SCK MODE0 90orAB 00 00 ADD1 SI MSB MSB HIGH HIGHIMPEDANCE IMPEDANCE SO BF DeviceID BF DeviceID MSB Note: ThemanufacturersanddeviceIDoutputstreamiscontinuousuntilterminatedbyalowtohightransitiononCE#. DeviceID=41HforSST25VF016B 1. 00HwilloutputthemanfacturersIDfirstand01HwilloutputdeviceIDfirstbeforetogglingbetweenthetwo. 1271RdID.0 Figure 21:Read-ID Sequence Table 7: Product Identification Address Data Manufacturer’sID 00000H BFH DeviceID SST25VF016B 00001H 41H T7.0 25044 ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 21

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Electrical Specifications AbsoluteMaximumStressRatings (Applied conditions greater than those listed under “Absolute MaximumStressRatings”maycausepermanentdamagetothedevice.Thisisastressratingonlyand functional operation of the device at these conditions or conditions greater than those defined in the operationalsectionsofthisdatasheetisnotimplied.Exposuretoabsolutemaximumstressratingcon- ditionsmayaffectdevicereliability.) TemperatureUnderBias.............................................. -55°Cto+125°C StorageTemperature................................................. -65°Cto+150°C D.C.VoltageonAnyPintoGroundPotential.............................-0.5VtoV +0.5V DD TransientVoltage(<20ns)onAnyPintoGroundPotential ..................-2.0VtoV +2.0V DD PackagePowerDissipationCapability(T =25°C)................................... 1.0W A SurfaceMountSolderReflowTemperature ........................... 260°Cfor10seconds OutputShortCircuitCurrent1................................................... 50mA 1. Outputshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime. Table 8: Operating Range Range AmbientTemp V DD Commercial 0°Cto+70°C 2.7-3.6V Industrial -40°Cto+85°C 2.7-3.6V Table 9: AC Conditions of Test1 InputRise/FallTime OutputLoad 5ns C =30pF L T9.125044 1. SeeFigures26and27 ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 22

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Table 10:DC Operating Characteristics Limits Symbol Parameter Min Max Units TestConditions I ReadCurrent 10 mA CE#=0.1V /0.9V @25MHz,SO=open DDR DD DD I ReadCurrent 15 mA CE#=0.1V /0.9V @50MHz,SO=open DDR2 DD DD I ReadCurrent 20 mA CE#=0.1V /0.9V @80MHz,SO=open DDR3 DD DD I ProgramandEraseCurrent 30 mA CE#=V DDW DD I StandbyCurrent 20 µA CE#=V ,V =V orV SB DD IN DD SS I InputLeakageCurrent 1 µA V =GNDtoV ,V =V Max LI IN DD DD DD I OutputLeakageCurrent 1 µA V =GNDtoV ,V =V Max LO OUT DD DD DD V InputLowVoltage 0.8 V V =V Min IL DD DD V InputHighVoltage 0.7V V V =V Max IH DD DD DD V OutputLowVoltage 0.2 V I =100µA,V =V Min OL OL DD DD V OutputLowVoltage 0.4 V I =1.6mA,V =V Min OL2 OL DD DD V OutputHighVoltage V -0.2 V I =-100µA,V =V Min OH DD OH DD DD T10.025044 Table 11:Capacitance (TA=25°C,f=1Mhz,otherpinsopen) Parameter Description TestCondition Maximum C 1 OutputPinCapacitance V =0V 12pF OUT OUT C 1 InputCapacitance V =0V 6pF IN IN T11.025044 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthis parameter. Table 12:Reliability Characteristics Symbol Parameter MinimumSpecification Units TestMethod N 1 Endurance 10,000 Cycles JEDECStandardA117 END T 1 DataRetention 100 Years JEDECStandardA103 DR I 1 LatchUp 100+I mA JEDECStandard78 LTH DD T12.025044 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthis parameter. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 23

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Table 13:AC Operating Characteristics 25MHz 50MHz 80MHz Symbol Parameter Min Max Min Max Min Max Units F 1 SerialClockFrequency 25 50 80 MHz CLK T SerialClockHighTime 18 9 6 ns SCKH T SerialClockLowTime 18 9 6 ns SCKL T 2 SerialClockRiseTime(SlewRate) 0.1 0.1 0.1 V/ns SCKR T SerialClockFallTime(SlewRate) 0.1 0.1 0.1 V/ns SCKF T 3 CE#ActiveSetupTime 10 5 5 ns CES T 3 CE#ActiveHoldTime 10 5 5 ns CEH T 3 CE#NotActiveSetupTime 10 5 5 ns CHS T 3 CE#NotActiveHoldTime 10 5 5 ns CHH T CE#HighTime 100 50 50 ns CPH T CE#HightoHigh-ZOutput 15 8 7 ns CHZ T SCKLowtoLow-ZOutput 0 0 0 ns CLZ T DataInSetupTime 5 2 2 ns DS T DataInHoldTime 5 5 4 ns DH T HOLD#LowSetupTime 10 5 5 ns HLS T HOLD#HighSetupTime 10 5 5 ns HHS T HOLD#LowHoldTime 10 5 5 ns HLH T HOLD#HighHoldTime 10 5 5 ns HHH T HOLD#LowtoHigh-ZOutput 20 8 7 ns HZ T HOLD#HightoLow-ZOutput 15 8 7 ns LZ T OutputHoldfromSCKChange 0 0 0 ns OH T OutputValidfromSCK 15 8 6 ns V T Sector-Erase 25 25 25 ms SE T Block-Erase 25 25 25 ms BE T Chip-Erase 50 50 50 ms SCE T Byte-Program 10 10 10 µs BP T13.025044 1. MaximumclockfrequencyforReadInstruction,03H,is25MHz 2. MaximumRiseandFalltimemaybelimitedbyTSCKHandTSCKLrequirements 3. RelativetoSCK. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 24

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet TCPH CE# TCHH TCES TSCKF TCEH TCHS SCK TDS TDH TSCKR MSB LSB SI SO HIGH-Z HIGH-Z 1271SerIn.0 Figure 22:Serial Input Timing Diagram CE# TSCKH TSCKL SCK TOH TCLZ TCHZ SO MSB LSB TV SI 1271SerOut.0 Figure 23:Serial Output Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 25

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet CE# THHH THLS THHS SCK THLH THZ TLZ SO SI HOLD# 1271Hold.0 Figure 24:Hold Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 26

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Power-Up Specifications All functionalities and DC specifications are specified for a V ramp rate of greater than 1V per 100 DD ms(0v-3.0Vinlessthan300ms).SeeTable14andFigure25formoreinformation. Table 14:Recommended System Power-up Timings Symbol Parameter Minimum Units T 1 V MintoReadOperation 100 µs PU-READ DD T 1 V MintoWriteOperation 100 µs PU-WRITE DD T14.025044 1. Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthis parameter. VDD VDDMax Chipselectionisnotallowed. Commandsmaynotbeacceptedorproperly interpretedbythedevice. VDDMin TPU-READ Devicefully accessible TPU-WRITE Time 1271PwrUp.0 Figure 25:Power-up Timing Diagram ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 27

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet VIHT VHT VHT INPUT REFERENCEPOINTS OUTPUT VLT VLT VILT 1271IORef.0 ACtestinputsaredrivenatV (0.9V )foralogic“1”andV (0.1V )foralogic“0”.Mea- IHT DD ILT DD surementreferencepointsforinputsandoutputsareV (0.6V )andV (0.4V ).Inputrise HT DD LT DD andfalltimes(10%90%)are<5ns. Note: VHT-VHIGHTest VLT-VLOWTest VIHT-VINPUTHIGHTest VILT-VINPUTLOWTest Figure 26:AC Input/Output Reference Waveforms TOTESTER TODUT CL 1271TstLd.0 Figure 27:A Test Load Example ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 28

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Product Ordering Information SST 25 VF 016B - 50 - 4C - S2AF XX XX XXXX - XX - XX - XXXX EnvironmentalAttribute F1=non-Pb/non-Sncontact(lead)finish: NickelplatingwithGoldtop(outer)layer PackageModifier A=8leadsorcontacts PackageType S2=SOIC200milbodywidth Q=WSON TemperatureRange C=Commercial=0°Cto+70°C I=Industrial=-40°Cto+85°C MinimumEndurance 4=10,000cycles OperatingFrequency 50=50MHz 75=75MHz(80MHz) DeviceDensity 016=16Mbit Voltage V=2.7-3.6V ProductSeries 25=SerialPeripheralInterfaceflash memory 1. Environmentalsuffix“F”denotesnon-Pb/non-SN solder. SSTnon-Pb/non-Snsolderdevicesare“RoHS Compliant”. Valid combinations for SST25VF016B SST25VF016B-50-4C-S2AF SST25VF016B-50-4C-QAF SST25VF016B-50-4I-S2AF SST25VF016B-50-4I-QAF SST25VF016B-75-4I-S2AF SST25VF016B-75-4I-QAF Note:Validcombinationsarethoseproductsinmassproductionorwillbeinmassproduction.ConsultyourSST salesrepresentativetoconfirmavailabilityofvalidcombinationsandtodetermineavailabilityofnewcombi- nations. ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 29

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Packaging Diagrams Pin#1 TOPVIEW SIDEVIEW Identifier 0.50 0.35 5.40 5.15 1.27BSC 0.25 ENDVIEW 0.05 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0° 0.19 8° Note: 1.Alllineardimensionsareinmillimeters(max/min). 0.80 2.Coplanarity:0.1mm 08-soic-EIAJ-S2A-3 0.50 3.Maximumallowablemoldflashis0.15mmatthepackageendsand0.25mmbetweenleads. 1mm Figure28:8-leadSmallOutlineIntegratedCircuit(SOIC)200milbodywidth(5.2mmx8mm) SSTPackageCode:S2A ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 30

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet TOPVIEW SIDEVIEW BOTTOMVIEW Pin#1 0.2 Pin#1 Corner 1.27BSC 5.00 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.05Max 0.50 6.00 0.10 0.80 0.70 CROSSSECTION Note: 1.Alllineardimensionsareinmillimeters(max/min). 2.Untoleranceddimensions(shownwithboxsurround) arenominaltargetdimensions. 0.80 3.Theexternalpaddleiselectricallyconnectedtothe 0.70 dieback-sideandpossiblytocertainVSSleads. 1mm ThispaddlecanbesolderedtothePCboard; itissuggestedtoconnectthispaddletotheVSSoftheunit. 8-wson-5x6-QA-9.0 Connectionofthispaddletoanyothervoltagepotentialcan resultinshortsand/orelectricalmalfunctionofthedevice. Figure 29:8-contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: QA ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 31

16 Mbit SPI Serial Flash SST25VF016B A Microchip Technology Company DataSheet Table 15:Revision History Revision Description Date 00 (cid:129) Initialreleaseofdatasheet Apr2005 01 (cid:129) Corrected“JEDECRead-ID”onpage20includingtimingdiagram Sep2005 (cid:129) CorrectedV andV valuesinFigure26onpage28 HT LT 02 (cid:129) MigrateddocumenttoaDataSheet Jan2006 (cid:129) UpdatedSurfaceMountSolderReflowTemperatureinformation 03 (cid:129) EditedClockFrequencyspeedfrom50MHzto80MHzinFeatures,page Sep2008 1 (cid:129) RevisedTable5for80MHz (cid:129) EditedHighSpeedReadfor80MHz,page10 (cid:129) EditedTable8,page21 (cid:129) Added80MHzcolumnstoTable12,page22 (cid:129) UpdatedProductOrderingInformationandValidCombination,page26 04 (cid:129) Updated“AutoAddressIncrement(AAI)Word-Program”,“End-of-Write Jan2011 Detection”,and“HardwareEnd-of-WriteDetection”onpage12. (cid:129) RevisedFigures10and11onpagepage14. (cid:129) Updateddocumenttonewformat. A (cid:129) Added“Power-UpSpecifications”onpage27 Aug2011 (cid:129) UpdatedTable14onpage27 (cid:129) Releaseddocumentunderletterrevisionsystem (cid:129) UpdatedSpecnumberfromS71271toDS25044 ISBN:978-1-61341-524-5 ©2011SiliconStorageTechnology,Inc–aMicrochipTechnologyCompany.Allrightsreserved. SST,SiliconStorageTechnology,theSSTlogo,SuperFlash,MTP,andFlashFlexareregisteredtrademarksofSiliconStorageTech- nology,Inc.MPF,SQI,SerialQuadI/O,andZ-ScalearetrademarksofSiliconStorageTechnology,Inc.Allothertrademarksand registeredtrademarksmentionedhereinarethepropertyoftheirrespectiveowners. Specificationsaresubjecttochangewithoutnotice.Refertowww.microchip.comforthemostrecentdocumentation.Forthemostcurrent packagedrawings,pleaseseethePackagingSpecificationlocatedathttp://www.microchip.com/packaging. Memorysizesdenoterawstoragecapacity;actualusablecapacitymaybeless. SSTmakesnowarrantyfortheuseofitsproductsotherthanthoseexpresslycontainedintheStandardTermsandConditionsof Sale. Forsalesofficelocationsandinformation,pleaseseewww.microchip.com. SiliconStorageTechnology,Inc. AMicrochipTechnologyCompany www.microchip.com ©2011SiliconStorageTechnology,Inc. DS25044A 08/11 32