16 Mbit SPI Serial Flash SST25VF016B SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory Data Sheet FEATURES: • Single Voltage Read and Write Operations (cid:129) Auto Address Increment (AAI) Programming – 2.7-3.6V – Decrease total chip programming time over Byte-Program operations (cid:129) Serial Interface Architecture (cid:129) End-of-Write Detection – SPI Compatible: Mode 0 and Mode 3 – Software polling the BUSY bit in Status Register (cid:129) High Speed Clock Frequency – Busy Status readout on SO pin in AAI Mode – Up to 80 MHz (cid:129) Hold Pin (HOLD#) (cid:129) Superior Reliability – Suspends a serial sequence to the memory – Endurance: 100,000 Cycles (typical) without deselecting the device – Greater than 100 years Data Retention (cid:129) Write Protection (WP#) (cid:129) Low Power Consumption: – Enables/Disables the Lock-Down function of the – Active Read Current: 10 mA (typical) status register – Standby Current: 5 µA (typical) (cid:129) Software Write Protection (cid:129) Flexible Erase Capability – Write protection through Block-Protection bits in – Uniform 4 KByte sectors status register – Uniform 32 KByte overlay blocks (cid:129) Temperature Range – Uniform 64 KByte overlay blocks – Commercial: 0°C to +70°C (cid:129) Fast Erase and Byte-Program: – Industrial: -40°C to +85°C – Chip-Erase Time: 35 ms (typical) (cid:129) Packages Available – Sector-/Block-Erase Time: 18 ms (typical) – Byte-Program Time: 7 µs (typical) – 8-lead SOIC (200 mils) – 8-contact WSON (6mm x 5mm) (cid:129) All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION SST’s 25 series Serial Flash family features a four-wire, The SST25VF016B devices significantly improve perfor- SPI-compatible interface that allows for a low pin-count mance and reliability, while lowering power consumption. package which occupies less board space and ultimately The devices write (Program or Erase) with a single power lowers total system costs. The SST25VF016B devices are supply of 2.7-3.6V for SST25VF016B. The total energy enhanced with improved operating frequency and even consumed is a function of the applied voltage, current, and lower power consumption than the original SST25VFxxxA time of application. Since for any given voltage range, the devices. SST25VF016B SPI serial flash memories are SuperFlash technology uses less current to program and manufactured with SST’s proprietary, high-performance has a shorter erase time, the total energy consumed during CMOS SuperFlash technology. The split-gate cell design any Erase or Program operation is less than alternative and thick-oxide tunneling injector attain better reliability and flash memory technologies. manufacturability compared with alternate approaches. The SST25VF016B device is offered in both 8-lead SOIC (200 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 2 for pin assignments. ©2008 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. S71271-03-000 9/08 These specifications are subject to change without notice. 1

16 Mbit SPI Serial Flash SST25VF016B Data Sheet SuperFlash X - Decoder Address Memory Buffers and Latches Y - Decoder I/O Buffers Control Logic and Data Latches Serial Interface CE# SCK SI SO WP# HOLD# 1271 B1.0 FIGURE 1: Functional block Diagram ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 2

16 Mbit SPI Serial Flash SST25VF016B Data Sheet PIN DESCRIPTION CE# 1 8 VDD CE# 1 8 VDD SO 2 7 HOLD# SO 2 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 1271 08-wson QA P2.0 1271 08-soic S2A P1.0 8-lead SOIC 8-Contact WSON FIGURE 2: Pin Assignments TABLE 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin. See “Hardware End-of-Write Detection” on page12 for details. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF016B DD V Ground SS T1.0 1271 ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 3

16 Mbit SPI Serial Flash SST25VF016B Data Sheet MEMORY ORGANIZATION The SST25VF016B SuperFlash memory array is orga- The SST25VF016B supports both Mode 0 (0,0) and Mode nized in uniform 4 KByte erasable sectors with 32 KByte 3 (1,1) of SPI bus operations. The difference between the overlay blocks and 64 KByte overlay erasable blocks. two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no DEVICE OPERATION data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the The SST25VF016B is accessed through the SPI (Serial Serial Data In (SI) is sampled at the rising edge of the SCK Peripheral Interface) bus compatible protocol. The SPI bus clock signal and the Serial Data Output (SO) is driven after consist of four control lines; Chip Enable (CE#) is used to the falling edge of the SCK clock signal. select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). CE# MODE 3 MODE 3 SCK MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB 1271 SPIprot.0 FIGURE 3: SPI Protocol ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 4

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Hold Operation The HOLD# pin is used to pause a serial sequence under- coincide with the SCK active low state, then the device way with the SPI flash memory without resetting the clock- exits in Hold mode when the SCK next reaches the active ing sequence. To activate the HOLD# mode, CE# must be low state. See Figure 4 for Hold Condition waveform. in active low state. The HOLD# mode begins when the Once the device enters Hold mode, SO will be in high- SCK active low state coincides with the falling edge of the impedance state while SI and SCK can be V or V HOLD# signal. The HOLD mode ends when the HOLD# IL IH. signal’s rising edge coincides with the SCK active low state. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is If the falling edge of the HOLD# signal does not coincide low, the memory remains in the Hold condition. To resume with the SCK active low state, then the device enters Hold communication with the device, HOLD# must be driven mode when the SCK next reaches the active low state. active high, and CE# must be driven active low. See Figure Similarly, if the rising edge of the HOLD# signal does not 24 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1271 HoldCond.0 FIGURE 4: Hold Condition Waveform Write Protection TABLE 2: Conditions to execute Write-Status- Register (WRSR) Instruction SST25VF016B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down WP# BPL Execute WRSR Instruction function of the status register. The Block-Protection bits L 1 Not Allowed (BP3, BP2, BP1, BP0, and BPL) in the status register pro- L 0 Allowed vide Write protection to the memory array and the status H X Allowed register. See Table 4 for the Block-Protection description. T2.0 1271 Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down func- tion of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 2). When WP# is high, the lock-down func- tion of the BPL bit is disabled. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 5

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Status Register The software status register provides status on whether the Program operation, the status register may be read only to flash memory array is available for any Read or Write oper- determine the completion of an operation in progress. ation, whether the device is Write enabled, and the state of Table 3 describes the function of each bit in the software the Memory Write protection. During an internal Erase or status register. TABLE 3: Software Status Register Default at Bit Name Function Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 R 0 = No internal Write operation is in progress 1 WEL 1 = Device is memory Write enabled 0 R 0 = Device is not memory Write enabled 2 BP0 Indicate current level of block write protection (See Table 4) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 4) 1 R/W 4 BP2 Indicate current level of block write protection (See Table 4) 1 R/W 5 BP3 Indicate current level of block write protection (See Table 4) 0 R/W 6 AAI Auto Address Increment Programming status 0 R 1 = AAI programming mode 0 = Byte-Program mode 7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 R/W 0 = BP3, BP2, BP1, BP0 are read/writable T3.0 1271 Busy Auto Address Increment (AAI) The Busy bit determines whether there is an internal Erase The Auto Address Increment Programming-Status bit pro- or Program operation in progress. A “1” for the Busy bit indi- vides status on whether the device is in AAI programming cates the device is busy with an operation in progress. A “0” mode or Byte-Program mode. The default at power up is indicates the device is ready for the next valid operation. Byte-Program mode. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the inter- nal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automati- cally reset under the following conditions: (cid:129) Power-up (cid:129) Write-Disable (WRDI) instruction completion (cid:129) Byte-Program instruction completion (cid:129) Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address (cid:129) Sector-Erase instruction completion (cid:129) Block-Erase instruction completion (cid:129) Chip-Erase instruction completion (cid:129) Write-Status-Register instructions ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 6

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Block Protection (BP3,BP2, BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP3, BP2, BP1, BP0) bits define the WP# pin driven low (V ), enables the Block-Protection- IL size of the memory area, as defined in Table 4, to be soft- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any ware protected against any memory Write (Program or further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. Erase) operation. The Write-Status-Register (WRSR) When the WP# pin is driven high (V ), the BPL bit has no IH instruction is used to program the BP3, BP2, BP1 and BP0 effect and its value is “Don’t Care”. After power-up, the BPL bits as long as WP# is high or the Block-Protect-Lock bit is reset to 0. (BPL) bit is 0. Chip-Erase can only be executed if Block- Protection bits are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to 1. TABLE 4: Software Status Register Block Protection FOR SST25VF016B1 Status Register Bit2 Protected Memory Address Protection Level BP3 BP2 BP1 BP0 16 Mbit None X 0 0 0 None Upper 1/32 X 0 0 1 1F0000H-1FFFFFH Upper 1/16 X 0 1 0 1E0000H-1FFFFFH Upper 1/8 X 0 1 1 1C0000H-1FFFFFH Upper 1/4 X 1 0 0 180000H-1FFFFFH Upper 1/2 X 1 0 1 100000H-1FFFFFH All Blocks X 1 1 0 000000H-1FFFFFH All Blocks X 1 1 1 000000H-1FFFFFH T4.0 1271 1. X = Don’t Care (RESERVED) default is “0 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected) ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 7

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Instructions Instructions are used to read, write (Erase and Program), of SCK starting with the most significant bit. CE# must be and configure the SST25VF016B. The instruction bus driven low before an instruction is entered and must be cycles are 8 bits each for commands (Op Code), data, and driven high after the last bit of the instruction has been addresses. Prior to executing any Byte-Program, Auto shifted in (except for Read, Read-ID, and Read-Status- Address Increment (AAI) programming, Sector-Erase, Register instructions). Any low to high transition on CE#, Block-Erase, Write-Status-Register, or Chip-Erase instruc- before receiving the last bit of an instruction bus cycle, will tions, the Write-Enable (WREN) instruction must be exe- terminate the instruction in progress and return the device cuted first. The complete list of instructions is provided in to standby mode. Instruction commands (Op Code), Table 5. All instructions are synchronized off a high to low addresses, and data are all input from the most significant transition of CE#. Inputs will be accepted on the rising edge bit (MSB) first. TABLE 5: Device Operation Instructions Address Dummy Data Maximum Instruction Description Op Code Cycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency Read Read Memory at 25 MHz 0000 0011b (03H) 3 0 1 to ∞ 25 MHz High-Speed Read Read Memory at 80 MHz 0000 1011b (0BH) 3 1 1 to ∞ 80 MHz 4 KByte Sector-Erase3 Erase 4 KByte of 0010 0000b (20H) 3 0 0 80 MHz memory array 32 KByte Block-Erase4 Erase 32 KByte block 0101 0010b (52H) 3 0 0 80 MHz of memory array 64 KByte Block-Erase5 Erase 64 KByte block 1101 1000b (D8H) 3 0 0 80 MHz of memory array Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 0 0 0 80 MHz 1100 0111b (C7H) Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 80 MHz AAI-Word-Program6 Auto Address Increment 1010 1101b (ADH) 3 0 2 to ∞ 80 MHz Programming RDSR7 Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ 80 MHz EWSR Enable-Write-Status-Register 0101b 0000b (50H) 0 0 0 80 MHz WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 80 MHz WREN Write-Enable 0000 0110b (06H) 0 0 0 80 MHz WRDI Write-Disable 0000 0100b (04H) 0 0 0 80 MHz RDID8 Read-ID 1001 0000b (90H) or 3 0 1 to ∞ 80 MHz 1010 1011b (ABH) JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to ∞ 80 MHz EBSY Enable SO to output RY/BY# 0111 0000b (70H) 0 0 0 80 MHz status during AAI programming DBSY Disable SO to output RY/BY# 1000 0000b (80H) 0 0 0 80 MHz status during AAI programming T5.0 1271 1. One bus cycle is eight clock periods. 2. Address bits above the most significant bit of each density can be VIL or VIH. 3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. 4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. 5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. 6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0=1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 8

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Read (25 MHz) The Read instruction, 03H, supports up to 25 MHz Read. beginning (wrap-around) of the address space. Once the The device outputs the data starting from the specified data from address location 1FFFFFH has been read, the address location. The data output stream is continuous next output will be from address location 000000H. through all addresses until terminated by a low to high tran- The Read instruction is initiated by executing an 8-bit com- sition on CE#. The internal address pointer will automati- mand, 03H, followed by address bits [A -A ]. CE# must cally increment until the highest memory address is 23 0 remain active low for the duration of the Read cycle. See reached. Once the highest memory address is reached, Figure 5 for the Read sequence. the address pointer will automatically increment to the CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 47 48 5556 6364 70 SCK MODE 0 03 ADD. ADD. ADD. SI MSB MSB N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1271 ReadSeq.0 FIGURE 5: Read Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 9

16 Mbit SPI Serial Flash SST25VF016B Data Sheet High-Speed-Read (80 MHz) The High-Speed-Read instruction supporting up to 80 MHz addresses until terminated by a low to high transition on Read is initiated by executing an 8-bit command, 0BH, fol- CE#. The internal address pointer will automatically incre- lowed by address bits [A -A ] and a dummy byte. CE# ment until the highest memory address is reached. Once 23 0 must remain active low for the duration of the High-Speed- the highest memory address is reached, the address Read cycle. See Figure 6 for the High-Speed-Read pointer will automatically increment to the beginning (wrap- sequence. around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be Following a dummy cycle, the High-Speed-Read instruc- from address location 000000H. tion outputs the data starting from the specified address location. The data output stream is continuous through all CE# MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 3940 47 48 55 56 63 64 71 72 80 SCK MODE 0 SI 0B ADD. ADD. ADD. X MSB MSB N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1271 HSRdSeq.0 Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) FIGURE 6: High-Speed-Read Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 10

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Byte-Program The Byte-Program instruction programs the bits in the Program instruction is initiated by executing an 8-bit com- selected byte to the desired data. The selected byte must mand, 02H, followed by address bits [A -A ]. Following the 23 0 be in the erased state (FFH) when initiating a Program address, the data is input in order from MSB (bit 7) to LSB operation. A Byte-Program instruction applied to a pro- (bit 0). CE# must be driven high before the instruction is tected memory area will be ignored. executed. The user may poll the Busy bit in the software status register or wait T for the completion of the internal Prior to any Write operation, the Write-Enable (WREN) BP self-timed Byte-Program operation. See Figure 7 for the instruction must be executed. CE# must remain active low Byte-Program sequence. for the duration of the Byte-Program instruction. The Byte- CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 SCK MODE 0 SI 02 ADD. ADD. ADD. DIN MSB MSB MSB LSB SO HIGH IMPEDANCE 1271 ByteProg.0 FIGURE 7: Byte-Program Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 11

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Auto Address Increment (AAI) Word-Program Hardware End-of-Write Detection The AAI program instruction allows multiple bytes of data to The hardware end-of-write detection method eliminates the be programmed without re-issuing the next sequential overhead of polling the Busy bit in the Software Status address location. This feature decreases total program- Register during an AAI Word program operation. The 8-bit ming time when multiple bytes or entire memory array is to command, 70H, configures the Serial Output (SO) pin to be programmed. An AAI Word program instruction pointing indicate Flash Busy status during AAI Word programming. to a protected memory area will be ignored. The selected (see Figure 8) The 8-bit command, 70H, must be executed address range must be in the erased state (FFH) when ini- prior to executing an AAI Word-Program instruction. Once tiating an AAI Word Program operation. While within AAI an internal programming operation begins, asserting CE# Word Programming sequence, the only valid instructions will immediately drive the status of the internal flash status are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users on the SO pin. A “0” indicates the device is busy and a “1” have three options to determine the completion of each indicates the device is ready for the next instruction. De- AAI Word program cycle: hardware detection by reading asserting CE# will return the SO pin to tri-state. the Serial Output, software detection by polling the BUSY The 8-bit command, 80H, disables the Serial Output (SO) bit in the software status register or wait T Refer to End- BP. pin to output busy status during AAI-Word-program opera- Of-Write Detection section for details. tion and return SO pin to output Software Status Register Prior to any write operation, the Write-Enable (WREN) data during AAI Word programming. (see Figure 9) instruction must be executed. The AAI Word Program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A -A ]. Following the 23 0 CE# addresses, two bytes of data is input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) MODE 3 0 1 2 3 4 5 6 7 will be programmed into the initial address [A -A ] with 23 1 SCK MODE 0 A =0, the second byte of Data (D1) will be programmed 0 into the initial address [A -A ] with A =1. CE# must be 23 1 0 driven high before the AAI Word Program instruction is exe- 70 SI cuted. The user must check the BUSY status before enter- MSB ing the next valid command. Once the device indicates it is SO HIGH IMPEDANCE no longer busy, data for the next two sequential addresses 1271 EnableSO.0 may be programmed and so on. When the last desired FIGURE 8: Enable SO as Hardware RY/BY# byte had been entered, check the busy status using the during AAI Programming hardware method or the RDSR instruction and execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. See Figures 10 and 11 CE# for AAI Word programming sequence. MODE 3 0 1 2 3 4 5 6 7 There is no wrap mode during AAI programming; once the SCK MODE 0 highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable- Latch bit (WEL=0) and the AAI bit (AAI=0). 80 SI MSB End-of-Write Detection SO HIGH IMPEDANCE There are three methods to determine completion of a pro- 1271 DisableSO.0 gram cycle during AAI Word programming: hardware FIGURE 9: Disable SO as Hardware RY/BY# detection by reading the Serial Output, software detection during AAI Programming by polling the BUSY bit in the Software Status Register or wait T The hardware end-of-write detection method is BP. described in the section below. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 12

16 Mbit SPI Serial Flash SST25VF016B Data Sheet CE# MODE 3 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 0 7 8 1516 23 0 7 0 7 8 15 SCK MODE 0 SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR Load AAI command, Address, 2 bytes data Last 2 WDRI to exit Data Bytes AAI Mode SO DOUT Wait TBP or poll Check for Flash Busy Status to load next valid1 command Software Status register to load any command Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming 1271 AAI.HW.0 FIGURE10: Auto Address Increment (AAI) Word-Program Sequence with Hardware End-of-Write Detection Wait TBP or poll Software Status register to load next valid1 command CE# MODE 3 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 0 7 8 1516 23 0 7 0 7 8 15 SCK MODE 0 SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR Load AAI command, Address, 2 bytes data Last 2 WDRI to exit Data Bytes AAI Mode SO DOUT Note: 1. Valid commands during AAI programming: AAI command or WRDI command Wait TBP or poll Software Status register to load any command 1271 AAI.SW.0 FIGURE11: Auto Address Increment (AAI) Word-Program Sequence with Software End-of-Write Detection ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 13

16 Mbit SPI Serial Flash SST25VF016B Data Sheet 4-KByte Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 Significant address) are used to determine the sector KByte sector to FFH. A Sector-Erase instruction applied to address (SA ), remaining address bits can be V or V X IL IH. a protected memory area will be ignored. Prior to any Write CE# must be driven high before the instruction is executed. operation, the Write-Enable (WREN) instruction must be The user may poll the Busy bit in the software status regis- executed. CE# must remain active low for the duration of ter or wait T for the completion of the internal self-timed SE any command sequence. The Sector-Erase instruction is Sector-Erase cycle. See Figure 12 for the Sector-Erase initiated by executing an 8-bit command, 20H, followed by sequence. address bits [A -A ]. Address bits [A -A ] (A =Most 23 0 MS 12 MS CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 20 ADD. ADD. ADD. SI MSB MSB SO HIGH IMPEDANCE 1271 SecErase.0 FIGURE12: Sector-Erase Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 14

16 Mbit SPI Serial Flash SST25VF016B Data Sheet 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the determine block address (BA ), remaining address bits can X selected 32 KByte block to FFH. A Block-Erase instruction be V or V CE# must be driven high before the instruction IL IH. applied to a protected memory area will be ignored. The is executed. The 64-Kbyte Block-Erase instruction is initi- 64-KByte Block-Erase instruction clears all bits in the ated by executing an 8-bit command D8H, followed by selected 64 KByte block to FFH. A Block-Erase instruction address bits [A -A ]. Address bits [A -A ] are used to 23 0 MS 15 applied to a protected memory area will be ignored. Prior to determine block address (BA ), remaining address bits can X any Write operation, the Write-Enable (WREN) instruction be V or V CE# must be driven high before the instruction IL IH. must be executed. CE# must remain active low for the is executed. The user may poll the Busy bit in the software duration of any command sequence. The 32-Kbyte Block- status register or wait T for the completion of the internal BE Erase instruction is initiated by executing an 8-bit com- self-timed 32-KByte Block-Erase or 64-KByte Block-Erase mand, 52H, followed by address bits [A -A ]. Address bits cycles. See Figures 13 and 14 for the 32-KByte Block- 23 0 [A -A ] (A =Most Significant Address) are used to Erase and 64-KByte Block-Erase sequences. MS 15 MS CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 52 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1271 32KBklEr.0 FIGURE13: 32-KByte Block-Erase Sequence CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 D8 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1271 63KBlkEr.0 FIGURE14: 64-KByte Block-Erase Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 15

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to by executing an 8-bit command, 60H or C7H. CE# must be FFH. A Chip-Erase instruction will be ignored if any of the driven high before the instruction is executed. The user may memory area is protected. Prior to any Write operation, the poll the Busy bit in the software status register or wait T CE Write-Enable (WREN) instruction must be executed. CE# for the completion of the internal self-timed Chip-Erase must remain active low for the duration of the Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence. instruction sequence. The Chip-Erase instruction is initiated CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 60 or C7 SI MSB SO HIGH IMPEDANCE 1271 ChEr.0 FIGURE15: Chip-Erase Sequence Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows read- CE# must be driven low before the RDSR instruction is ing of the status register. The status register may be read at entered and remain low until the status data is read. Read- any time even during a Write (Program/Erase) operation. Status-Register is continuous with ongoing clock cycles When a Write operation is in progress, the Busy bit may be until it is terminated by a low to high transition of the CE#. checked before sending any new commands to assure that See Figure 16 for the RDSR instruction sequence. the new commands are properly received by the device. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE 0 05 SI MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB Status Register Out 1271 RDSRseq.0 FIGURE16: Read-Status-Register (RDSR) Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 16

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- the Write-Status-Register (WRSR) instruction; however, Enable-Latch bit in the Status Register to 1 allowing Write the Write-Enable-Latch bit in the Status Register will be operations to occur. The WREN instruction must be exe- cleared upon the rising edge CE# of the WRSR instruction. cuted prior to any Write (Program/Erase) operation. The CE# must be driven high before the WREN instruction is WREN instruction may also be used to allow execution of executed. CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 06 SI MSB SO HIGH IMPEDANCE 1271 WREN.0 FIGURE17: Write Enable (WREN) Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write- gram operation in progress may continue up to T after BP Enable-Latch bit and AAI bit to 0 disabling any new Write executing the WRDI instruction. CE# must be driven high operations from occurring. The WRDI instruction will not before the WRDI instruction is executed. terminate any programming operation in progress. Any pro- CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 04 SI MSB SO HIGH IMPEDANCE 1271 WRDI.0 FIGURE18: Write Disable (WRDI) Sequence Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction any accidental alteration of the status register values. CE# arms the Write-Status-Register (WRSR) instruction and must be driven low before the EWSR instruction is entered opens the status register for alteration. The Write-Status- and must be driven high before the EWSR instruction is Register instruction must be executed immediately after the executed. execution of the Enable-Write-Status-Register instruction. This two-step instruction sequence of the EWSR instruc- tion followed by the WRSR instruction works like SDP (soft- ware data protection) command structure which prevents ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 17

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to BPL bit is disabled and the BPL, BP0, and BP1 and BP2 the BP3, BP2, BP1, BP0, and BPL bits of the status regis- bits in the status register can all be changed. As long as ter. CE# must be driven low before the command BPL bit is set to 0 or WP# pin is driven high (V ) prior to the IH sequence of the WRSR instruction is entered and driven low-to-high transition of the CE# pin at the end of the high before the WRSR instruction is executed. See Figure WRSR instruction, the bits in the status register can all be 19 for EWSR or WREN and WRSR instruction sequences. altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down Executing the Write-Status-Register instruction will be the status register as well as altering the BP0, BP1, and ignored when WP# is low and BPL bit is set to “1”. When BP2 bits at the same time. See Table 2 for a summary the WP# is low, the BPL bit can only be set from “0” to “1” to description of WP# and BPL functions. lock-down the status register, but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the CE# MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 101112131415 SCK MODE 0 MODE 0 STATUS REGISTER IN 50 or 06 01 7 6 5 4 3 2 1 0 SI MSB MSB MSB HIGH IMPEDANCE SO 1271 EWSR.0 FIGURE19: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 18

16 Mbit SPI Serial Flash SST25VF016B Data Sheet JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as sequence is shown in Figure 20. The JEDEC Read ID SST25VF016B and the manufacturer as SST. The device instruction is terminated by a low to high transition on CE# information can be read from executing the 8-bit command, at any time during data output. If no other command is 9FH. Following the JEDEC Read-ID instruction, the 8-bit issued after executing the JEDEC Read-ID instruction, manufacturer’s ID, BFH, is output from the device. After issue a 00H (NOP) command before going into Standby that, a 16-bit device ID is shifted out on the SO pin. Byte 1, Mode (CE#=V ). IH BFH, identifies the manufacturer as SST. Byte 2, 25H, iden- tifies the memory type as SPI Serial Flash. Byte 3, 41H, identifies the device as SST25VF016B. The instruction CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334 SCK MODE 0 SI 9F HIGH IMPEDANCE BF 25 41 SO MSB MSB 1271 JEDECID.1 FIGURE20: JEDEC Read-ID Sequence TABLE 6: JEDEC Read-ID Data Manufacturer’s ID Device ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 BFH 25H 41H T6.0 1271 ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 19

16 Mbit SPI Serial Flash SST25VF016B Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as turer’s ID is located in address 00000H and the device ID is SST25VF016B and manufacturer as SST. This command located in address 00001H. Once the device is in Read-ID is backward compatible to all SST25xFxxxA devices and mode, the manufacturer’s and device ID output data tog- should be used as default device identification when multi- gles between address 00000H and 00001H until termi- ple versions of SPI Serial Flash devices are used in a nated by a low to high transition on CE#. design. The device information can be read from executing Refer to Tables 6 and 7 for device identification data. an 8-bit command, 90H or ABH, followed by address bits [A -A ]. Following the Read-ID instruction, the manufac- 23 0 CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 4748 5556 63 SCK MODE 0 90 or AB 00 00 ADD1 SI MSB MSB HIGH HIGH IMPEDANCE IMPEDANCE SO BF Device ID BF Device ID MSB Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. Device ID = 41H for SST25VF016B 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1271 RdID.0 FIGURE21: Read-ID Sequence TABLE 7: Product Identification Address Data Manufacturer’s ID 00000H BFH Device ID SST25VF016B 00001H 41H T7.01271 ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 20

16 Mbit SPI Serial Flash SST25VF016B Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Package Power Dissipation Capability (T = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W A Surface Mount Solder Reflow Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. Operating Range AC Conditions of Test Range Ambient Temp V Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns DD Commercial 0°C to +70°C 2.7-3.6V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF Industrial -40°C to +85°C 2.7-3.6V See Figures 26 and 27 TABLE 8: DC Operating Characteristics Limits Symbol Parameter Min Max Units Test Conditions I Read Current 10 mA CE#=0.1 V /0.9 V @25 MHz, SO=open DDR DD DD I Read Current 15 mA CE#=0.1 V /0.9 V @50 MHz, SO=open DDR2 DD DD I Read Current 20 mA CE#=0.1 V /0.9 V @80 MHz, SO=open DDR3 DD DD I Program and Erase Current 30 mA CE#=V DDW DD I Standby Current 20 µA CE#=V , V =V or V SB DD IN DD SS I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 1 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 0.7 V V V =V Max IH DD DD DD V Output Low Voltage 0.2 V I =100 µA, V =V Min OL OL DD DD V Output Low Voltage 0.4 V I =1.6 mA, V =V Min OL2 OL DD DD V Output High Voltage V -0.2 V I =-100 µA, V =V Min OH DD OH DD DD T8.0 1271 TABLE 9: Recommended System Power-up Timings Symbol Parameter Minimum Units T 1 V Min to Read Operation 10 µs PU-READ DD T 1 V Min to Write Operation 10 µs PU-WRITE DD T9.0 1271 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 21

16 Mbit SPI Serial Flash SST25VF016B Data Sheet TABLE 10: Capacitance (TA = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C 1 Output Pin Capacitance V = 0V 12 pF OUT OUT C 1 Input Capacitance V = 0V 6 pF IN IN T10.0 1271 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method N 1 Endurance 10,000 Cycles JEDEC Standard A117 END T 1 Data Retention 100 Years JEDEC Standard A103 DR I 1 Latch Up 100 + I mA JEDEC Standard 78 LTH DD T11.0 1271 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: AC Operating Characteristics 25 MHz 50 MHz 80 MHz Symbol Parameter Min Max Min Max Min Max Units F 1 Serial Clock Frequency 25 50 80 MHz CLK T Serial Clock High Time 18 9 6 ns SCKH T Serial Clock Low Time 18 9 6 ns SCKL T 2 Serial Clock Rise Time (Slew Rate) 0.1 0.1 0.1 V/ns SCKR T Serial Clock Fall Time (Slew Rate) 0.1 0.1 0.1 V/ns SCKF T 3 CE# Active Setup Time 10 5 5 ns CES T 3 CE# Active Hold Time 10 5 5 ns CEH T 3 CE# Not Active Setup Time 10 5 5 ns CHS T 3 CE# Not Active Hold Time 10 5 5 ns CHH T CE# High Time 100 50 50 ns CPH T CE# High to High-Z Output 15 8 7 ns CHZ T SCK Low to Low-Z Output 0 0 0 ns CLZ T Data In Setup Time 5 2 2 ns DS T Data In Hold Time 5 5 4 ns DH T HOLD# Low Setup Time 10 5 5 ns HLS T HOLD# High Setup Time 10 5 5 ns HHS T HOLD# Low Hold Time 10 5 5 ns HLH T HOLD# High Hold Time 10 5 5 ns HHH T HOLD# Low to High-Z Output 20 8 7 ns HZ T HOLD# High to Low-Z Output 15 8 7 ns LZ T Output Hold from SCK Change 0 0 0 ns OH T Output Valid from SCK 15 8 6 ns V T Sector-Erase 25 25 25 ms SE T Block-Erase 25 25 25 ms BE T Chip-Erase 50 50 50 ms SCE T Byte-Program 10 10 10 µs BP T12.0 1271 1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz 2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements 3. Relative to SCK. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 22

16 Mbit SPI Serial Flash SST25VF016B Data Sheet TCPH CE# TCHH TCES TSCKF TCEH TCHS SCK TDS TDH TSCKR MSB LSB SI SO HIGH-Z HIGH-Z 1271 SerIn.0 FIGURE22: Serial Input Timing Diagram CE# TSCKH TSCKL SCK TOH TCLZ TCHZ SO MSB LSB TV SI 1271 SerOut.0 FIGURE23: Serial Output Timing Diagram ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 23

16 Mbit SPI Serial Flash SST25VF016B Data Sheet CE# THHH THLS THHS SCK THLH THZ TLZ SO SI HOLD# 1271 Hold.0 FIGURE24: Hold Timing Diagram VDD VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. VDD Min TPU-READ Device fully accessible TPU-WRITE Time 1271 PwrUp.0 FIGURE25: Power-up Timing Diagram ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 24

16 Mbit SPI Serial Flash SST25VF016B Data Sheet VIHT VHT VHT INPUT REFERENCE POINTS OUTPUT VLT VLT VILT 1271 IORef.0 AC test inputs are driven at V (0.9V ) for a logic “1” and V (0.1V ) for a logic “0”. Measurement reference points IHT DD ILT DD for inputs and outputs are V (0.6V ) and V (0.4V ). Input rise and fall times (10% ↔ 90%) are <5 ns. HT DD LT DD Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE26: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1271 TstLd.0 FIGURE27: A Test Load Example ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 25

16 Mbit SPI Serial Flash SST25VF016B Data Sheet PRODUCT ORDERING INFORMATION SST 25 VF 016 B - 50 - 4C - S2A F XX XX XXX X - XX - XX - XXX X Environmental Attribute F1 = non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer Package Modifier A = 8 leads or contacts Package Type S2 = SOIC 200 mil body width Q = WSON Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 50 = 50 MHz 75 = 75 MHz (80MHz) Device Density 016 = 16 Mbit Voltage V = 2.7-3.6V Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “F” denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are “RoHS Compliant”. Valid combinations for SST25VF016B SST25VF016B-50-4C-S2AF SST25VF016B-50-4C-QAF SST25VF016B-50-4I-S2AF SST25VF016B-50-4I-QAF SST25VF016B-75-4I-S2AF SST25VF016B-75-4I-QAF Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 26

16 Mbit SPI Serial Flash SST25VF016B Data Sheet PACKAGING DIAGRAMS Pin #1 TOP VIEW SIDE VIEW Identifier 0.50 0.35 5.40 5.15 1.27 BSC 0.25 END VIEW 0.05 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0° 0.19 8° Note: 1. All linear dimensions are in millimeters (max/min). 0.80 2. Coplanarity: 0.1 mm 0.50 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 1mm 08-soic-EIAJ-S2A-3 FIGURE28: 8-lead Small Outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm) SST Package Code: S2A ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 27

16 Mbit SPI Serial Flash SST25VF016B Data Sheet TOP VIEW SIDE VIEW BOTTOM VIEW Pin #1 0.2 Pin #1 Corner 1.27 BSC 5.00 ± 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.05 Max 0.50 6.00 ± 0.10 0.80 0.70 CROSS SECTION Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 0.80 3. The external paddle is electrically connected to the 0.70 die back-side and possibly to certain VSS leads. This paddle can be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. 1mm 8-wson-5x6-QA-9.0 FIGURE29: 8-contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: QA TABLE 13: Revision History Number Description Date 00 (cid:129) Initial release of data sheet Apr 2005 01 (cid:129) Corrected “JEDEC Read-ID” on page19 including timing diagram Sep 2005 (cid:129) Corrected V and V values in Figure 26 on page25 HT LT 02 (cid:129) Migrated document to a Data Sheet Jan 2006 (cid:129) Updated Surface Mount Solder Reflow Temperature information 03 (cid:129) Edited Clock Frequency speed from 50 MHz to 80 MHz in Features, page 1 Sep 2008 (cid:129) Revised Table 5 for 80 MHz (cid:129) Edited High Speed Read for 80 MHz, page 10 (cid:129) Edited Table 8, page 21 (cid:129) Added 80 MHz columns to Table 12, page 22 (cid:129) Updated Product Ordering Information and Valid Combination, page 26 Silicon Storage Technology, Inc. (cid:129) 1171 Sonora Court (cid:129) Sunnyvale, CA 94086 (cid:129) Telephone 408-735-9110 (cid:129) Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2008 Silicon Storage Technology, Inc. S71271-03-000 9/08 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: SST25VF016B-50-4C-QAF SST25VF016B-50-4C-S2AF SST25VF016B-50-4I-QAF SST25VF016B-50-4I-S2AF SST25VF016B-75-4I-QAF SST25VF016B-75-4I-S2AF SST25VF016B-50-4C-QAF-T SST25VF016B-50-4I-QAF-T SST25VF016B-50-4I-S2AF-T OLD SST P/N SST25VF016B-50-4C-S2AF-T OLD SST P/N SST25VF016B-75-4I-QAF OLD SST P/N SST25VF016B-50-4I-S2AF OLD SST P/N SST25VF016B-50-4I-QAF OLD SST P/N SST25VF016B-75- 4I-S2AF OLD SST P/N SST25VF016B-50-4C-S2AF OLD SST P/N SST25VF016B-50-4C-QAF OLD SST P/N