SST25VF016B 16 Mbit SPI Serial Flash Features Product Description • Single Voltage Read and Write Operations The 25 series Serial Flash family features a four-wire, - 2.7-3.6V SPI-compatible interface that allows for a low pin-count package which occupies less board space and ulti- • Serial Interface Architecture mately lowers total system costs. The SST25VF016B - SPI Compatible: Mode 0 and Mode 3 devices are enhanced with improved operating fre- • High Speed Clock Frequency quency and even lower power consumption than the - Up to 50 MHz original SST25VFxxxA devices. SST25VF016B SPI • Superior Reliability serial flash memories are manufactured with propri- - Endurance: 100,000 Cycles (typical) etary, high-performance CMOS SuperFlash technol- ogy. The split-gate cell design and thick-oxide tunneling - Greater than 100 years Data Retention injector attain better reliability and manufacturability • Low Power Consumption: compared with alternate approaches. - Active Read Current: 10 mA (typical) SST25VF016B devices significantly improve perfor- - Standby Current: 5 µA (typical) mance and reliability, while lowering power consump- • Flexible Erase Capability tion. The devices write (Program or Erase) with a single - Uniform 4 KByte sectors power supply of 2.7-3.6V for SST25VF016B. The total - Uniform 32 KByte overlay blocks energy consumed is a function of the applied voltage, - Uniform 64 KByte overlay blocks current, and time of application. Since for any given • Fast Erase and Byte-Program: voltage range, the SuperFlash technology uses less - Chip-Erase Time: 35 ms (typical) current to program and has a shorter erase time, the - Sector-/Block-Erase Time: 18 ms (typical) total energy consumed during any Erase or Program - Byte-Program Time: 7 µs (typical) operation is less than alternative flash memory technol- ogies. • Auto Address Increment (AAI) Programming - Decrease total chip programming time over The SST25VF016B device is offered in both 8-lead Byte-Program operations SOIC (200 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 2-1 for pin assignments. • End-of-Write Detection - Software polling the BUSY bit in Status Register - Busy Status readout on SO pin in AAI Mode • Hold Pin (HOLD#) - Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register • Software Write Protection - Write protection through Block-Protection bits in status register • Temperature Range - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C • Packages Available - 8-lead SOIC (200 mils) - 8-contact WSON (6mm x 5mm) • All devices are RoHS compliant  2015 Microchip Technology Inc. DS20005044C-page 1

SST25VF016B TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E- mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS20005044C-page 2  2015 Microchip Technology Inc.

SST25VF016B 1.0 BLOCK DIAGRAM FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM SuperFlash X - Decoder Address Memory Buffers and Latches Y - Decoder I/O Buffers Control Logic and Data Latches Serial Interface CE# SCK SI SO WP# HOLD# 1271 B1.0  2015 Microchip Technology Inc. DS20005044C-page 3

SST25VF016B 2.0 PIN DESCRIPTION FIGURE 2-1: PIN ASSIGNMENTS CE# 1 8 VDD CE# 1 8 VDD SO 2 7 HOLD# SO 2 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 1271 08-wson QA P2.0 1271 08-soic S2A P1.0 8-Lead SOIC 8-Contact WSON TABLE 2-1: PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin. See “Hardware End-of-Write Detection” on page11 for details. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF016B DD V Ground SS DS20005044C-page 4  2015 Microchip Technology Inc.

SST25VF016B 3.0 MEMORY ORGANIZATION used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and The SST25VF016B SuperFlash memory array is orga- Serial Clock (SCK). nized in uniform 4 KByte erasable sectors with The SST25VF016B supports both Mode 0 (0,0) and 32KByte overlay blocks and 64 KByte overlay eras- Mode 3 (1,1) of SPI bus operations. The difference able blocks. between the two modes, as shown in Figure 4-1, is the state of the SCK signal when the bus master is in 4.0 DEVICE OPERATION Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for The SST25VF016B is accessed through the SPI (Serial Mode 3. For both modes, the Serial Data In (SI) is sam- Peripheral Interface) bus compatible protocol. The SPI pled at the rising edge of the SCK clock signal and the bus consist of four control lines; Chip Enable (CE#) is Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. FIGURE 4-1: SPI PROTOCOL CE# MODE 3 MODE 3 SCK MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB 1271 SPIprot.0 4.1 Hold Operation HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the The HOLD# pin is used to pause a serial sequence SCK next reaches the active low state. See Figure 4-2 underway with the SPI flash memory without resetting for Hold Condition waveform. the clocking sequence. To activate the HOLD# mode, Once the device enters Hold mode, SO will be in high- CE# must be in active low state. The HOLD# mode impedance state while SI and SCK can be V or V begins when the SCK active low state coincides with IL IH. the falling edge of the HOLD# signal. The HOLD mode If CE# is driven active high during a Hold condition, it ends when the HOLD# signal’s rising edge coincides resets the internal logic of the device. As long as with the SCK active low state. HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, If the falling edge of the HOLD# signal does not coin- HOLD# must be driven active high, and CE# must be cide with the SCK active low state, then the device driven active low. See Figure 5-3 for Hold timing. enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the FIGURE 4-2: HOLD CONDITION WAVEFORM SCK HOLD# Active Hold Active Hold Active 1271 HoldCond.0 4.2 Write Protection register provide Write protection to the memory array and the status register. See Table 4-3 for the Block-Pro- SST25VF016B provides software Write protection. The tection description. Write Protect pin (WP#) enables or disables the lock- down function of the status register. The Block-Protec- tion bits (BP3, BP2, BP1, BP0, and BPL) in the status  2015 Microchip Technology Inc. DS20005044C-page 5

SST25VF016B 4.2.1 WRITE PROTECT PIN (WP#) Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4-1). When WP# is The Write Protect (WP#) pin enables the lock-down high, the lock-down function of the BPL bit is disabled. function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write- TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION WP# BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed 4.3 Status Register During an internal Erase or Program operation, the sta- tus register may be read only to determine the comple- The software status register provides status on tion of an operation in progress. Table 4-2 describes whether the flash memory array is available for any the function of each bit in the software status register. Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. TABLE 4-2: SOFTWARE STATUS REGISTER Default at Bit Name Function Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 R 0 = No internal Write operation is in progress 1 WEL 1 = Device is memory Write enabled 0 R 0 = Device is not memory Write enabled 2 BP0 Indicate current level of block write protection (See Table 4-3) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 4-3) 1 R/W 4 BP2 Indicate current level of block write protection (See Table 4-3) 1 R/W 5 BP3 Indicate current level of block write protection (See Table 4-3) 0 R/W 6 AAI Auto Address Increment Programming status 0 R 1 = AAI programming mode 0 = Byte-Program mode 7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 R/W 0 = BP3, BP2, BP1, BP0 are read/writable 4.3.1 BUSY • Power-up The Busy bit determines whether there is an internal • Write-Disable (WRDI) instruction completion Erase or Program operation in progress. A “1” for the • Byte-Program instruction completion Busy bit indicates the device is busy with an operation • Auto Address Increment (AAI) programming is in progress. A “0” indicates the device is ready for the completed or reached its highest unprotected next valid operation. memory address • Sector-Erase instruction completion 4.3.2 WRITE ENABLE LATCH (WEL) • Block-Erase instruction completion The Write-Enable-Latch (WEL) bit indicates the status • Chip-Erase instruction completion of the internal memory Write Enable Latch. If the Write- • Write-Status-Register instructions Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates 4.3.3 AUTO ADDRESS INCREMENT (AAI) the device is not Write enabled and does not accept any memory Write (Program/Erase) commands. The The Auto Address Increment Programming-Status bit Write-Enable-Latch bit is automatically reset under the provides status on whether the device is in Auto following conditions: Address Increment (AAI) programming mode or Byte- Program mode. The default at power up is Byte-Pro- gram mode. DS20005044C-page 6  2015 Microchip Technology Inc.

SST25VF016B 4.3.4 BLOCK PROTECTION (BP3,BP2, 4.3.5 BLOCK PROTECTION LOCK-DOWN BP1, BP0) (BPL) The Block-Protection (BP3, BP2, BP1, BP0) bits define WP# pin driven low (V ), enables the Block-Protection- IL the size of the memory area, as defined in Table 4-3, to Lock-Down (BPL) bit. When BPL is set to 1, it prevents be software protected against any memory Write (Pro- any further alteration of the BPL, BP3, BP2, BP1, and gram or Erase) operation. The Write-Status-Register BP0 bits. When the WP# pin is driven high (V ), the IH (WRSR) instruction is used to program the BP3, BP2, BPL bit has no effect and its value is “Don’t Care”. After BP1 and BP0 bits as long as WP# is high or the Block- power-up, the BPL bit is reset to 0. Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power- up, BP3, BP2, BP1 and BP0 are set to 1. TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF016B1 Status Register Bit2 Protected Memory Address Protection Level BP3 BP2 BP1 BP0 16 Mbit None X 0 0 0 None Upper 1/32 X 0 0 1 1F0000H-1FFFFFH Upper 1/16 X 0 1 0 1E0000H-1FFFFFH Upper 1/8 X 0 1 1 1C0000H-1FFFFFH Upper 1/4 X 1 0 0 180000H-1FFFFFH Upper 1/2 X 1 0 1 100000H-1FFFFFH All Blocks X 1 1 0 000000H-1FFFFFH All Blocks X 1 1 1 000000H-1FFFFFH 1. X = Don’t Care (RESERVED) default is “0 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)  2015 Microchip Technology Inc. DS20005044C-page 7

SST25VF016B 4.4 Instructions of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be Instructions are used to read, write (Erase and Pro- driven low before an instruction is entered and must be gram), and configure the SST25VF016B. The instruc- driven high after the last bit of the instruction has been tion bus cycles are 8 bits each for commands (Op shifted in (except for Read, Read-ID, and Read-Status- Code), data, and addresses. Prior to executing any Register instructions). Any low to high transition on Byte-Program, Auto Address Increment (AAI) program- CE#, before receiving the last bit of an instruction bus ming, Sector-Erase, Block-Erase, Write-Status-Regis- cycle, will terminate the instruction in progress and ter, or Chip-Erase instructions, the Write-Enable return the device to standby mode. Instruction com- (WREN) instruction must be executed first. The com- mands (Op Code), addresses, and data are all input plete list of instructions is provided in Table 4-4. All from the most significant bit (MSB) first. instructions are synchronized off a high to low transition TABLE 4-4: DEVICE OPERATION INSTRUCTIONS Address Dummy Data Maximum Instruction Description Op Code Cycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency Read Read Memory at 25 MHz 0000 0011b (03H) 3 0 1 to  25 MHz High-Speed Read Memory at 50 MHz 0000 1011b (0BH) 3 1 1 to  50 MHz Read 4 KByte Sector- Erase 4 KByte of 0010 0000b (20H) 3 0 0 50 MHz Erase3 memory array 32 KByte Block- Erase 32 KByte block 0101 0010b (52H) 3 0 0 50 MHz Erase4 of memory array 64 KByte Block- Erase 64 KByte block 1101 1000b (D8H) 3 0 0 50 MHz Erase5 of memory array Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 0 0 0 50 MHz 1100 0111b (C7H) Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 50 MHz AAI-Word-Pro- Auto Address Increment 1010 1101b (ADH) 3 0 2 to  50 MHz gram6 Programming RDSR7 Read-Status-Register 0000 0101b (05H) 0 0 1 to  50 MHz EWSR Enable-Write-Status-Register 0101b 0000b (50H) 0 0 0 50 MHz WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 50 MHz WREN Write-Enable 0000 0110b (06H) 0 0 0 50 MHz WRDI Write-Disable 0000 0100b (04H) 0 0 0 50 MHz RDID8 Read-ID 1001 0000b (90H) or 3 0 1 to  50 MHz 1010 1011b (ABH) JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to  50 MHz EBSY Enable SO to output RY/BY# 0111 0000b (70H) 0 0 0 50 MHz status during AAI program- ming DBSY Disable SO as RY/BY# 1000 0000b (80H) 0 0 0 50 MHz status during AAI program- ming 1. One bus cycle is eight clock periods. 2. Address bits above the most significant bit of each density can be V or V . IL IH 3. 4KByte Sector Erase addresses: use A -A remaining addresses are don’t care but must be set either at V or V MS 12, IL IH. 4. 32KByte Block Erase addresses: use A -A remaining addresses are don’t care but must be set either at V or V MS 15, IL IH. 5. 64KByte Block Erase addresses: use A -A remaining addresses are don’t care but must be set either at V or V MS 16, IL IH. 6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A -A ] with A =0, Data Byte 1 will be pro- 23 1 0 grammed into the initial address [A -A ] with A =1. 23 1 0 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A =0, and Device ID is read with A =1. All other address bits are 00H. The Manufacturer’s ID 0 0 and device ID output stream is continuous until terminated by a low-to-high transition on CE#. DS20005044C-page 8  2015 Microchip Technology Inc.

SST25VF016B 4.4.1 READ (25 MHZ) cally increment to the beginning (wrap-around) of the address space. Once the data from address location The Read instruction, 03H, supports up to 25 MHz 1FFFFFH has been read, the next output will be from Read. The device outputs the data starting from the address location 000000H. specified address location. The data output stream is continuous through all addresses until terminated by a The Read instruction is initiated by executing an 8-bit low to high transition on CE#. The internal address command, 03H, followed by address bits [A23-A0]. CE# pointer will automatically increment until the highest must remain active low for the duration of the Read memory address is reached. Once the highest memory cycle. See Figure 4-3 for the Read sequence. address is reached, the address pointer will automati- FIGURE 4-3: READ SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 47 48 5556 6364 70 SCK MODE 0 03 ADD. ADD. ADD. SI MSB MSB N N+1 N+2 N+3 N+4 HIGH IMPEDANCE SO DOUT DOUT DOUT DOUT DOUT MSB 1271 ReadSeq.0 4.4.2 HIGH-SPEED-READ (50 MHZ) through all addresses until terminated by a low to high transition on CE#. The internal address pointer will The High-Speed-Read instruction supporting up to 50 automatically increment until the highest memory MHz Read is initiated by executing an 8-bit command, address is reached. Once the highest memory address 0BH, followed by address bits [A -A ] and a dummy 23 0 is reached, the address pointer will automatically incre- byte. CE# must remain active low for the duration of the ment to the beginning (wrap-around) of the address High-Speed-Read cycle. See Figure 4-4 for the High- space. Once the data from address location 1FFFFFH Speed-Read sequence. has been read, the next output will be from address Following a dummy cycle, the High-Speed-Read location 000000H. instruction outputs the data starting from the specified address location. The data output stream is continuous FIGURE 4-4: HIGH-SPEED-READ SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 23 24 3132 3940 4748 55 56 6364 7172 80 SCKMODE 0 SI 0B ADD. ADD. ADD. X MSB MSB N N+1 N+2 N+3 N+4 SO HIGH IMPEDANCE DOUT DOUT DOUT DOUT DOUT MSB Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) 1271 HSRdSeq.0  2015 Microchip Technology Inc. DS20005044C-page 9

SST25VF016B 4.4.3 BYTE-PROGRAM The Byte-Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A - The Byte-Program instruction programs the bits in the 23 A ]. Following the address, the data is input in order selected byte to the desired data. The selected byte 0 from MSB (bit 7) to LSB (bit 0). CE# must be driven must be in the erased state (FFH) when initiating a Pro- high before the instruction is executed. The user may gram operation. A Byte-Program instruction applied to a poll the Busy bit in the software status register or wait protected memory area will be ignored. T for the completion of the internal self-timed Byte- BP Prior to any Write operation, the Write-Enable (WREN) Program operation. See Figure 4-5 for the Byte-Pro- instruction must be executed. CE# must remain active gram sequence. low for the duration of the Byte-Program instruction. FIGURE 4-5: BYTE-PROGRAM SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 SCK MODE 0 SI 02 ADD. ADD. ADD. DIN MSB MSB MSB LSB SO HIGH IMPEDANCE 1271 ByteProg.0 4.4.4 AUTO ADDRESS INCREMENT (AAI) device indicates it is no longer busy, data for the next WORD-PROGRAM two sequential addresses may be programmed, fol- lowed by the next two, and so on. The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next When programming the last desired word, or the high- sequential address location. This feature decreases est unprotected memory address, check the busy sta- total programming time when multiple bytes or entire tus using either the hardware or software (RDSR memory array is to be programmed. An AAI Word pro- instruction) method to check for program completion. gram instruction pointing to a protected memory area Once programming is complete, use the applicable will be ignored. The selected address range must be in method to terminate AAI. If the device is in Software the erased state (FFH) when initiating an AAI Word End-of-Write Detection mode, execute the Write-Dis- Program operation. While within AAI Word Program- able (WRDI) instruction, 04H. If the device is in AAI ming sequence, only the following instructions are Hardware End-of-Write Detection mode, execute the valid: for software end-of-write detection—AAI Word Write-Disable (WRDI) instruction, 04H, followed by the (ADH), WRDI (04H), and RDSR (05H); for hardware 8-bit DBSY command, 80H. There is no wrap mode end-of-write detection—AAI Word (ADH) and WRDI during AAI programming once the highest unprotected (04H). There are three options to determine the com- memory address is reached. See Figures 4-8 and 4-9 pletion of each AAI Word program cycle: hardware for the AAI Word programming sequence. detection by reading the Serial Output, software detec- 4.4.5 END-OF-WRITE DETECTION tion by polling the BUSY bit in the software status reg- ister, or wait TBP. Refer to“End-of-Write Detection” for There are three methods to determine completion of a details. program cycle during AAI Word programming: hard- Prior to any write operation, the Write-Enable (WREN) ware detection by reading the Serial Output, software instruction must be executed. Initiate the AAI Word detection by polling the BUSY bit in the Software Status Register, or wait T The Hardware End-of-Write Program instruction by executing an 8-bit command, BP. ADH, followed by address bits [A -A ]. Following the detection method is described in the section below. 23 0 addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) is programmed into the initial address [A - 23 A ] with A =0, the second byte of Data (D1) is pro- 1 0 grammed into the initial address [A -A ] with A =1. 23 1 0 CE# must be driven high before executing the AAI Word Program instruction. Check the BUSY status before entering the next valid command. Once the DS20005044C-page 10  2015 Microchip Technology Inc.

SST25VF016B 4.4.6 HARDWARE END-OF-WRITE on the SO pin. A ‘0’ indicates the device is busy and a DETECTION ‘1’ indicates the device is ready for the next instruction. De-asserting CE# will return the SO pin to tri-state. The Hardware End-of-Write detection method elimi- While in AAI and Hardware End-of-Write detection nates the overhead of polling the Busy bit in the Soft- mode, the only valid instructions are AAI Word (ADH) ware Status Register during an AAI Word program and WRDI (04H). operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status To exit AAI Hardware End-of-Write detection, first exe- during AAI Word programming. (see Figure 4-6) The 8- cute WRDI instruction, 04H, to reset the Write-Enable- bit command, 70H, must be executed prior to initiating Latch bit (WEL=0) and AAI bit. Then execute the 8-bit an AAI Word-Program instruction. Once an internal DBSY command, 80H, to disable RY/BY# status during programming operation begins, asserting CE# will the AAI command. See Figures 4-7 and 4-8. immediately drive the status of the internal flash status FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 70 SI MSB SO HIGH IMPEDANCE 1271 EnableSO.0 FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 80 SI MSB SO HIGH IMPEDANCE 1271 DisableSO.0  2015 Microchip Technology Inc. DS20005044C-page 11

SST25VF016B FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETECTION CE# MODE 3 0 7 0 7 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 SCKMODE 0 SI EBSY WREN AD A A A D0 D1 AD D2 D3 Load AAI command, Address, 2 bytes data SO Check for Flash Busy Status to load next valid1 command CE# cont. 0 7 8 1516 23 0 7 0 7 0 7 8 15 SCK cont. SI cont. AD Dn-1 Dn WRDI DBSY RDSR Last 2 WRDI followed by DBSY Data Bytes to exit AAI Mode SO cont. DOUT Check for Flash Busy Status to load next valid1 command Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming 1271 AAI.HW.3 FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETECTION Wait TBP or poll Software Status register to load next valid1 command CE# MODE 3 0 7 8 1516 2324 3132 3940 47 0 7 8 1516 23 0 7 8 1516 23 0 7 0 7 8 15 SCK MODE 0 SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR Load AAI command, Address, 2 bytes data Last 2 WRDI to exit Data Bytes AAI Mode SO DOUT Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command 1271 AAI.SW.1 DS20005044C-page 12  2015 Microchip Technology Inc.

SST25VF016B 4.4.7 4-KBYTE SECTOR-ERASE bits [A -A ]. Address bits [A -A ] (A =Most Sig- 23 0 MS 12 MS nificant address) are used to determine the sector The Sector-Erase instruction clears all bits in the address (SA ), remaining address bits can be V or V selected 4 KByte sector to FFH. A Sector-Erase X IL IH. CE# must be driven high before the instruction is exe- instruction applied to a protected memory area will be cuted. The user may poll the Busy bit in the software ignored. Prior to any Write operation, the Write-Enable status register or wait T for the completion of the (WREN) instruction must be executed. CE# must SE internal self-timed Sector-Erase cycle. See Figure 4-10 remain active low for the duration of any command for the Sector-Erase sequence. sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address FIGURE 4-10: SECTOR-ERASE SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 20 ADD. ADD. ADD. SI MSB MSB SO HIGH IMPEDANCE 1271 SecErase.0 4.4.8 32-KBYTE AND 64-KBYTE BLOCK- nificant Address) are used to determine block address ERASE (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The The 32-KByte Block-Erase instruction clears all bits in 64-Kbyte Block-Erase instruction is initiated by executing an the selected 32 KByte block to FFH. A Block-Erase 8-bit command D8H, followed by address bits [A -A ]. instruction applied to a protected memory area will be 23 0 Address bits [A -A ] are used to determine block address ignored. The 64-KByte Block-Erase instruction clears all bits MS 15 (BA ), remaining address bits can be V or V CE# must in the selected 64 KByte block to FFH. A Block-Erase X IL IH. be driven high before the instruction is executed. The user instruction applied to a protected memory area will be may poll the Busy bit in the software status register or wait ignored. Prior to any Write operation, the Write-Enable T for the completion of the internal self-timed 32- (WREN) instruction must be executed. CE# must remain BE KByte Block-Erase or 64-KByte Block-Erase cycles. active low for the duration of any command sequence. See Figures 4-11 and 4-12 for the 32-KByte Block- The 32-Kbyte Block-Erase instruction is initiated by Erase and 64-KByte Block-Erase sequences. executing an 8-bit command, 52H, followed by address bits [A -A ]. Address bits [A -A ] (A =Most Sig- 23 0 MS 15 MS FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 52 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1271 32KBklEr.0  2015 Microchip Technology Inc. DS20005044C-page 13

SST25VF016B FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 31 SCK MODE 0 D8 ADDR ADDR ADDR SI MSB MSB SO HIGH IMPEDANCE 1271 63KBlkEr.0 4.4.9 CHIP-ERASE instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction The Chip-Erase instruction clears all bits in the device is executed. The user may poll the Busy bit in the software to FFH. A Chip-Erase instruction will be ignored if any status register or wait T for the completion of the of the memory area is protected. Prior to any Write oper- CE internal self-timed Chip-Erase cycle. See Figure 4-13 ation, the Write-Enable (WREN) instruction must be exe- for the Chip-Erase sequence. cuted. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase FIGURE 4-13: CHIP-ERASE SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 60 or C7 SI MSB SO HIGH IMPEDANCE 1271 ChEr.0 DS20005044C-page 14  2015 Microchip Technology Inc.

SST25VF016B 4.4.10 READ-STATUS-REGISTER (RDSR) properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain The Read-Status-Register (RDSR) instruction allows low until the status data is read. Read-Status-Register reading of the status register. The status register may is continuous with ongoing clock cycles until it is termi- be read at any time even during a Write (Program/ nated by a low to high transition of the CE#. See Figure Erase) operation. When a Write operation is in prog- 4-14 for the RDSR instruction sequence. ress, the Busy bit may be checked before sending any new commands to assure that the new commands are FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE 0 05 SI MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB Status Register Out 1271 RDSRseq.0 4.4.11 WRITE-ENABLE (WREN) execution of the Write-Status-Register (WRSR) instruc- tion; however, the Write-Enable-Latch bit in the Status The Write-Enable (WREN) instruction sets the Write- Register will be cleared upon the rising edge CE# of the Enable-Latch bit in the Status Register to 1 allowing WRSR instruction. CE# must be driven high before the Write operations to occur. The WREN instruction must WREN instruction is executed. be executed prior to any Write (Program/Erase) opera- tion. The WREN instruction may also be used to allow FIGURE 4-15: WRITE ENABLE (WREN) SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 06 SI MSB SO HIGH IMPEDANCE 1271 WREN.0  2015 Microchip Technology Inc. DS20005044C-page 15

SST25VF016B 4.4.12 WRITE-DISABLE (WRDI) terminate any programming operation in progress. Any program operation in progress may continue up to T The Write-Disable (WRDI) instruction resets the Write- BP after executing the WRDI instruction. CE# must be driven Enable-Latch bit and AAI bit to 0 disabling any new Write high before the WRDI instruction is executed. operations from occurring. The WRDI instruction will not FIGURE 4-16: WRITE DISABLE (WRDI) SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 SCK MODE 0 04 SI MSB SO HIGH IMPEDANCE 1271 WRDI.0 4.4.13 ENABLE-WRITE-STATUS- command sequence of the WRSR instruction is REGISTER (EWSR) entered and driven high before the WRSR instruction is executed. See Figure 4-17 for EWSR or WREN and The Enable-Write-Status-Register (EWSR) instruction WRSR instruction sequences. arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write- Executing the Write-Status-Register instruction will be Status-Register instruction must be executed immedi- ignored when WP# is low and BPL bit is set to “1”. ately after the execution of the Enable-Write-Status- When the WP# is low, the BPL bit can only be set from Register instruction. This two-step instruction “0” to “1” to lock-down the status register, but cannot be sequence of the EWSR instruction followed by the reset from “1” to “0”. When WP# is high, the lock-down WRSR instruction works like SDP (software data pro- function of the BPL bit is disabled and the BPL, BP0, tection) command structure which prevents any acci- and BP1 and BP2 bits in the status register can all be dental alteration of the status register values. CE# must changed. As long as BPL bit is set to 0 or WP# pin is be driven low before the EWSR instruction is entered driven high (VIH) prior to the low-to-high transition of the and must be driven high before the EWSR instruction CE# pin at the end of the WRSR instruction, the bits in is executed. the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can 4.4.14 WRITE-STATUS-REGISTER (WRSR) set the BPL bit to “1” to lock down the status register as well as altering the BP0, BP1, and BP2 bits at the same The Write-Status-Register instruction writes new val- time. See Table 4-1 for a summary description of WP# ues to the BP3, BP2, BP1, BP0, and BPL bits of the sta- and BPL functions. tus register. CE# must be driven low before the FIGURE 4-17: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 101112131415 SCK MODE 0 MODE 0 STATUS REGISTER IN 50 or 06 01 7 6 5 4 3 2 1 0 SI MSB MSB MSB HIGH IMPEDANCE SO 1271 EWSR.0 DS20005044C-page 16  2015 Microchip Technology Inc.

SST25VF016B 4.4.15 JEDEC READ-ID type as SPI Serial Flash. Byte 3, 41H, identifies the device as SST25VF016B. The instruction sequence is The JEDEC Read-ID instruction identifies the device as shown in Figure 4-18. The JEDEC Read ID instruction SST25VF016B and the manufacturer as Microchip. is terminated by a low to high transition on CE# at any The device information can be read from executing the time during data output. If no other command is issued 8-bit command, 9FH. Following the JEDEC Read-ID after executing the JEDEC Read-ID instruction, issue a instruction, the 8-bit manufacturer’s ID, BFH, is output 00H (NOP) command before going into Standby Mode from the device. After that, a 16-bit device ID is shifted (CE#=V ). out on the SO pin. Byte 1, BFH, identifies the manufac- IH turer as Microchip. Byte 2, 25H, identifies the memory FIGURE 4-18: JEDEC READ-ID SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334 SCK MODE 0 SI 9F HIGH IMPEDANCE BF 25 41 SO MSB MSB 1271 JEDECID.1 TABLE 4-5: JEDEC READ-ID DATA Device ID Manufacturer’s ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 BFH 25H 41H  2015 Microchip Technology Inc. DS20005044C-page 17

SST25VF016B 4.4.16 READ-ID (RDID) Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in The Read-ID instruction (RDID) identifies the devices address 00001H. Once the device is in Read-ID mode, as SST25VF016B and manufacturer as Microchip. This the manufacturer’s and device ID output data toggles command is backward compatible to all SST25xFxxxA between address 00000H and 00001H until terminated devices and should be used as default device identifi- by a low to high transition on CE#. cation when multiple versions of SPI Serial Flash devices are used in a design. The device information Refer to Tables 4-5 and 4-6 for device identification can be read from executing an 8-bit command, 90H or data. ABH, followed by address bits [A -A ]. Following the 23 0 FIGURE 4-19: READ-ID SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 1516 2324 3132 3940 4748 5556 63 SCK MODE 0 90 or AB 00 00 ADD1 SI MSB MSB HIGH HIGH IMPEDANCE IMPEDANCE SO BF Device ID BF Device ID MSB Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. Device ID = 41H for SST25VF016B 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1271 RdID.0 TABLE 4-6: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 00000H BFH Device ID SST25VF016B 00001H 41H DS20005044C-page 18  2015 Microchip Technology Inc.

SST25VF016B 5.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi- mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Package Power Dissipation Capability (T = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W A Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. TABLE 5-1: OPERATING RANGE Range Ambient Temp V DD Commercial 0°C to +70°C 2.7-3.6V Industrial -40°C to +85°C 2.7-3.6V TABLE 5-2: AC CONDITIONS OF TEST1 Input Rise/Fall Time Output Load 5ns C = 30 pF L 1. See Figures 5-5 and 5-6 TABLE 5-3: DC OPERATING CHARACTERISTICS Limits Symbol Parameter Min Max Units Test Conditions I Read Current 10 mA CE#=0.1 V /0.9 V @25 MHz, SO=open DDR DD DD I Read Current 15 mA CE#=0.1 V /0.9 V @50 MHz, SO=open DDR2 DD DD I Read Current 20 mA CE#=0.1 V /0.9 V @50 MHz, SO=open DDR3 DD DD I Program and Erase Current 30 mA CE#=V DDW DD I Standby Current 20 µA CE#=V , V =V or V SB DD IN DD SS I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 1 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 0.7 V V V =V Max IH DD DD DD V Output Low Voltage 0.2 V I =100 µA, V =V Min OL OL DD DD V Output Low Voltage 0.4 V I =1.6 mA, V =V Min OL2 OL DD DD V Output High Voltage V -0.2 V I =-100 µA, V =V Min OH DD OH DD DD  2015 Microchip Technology Inc. DS20005044C-page 19

SST25VF016B TABLE 5-4: CAPACITANCE (T = 25°C, F=1 MHz, OTHER PINS OPEN) A Parameter Description Test Condition Maximum C 1 Output Pin Capacitance V = 0V 12 pF OUT OUT C 1 Input Capacitance V = 0V 6 pF IN IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 5-5: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N 1 Endurance 10,000 Cycles JEDEC Standard A117 END T 1 Data Retention 100 Years JEDEC Standard A103 DR I 1 Latch Up 100 + I mA JEDEC Standard 78 LTH DD 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 5-6: AC OPERATING CHARACTERISTICS 25 MHz 50 MHz Symbol Parameter Min Max Min Max Units F 1 Serial Clock Frequency 25 50 MHz CLK T Serial Clock High Time 18 9 ns SCKH T Serial Clock Low Time 18 9 ns SCKL T 2 Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns SCKR T Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns SCKF T 3 CE# Active Setup Time 10 5 ns CES T 3 CE# Active Hold Time 10 5 ns CEH T 3 CE# Not Active Setup Time 10 5 ns CHS T 3 CE# Not Active Hold Time 10 5 ns CHH T CE# High Time 100 50 ns CPH T CE# High to High-Z Output 15 8 ns CHZ T SCK Low to Low-Z Output 0 0 ns CLZ T Data In Setup Time 5 2 ns DS T Data In Hold Time 5 5 ns DH T HOLD# Low Setup Time 10 5 ns HLS T HOLD# High Setup Time 10 5 ns HHS T HOLD# Low Hold Time 10 5 ns HLH T HOLD# High Hold Time 10 5 ns HHH T HOLD# Low to High-Z Output 20 8 ns HZ T HOLD# High to Low-Z Output 15 8 ns LZ T Output Hold from SCK Change 0 0 ns OH T Output Valid from SCK 15 8 ns V T Sector-Erase 25 25 ms SE T Block-Erase 25 25 ms BE T Chip-Erase 50 50 ms SCE T Byte-Program 10 10 µs BP 1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz 2. Maximum Rise and Fall time may be limited by T and T requirements SCKH SCKL 3. Relative to SCK. DS20005044C-page 20  2015 Microchip Technology Inc.

SST25VF016B FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM TCPH CE# TCHH TCES TSCKF TCEH TCHS SCK TDS TDH TSCKR MSB LSB SI SO HIGH-Z HIGH-Z 1271 SerIn.0 FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM CE# TSCKH TSCKL SCK TOH TCLZ TCHZ SO MSB LSB TV SI 1271 SerOut.0 FIGURE 5-3: HOLD TIMING DIAGRAM CE# THHH THLS THHS SCK THLH THZ TLZ SO SI HOLD# 1271 Hold.0  2015 Microchip Technology Inc. DS20005044C-page 21

SST25VF016B 5.1 Power-Up Specifications All functionalities and DC specifications are specified for a V ramp rate of greater than 1V per 100 ms (0v DD - 3.0V in less than 300 ms). See Table 5-7 and Figure 5-4 for more information. TABLE 5-7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T 1 V Min to Read Operation 100 µs PU-READ DD T 1 V Min to Write Operation 100 µs PU-WRITE DD 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. FIGURE 5-4: POWER-UP TIMING DIAGRAM VDD VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. VDD Min TPU-READ Device fully accessible TPU-WRITE Time 1271 PwrUp.0 DS20005044C-page 22  2015 Microchip Technology Inc.

SST25VF016B FIGURE 5-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS VIHT VHT VHT INPUT REFERENCE POINTS OUTPUT VLT VLT VILT 1271 IORef.0 AC test inputs are driven at V (0.9V ) for a logic “1” and V (0.1V ) for a logic “0”. Measurement IHT DD ILT DD reference points for inputs and outputs are V (0.6V ) and V (0.4V ). Input rise and fall times (10% HT DD LT DD  90%) are <5 ns. Note: V - V Test HT HIGH V - V Test LT LOW V - V HIGH Test IHT INPUT V - V LOW Test ILT INPUT FIGURE 5-6: A TEST LOAD EXAMPLE TO TESTER TO DUT CL 1271 TstLd.0  2015 Microchip Technology Inc. DS20005044C-page 23

SST25VF016B 6.0 PACKAGING DIAGRAMS 8-Lead Small Outline Integrated Circuit (S2AE/F) - .208 Inch Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0.1 mm 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. Microchip Technology Drawing C04-14005A Sheet 1 of 1 DS20005044C-page 24  2015 Microchip Technology Inc.

SST25VF016B 8-Lead Very, Very Thin Small Outline No-Leads (QAE/F) - 5x6 mm Body [WSON] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain VSS leads. This paddle can be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. Microchip Technology Drawing C04-14008A Sheet 1 of 1  2015 Microchip Technology Inc. DS20005044C-page 25

SST25VF016B TABLE 6-1: REVISION HISTORY Revision Description Date 00 (cid:129) Initial release of data sheet Apr 2005 01 (cid:129) Corrected “JEDEC Read-ID” on page17 including timing diagram Sep 2005 (cid:129) Corrected V and V values in Figure 5-5 on page23 HT LT 02 (cid:129) Migrated document to a Data Sheet Jan 2006 (cid:129) Updated Surface Mount Solder Reflow Temperature information 03 (cid:129) Edited Clock Frequency speed from 50 MHz to 80 MHz in Features, page 1 Sep 2008 (cid:129) Revised Table 5 for 80 MHz (cid:129) Edited High Speed Read for 80 MHz, page 10 (cid:129) Edited Table 8, page 21 (cid:129) Added 80 MHz columns to Table 12, page 22 (cid:129) Updated Product Ordering Information and Valid Combination, page 26 04 (cid:129) Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write Jan 2011 Detection”, and “Hardware End-of-Write Detection” on page11. (cid:129) Revised Figures 4-8 and 4-9 on page page12. (cid:129) Updated document to new format. A (cid:129) Added “Power-Up Specifications” on page22 Aug 2011 (cid:129) Updated Table5-7 on page22 (cid:129) Released document under letter revision system (cid:129) Updated Spec number from S71271 to DS25044 B (cid:129) Updated document to new corporate format Jan 2015 (cid:129) EOL of all 75 MHz parts. Replacement parts are the 50 MHz parts found in this data sheet. C (cid:129) Fixed an error in “Product Identification System” on page28 Jul 2015 DS20005044C-page 26  2015 Microchip Technology Inc.

SST25VF016B THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following informa- tion: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, appli- cation notes and sample programs, design Customers should contact their distributor, representa- resources, user’s guides and hardware support tive or Field Application Engineer (FAE) for support documents, latest software releases and archived Local sales offices are also available to help custom- software ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions.  2015 Microchip Technology Inc. DS20005044C-page 27

SST25VF016B 7.0 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – XX – XX – XX – X Valid Combinations: Device Operating Minimum Temp Package Tape/Reel SST25VF016B-50-4C-S2AF Frequency Endurance Range Indicator SST25VF016B-50-4C-S2AF-T SST25VF016B-50-4I-S2AF SST25VF016B-50-4I-S2AF-T SST25VF016B-50-4I-S2AE Device: SST25VF016B =16 Mbit, 2.7-3.6V, SPI Flash Memory SST25VF016B-50-4I-S2AE-T SST25VF016B-50-4C-QAF Operating 50 =50 MHz SST25VF016B-50-4C-QAF-T Frequency: SST25VF016B-50-4I-QAF SST25VF016B-50-4I-QAF-T Minimum 4 =10,000 cycles SST25VF016B-50-4I-QAE Endurance SST25VF016B-50-4I-QAE-T Temperature: I =-40°C to +85°C C =0°C to +70°C Package: QAF/QAE1 =WSON (6mm x 5mm Body), 8-lead S2AF/S2AE1 =SOIC (200 mil Body), 8-lead Tape and T =Tape and Reel Reel Flag: 1. Suffix E = Matte Tin finish Suffix F = Nickel plating with Gold top (outer) layer finish DS20005044C-page 28  2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights unless otherwise stated. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A.,3 All Rights Reserved. ISBN: 978-1-6277-622-8 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California CERTIFIED BY DNV and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping == ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2015 Microchip Technology Inc. DS20005044C-page 29

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