SP690T/S/R, SP802T/S/R, ® SP804T/S/R, and SP805T/S/R 3.0V/3.3V Low Power Microprocessor Supervisory with Battery Switch-Over n RESET and RESET Outputs n Reset asserted down to V = 1V CC n Reset Time Delay - 200ms n Watchdog Timer - 1.6 sec timeout n 40m A Maximum V Supply Current CC n 1m A Maximum Battery Supply Current n Power Switching 50mA Output in V Mode (1.5W ) CC 10mA Output in Battery Mode (15W ) n Battery Can Exceed V in Normal Operation CC n Precision Voltage Monitor for Power-Fail or Low-Battery Warning n Available in 8 pin SO and DIP packages n Pin Compatible Upgrades to MAX690T/S/R, MAX802T/S/R, MAX804T/S/R, MAX805T/S/R DESCRIPTION The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices are a family of microprocessor (m P) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in m P and digital systems. The series will significantly improve system reliability and operational efficiency when compared to discrete solutions. The features of the SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices include a watchdog timer, a m P reset and backup- battery switchover, and power-failure warning; a complete m P monitoring and watchdog solution. The series is ideal for 3.0V or 3.3V applications in portable electronics, computers, controllers, and intelligent instruments and is a solid match for designs where it is critical to monitor the power supply to the m P and it’s related digital components. Refer to Sipex's SP690A/692A/802L/802M/805L/805M series for similar devices designed for +5V systems. RE S E T RES E T RE S E T PFI W at ch d og Ba c k u p- Ba t t e r y Pa r t Nu m b e r AAAAAccccctttt tiiii ivvvv veeee e TTTTThhhhhrrrr reeee esssss hhhh hoooo ollll ldddd d AAAAAccccccccc cuuuu urrr rraaaa acccc cyyyy y AAAAAccccccccc cuuuuu rrrr raaaa acccc cyyyyy IIIIInnnnnpppp puuu uutttt t SSSSSwwwwwiiii itttt tccc cchhhhh SP 6 9 0 T / 80 5 T LO W / HI G H 3. 07 5 V ±7 5 m V ±4 % YE S YES SP 8 0 2 T / 80 4 T LO W / HI G H 3. 07 5 V ±6 0 m V ±2 % YE S YES SP 6 9 0 S / 80 5 S LO W / HI G H 2. 92 5 V ±7 5 m V ±4 % YE S YES SP 8 0 2 S / 80 4 S LO W / HI G H 2. 92 5 V ±6 0 m V ±2 % YE S YES SP 6 9 0 R /80 5 R LO W / HI G H 2. 62 5 V ±7 5 m V ±4 % YE S YES SP 8 0 2 R /80 4 R LO W / HI G H 2. 62 5 V ±6 0 m V ±2 % YE S YES SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 1

ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V ..................................................................................-0.3V to 6.0V CC V ................................................................................-0.3V to 6.0V BATT All Other Inputs (NOTE 1).................................-0.3V to the higher of V or V CC BATT Continuous Input Current: V ..................................................................................100mA CC V ..................................................................................20mA BATT GND..................................................................................20mA WDI, PFI...........................................................................20mA Continuous Output Current: RESET, RESET, PFO.........................................................20mA V ......................................................................................100mA OUT Power Dissipation per Package: 8pin NSOIC (derate 6.14mW/(cid:176)C above +70(cid:176)C)..............500mW 8pin PDIP (derate 11.8mW/(cid:176)C above +70(cid:176)C)..............1,000mW Storage Temperature........................................-65(cid:176)C to +160(cid:176)C Lead Temperature(soldering,10sec).............................................+300(cid:176)C ESD Rating........................................................4KV Human Body Model SPECIFICATIONS V = 3.17V to 5.50V for the SP690T/SP80_T, V = 3.02V to 5.50V for the SP690S/SP80_S, V = 2.72V to 5.50V for the SP690R/SP80_R, V = 3.60V, and CC CC CC BATT T = T to T unless otherwise noted. Typical values taken at T = +25OC. A MIN MAX AMB PA R A M E T E R S MI N . T YP . MA X . UN I T S CON D I T IO N S Op e r at i n g Vo lt ag e Ra n g e , 1 .0 5. 5 Vol t s V or V , NO T E 1 CC BA T T E R Y V Su p p l y Cu r r en t , I 25 40 m A ex c l u d i n g I CC SU P P L Y OUT V Su p p l y Cu r r en t in Ba t t e ry V =2 . 0 V , V =2. 3 V , CC 20 40 m A CC BA T T E R Y Ba c k u p Mo d e ex c l u d i n g I OUT V Sup p l y Cu r re n t in BA T T E R Y 0. 4 1 m A ex c l u d i n g I An y Mo d e , NO T E2 OUT V Le a k a ge Cu rr e nt , NO TE 3 0. 0 0 1 0 .5 m A BA T T E R Y V Le a k a ge Cu rr e nt , NO TE 4 -0 .1 0 .0 2 m A 3. 3V >V >V +0. 2 V BA T T E R Y CC BA T T E R Y Ou tp u t Vo l t a g e , V V -0. 0 3 V -0. 0 0 7 5 I =5m A OU T CC CC V -0. 3 V -0. 0 7 5 V I =50 mA CC CC OU T V -0. 0 0 1 5 V -0. 0 0 0 3 I = 25 0 m A, V >2. 5 V CC CC OU T CC V in Ba t t e r y - Ba c k u p M od e V - 0. 0 2 V -0. 0 0 4 5 I = 25 0 µ A, V =2. 3 V OU T BA T T E R Y BA T T E R Y V OU T BA T T E R Y V -0. 0 1 8 I = 1m A, V =2. 3 V BA T T E R Y OU T BA T T E R Y V -0. 1 5 I = 10 mA , VB =3. 3 V BA T T E R Y OU T AT T E R Y Ba t t e ry Sw i t c h T hr e s h o l d , 0.0 6 5 0.0 2 5 V - V , V > V >1. 75 V , NO T E 5 V BA T T E R Y CC SW CC V fal l i n g 2.3 0 2. 4 0 2. 50 V > V ,NO T E 6 CC BA T T E R Y CC Ba t te r y Sw i t c h T hr e s h o ld , Val u e s ar e id e nt i c a l t o th e Re s et V V CC ri s i n g , NO T E 7 T hr e s h o ld va lu es a t VC C ris i n g SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 2

SPECIFICATIONS (continued) V = 3.17V to 5.50V for the SP690T/SP80_T, V = 3.02V to 5.50V for the SP690S/SP80_S, V = 2.72V to 5.50V for the SP690R/SP80_R, V = 3.60V, and CC CC CC BATT T = T to T unless otherwise noted. Typical values taken at T = +25OC. A MIN MAX AMB PA R A M E T E R S MI N . T YP . MA X . UN I T S CON D I T I O N S 3.0 0 3.0 7 5 3.1 5 SP 6 9 0 T / 80 5 T , V fal l i n g CC 3.0 0 3.0 8 5 3.1 7 SP 6 9 0 T / 80 5 T , V ris i n g CC 2.8 5 2.9 2 5 3.0 0 SP 6 9 0 S / 80 5 S , V fal l i n g V CC 2.8 5 2.9 3 5 3.0 2 SP 6 9 0 S / 80 5 S , V ris i n g CC 2.5 5 2.6 2 5 2.7 0 SP 6 9 0 R / 80 5 R , V fal l i n g CC Re s e t Th r e s h o l d , V 2.5 5 2.6 3 5 2.7 2 SP 6 9 0 R / 80 5 R , V ris i n g RST CC NOT E 8 3.0 0 3.0 7 5 3.1 2 SP 8 0 2 T / 80 4 T , V fal l i n g CC 3.0 0 3.0 8 5 3.1 4 SP 8 0 2 T / 80 4 T , V ris i n g CC 2.8 8 2.9 2 5 3.0 0 SP 8 0 2 S / 80 4 S , V fal l i n g V CC 2.8 8 2.9 3 5 3.0 2 SP 8 0 2 S / 80 4 S , V ris i n g CC 2.5 9 2.6 2 5 2.7 0 SP 8 0 2 R / 80 4 R , V fal l i n g CC 2.5 9 2.6 3 5 2.7 2 SP 8 0 2 R / 80 4 R , V ris i n g CC Re s e t Ti m e o u t Pe r i o d , t 14 0 20 0 28 0 ms WP RE S E T , PF O Ou t p u t Vo l t a g e , V V - 0. 3 V - 0. 1 5 V I =30 µ A OH CC CC SO U R C E I =1. 2 m A , SP 6 9 0 _ / 8 0 2 _ wh e r e R ES E T , PF O Ou t p u t Vo l t a g e , V 0. 0 6 0. 3 0 V SI N K OL V = V min i m u m CC RS T RE S E T , PF O Ou t p u t Vo l t a g e , V 0. 1 3 0. 3 0 V V = 0V , V = 1. 0 V , I =40 µ A OL B AT T E R Y CC SI N K I =1. 2 m A , SP 8 0 4 _ / 8 0 5 _ wh e r e R ES E T Ou t p u t Vo l t a g e , V 0. 0 6 0. 3 0 V SI N K OL V = V max i m u m CC RS T RES E T Ou t p u t Le a k a g e Cu r r e n t , V = 0V , V = V min i m u m , -1 -1 m A B AT T E R Y CC RS T N OT E 11 V = 0V or V RE S E T CC Ou t p u t Sh o r t to GN D Cu r r e n t , I , OS 18 0 50 0 m A V = 3. 3 V , V =0V PF O an d RE S E T CC OH Wa t c h d o g Ti m e o u t , t 1. 1 2 1. 6 0 2. 2 4 s V <3. 6 V WD CC WD I Pu l s e Wi d t h 1 m s WD I In p u t Th r e s h o l d V 0. 7 x V V IH CC V IL 0. 3 x VC C WD I In p u t Cu r r e n t -1 0. 0 1 1 m A 0V < V <5. 5 V CC PF I In p u t Th r e s h o l d 1.2 0 0 1.2 5 1.3 0 0 SP 6 9 0 _ / 8 0 5 _ , V < 3. 6 V , V fal l i n g V CC PF I 1.2 2 5 1.2 5 1. 2 7 5 SP 8 0 2 _ / 8 0 4 _ , V < 3. 6 V , V fal l i n g CC PF I PF I In p u t Cu r r e n t -2 5 0. 0 1 25 nA PF I Hy s t e r e s i s , V 10 20 m V PF I ri s i n g , V < 3.6 V PF H CC SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 3

SPECIFICATIONS (continued) V = 3.17V to 5.50V for the SP690T/SP80_T, V = 3.02V to 5.50V for the SP690S/SP80_S, V = 2.72V to 5.50V for the SP690R/SP80_R, V = 3.60V, and CC CC CC BATT T = T to T unless otherwise noted. Typical values taken at T = +25OC. A MIN MAX AMB NOTE 1: The following are tested at V = 3.6V and V = 5.5V: V supply current, watchdog BATT CC CC functionality, logic input leakage, PFI functionality, and the RESET and RESET states. The state of RESET or RESET and PFO is tested at V = V (min). CC CC NOTE 2: Tested V = 3.6V, V = 3.5V and 0V. BATT CC NOTE 3: Leakage current into the battery is tested under the following worst-case conditions: V CC = 5.5V, V = 1.8V and at V = 1.5V, V = 1.0V. BATT CC BATT NOTE 4: "-" equals the battery-charging current, "+" equals the battery-discharging current. NOTE 5: When V > V > V , V remains connected to V until V drops below V . The SW CC BATT OUT CC CC BATT V -to-V comparator has a small 25mV typical hysteresis to prevent oscillation. CC BATT NOTE 6: When V > V > V , V remains connected to V until V drops below the battery BATT CC SW OUT CC CC switch threshold, V . SW NOTE 7: V switches from V to V when V rises above the reset threshold, independent of OUT BATT CC CC V . Switchover back to V occurs at the exact voltage that causes RESET to go HIGH (on the BATT CC SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset. NOTE 8: The reset threshold tolerance is wider for V rising than for V falling to accommodate the CC CC 10mV typical hysteresis, which prevents internal oscillation. NOTE 9: SP690_ and SP802_ devices only. NOTE 10: SP804_ and SP805_ devices only. NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET output high impedance). SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 4

INTERNAL BLOCK DIAGRAM VBVACTCT 8 SWBCIATIRTCTCHEUORIVTYE R 1 VOUT 2 SP690T/S/R SP802T/S/R SP804T/S/R SP805T/S/R BATTERY SWITCHOVER COMPARATOR 1.25V RESET GENERATOR RESET / RESET* 7 RESET COMPARATOR 1.25V WATCHDOG WDI6 TIMER PFI 4 PFO 5 POWER-FAIL COMPARATOR 1.25V GND 3 *SP804T/S/R and SP805T/S/R only SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 5

PINOUT V 1 8 V OUT BATTERY V 2 SP690T/S/R 7 RESET / RESET* CC SP802T/S/R GND 3 SP804T/S/R 6 WDI SP805T/S/R PFI 4 5 PFO *SP804T/S/R and SP805T/S/R only PIN ASSIGNMENTS Pin 1 —V — Output Supply Voltage for Pin 7 for SP690_/802_ only — Active-LOW OUT CMOS RAM. When V is above the Reset Output. — Whenever RESET is CC reset threshold, V connects to V triggered by a watchdog timeout, it goes OUT CC through a P-channel MOSFET switch. LOW for 200ms. It stays LOW whenever When V falls below the V and V is below the reset threshold and re- CC SW CC V , V connects to V . mains LOW for 200ms after V rises BATTERY BATTERY OUT CC Connect to V if no battery is used. above the reset threshold or when the CC watchdog triggers a reset. Pin 2 — V — +5V Supply Input CC Pin 7 for SP804_/805_ only — Active-HIGH Pin 3 — GND — Ground reference for all Open-Drain Reset Output. — The signals inverse operation of RESET. Pin 4 — PFI — Power-Fail Comparator Input. Pin 8 — V — Backup-Battery Input. When PFI is less than 1.25V or when V BATTERY CC When V falls below V and V , falls below the V , PFO goes LOW, CC SW BATTERY SW V switchesfrom V to V . otherwise PFO remains HIGH. Connect OUT CC BATTERY When V rises above the reset threshold, to GND if unused. CC V reconnects to V . V may OUT CC BATTERY exceed V . Connect to V if no battery Pin 5 — PFO — Power-Fail Comparator CC CC is used. Output. Leave open if unused. Pin 6 — WDI — Watchdog Input. If WDI remains HIGH or LOW for 1.6 seconds, the internal watchdog timer triggers a reset. The internal watchdog timer clears when reset is asserted or WDI sees a rising or falling edge. The watchdog function cannot be disabled. SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 6

TYPICAL CHARACTERISTICS (T = 25oC, unless otherwise noted) AMB 10000 40 1000 A) 35 y mply Current ( 30 attery SupplCurrent (nA) 10100 p B u S 25 1 20 0.1 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -35 -10 15 40 65 90 115 140 Temperature (oC) Temperature (oC) Figure 1. V Supply Current vs. Temperature (Normal Figure 2. Battery Supply Current vs. Temperature CC Mode) 1.262 30 1.26 W e () 25 Volts) 1.258 stanc 20 PFI Threshold ( 111...1222.55525642 V to V On-ResiBATTERYOUT 11505 1.248 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) Temperature (oC) Figure 3. PFI Threshold vs. Temperature Figure 4. V to V ON-Resistance vs. Temperature BATTERY OUT 3.15 3.5 3 3.13 s) ) 2.5 Volt WOn Resistance ( 1.25 set Threshold ( 33..0119 1 e R 3.07 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 3.05 -60 -35 -10 15 40 65 90 115 140 Temperature (oC) Temperature (oC) Figure 5. V to V On-Resistance vs. Temperature Figure 6. Reset Threshold vs. Temperature CC OUT SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 7

14000 185 12000 ) We ( c 10000 an S) st m esi 8000 ut ( ut R meo 180 Outp 6000 set Ti ET 4000 Re S E R 2000 175 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -35 -10 15 40 65 90 115 140 Temperature (oC) Temperature (oC) Figure 7. Reset Output Resistance vs. Temperature Figure 8. Reset Timeout vs. Temperature 30 1E-06 26 s) deca/ddiev melay ( 22 D n o gati 18 a p o Pr 14 1E-14 10 -60 -40 -20 0 20 40 60 80 100 120 140 .0000 5.000 V3 .5000/div (V) Temperature (oC) Figure 9. Battery Current vs. V Voltage Figure 10. Reset-Comparator Propagation Delay vs. CC Temperature 1000 1000 VCC = 0V VVBCACT T=E 4RY.5 =V 0V ]OUT VBATTERY = 4.5V V ]OUT - VRY 100 mV) [ V - CC 100 V) [ VBATTE e Drop ( 10 Drop (m 10 ag e Volt Voltag 1 1 1 10 100 1 10 IOUT (mA) IOUT (mA) Figure 11. V to V Vs. Output Current Figure 12. V to V Vs. Output Current CC OUT BATTERY OUT SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 8

V CC V = 0V BATTERY T = +25 C A 2dViv T VCC VCC 2KW 0V RESET RESET RESET 0V 1 330pF 1 sec / div GND Figure 13A. SP690A RESET Output Voltage vs. Figure 13B. Circuit for the SP690A/802L RESET Supply Voltage Output Voltage vs. Supply Voltage V CC V CC V 1dViv VCC CC 10KW 0V RESET 1 RESET V BATTERY 330pF 0V GND 1 sec /div Figure 14A. SP805L RESET Output Voltage vs. Figure 14B. Circuit for the SP805 RESET Output Supply Voltage Voltage vs. Supply Voltage V CC [ T ] T = +25 C 1V / div A 3.1V VCC 1 2V V CC 10KW RESET 3.1V T RESET 0 30pF 10mS / div GND Figure 15A. SP690A RESET Response Time Figure 15B. Circuit for the SP690A/802L RESET Response Time SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 9

V CC V [ T ] CC 1V / div 3.1V VCC V CC 1 2V 10KW RESET RESET T 0V 330pF GND 10 ms / div Figure 16A. SP805L RESET Response Time Figure 16B. Circuit for the SP805 RESET Response Time +5V 1.3V PFI V = +5V 1.2V CC VCC= 5V T = +25 C A VBATTERY= 0 1KW PFI PFO 5V PFO 0V 30pF +1.25V 500ns / div Figure 17A. Power-Fail Comparator Response Time (fall) Figure 17B. Circuit for the Power-Fail Comparator Response Time (fall) 1 +5V 1.3V PFI 1.2V VCC= 5 VCC = +5V VBATTERY= 0 T = +25 C A PFI PFO PFO +1.25V 30pF 1KW 1 2 T 500ns / div Figure 18A. Power-Fail Comparator Response Time (rise) Figure 18B. Circuit for the Power-Fail Comparator Response Time (rise) SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 10

3.0V or 3.3V V RST V V CC SW 0V 3.0V or 3.3V V VBATTERY=3.6V OUT V SW 0V 3.0V or 3.3V t WP RESET 0V 3.0V or 3.3V RESET* 0V 3.0V or 3.3V V =PFI=3.6V PFO BATTERY I =0mA OUT 0V *SP804T/S/R and SP805T/S/R only; Reset externally pulled up to V . CC Figure 19. Timing Diagram SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 11

FEATURES THEORY OF OPERATION The SP690T/S/R, SP802T/S/R, SP804T/S/R The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices provide four key and SP805T/S/R devices are microprocessor functions: (m P) supervisory circuits that monitor the power 1. A battery backup switch for CMOS RAM, supplied to digital circuits such as microproces- CMOS microprocessors, or other logic. sors, microcontrollers, or memory. The series is 2. A reset output during power-up, power-down an ideal solution for portable, battery-powered and brownout conditions. equipment that requires power supply monitoring. 3. A reset pulse if the optional watchdog timer Implementing this series will reduce the has not been toggled within a specified time. number of components and overall complexity. 4. A 1.25V threshold detector for power-fail The watchdog functions of this product family warning, low battery detection, or to monitor a will continuously oversee the operational status power supply other than 3.3V or 3.0V. of a system. The SP690T/S/R, SP802T/S/R, SP804T/S/R These m P supervisory circuits are not short- and SP805T/S/R devices differ in their reset- circuit protected. Shorting V to ground - OUT voltage threshold levels and are ideally suited excluding power-up transients such as charging for applications in automotive systems, intelligent a decoupling capacitor - may potentially damage instruments, and battery-powered computers and these devices. Decouple both V and V CC BATTERY controllers. The series is a solid match for pins to ground by placing 0.1m F capacitors as designs where it is critical to monitor the close to the device as possible. The operational power supply to the m P and it’s related digital features and benefits of the SP690T/S/R, components. SP802T/S/R, SP804T/S/R and SP805T/S/R devices are described in more detail below. Reset Output Regulated +3.3V or +3.0V The microprocessor's (m P's) reset input starts the m P in a known state. When the m P is in an Unregulated V 0.1m F DC unknown state, it should be held in reset. The CC SP690T/S/R, SP802T/S/R, SP804T/S/R and V m P RESET pin 7* CC R1 SP805T/S/R devices assert reset during PFI power-up and prevent code execution errors NMI PFO SSPP689002TT//SS//RR during power-down or brownout conditions. I/O LINE WDI SSPP880045TT//SS//RR R2 GND VOUT VBATTERY RESET is guaranteed to be a logic LOW for 0V < V < V , provided that V is greater CC RST BATTERY BUS GND than 1V. Without a backup battery, RESET is guaranteed valid for V > 1V. Once V CC CC exceeds the reset threshold, an internal timer CMOS VCC 3.6V keeps RESET low for the reset timeout period. RAM Lithium Battery After this period, RESET goes HIGH, as seen in 0.1m F Figure 19. GND If a brownout condition occurs and V dips CC *RESET for the SP690T/S/R and the SP802T/S/R below the reset threshold, RESET goes LOW. RESET for the SP804T/S/R and the SP805T/S/R Each time RESET is triggered, it stays low for Figure 20. Typical Operating Circuit the reset timeout period. Any time V goes CC below the reset threshold, the internal timer restarts. SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 12

The watchdog timer can also initiate a reset. Watchdog Input Refer to the Watchdog Input section. The watchdog circuit monitors the m P's activity. The SP804T/S/R and SP805T/S/R active-HIGH If the m P does not toggle the watchdog input RESET output is open drain and the inverse (WDI) within 1.6sec, a reset pulse is triggered. of the SP690T/S/R and SP802T/S/R RESET The internal 1.6sec timer is cleared by either a outputs. reset pulse or by a transition (LOW-to-HIGH or HIGH-to-LOW) at WDI. If WDI is tied HIGH RESET is also triggered by a watchdog timeout. or LOW, a RESET pulse is triggered every If WDI remains either high or low for a period 1.8sec (t plus t ). WD RS that exceeds the watchdog timeout period (1.6 sec), RESET pulses low for 200mS. As long as As long as reset is asserted, the timer remains RESET is asserted, the watchdog timer remains cleared and does not count. As soon as reset is cleared. When RESET comes high, the watch- de-asserted, the timer starts counting. Unlike dog resumes timing and must be serviced within the 5V SP690A series, the watchdog function 1.6sec. If WDI is tied high or low, a RESET cannot be disabled. pulse is triggered every 1.8sec (t plus t ). WD RS Power-Fail Comparator Reset Threshold The power-fail comparator can be used as an The SP690T and SP805T devices are designed under-voltage detector to signal the failing of a for 3.3V systems with a – 5% power-supply power supply (it is completely separate from the tolerance and a 10% system tolerance. Except rest of the circuitry and does not need to be for watchdog faults, reset will not assert as long dedicated to this function). The PFI input is as the power supply remains above 3.15V (3.3V compared to an internal 1.25V. If PFI is less than - 5%). Reset is guaranteed to assert before the V , PFO goes low. PFT power supply falls below 3.0V. The power-fail comparator turns off and PFO The SP690S and SP805S devices are designed goes LOW when V falls below V on CC SW for 3.3V – 10% power supplies. Except for power-down. The power-fail comparator turns watchdog faults, they are guaranteed not to on as V crosses V on power-up. If the CC SW assert reset as long as the supply remains above comparator is not used, connect PFI to ground 3.0V (3.3V - 10%). Reset is guaranteed to and leave PFO unconnected. assert before the power supply fails below 2.85V (V - 14%). Backup-Battery Switchover CC The SP690R and SP805R devices are optimized In the event of a brownout or power failure, it for monitoring 3.0V – 10% power supplies. Reset may be necessary to preserve the contents of will not occur until V falls below 2.7V (3.0V RAM. With a backup battery installed at CC - 10%), but is guaranteed to occur before the V , the devices automatically switch BATTERY supply falls below 2.55V (3.0V - 15%). RAM to backup power when V fails. CC The SP802T/S/R and SP804T/S/R devices are This family of m P supervisors (designed for respectively similar to the SP690T/S/R and 3.3V and 3V systems) doesn't always connect SP805T/S/R devices with tightened reset V to V when V is greater BATTERY OUT BATTERY and power-fail threshold tolerances. than V . V connects to V (through CC BATTERY OUT a 15W switch) when V is below V and CC SW V is greater than V . BATTERY CC SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 13

A) 3.0V or 3.3V B) +5V 3.0V or 3.3V 1N4148 VCC 1N4148 VCC VOUT CONNECT TO VOUT CONNECT TO VBATTERY STATIC RAM VBATTERY STATIC RAM 0.1F pin 7* CONNECT 0.1F pin 7* CONNECT TO m P TO m P GND GND *RESET for the SP690T/S/R and the SP802T/S/R RESET for the SP804T/S/R and the SP805T/S/R Figure 21. Using a High Capacity Capacitor as a Backup Power Source Switchover at V (2.40V) ensures that battery- Replacing the Backup Battery SW backup mode is entered before V gets too OUT close to the 2.0V minimum required to reliably If V is decoupled with a 0.1m F capacitor BATTERY retain data in CMOS RAM. Switchover at higher to ground, the backup battery can be removed V voltages would decrease backup-battery while V remains valid without danger of CC CC life. When V recovers, switchover is deferred triggering RESET/RESET. As long as V CC CC until V rises above the reset threshold, V , stays above V , battery-backup mode cannot CC RST SW to ensure a stable supply. V is connected to be entered. OUT V through a 1.5W PMOS power switch. CC Adding Hysteresis to the Power-Fail Using a High Capacity Capacitor as a Comparator Backup Power Source The power-fail comparator has a typical input Figure 21 shows two ways to use a High Value hysteresis of 10mV. This is sufficient for most Capacitor as a backup power source. The High applications where a power-supply line is being Value Capacitor may be connected through a monitored through an external voltage divider diode to the 3V input as in Figure 21A or, if a (refer to the Monitoring an Additional Power 5V supply is also available, the High Value Supply section). Capacitor may be charged up to the 5V supply as in Figure 21B allowing a longer backup If additional noise margin is desired, connect a period. Since V can exceed V while V resistor between PFO and PFI as shown in BATTERY CC CC is above the reset threshold, there are no Figure 22A. Select the ratio of R1 and R2 such special precautions when using these m P that PFI sees 1.25V when V falls to its trip IN supervisors with a High Value Capacitor. point (V ). R3 adds the hysteresis and will TRIP typically be more than 10 times the value of R1 Operation Without a Backup Power or R2. The hysteresis window extends both Source above (V ) and below (V ) the original trip H L point (V ). TRIP These m P supervisors were designed for battery-backed applications. If a backup power source is not used, connect both VBATTERY and V to V . Since there is no need to OUT CC switch over to any backup power source, V OUT does not need to be switched. A direct connec- tion to V eliminates any voltage drops across CC the switch which may push V below V . OUT CC SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 14

VIN VIN A.) B.) R1 R1 PFI VCC PFI VCC + SP690T/S/R + SP690T/S/R R2 *C1 R3 SSPP880024TT//SS//RR R2 *C1 R3 SSPP880024TT//SS//RR SP805T/S/R SP805T/S/R PFO PFO GND GND TOmP TOmP *OPTIONAL PFO PFO 0V0V VL VTRIP VH VIN 0V0V VTRIP VH VIN VTRIP = VPFT (R 1R +2 R2 ) VTRIP = VPFT (R 1R +2 R2 ) VVHL == (RV1 PF[TV +P FVT( P F RH)11 ( +R R1 )12 ( + R 1 1 R 1 3+ ) R 12 - + VR C R31C3]) VWLH =E RR1E[ ( VV PPFFTT + = V P1F.H)2(5 V R11 + R 12 + R13)- (V C RC 3- VD) ] WHERE VPFT = 1.25V VPFH = 10mV VPFH = 10mV VD = DIOD FORWARD VOLTAGE DROP Figure 22A. Adding Additional Hysteresis to the Power-Fail Comparator. Figure 22B. Shifting the Additional Hysteresis above V PFT Connecting an ordinary signal diode in series The current through R1 and R2 should be at least with R3, as in Figure 22B, causes the lower trip 1m A to ensure that the 25nA (max over extended point (V ) to coincide with the trip point without temperature range) PFI input current does not L hysteresis (V ), so the entire hysteresis shift the trip point. R3 should be larger than window occursT RaIbPove V . This method pro- 10kW so it does not load down the PFO pin. TRIP vides additional noise margin without compro- Capacitor C1 adds additional noise rejection. mising the accuracy of the power-fail threshold when the monitored voltage is falling. It is useful for accurately detecting when a voltage falls past a threshold. VIN 3.0V OR 3.3V R1 VCC VCC SSPP689002TT//SS//RR R1 SSPP689002TT//SS//RR PFI PFO PFI PFO R2 SSPP880045TT//SS//RR R2 SSPP880045TT//SS//RR GND GND V- VCC VCC PFO PFO VL VTRIP 0V V- VTRIP VH VIN VTRIP = R2[(V PFT + VPFH)( R 11 + R 12)- VRC1C] VTRIP = VPFT (R 1R +2 R2 ) VL = R2[V PFT( R1 1 + R 12)- VRC3C ] VH =(V PFT + VPFH)( R 1 R +2 R2) WHERE VPFT = 1.25V VPFH = 10mV NOTE: VTRIP IS NEGATIVE Figure 23. Using the Power-Fail Comparator to Monitor an Additional Power Supply SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 15

Buffered RESET connects to System Components 1nF Capacitor V TO GND VCC VCC OUT m P Above Line RESET RESET RESET Generated 4.7KW NO RESET Generated GND GND Figure 24. Interfacing to Microprocessors with Figure 25. Maximum Transient Duration without Bidirectional RESET I/O Causing a Reset Pulse vs. Reset Comparator Overdrive Monitoring an Additional Power Supply These m P supervisors can monitor either positive Figure 25 shows maximum transient duration or negative supplies using a resistor voltage vs. reset-comparator overdrive, for which reset divider to PFI. PFO can be used to generate an pulses are not generated. The data was generated interrupt to the m P, as seen in Figure 23. using negative-going V pulses, starting at CC 3.3V and ending below the reset threshold by Interfacing to m Ps with Bidirectional the magnitude indicated (reset comparator Reset Pins overdrive). The graph shows the maximum pulse width a negative-going V transient may CC Any m Ps with bidirectional reset pins, such as typically have without causing a reset pulse to the Motorola 68HC11 series, can interface with be issued. As the amplitude of the transient the SP690_ and the SP802_ RESET outputs. increases (i.e. goes farther below the reset For example, if the RESET output is driven threshold), the maximum allowable pulse width HIGH and the m P wants to pull it LOW, decreases. Typically, a V transient that goes CC indeterminate logic levels may result. To correct 100mV below the reset threshold and lasts for this, connect a 4.7kW resistor between the 40m s or less will not cause a reset pulse to be RESET output and the m P reset I/O, as in issued. A 100nF bypass capacitor mounted close Figure 24. Buffer the RESET output to other to the V pin provides additional transient CC system components. immunity. Negative-Going V Transients CC While issuing resets to the m P during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short- duration negative-going V transients CC (glitches). It is usually undesirable to reset the m P when V experiences only small glitches. CC SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 16

PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). A2 C Ø L B1 e = 0.100 BSC B e = 0.300 BSC A (2.540 BSC) (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum 8–PIN 14–PIN 16–PIN 18–PIN 20–PIN 22–PIN (mm) A2 0.115/0.195 0.115/0.195 0.115/0.195 0.115/0.195 0.115/0.195 0.115/0.195 (2.921/4.953) (2.921/4.953) (2.921/4.953) (2.921/4.953) (2.921/4.953) (2.921/4.953) B 0.014/0.022 0.014/0.022 0.014/0.022 0.014/0.022 0.014/0.022 0.014/0.022 (0.356/0.559) (0.356/0.559) (0.356/0.559) (0.356/0.559) (0.356/0.559) (0.356/0.559) B1 0.045/0.070 0.045/0.070 0.045/0.070 0.045/0.070 0.045/0.070 0.045/0.070 (1.143/1.778) (1.143/1.778) (1.143/1.778) (1.143/1.778) (1.143/1.778) (1.143/1.778) C 0.008/0.014 0.008/0.014 0.008/0.014 0.008/0.014 0.008/0.014 0.008/0.014 (0.203/0.356) (0.203/0.356) (0.203/0.356) (0.203/0.356) (0.203/0.356) (0.203/0.356) D 0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685)(19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) E 0.300/0.325 0.300/0.325 0.300/0.325 0.300/0.325 0.300/0.325 0.300/0.325 (7.620/8.255) (7.620/8.255) (7.620/8.255) (7.620/8.255) (7.620/8.255) (7.620/8.255) E1 0.240/0.280 0.240/0.280 0.240/0.280 0.240/0.280 0.240/0.280 0.240/0.280 (6.096/7.112) (6.096/7.112) (6.096/7.112) (6.096/7.112) (6.096/7.112) (6.096/7.112) L 0.115/0.150 0.115/0.150 0.115/0.150 0.115/0.150 0.115/0.150 0.115/0.150 (2.921/3.810) (2.921/3.810) (2.921/3.810) (2.921/3.810) (2.921/3.810) (2.921/3.810) Ø 0°/ 15° 0°/ 15° 0°/ 15° 0°/ 15° 0°/ 15° 0°/ 15° (0°/15°) (0°/15°) (0°/15°) (0°/15°) (0°/15°) (0°/15°) SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 17

PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) E H h x 45° D A Ø A1 e B L DIMENSIONS (Inches) Minimum/Maximum 8–PIN 14–PIN 16–PIN (mm) A 0.053/0.069 0.053/0.069 0.053/0.069 (1.346/1.748) (1.346/1.748) (1.346/1.748) A1 0.004/0.010 0.004/0.010 0.004/0.010 (0.102/0.249 (0.102/0.249) (0.102/0.249) B 0.014/0.019 0.013/0.020 0.013/0.020 (0.35/0.49) (0.330/0.508) (0.330/0.508) D 0.189/0.197 0.337/0.344 0.386/0.394 (4.80/5.00) (8.552/8.748) (9.802/10.000) E 0.150/0.157 0.150/0.157 0.150/0.157 (3.802/3.988) (3.802/3.988) (3.802/3.988) e 0.050 BSC 0.050 BSC 0.050 BSC (1.270 BSC) (1.270 BSC) (1.270 BSC) H 0.228/0.244 0.228/0.244 0.228/0.244 (5.801/6.198) (5.801/6.198) (5.801/6.198) h 0.010/0.020 0.010/0.020 0.010/0.020 (0.254/0.498) (0.254/0.498) (0.254/0.498) L 0.016/0.050 0.016/0.050 0.016/0.050 (0.406/1.270) (0.406/1.270) (0.406/1.270) Ø 0°/8° 0°/8° 0°/8° (0°/8°) (0°/8°) (0°/8°) SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 18

ORDERING INFORMATION Model Temperature Range Package Types SP690TCN......................................................0(cid:176) C to +70(cid:176) C......................................................8-Pin NSOIC SP690TCP......................................................0(cid:176) C to +70(cid:176) C.........................................................8-Pin PDIP SP690TEN.....................................................-40(cid:176) C to +85(cid:176) C....................................................8-Pin NSOIC SP690TEP.....................................................-40(cid:176) C to +85(cid:176) C.......................................................8-Pin PDIP SP690SCN......................................................0(cid:176) C to +70(cid:176) C......................................................8-Pin NSOIC SP690SCP......................................................0(cid:176) C to +70(cid:176) C.........................................................8-Pin PDIP SP690SEN.....................................................-40(cid:176) C to +85(cid:176) C....................................................8-Pin NSOIC SP690SEP.....................................................-40(cid:176) C to +85(cid:176) C.......................................................8-Pin PDIP SP690RCN......................................................0(cid:176) C to +70(cid:176) C......................................................8-Pin NSOIC SP690RCP......................................................0(cid:176) C to +70(cid:176) C.........................................................8-Pin PDIP SP690REN.....................................................-40(cid:176) C to +85(cid:176) C....................................................8-Pin NSOIC SP690REP.....................................................-40(cid:176) C to +85(cid:176) C.......................................................8-Pin PDIP SP802TCN........................................................0(cid:176) C to +70(cid:176) C....................................................8-Pin NSOIC SP802TCP........................................................0(cid:176) C to +70(cid:176) C.......................................................8-Pin PDIP SP802TEN.......................................................-40(cid:176) C to +85(cid:176) C..................................................8-Pin NSOIC SP802TEP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP SP802SCN........................................................0(cid:176) C to +70(cid:176) C....................................................8-Pin NSOIC SP802SCP........................................................0(cid:176) C to +70(cid:176) C.......................................................8-Pin PDIP SP802SEN.......................................................-40(cid:176) C to +85......................................................8-Pin NSOIC SP802SEP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP SP802RCN........................................................0(cid:176) C to 0(cid:176) C........................................................8-Pin NSOIC SP802RCP........................................................0(cid:176) C to+70(cid:176) C...................................................... 8-Pin PDIP SP802REN.......................................................-40(cid:176) C to +85(cid:176) C..................................................8-Pin NSOIC SP802REP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP SP804TCN.......................................................0(cid:176) C to +70(cid:176) C.....................................................8-Pin NSOIC SP804TCP.......................................................0(cid:176) C to +70(cid:176) C........................................................8-Pin PDIP SP804TEN......................................................-40(cid:176) C to +85(cid:176) C...................................................8-Pin NSOIC SP804TEP......................................................-40(cid:176) C to +85(cid:176) C......................................................8-Pin PDIP SP804SCN.......................................................0(cid:176) C to +70(cid:176) C.....................................................8-Pin NSOIC SP804SCP.......................................................0(cid:176) C to +70(cid:176) C........................................................8-Pin PDIP SP804SEN......................................................-40(cid:176) C to +85(cid:176) C...................................................8-Pin NSOIC SP804SEP......................................................-40(cid:176) C to +85(cid:176) C......................................................8-Pin PDIP SP804RCN.......................................................0(cid:176) C to +70(cid:176) C.....................................................8-Pin NSOIC SP804RCP.......................................................0(cid:176) C to +70(cid:176) C........................................................8-Pin PDIP SP804REN......................................................-40(cid:176) C to +85(cid:176) C...................................................8-Pin NSOIC SP804REP......................................................-40(cid:176) C to +85(cid:176) C......................................................8-Pin PDIP SP805TCN........................................................0(cid:176) C to +70(cid:176) C....................................................8-Pin NSOIC SP805TCP........................................................0(cid:176) C to +70(cid:176) C.......................................................8-Pin PDIP SP805TEN.......................................................-40(cid:176) C to +8C.................................................. ..8-Pin NSOIC SP805TEP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP SP805SCN........................................................0(cid:176) C to+70(cid:176) C.....................................................8-Pin NSOIC SP805SCP........................................................0(cid:176) C to +70(cid:176) C.......................................................8-Pin PDIP SP805SEN.......................................................-40(cid:176) C to +85(cid:176) C..................................................8-Pin NSOIC SP805SEP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP SP805RCN........................................................0(cid:176) C to +70(cid:176) C....................................................8-Pin NSOIC SP805RCP........................................................0(cid:176) C to +70(cid:176) C.......................................................8-Pin PDIP SP805REN.......................................................-40(cid:176) C to +85(cid:176) C..................................................8-Pin NSOIC SP805REP.......................................................-40(cid:176) C to +85(cid:176) C.....................................................8-Pin PDIP Please consult the factory for pricing and availability on a Tape-On-Reel option. SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 19

Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation 20