SP690A/692A/802L/ ® 802M/805L/805M Low Power Microprocessor Supervisory with Battery Switch-Over FEATURES ■ Precision Voltage Monitor: VOUT 1 8 PIN NSOIC 8 VBATT SP690A/SP802L/SP805L at 4.65V VCC 2 7 RESET (RESET)* SP692A/SP802M/SP805M at 4.40V GND 3 6 WDI ■ Reset Time Delay - 200ms PFI 4 5 PFO ■ Watchdog Timer - 1.6 sec timeout *SP805 only ■ Minimum component count Now Available in Lead Free Packaging ■ 60(cid:181)A Maximum Operating Supply Current ■ 0.6(cid:181)A Maximum Battery Backup Current ■ 0.1(cid:181)A Maximum Battery Standby Current ■ Pin Compatible Upgrades to ■ Power Switching MAX690A/692A/802L/802M/805L 250mA Output in V Mode (0.6Ω) CC APPLICATIONS 25mA Output in Battery Mode (5Ω) ■ Voltage Monitor for Power Fail or ■ Critical (cid:181)P Power Monitoring ■ Intellegent Instruments Low Battery Warning ■ Available in 8 pin SO and DIP packages ■ Computers ■ RESET asserted down to V = 1V ■ Controllers CC DESCRIPTION The SP690A/692A/802L/802M/805L/805M are a family of microprocessor ((cid:181)P) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power- supply and battery-control functions in (cid:181)P and digital systems. The series will significantly improve system reliability and operational efficiency when compared to discrete solutions. The features of the SP690A/692A/802L/802M/805L/805M include a watchdog timer, a (cid:181)P reset and backup-battery switchover, and power-failure warning, a complete (cid:181)P monitoring and watchdog solution. The series is ideal for applications in automotive systems, computers, controllers, and intelligent instruments. All designs where it is critical to monitor the power supply to the (cid:181)P and it’s related digital components will find the series to be an ideal solution. RESET RESET PARTNUMBER RESETActive PFIAccuracy TTTTThhhhhrrrrreeeeessssshhhhhooooolllllddddd AAAAAccccccccccuuuuurrrrraaaaacccccyyyyy SP690A 4.65V 125mV LOW 4% SP692A 4.40V 125mV LOW 4% SP802L 4.65V 75mV LOW 2% SP802M 4.40V 75mV LOW 2% SP805L 4.65V 125mV HIGH 4% SP805M 4.40V 125mV HIGH 4% Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 1

ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica- tions below is not implied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V ........................................................-0.3V to 6.0V CC V .....................................................-0.3V to 6.0V BATT All Other Inputs (NOTE 1)..................-0.3V to (V to 0.3V) CC Input Current: V .........................................................250mA CC V ........................................................50mA BATT GND........................................................20mA Output Current: V .....Short-Circuit Protected for up to 10sec OUT All Other Inputs.................................20mA Rate of Rise, V ,V ..................100V/(cid:181)s CC BATT Continuous Power Dissipation.......500mW Storage Temperature.......-65(cid:176)C to +160(cid:176)C Lead Temperature(soldering,10sec).................+300(cid:176)C ESD Rating.............................................................4KV ELECTRICAL CHARACTERISTICS V =4.75v to 5.50V for SP690A/SP802L/SP805L, V =4.50V to 5.50V for SP692A/SP802M/SP805M, V =2.80V, T=T to T , typical specified at 25OC, cc CC BATT A MIN MAX unless otherwise noted. PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS OperatingVoltageRange, 0 5.5 Volts V orV ,Note2 CC BATT SupplyCurrent,I , 35 60 µA excludingI SUPPLY OUT I inBatteryBackupMode, SUPPLY 0.001 0.6 µA V =0V,V =2.8V CC BATT V StandbyCurrent,NOTE3 -0.1 0.02 µA V >V +0.2V BATT CC BATT V Output V -0.1 V -0.03 I =50mA OUT CC CC Volts OUT V -0.15 I =250mA CC OUT V inBattery-BackupMode V -0.15 V -0.04 I =5mA OUT BATT BATT Volts OUT V <V -0.2V V -0.20 I =25mA CC BATT BATT OUT BatterySwitchThreshold, 20 Power-up mV V toV -20 Power-down CC BATT BatterySwitchoverHysteresis 40 mV PeaktoPeak ResetThreshold 4.50 4.65 4.75 SP690A,SP802L,SP805L 4.25 4.40 4.50 SP692A,SP802M,SP805M Volts 4.55 4.70 SP802L,T =+25°C,V falling A CC 4.30 4.45 SP802M,T =+25°C,V falling A CC Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 2

ELECTRICAL CHARACTERISTICS V =4.75v to 5.50V for SP690A/SP802L/SP805L, V =4.50V to 5.50V for SP692A/SP802M/SP805M, V =2.80V, T=T to T , typical specified at 25OC, cc CC BATT A MIN MAX unless otherwise noted. PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS ResetThresholdHysteresis 40 mV PeaktoPeak ResetPulseWidth,t 140 200 280 ms RS RESETOutputVoltage, V -1.5 I =800µA CC SOURCE NOTE5 0.1 0.4 Volts I =3.2mA SINK 0.004 0.3 I =50µA,V =1.0 SINK CC RESETOutputVoltage, 0.8 I =4µA,V =1.0V, SOURCE CC NOTE6 V -1.5 Volts I =800µA CC SOURCE 0.1 0.4 I =3.2mA SINK WatchdogTimeout,t 1.00 1.60 2.25 sec WD WDIPulseWidth,t NOTE 7 50 ns V =0.4V,V =(0.8)(V ) WP IL IH CC WDIInputThreshold, 0.8 Logiclow Volts V =5V,NOTE4 3.5 Logichigh CC WDIInputCurrent 50 150 WDI=V µA CC -150 -50 WDI=0V PFIInputThreshold 1.200 1.250 1.300 SP690A/692A,SP805L/M Volts 1.225 1.250 1.275 SP802L/M PFIInputCurrent -25 0.01 25 nA PFOOutputVoltage V -1.5 I =800µA CC Volts SOURCE 0.1 0.4 I =3.2mA SINK NOTE 1: The input voltage limits on PFI (pin 4) and WDI (pin 6) may be exceeded if the current into these pins is limited to less than 10 mA. NOTE 2: Either V or V can go to 0V if the other is greater than 2.0V. CC BATT NOTE 3: "-" equals the battery-charging current, "+" equals the battery-discharging current. NOTE 4: WDI is guaranteed to be in an intermediate, non-logic level state if WDI is floating and V CC is in the operating voltage range. WDI is internally biased to 35% of V with an input impedance of CC 50KΩ. NOTE 5: SP690A, SP692A, SP802L, and SP802M only. NOTE 6: SP805L and SP805M only. NOTE 7: WDI Minimum Rise/Fall time is 2(cid:181)s. Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 3

VBATT BATTECRIYR-CSWUIITTRCYHOVER VOUT VOUT 1 8 VBATT VCC 2 7 RESET (RESET)* VCC RESET RESET GENERATOR (RESET)* GND 3 6 WDI PFI 4 5 PFO 1.25V *( ) SP805 only 3.5V WATCHDOG WDI Figure 10. Pinout TIMER PIN ASSIGNMENTS Pin 1 —V — Output Supply Voltage. V 0.8V OUT OUT connects to V when V is greater than CC CC PFI V and V is above the reset thresh- PFO BATT CC old. When V falls below V and CC BATT V is below the reset threshold, V 1.25V CC OUT *( ) SP805 only connects to V . Connect a 0.1(cid:181)F BATT capacitor from V to GND. OUT Pin 2 — V — +5V Supply Input CC Figure 11. Internal Block Diagram Pin3 — GND — Ground reference for all signals Pin 7 for SP805 only — RESET (Active High)– Pin 4 — PFI — Power-Fail Input. This is the Reset Output is the inverse of RESET; noninverting input to the power-fail com- when RESET is asserted, the RESET parator. When PFI is less than 1.25V, output voltage = V or V , PFO goes low. Connect PFI to GND or whichever is higher. CC BATT V when not used. OUT Pin 8 — V — Backup-Battery Input. When Pin 5 — PFO — Power-Fail Output. V B fAaTllTs below the reset threshold, V CC BATT will be switched to V if V is Pin 6 — WDI — Watchdog Input. WDI is a OUT BATT 20mV greater than V . When V rises three level input. If WDI remains high or CC CC 20mV above V , V will be low for 1.6sec, the internal watchdog timer BATT OUT reconnected to V . The 40mV triggers a reset. If WDI is left floating or CC hysteresis prevents repeated switching if connected to a high-impedance tri-state V falls slowly. buffer, the watchdog feature is disabled. CC The internal watchdog timer clears when- ever reset is asserted. Pin 7 for SP690A/692A/802 only — RESET (Active Low)– Reset Output. RESET Out- put goes low whenever V falls below CC the reset threshold or whenever WDI remains high or low longer than 1.6 seconds. RESET remains low for 200ms after V crosses the reset threshold CC voltage on power-up or after being trig- gered by WDI. Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 4

TYPICAL PERFORMANCE CHARACTERISTICS V Supply Current vs. PFI Threshold TempCCerature (Normal Mode) Battery Supply Current vs. vs. Temperature Temperature (Backup Mode) 1.256 V Current (A)(cid:181)CC 54433321739517 VBVATCTC==25.V8V V Current (A)(cid:181)BATT22110.....94949 VBVATCTC==20.V8V PFI Threshold (V)1111....222255544208 NO LOVVABCACDT=T 5=OV0N PFO 0.4 23 19 -0.1 1.246 -60 -30 0 30 60 90 120 150 -60-40-20 0 20 40 60 80100120140 -60 -30 0 30 60 90 120 150 Temperature Deg. C Temperature Deg. C Temperature Deg. C VBATT to VOUT ON VCC to VOUT On Reset Threshold Resistance vs. Temperature Resistance vs. Temperature vs. Temperature 15 0.9 4.70 esistance (ohms)105 VCC=0V VBAVTTB=VA2TBTAV=TT4=.25.V8V Resistance (ohms)00000.....87654 VVBCACT=T=50VV Reset Threshold (V) 44444444........6666666698765432 SP690A PoVwBAeTrT =D0oVwn R 4.61 0 0.3 4.60 -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150 Temperature Deg. C Temperature Deg. C Temperature Deg. C Reset Output Resistance Reset Delay vs. Temperature vs. Temperature Battery Current vs. V Voltage 600 212 CC esistance (ohms) 543200000000 VSCCo=u5cVin,Vg BCATuT=rr2e.n8tV Reset Delay (mS) 222210000864 VCC=V0BVA TtTo= 25.V8 VStep, urrent(A) Log Scale(cid:181) IIIIIIIIEEEEEEEE+++-----21012345 VBATT=2.8V R 1000 VCCS=i0nVk, VCBuArTrTe=n2t.8V 220020 V CBATT IIIEEE---678 -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150 .0000 5.000 V (0.5V/div) Temperature Deg. C Temperature Deg. C CC (25oC, unless otherwise noted) Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 5

1000 1000 V =4.5V V =4.5V CC BATT V =0V V =0V BATT CC Slope=0.6Ω Slope=5Ω mV) 100 mV) 100 Voltage Drop( 10 Voltage Drop( 10 1 1 1 10 100 1000 1 10 100 IOUT (mA) IOUT (mA) Figure 1. V to V Vs. Output Current Figure 2. V to V Vs. Output Current CC OUT BATT OUT V CC V = 0V BATT T = +25 C A VCC 2V VBATT = 0V div TA = 25o C V 0V CC RESET 2KΩ RESET RESET 0V 330pF GND 1sec/div Figure 3A. SP690A RESET Output Voltage vs. Figure 3B. Circuit for the SP690A/802L RESET Supply Voltage Output Voltage vs. Supply Voltage V CC VCC V CC 2V div 0V 5V RESET RESET V 0V BATT 330pF 10KΩ GND 1sec/div Figure 4A. SP805L RESET Output Voltage vs. Figure 4B. Circuit for the SP805 RESET Output Supply Voltage Voltage vs. Supply Voltage Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 6

V CC VCC +5V T = +25 C A +4V V CC +5V RESET 10KΩ RESET 0V 30pF GND 2(cid:181)s/div Figure 5A. SP690A RESET Response Time Figure 5B. Circuit for the SP690A/802L RESET Response Time V CC +5V +4V VCC VCC +4V RESET RESET V 0V BATT 330pF 10KΩ GND 2(cid:181)s/div Figure 6A. SP805L RESET Response Time Figure 6B. Circuit for the SP805 RESET Response Time +5V VCC = 5V VBATT = 0V +1.3V PFI V = +5V CC +1.2V T = +25 C A 1KΩ PFO 5V PFI PFO 0V 30pF +1.25V 500ns/div Figure 7A. Power-Fail Comparator Response Time (FALL) Figure 7B. Circuit for the Power-Fail Comparator Response Time (FALL) Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 7

VCC = 5V PFI VBATT = 0V +5V +1.3V +1.2V VCC = +5V T = +25 C A PFI PFO 3V PFO +1.25V 30pF 1KΩ 0V 2(cid:181)s/div Figure 8A. Power-Fail Comparator Response Time (RISE) Figure 8B. Circuit for the Power-Fail Comparator Response Time (RISE) +5V V CC 0V +5V RESET* tRS 0V +5V RESET** 3.0V 0V +5V V OUT 3.0V 0V +5V PFO 0V V = PFI = 3.0V *SP690A/692A/802L/802M BATT **SP805L/805M Figure 9. Timing Diagram Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 8

FEATURES THEORY OF OPERATION The SP690A/692A/802L/802M/805L/805M The SP690A/692A/802L/802M/805L/805M provide four key functions: microprocessor ((cid:181)P) supervisory circuits 1. A battery backup switching for CMOS RAM, monitor the power supplied to digital circuits CMOS microprocessors, or other logic. such as microprocessors, microcontrollers, or 2. A reset output during power-up, power-down memory. The series is an ideal solution for and brownout conditions. portable, battery-powered equipment that 3. A reset pulse if the optional watchdog timer requires power supply monitoring. Implementing has not been toggled within a specified time. this series will reduce the number of 4. A 1.25V threshold detector for power-fail components and overall complexity. The warning, low battery detection, or to monitor a watchdog functions of this product family will power supply other than +5V. continuously oversee the operational status of a system. The operational features and benefits of The parts differ in their reset-voltage threshold the SP690A/692A/802L/802M/805L/805M are levels and reset outputs. The SP690A/802L/ described in more detail below. 805L generate a reset when the supply voltage drops below 4.65V. The SP692A/802M/805M Reset Output generate a reset below 4.40V. The microprocessor's ((cid:181)P's) reset input starts The SP690A/692A/802L/802M/805L/805M the (cid:181)P in a known state. When the (cid:181)P is in an are ideally suited for applications in automotive unknown state, it should be held in reset. The systems, intelligent instruments, and battery- SP690A/SP692A/SP802 assert reset during powered computers and controllers. All designs power-up and prevent code execution errors into an environment where it is critical to during power-down or brownout conditions. monitor the power supply to the (cid:181)P and it’s related digital components will find the On power-up, once V reaches 1V, RESET is CC SSP690A/692A/802L/802M/805L/805M ideal. guaranteed to be a logic low. As V rises, CC RESET remains low. When V exceeds the CC reset threshold, RESET will remain low for 200ms, Figure 9. If a brownout condition occurs and V dips below the reset threshold, Regulated +5V CC RESET is triggered. Each time RESET is triggered, it stays low for the reset pulse width Unregulated VCC 0.1(cid:181)F DC interval. If a brownout condition interrupts a previously initiated reset pulse, the reset pulse (cid:181)P RESET RESET VCC R1 continues for another 200ms. On power-down, PFI once V goes below the threshold, RESET is NMI PFO CC guaranteed to be logic low until V drops I/O LINE WDI R2 below 1V. CC GND VOUT VBATT RESET is also triggered by a watchdog timeout. GND BUS If WDI remains either high or low for a period that exceeds the watchdog timeout period (1.6 3.6V Lithium sec), RESET pulses low for 200mS. As long as Battery CMOS VCC RESET is asserted, the watchdog timer remains RAM clear. When RESET comes high, the watchdog GND resumes timing and must be serviced within 1.6sec. If WDI is tied high or low, a RESET pulse is triggered every 1.8sec (t plus t ). WD RS Figure 12. Typical Operating Circuit Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 9

The SP805L/M active-high RESET output is Power-Fail Comparator the inverse of the SP690A/SP692A/SP802 RE- SET output, and is valid with V down to 1V. The Power-Fail Comparator can be used as an CC Some (cid:181)P's, such as Intel's 80C51, require an under-voltage detector to signal the failing of a active-high reset pulse. power supply (it is completely separate from the rest of the circuitry and does not need to be Watchdog Input dedicated to this function). The PFI input is compared to an internal 1.25V reference. If PFI The watchdog circuit monitors the (cid:181)P's activity. is less than 1.25V, PFO goes low. The external If the (cid:181)P does not toggle the watchdog input voltage divider drives PFI to sense the (WDI) within 1.6sec, a reset pulse is triggered. unregulated DC input to the +5V regulator. The The internal 1.6sec timer is cleared by either a voltage-divider ratio can be chosen such that the reset pulse or by floating the WDI input. As long voltage at PFI falls below 1.25V just before the as RESET is asserted or the WDI input is +5V regulator drops out. PFO then triggers an floating, the timer remains cleared and does not interrupt which signals the (cid:181)P to prepare for count. As soon as RESET is released and WDI power-down. is driven high or low, the timer starts counting. It can detect pulses as short as 50ns. When V connects to V , the power-fail BATT OUT comparator is turned off and PFO is forced low to conserve backup-battery power. Backup-Battery Switchover In the event of a brownout or power failure, it V V BATT CC may be necessary to preserve the contents of RAM. With a backup battery installed at V , BATT the RAM is assured to have power if V fails. CC D1 D2 As long as V exceeds the reset threshold, SW1 SW2 CC V connects to V through a 0.6Ω PMOS OUT CC power switch. Once V falls below the reset CC threshold, V or V , whichever is higher, D3 CC BATT VOUT switches to V . V connects to V OUT BATT OUT through a 5Ω switch only when V is below the CC reset threshold and V is greater than V . BATT CC GND When V exceeds the reset threshold, it is CC connected to V , regardless of the voltage CONDITION SW1 SW2 OUT applied to V Figure 13. During this time, BATT the diode (D1) between V and V will VCC>ResetThreshold Open Closed conduct current from V B tAoT VT if VOUT is BATT OUT BATT more than .6V above V . V <ResetThresholdand OUT CC Open Closed V >V CC BATT When V connects to V , backup mode is V <ResetThresholdand BATT OUT CC Closed Open activated and the internal circuitry will be pow- V <V CC BATT ered from the battery Figure 14. When V is CC Reset Threshold = 4.65V in SP690A/802L/805L just below V , in the backup mode the BATT Reset Threshold = 4.40V in SP692A/802M/805M current drawn from V will be typically BATT 30(cid:181)A. When V drops to more than 1V below Figure 13. BACKUP-BATTERY Switchover Block Diagram CC V , the internal switchover comparator shuts BATT off and the supply current falls to less than 0.6(cid:181)A. Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 10

SIGNAL STATUS +5V V DisconnectedfromV CC OUT ConnectedtoV through VCC V BATT OUT aninternal8ΩPMOSswitch V CONNECT TO OUT ConnectedtoV . Current VBATT STATIC RAM OUT drawnfromthebatteryis VBATT lessthan0.6µA,aslongas 0.1F RESET CONNECT (RESET)* TO (cid:181)P V <V -1V. CC BATT GND *( ) SP805L only Power-failcomparatoris PFI disabled. PFO Logiclow Figure 16. Backup Power Source Using High Capacity Capacitor with SP690A/802L/805L and a +5V –5% Supply RESET Logiclow RESET Logichigh(SP805only) If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and WDI Watchdogtimerisdisabled VCC from VBATT until the voltage at VBATT is Figure 14. Input and Output Status in Battery-Backup Mode. less than 0.5V above VCC. To enter the Battery-Backup mode, V must be less than the CC Reset threshold and less than V . BATT Leakage current through the capacitor charging diode and the SP690A/SP802L/SP805L internal Using a High Capacity Capacitor power diode eventually discharges the capacitor as a Backup Power Source to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at VBATT has the same operating voltage range as VCC, and the battery-switchover threshold volt- VCC, the capacitor on VBATT discharges through ages are typically +20mV centered at VBATT, VCC until VBATT reaches the reset threshold; the SP690A/SP802L/SP805L then switches to allowing use of a capacitor and a simple charging battery-backup mode. circuit as a backup source (see Figure 16). MAXIMUM PART +5V BBBBBAAAAACCCCCKKKKKUUUUUPPPPP-----BBBBBAAAAATTTTTTTTTTEEEEERRRRRYYYYY NNNNNUUUUUMMMMMBBBBBEEEEERRRRR VVVVVOOOOOLLLLLTTTTTAAAAAGGGGGEEEEE[[[[[VVVVV]]]]] VCC SP690A VOUT CONNECT TO VBATT STATIC RAM SP802L 4.80 SP805L 0.1F RESET CONNECT SP692A 100KΩ (RESET)* TO (cid:181)P GND SP802M 4.55 *( ) SP805M only SP805M Figure 15. Allowable BACKUP-BATTERY Voltages Figure 17. Backup Power Source Using High Capacity Capacitor with SP692A/802M/805M and a +5V –10% Supply Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 11

Operation Without a Backup Power +5V Source V IN VCC R1 If a backup power source is not used, ground V and connect V to V . Since there is PFI BATT OUT CC no need to switch over to any backup power source, V does not need to be switched. A R3 *C1 R2 direct conOnUecTtion to V eliminates any voltage CC PFO drops across the switch which may push V OUT *optional below V . CC GND connect to (cid:181)P Replacing the Backup Battery 1.25 V = TRIP R The backup battery can be removed while V 2 CC R1 + R2 remains valid, without danger of triggering RESET/RESET. As long as V stays above the 1.25 = VL - 1.25 + 5.0 - 1.25 reset threshold, battery-backuCpC mode cannot be R2 R1 R3 entered. 1.25 V = H R || R Adding Hysteresis to the Power-Fail 2 3 PFO R + R || R Comparator 1 2 3 Hysteresis adds a noise margin to the power-fail +5V comparator and prevents repeated triggering of 0V V IN PFO when V is close to its trip point. Figure 18 0V VL VTRIP VH IN shows how to add hysteresis to the power-fail comparator. Select the ratio of R and R such Figure 18. Adding Hysteresis to the POWER-FAIL 1 2 Comparator that PFI sees 1.25V when V falls to its trip IN point (V ). R adds the hysteresis. It will TRIP 3 typically be an order of magnitude greater (about 10 times) than R or R . The current through R Allowable Backup Power-Source 1 2 1 and R should be at least 1(cid:181)A to ensure that the Batteries 2 25nA (max) PFI input current does not shift the trip point. R should be larger than 10KΩ so it Lithium batteries work very well as backup 3 does not load down the PFO pin. Capacitor C1 batteries due to very low self-discharge rate and adds additional noise rejection. high energy density. Single lithium batteries with open-circuit voltages of 3.0V to 3.6V are Monitoring a Negative Voltage ideal. Any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3V The power-fail comparator can be used to monitor can be connected directly to the V input of BATT a negative supply rail using the circuit of Figure this series with no additional circuitry; see 19. When the negative rail is valid, PFO is low. FIGURE 12. However, batteries with open- When the negative supply voltage drops, PFO circuit voltages that are greater than this value goes high. This circuit's accuracy is cannot be used for backup, as current is sourced affected by the PFI threshold tolerance, the V into V through the diode (D1 in Figure 13) CC OUT voltage, and the resistors, R1 and R2. when V is close to the reset threshold. CC Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 12

+5V Buffered RESET connects to System Components VCC R1 PFI +5V +5V R2 VCC VCC PFO (cid:181)P V- RESET RESET GND 4.7KΩ 5.0 - 1.25 =1.25 - VTRIP GND GND R1 R2 PFO Figure 20. Interfacing to Microprocessors with Bidirectional RESET I/O +5V 0V V- *V 0V TRIP *V is a negative voltage TRIP Figure 19. Monitoring a Negative Voltage Interfacing to Microprocessors with Bidirectional Reset Pins Microprocessors with bidirectional reset pins, such as the Motorola 68HC11 series, can con- tend with this series' RESET output. If, for example, the RESET output is driven high and the (cid:181)P wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7KΩ resistor between the RESET output and the (cid:181)P reset I/O, as in Figure 20. Buffer the RESET output to other system components. Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 13

PACKAGE: 8 PIN PDIP N E INDEX AREA E1 E 1 2 3 N/2 c eA A1 eB D A e A2 D1 L b b3 b2 b c 8 PIN PDIP JEDEC MS-001 (BA) Variation SYMBOL MIN NOM MAX A - - 0.21 A1 0.15 - - A2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 D 0.355 0.365 0.4 D1 0.005 - - E 0.3 0.31 0.325 E1 0.24 0.25 0.28 e .100 BSC eA .300 BSC eB - - 0.43 L 0.115 0.13 0.15 Note: Dimensions in (mm) Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 14

PACKAGE: 8 PIN NSOIC D Ø e E/2 E1/2E1 L2 E Seating Plane Ø1 L Ø L1 Gauge Plane VIEW C 1 b INDEX AREA (D/2 X E1/2) TOP VIEW A A1 Seating Plane A2 SIDE VIEW 8 Pin NSOIC JEDEC MO-012 (AA) Variation SYMBOL MIN NOM MAX A 1.35 - 1.75 B A1 0.1 - 0.25 A2 1.25 - 1.65 B b 0.31 - 0.51 SEE VIEW C c 0.17 - 0.24 D 4.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.4 - 1.27 b L1 1.04 REF L2 0.25 BSC ø 0º - 8º ø1 5º - 15º c Note: Dimensions in (mm) BASE METAL SECTION B-B WITH PLATING Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 15

ORDERING INFORMATION Model Temperature Range Package Types SP690ACN........................................................0(cid:176)C to +70(cid:176)C.....................................................8-Pin NSOIC SP690ACN/TR...................................................0(cid:176)C to +70(cid:176)C.....................................................8-Pin NSOIC SP690ACP........................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP690AEN......................................................-40(cid:176)C to +85(cid:176)C.....................................................8-Pin NSOIC SP690AEN/TR.................................................-40(cid:176)C to +85(cid:176)C.....................................................8-Pin NSOIC SP690AEP.......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP SP692ACN........................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP692ACN/TR..................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP692ACP........................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP692AEN......................................................-40(cid:176)C to +85(cid:176)C.....................................................8-Pin NSOIC SP692AEN/TR................................................-40(cid:176)C to +85(cid:176)C.....................................................8-Pin NSOIC SP692AEP.......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP SP802LCN........................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP802LCN/TR..................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP802LCP........................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP802LEN.......................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP802LEN/TR.................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP802LEP.......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP SP802MCN.......................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP802MCN/TR.................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP802MCP.......................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP802MEN......................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP802MEN/TR................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP802MEP......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP SP805LCN........................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP805LCN/TR..................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP805LCP........................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP805LEN.......................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP805LEN/TR.................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP805LEP.......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP SP805MCN.......................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP805MCN/TR..................................................0(cid:176)C to +70(cid:176)C......................................................8-Pin NSOIC SP805MCP.......................................................0(cid:176)C to +70(cid:176)C.........................................................8-Pin PDIP SP805MEN......................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP805MEN/TR................................................-40(cid:176)C to +85(cid:176)C....................................................8-Pin NSOIC SP805MEP......................................................-40(cid:176)C to +85(cid:176)C.......................................................8-Pin PDIP Available in lead free packaging. To order add “-L” suffix to part number. Example: SP802LCN/TR = standard; SP802LCN-L/TR = lead free /TR = Tape and Reel Pack quantity 2,500 for NSOIC. CLICK HERE TO ORDER SAMPLES Sipex Corporation Corporation Headquarters and ANALOG EXCELLENCE Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Date: 11/29/04 SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2004 Sipex Corporation 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: E xar: SP690AEN-L SP805LEN-L/TR SP690AEP-L SP690ACN-L/TR SP805LCN-L/TR SP805LCN-L SP805LEN-L SP690SEN-L SP805LEP-L SP690SCN-L SP690TCN-L SP805LCP-L SP690ACN-L SP690AEN-L/TR SP690TCN- L/TR SP690TEN-L/TR SP690SEN-L/TR SP690SCN-L/TR SP690ACP-L