SP3508 Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES • Fast 20Mbps Differential Transmission Rates Now Available in Lead Free Packaging • Internal Transceiver Termination Resistors Refer to page 9 for pinout for V. & V.35 • Interface Modes: — RS-232 (V.28) — EIA-530 (V.0 & V.) — X.2 (V.) — EIA-530A (V.0 & V.) — RS-449/V.36 — V.35 (V.35 & V.28) (V.0 & V.) • Protocols are Software Selectable with 3-Bit Word • Eight (8) Drivers and Eight (8) Receivers •Termination Network Disable Option APPLICATIONS • Internal Line or Digital Loopback for Diagnostic Testing • Router • Certified conformance to NET1/NET2 and TBR-1 • Frame Relay TBR-2 by TUV Rheinland (TBR2/3045940.00/04) • CSU • Easy Flow-Through Pinout • DSU • +3.3V Only Operation • PBX • Individual Driver and Receiver Enable/Disable Controls • Secure Communication Terminals •Operates in either DTE or DCE Mode DESCRIPTION The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a regulated charge pump allowing +3.3V only operation. Exar's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V. receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V. or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 

ABSOLUTE MAXIMUM RATINGS VCC .................................................................................................+7V Package Derating: Input Voltages: ø ...................................................................36.9 °C/W LDorigviecr .s. ............................................................................................--00..33VV ttoo ((VVCC++00..55VV)) øJJAC .....................................................................6.5 °C/W CC Receivers .............................................................±5.5V Output Voltages: These are stress ratings only and functional operation of the Logic ................................................-0.3V to (V +0.5V) Drivers ................................................................C..C...±2V device at these ratings or any other above those indicated in Receivers .........................................-0.3V to (VCC+0.5V) the operation sections of the specifications below is not implied. Storage Temperature ..................................................-65°C to +50°C Power Dissipation ...................................................................520mW Exposure to absolute maximum rating conditions for extended (derate 9.0mW/°C above +70°C) periods of time may affect reliability. Junction Temperature T ......................................................... +4°C J STORAGE CONSIDERATIONS Due to the relatively large package size of the 00-pin quad used within 48 hours or stored in an environment at or below flat-pack, storage in a low humidity environment is preferred. 20%RH. If the above conditions cannot be followed, the parts Large high density plastic packages are moisture sensitive and should be baked for four hours at 25°C in order to remove should be stored in Dry Vapor Barrier Bags. Prior to usage, moisture prior to soldering. Exar ships the 00-pin LQFP in Dry the parts should remain bagged and stored below 40°C and Vapor Barrier Bags with a humidity indicator card and desiccant 60%RH. If the parts are removed from the bag, they should be pack. The humidity indicator should be below 30%RH. ELECTRICAL SPECIFICATIONS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera- A CC ture range (-40°C to +85°C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS LOGIC INPUTS V 0.8 ♦ V IL V 2.0 ♦ V IH LOGIC OUTPUTS V 0.4 ♦ V I = -3.2mA OL OUT V V V ♦ V I = .0mA OH CC CC OUT - 0.6 - 0.3 V.28 DRIVER DC Parameters (OUTPUTS) Open Circuit Voltage +/-0 ♦ V Per Figure  Loaded Voltage +/-5.0 ♦ V Per Figure 2 Short-Circuit Current +/-00 ♦ mA Per Figure 4 Power-Off Impedance 300 ♦ Ω Per Figure 5 V.28 DRIVER AC Parameters (Outputs) V = 3.3V for AC parameters CC Transition Time .5 ♦ µs Per Figure 6, +3V to -3V Instantaneous Slew Rate 30 V/ µs Per Figure 3 Propagation Delay: t 0.5 .0 3.0 ♦ µs PHL Propagation Delay: t 0.5 .0 3.0 ♦ µs PLH Max. Transmission Rate 20 230 ♦ kbps Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 2

ELECTRICAL SPECIFICATIONS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera- A CC ture range (-40°C to +85°C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER DC Parameters (Inputs) Input Impedance 3 7 ♦ kΩ Per Figure 7 Open-Circuit Bias +2.0 ♦ V Per Figure 8 HIGH Threshold .7 3.0 ♦ V LOW Threshold 0.8 .2 ♦ V V.28 RECEIVER AC Parameters V = 3.3V for AC parameters CC Propagation Delay: t 00 500 ns PHL Propagation Delay: t 00 500 ns PLH Max. Transmission Rate 20 230 kbps V.10 DRIVER DC Parameters (Outputs) Open Circuit Voltage +/-4.0 +/-6.0 ♦ V Per Figure 9 Test-Terminated Voltage 0.9V V Per Figure 0 CC Short-Circuit Current +/-50 mA Per Figure  Power-Off Current +/-00 ♦ µA Per Figure 2 V.10 DRIVER AC Parameters (Outputs) V = 3.3V for AC parameters CC Transition Time 200 ♦ ns Per Figure 3, 0% to 90% Propagation Delay: t 00 500 ♦ ns PHL Propagation Delay: t 00 500 ♦ ns PLH Max. Transmission Rate 20 ♦ kbps V.10 RECEIVER DC Parameters (Inputs) Input Current -3.25 +3.25 mA Per Figures 4 and 5 Input Impedance 4 ♦ kΩ Sensitivity +/-0.3 ♦ V V.10 RECEIVER AC Parameters V = 3.3V for AC parameters CC Propagation Delay: t 20 250 ♦ ns PHL Propagation Delay: t 20 250 ♦ ns PLH Max. Transmission Rate 20 ♦ kbps Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 3

ELECTRICAL SPECIFICATIONS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera- A CC ture range (-40°C to +85°C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.11 DRIVER DC Parameters (Outputs) Open Circuit Voltage (V ) +/-6.0 ♦ V Per Figure 6 OC Test Terminated Voltage +/-2.0 ♦ V Per Figure 7 0.5(V ) ♦ V OC Balance +/-0.4 V Per Figure 7 Offset +3.0 ♦ V Per Figure 7 Short-Circuit Current +/-50 ♦ mA Per Figure 8 Power-Off Current +/-00 ♦ µA Per Figure 9 V.11 DRIVER AC Parameters (Outputs) V = 3.3V for AC parameters CC Transition Time 0 ♦ ns Per Figures 2 and 35, 0% to 90% using C = 50pF L Propagation Delay: t 30 85 ♦ ns Per Figures 32 and 35 PHL Propagation Delay: t 30 85 ♦ ns Per Figures 32 and 35 PLH Differential Skew 5 0 ♦ ns Per Figures 32 and 35 Max. Transmission Rate 20 ♦ Mbps V.11 RECEIVER DC Parameters (Inputs) Common Mode Range -7 +7 ♦ V Sensitivity +/-0.2 ♦ V Input Current -3.25 +3.25 mA Per Figures 20 and 22; Power on or off Current with 100Ω +/-60 mA Per Figures 23 and 24 Termination Input Impedance 4 ♦ kΩ V.11 RECEIVER AC Parameters V = 3.3V for AC parameters us- CC ing CL = 50pF Propagation Delay: t 30 85 ns Per Figures 32 and 37 PHL Propagation Delay: t 30 85 ns Per Figures 32 and 37 PLH Skew 5 0 ns Per Figure 32 Max. Transmission Rate 20 Mbps Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 4

ELECTRICAL SPECIFICATIONS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera- A CC ture range (-40°C to +85°C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.35 DRIVER DC Parameters (Outputs) Open Circuit Voltage +/-.20 V Per Figure 6 Test Terminated Voltage +/-0.44 +/-0.66 V Per Figure 25 Offset +/-0.6 ♦ V Per Figure 25 Output Overshoot -0.2V +0.2V ♦ V Per Figure 25; V = Steady State ST ST ST value Source Impedance 50 50 ♦ Ω Per Figure 26; Z = V/V x 50 S 2  Short-Circuit Impedance 35 65 Ω Per Figure 27 V.35 DRIVER AC Parameters (Outputs) V = 3.3V for AC parameters CC Transition Time 20 ♦ ns Propagation Delay: t 30 85 ♦ ns Per Figures 32 and 35; C = 20pF PHL L Propagation Delay: t 30 85 ♦ ns Per Figures 32 and 35; C = 20pF PLH L Differential Skew 5 ♦ ns Per Figures 32 and 35; C = 20pF L Max. Transmission Rate 20 ♦ Mbps V.35 RECEIVER DC Parameters (Inputs) Sensitivity +/-50 +/-200 ♦ mV Source Impedance 90 0 Ω Per Figure 29; Z = V/V x 50Ω S 2  Short-Circuit Impedance 35 65 Ω Per Figure 30 V.35 RECEIVER AC Parameters V = 3.3V for AC parameters CC Propagation Delay: t 30 85 ns Per Figures 32 and 37; C = 20pF PHL L Propagation Delay: t 30 85 ns Per Figures 32 and 37; C = 20pF PLH L Skew 5 0 ns Per Figure 32; C = 20pF L Max. Transmission Rate 20 Mbps TRANSCEIVER LEAKAGE CURRENTS Driver Output 3-State Cur- 200 µA Per Figure 3; Drivers Disabled rent Receiver Output 3-State  0 µA D =  X Current Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 5

ELECTRICAL SPECIFICATIONS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera- A CC ture range (-40°C to +85°C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS POWER REQUIREMENTS V 3.5 3.3 3.45 V CC I (No Mode Selected)  ♦ µA All I values are with V = +3.3V CC CC CC (V.28 / RS-232) 95 ♦ mA f = 230kbps; Drivers active and IN loaded (V. / RS-422) 230 ♦ mA f = 20Mbps; Drivers active and IN loaded (EIA-530 & RS-449) 270 ♦ mA f = 20Mbps; Drivers active and IN loaded (V.35) 70 ♦ mA V.35 @ f = 20Mbps, V.28 @ f = IN IN 230kbps Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 6

OTHER AC CHARACTERISTICS T = 0 to 70°C and V = 3.3V ± 5% unless otherwise noted. A CC PARAMETER MIN. TYP. MAX. Units CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 t ; Tri-state to Output LOW 0.70 5.0 µs C = 00pF, Fig. 33 & 39; S closed PZL L  t ; Tri-state to Output HIGH 0.40 2.0 µs C = 00pF, Fig. 33 & 39; S closed PZH L 2 t ; Output LOW to Tri-state 0.20 2.0 µs C = 00pF, Fig. 33 & 39; S closed PLZ L  t ; Output HIGH to Tri-state 0.40 2.0 µs C = 00pF, Fig. 33 & 39; S closed PHZ L 2 RS-423/V.10 t ; Tri-state to Output LOW 0.5 2.0 µs C = 00pF, Fig. 33 & 39; S closed PZL L  t ; Tri-state to Output HIGH 0.20 2.0 µs C = 00pF, Fig. 33 & 39; S closed PZH L 2 t ; Output LOW to Tri-state 0.20 2.0 µs C = 00pF, Fig. 33 & 39; S closed PLZ L  t ; Output HIGH to Tri-state 0.5 2.0 µs C = 00pF, Fig. 33 & 39; S closed PHZ L 2 RS-422/V.11 t ; Tri-state to Output LOW 2.80 0.0 µs C = 00pF, Fig. 33 & 36; S closed PZL L  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 33 & 36; S closed PZH L 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 5pF, Fig. 33 & 36; S closed PLZ L  t ; Output HIGH to Tri-state 0.0 2.0 µs C = 5pF, Fig. 33 & 36; S closed PHZ L 2 V.35 t ; Tri-state to Output LOW 2.60 0.0 µs C = 00pF, Fig. 33 & 36; S closed PZL L  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 33 & 36; S closed PZH L 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 5pF, Fig. 33 & 36; S closed PLZ L  t ; Output HIGH to Tri-state 0.5 2.0 µs C = 5pF, Fig. 33 & 36; S closed PHZ L 2 RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 t ; Tri-state to Output LOW 0.2 2.0 µs C = 00pF, Fig. 34 & 37; S closed PZL L  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PZH L 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PLZ L  t ; Output HIGH to Tri-state 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PHZ L 2 RS-423/V.10 t ; Tri-state to Output LOW 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PZL L  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PZH L 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PLZ L  t ; Output HIGH to Tri-state 0.0 2.0 µs C = 00pF, Fig. 34 & 37; S closed PHZ L 2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 7

OTHER AC CHARACTERISTICS: Continued T = 0 to 70°C and V = +3.3V unless otherwise noted. A CC PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11 t ; Tri-state to Output LOW 0.0 2.0 µs C = 00pF, Fig. 34 & PZL L 38; S closed  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 34 & PZH L 38; S closed 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 5pF, Fig. 34 & PLZ L 38; S closed  t ; Output HIGH to Tri-state 0.0 2.0 µs C = 5pF, Fig. 34 & PHZ L 38; S closed 2 V.35 t ; Tri-state to Output LOW 0.0 2.0 µs C = 00pF, Fig. 34 & PZL L 38; S closed  t ; Tri-state to Output HIGH 0.0 2.0 µs C = 00pF, Fig. 34 & PZH L 38; S closed 2 t ; Output LOW to Tri-state 0.0 2.0 µs C = 5pF, Fig. 34 & PLZ L 38; S closed  t ; Output HIGH to Tri-state 0.0 2.0 µs C = 5pF, Fig. 34 & PHZ L 38; S closed 2 TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 32, 35, 37) RS-232 Driver 00 ns [ (t )Tx – (t )Txn ] PHL PHL 00 ns [ (t )Tx – (t )Txn] PLH PLH RS-232 Receiver 20 ns [ (t )Rx – (t )Rxn ] PHL PHL 20 ns [ (t )Rx – (t )Rxn ] PLH PLH RS-422 Driver 2 ns [ (t )Tx – (t )Txn ] PHL PHL 2 ns [ (t )Tx – (t )Txn ] PLH PLH RS-422 Receiver 3 ns [ (t )Rx – (t )Rxn ] PHL PHL: 3 ns [ (t )Rx – (t )Rxn ] PLH PLH RS-423 Driver 5 ns [ (t )Tx2 – (t )Txn ] PHL PHL 5 ns [ (t )Tx2 – (t )Txn ] PLH PLH RS-423 Receiver 5 ns [ (t )Rx2 – (t )Rxn ] PHL PHL 5 ns [ (t )Rx2 – (t )Rxn ] PLH PLH V.35 Driver 4 ns [ (t )Tx – (t )Txn ] PHL PHL 4 ns [ (t )Tx – (t )Txn ] PLH PLH V.35 Receiver 6 ns [ (t )Rx – (t )Rxn ] PHL PHL 6 ns [ (t )Rx – (t )Rxn] PLH PLH Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 8

PINOUT Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 9

SP3508 Pin Designation Pin Number Pin Name Description  GND Signal Ground 2 SDEN TxD Driver Enable Input 3 TTEN TxCE Driver Enable Input 4 STEN ST Driver Enabe Input 5 RSEN RTS Driver Enable Input 6 TREN DTR Driver Enable Input 7 RRCEN DCD Driver Enable Input 8 RLEN RL Driver Enable Input 9 LLEN# LL Driver Enable Input 0 RDEN# RxD Receiver Enabe Input  RTEN# RxC Receiver Enable Input 2 TxCEN# TxC Receiver Enable Input 3 CSEN# CTS Receiver Enable Input 4 DMEN# DSR Receiver Enable Input 5 RRTEN# DCD Receiver Enable Input DTE 6 ICEN# RI Receiver Enable Input 7 TMEN TM Receiver Enable Input 8 D0 Mode Select Input 9 D Mode Select Input 20 D2 Mode Select Input 2 DLATCH# Decoder Latch Input 22 TERM_OFF Termination Disable Input 23 VCC Power Supply Input 24 C3P Charge Pump Capacitor 25 GND Signal Ground Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 0

SP3508 Pin Designation Pin Number Pin Name Description 26 C3N Charge Pump Capacitor 27 VSS2 Minus VCC 28 AGND Signal Ground 29 AVCC Power Supply Input 30 LOOPBACK# Loopback Mode Enable Input 3 TxD TxD Driver TTL Input 32 TxCE TxCE Driver TTL input 33 ST ST Driver TTL Input 34 RTS RTS Driver TTL Input 35 DTR DTR Driver TTL Input 36 DCD_DCE DCD Driver TTL Input DCE 37 RL RL Driver TTL Input 38 LL LL Driver TTL Input 39 RxD RxD Receiver TTL Output 40 RxC RxC Receiver TTL Output 4 TxC TxC Receiver TTL Output 42 CTS CTS Receiver TTL Output 43 DSR DSR Receiver TTL Output 44 DCD_DTE DCD Receiver TTL Output DTE 45 RI RI Receiver TTL Output 46 TM TM Receiver TTL Output 47 GND Signal Ground 48 VCC Power Supply Input 49 RD(B) RxD Non-Inverting Input 50 RD(A) RxD Inverting Input Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 

SP3508 Pin Designation Pin Number Pin Name Description 5 RT(B) RxC Non-Inverting Input 52 RT(A) RxC Inverting Input 53 TxC(B) TxC Non-Inverting Input 54 GND Signal Ground 55 TxC(A) TxC Inverting Input 56 CS(B) CTS Non-Inverting Input 57 CS(A) CTS Inverting Input 58 DM(B) DSR Non-Inverting Input 59 DM(A) DSR Inverting Input 60 GNDV0 V.0 RX Reference Node 6 RRT(B) DCD Non-Inverting Input DTE 62 RRT(A) DCD Inverting Input DTE 63 IC RI Receiver Input 64 TM(A) TM Receiver Input 65 LL(A) LL Driver Output 66 VCC Power Supply Input 67 RL(A) RL Driver Output 68 VSS -2xVCC Charge Pump Output 69 C2N Charge Pump Capacitor 70 CN Charge Pump Capacitor 7 GND Signal Ground 72 C2P Charge Pump Capacitor 73 VCC Power Supply Input 74 CP Charge Pump Capacitor 75 GND Signal Ground Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 2

SP3508 Pin Designation Pin Number Pin Name Description 76 VDD 2xVCC Charge Pump Output 77 RRC(B) DCD Non-Inverting Output DCE 78 VCC Power Supply Input 79 RRC(A) DCD Inverting Output DCE 80 GND Signal Ground 8 RS(A) RTS Inverting Output 82 VCC Power Supply Input 83 RS(B) RTS Non-Inverting Output 84 GND Signal Ground 85 TR(A) DTR Inverting Output 86 VCC Power Supply Input 87 TR(B) DTR Non-Inverting Output 88 GND Signal Ground 89 ST(A) ST Inverting Output 90 VCC Power Supply Input 9 ST(B) ST Non-Inverting Output 92 GND Signal Ground 93 TT(A) TxCE Inverting Output 94 VCC Power Supply Input 95 TT(B) TxCE Non-Inverting Output 96 GND Signal Ground 97 SD(A) TxD Inverting Output 98 VCC Power Supply Input 99 SD(B) TxD Non-Inverting Output 00 VCC Power Supply Input Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 3

SP3508 Driver Table RS-232 RS-449 Driver Output EIA-530 EIA-530A X.21 Mode Suggested V.35 Mode Mode Mode Shutdown Pin Mode Mode (V.11) Signal (V.28) (V.36) MODE (D0, D1, D2) 001 010 011 100 101 110 111 TOUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxD(a) 1 TOUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxD(b) 1 TOUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxCE(a) 2 TOUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxCE(b) 2 TOUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DCE(a) 3 TOUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DCE(b) 3 TOUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z RTS(a) 4 TOUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z RTS(b) 4 TOUT(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DTR(a) 5 TOUT(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DTR(b) 5 TOUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DCE(a) 6 TOUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DCE(b) 6 TOUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RL 7 TOUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z LL 8 Table . Driver Mode Selection SP3508 Receiver Table RS-232 RS-449 Receiver Input EIA-530 EIA-530A X.21 Mode Suggested V.35 Mode Mode Mode Shutdown Pin Mode Mode (V.11) Signal (V.28) (V.36) MODE (D0, D1, D2) 001 010 011 100 101 110 111 R IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z RxD(a) 1 R IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxD(b) 1 R IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z RxC(a) 2 R IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxC(b) 2 R IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DTE(a) 3 R IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DTE(b) 3 R IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z CTS(a) 4 R IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z CTS(b) 4 R IN(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DSR(a) 5 R IN(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DSR(b) 5 R IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DTE(a) 6 R IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DTE(b) 6 R IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RI 7 R IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z TM 8 Table 2. Receiver Mode Selection Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 4

TEST CIRCUITS A A VOC 3kΩ VT C C Figure . V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A 7kΩ VT Oscilloscope Isc C C Scope used for slew rate measurement. Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A A I x ±2V 3kΩ 2500pF Oscilloscope C C Figure 5. V.28 Driver Output Power-Off Impedance Figure 6. V.28 Driver Output Rise/Fall Times Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 5

A A I ia ±15V v oc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9kΩ VOC 450Ω Vt C C Figure 9. V.0 Driver Output Open-Circuit Voltage Figure 0. V.0 Driver Output Test Terminated Volt- age VCC = 0V A A I x ±0.25V I sc C C Figure . V.0 Driver Output Short-Circuit Current Figure 2. V.0 Driver Output Power-Off Current Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 6

A A I ia ±10V 450Ω Oscilloscope C C Figure 3. V.0 Driver Output Transition Time Figure 4. V.0 Receiver Input Current A V.10 RECEIVER +3.25mA VOCA 3.9kΩ VOC VOCB -10V -3V B +3V +10V Maximum Input Current Versus Voltage C -3.25mA Figure 5. V.0 Receiver Input IV Graph Figure 6. V. Driver Output Open-Circuit Voltage A A I sa 50Ω V T 50Ω I sb B VOS B C C Figure 7. V. Driver Output Test Terminated Volt- Figure 8. V. Driver Output Short-Circuit Current age Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 7

V = 0V CC A I A ia I xa ±10V ±0.25V B B C C V = 0V CC A A ±0.25V ±10V B Ixb B Iib C C Figure 9. V. Driver Output Power-Off Current Figure 20. V. Receiver Input Current A V.11 RECEIVER 50Ω +3.25mA Oscilloscope 50Ω -10V -3V B 50Ω VE +3V +10V C Maximum Input Current Versus Voltage -3.25mA Figure 2. V. Driver Output Rise/Fall Time Figure 22. V. Receiver Input IV Graph Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 8

A V.11 RECEIVER I ia w/ Optional Cable Termination (100W to 150W) i [mA] = V [V] / 0.1 ±6V 100Ω to i [mA] = V [V] - 3) / 4.0 150Ω -6V -3V B +3V +6V i [mA] = V [V] - 3) / 4.0 Maximum Input Current C i [mA] = V [V] / 0.1 versus Voltage Figure 24. V. Receiver Input Graph with Termina- tion A ±6V A 100Ω to 150Ω 50Ω V I T ib B 50Ω B VOS C C Figure 23. V. Receiver Input Current w/ Termina- Figure 25. V.35 Driver Output Test Terminated Volt- tion age V 1 A A 50Ω 2S4inkeH Wz, a5v5e0mVp-p V 2 B ISC B ±2V C C Figure 26. V.35 Driver Output Source Impedance Figure 27. V.35 Driver Output Short-Circuit Imped- ance Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 9

A V1 A 50Ω 50Ω Oscilloscope 2S4inkeH Wz, a5v5e0mVp-p V2 50Ω B 50Ω B C C Figure 28. V.35 Driver Output Rise/Fall Time Figure 29. V.35 Receiver Input Source Impedance Any one of the three conditions f or disabling the driver. A VCC = 0V 1 1 1 D2 D1 D0 A VCC IZSC ±10V B Isc Logic “1” IZSC ±10V ±2V B C Figure 30. V.35 Receiver Input Short-Circuit Imped- Figure 3. Driver Output Leakage Current Test ance CL1 TIN B B ROUT A A CL2 15pF fIN (50% Duty Cycle, 2.5V P-P) Figure 32. Driver/Receiver Timing Test Circuit Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 20

Output 500Ω S1 VCC ReOcuetipveurt Test Point S1 1KΩ VCC Under Test CL CRL 1KΩ S2 S2 Figure 33. Driver Timing Test Load Circuit Figure 34. Receiver Timing Test Load Circuit f > 10MHz; tR< 5ns; tF< 5ns +3V DRIVER 1.5V 1.5V INPUT 0V tPLH tPHL DRIVER A VO1/2VO 1/2VO OUTPUT B tDPLH tDPHL DIFFERENTIAL VO+ OUTPUT 0V VB – VA VO– tR tF tSKEW = | tDPLH - tDPHL | Figure 35. Driver Propagation Delays f = 1MHz; tR ≤ 10ns; tF ≤ 10ns Mx or Tx_Enable +3V 1.5V 1.5V 0V tZL tLZ 5V A, B 2.3V Output normally LOW 0.5V VOL VOH Output normally HIGH 0.5V A, B 2.3V 0V tZH tHZ Figure 36. Driver Enable and Disable Times f > 10MHz; t < 5ns; t < 5ns R F V + 0D2 A – B 0V 0V V – INPUT 0D2 OUTPUT V OH RECEIVER OUT (VOH - VOL)/2 (VOH - VOL)/2 V OL t t PLH PHL tSKEW = | tPHL - tPLH | Figure 37. Receiver Propagation Delays Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 2

f = 1MHz; tR < 10ns; tF< 10ns DECx +3V 1.5V 1.5V RxENABLE 0V tZL tLZ +3.3V RECEIVER OUT 1.5V Output normally LOW 0.5V VIL VIH Output normally HIGH 0.5V RECEIVER OUT 1.5V 0V tZH tHZ Figure 38. Receiver Enable and Disable Times f = 60kHz; t < 10ns; t < 10ns R F +3V Tx_Enable 1.5V 1.5V 0V t t LZ ZL 0V T OUT V VOL-0.5V VOL-0.5V OL Output LOW f = 60kHz; t < 10ns; t < 10ns R F +3V Tx_Enable 1.5V 1.5V 0V t tZH Output HIGH HZ V OH VOH-0.5V T OUT 0V Figure 39. V.28 (RS-232) and V.0 (RS-423) Driver Enable and Disable Times Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 22

Figure 40. Typical V.0 Driver Output Waveform. Figure 4. Typical V. Driver Output Waveform. Figure 42. Typical V.28 Driver Output Waveform. Figure 43. Typical V.35 Driver Output Waveform. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 23

(See pinout assignments for +3.3V (decoupling capacitor not shown) GND and VCC pins) C1 C2 CVDD 1mF 1mF +3.31VmF VCC 74C1+ C17-0 C27+2 C26-9 C3+ 24 1mF C3 76 VDD C3-26 Regulated Charge Pump VSS1 68 1mF CVSS1 29 AVCC Inverter VSS2 27 1mF CVSS2 RD(a) 50 31 TxD 97 SD(a) RxD 39 RDEN 10 99 SD(b) RD(b) 49 2 SDEN RT(a) 52 32 TxCE 93 TT(a) 40 RxC RTEN 11 95 TT(b) RT(b) 51 3 TTEN TxC(a) 55 33 ST 89 ST(a) TxC 41 TxCEN 12 91 ST(b) TxC(b) 53 4 STEN CS(a) 57 34 RTS 81 RS(a) CTS 42 CSEN 13 83 RS(b) CS(b) 56 5 RSEN DM(a) 59 35 DTR 85 TR(a) DSR 43 DMEN 14 87 TR(b) DM(b) 58 6 TREN RRT(a) 62 36 DCD_DCE 79 DCD_DTE 44 RRC(a) RRTEN 15 77 RRT(b) 61 7 RRRRCC(EbN) IC 63 37 RL ICERNI 4156 67 RL(a) 8 RLEN TM(a) 64 38 LL TMETNM 4167 65 LL(a) 9 LLEN 18 D0 19 D1 SP3508 V.10-GND 60 20 D2 AGND 28 21 D-LATCH 22 TERM-OFF RECEIVER TERMINATION NETWORK 30 LOOPBACK V.35 DRIVER TERMINATION NETWORK V.35 MODE 51ohms GND V.11 MODE 124ohms 51ohms RX ENABLE V.35 MODE 124ohms 51ohms TX ENABLE 51ohms Figure 44. Functional Diagram Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 24

FEATURES The SP3508 contains highly integrated se- There are four basic types of driver circuits – rial transceivers that offer programmability ITU-T-V.28 (RS-232), ITU-T-V.0 (RS-423), between interface modes through software ITU-T-V. (RS-422), and CCITT-V.35. control. The SP3508 offers the hardware The V.28 (RS-232) drivers output single- interface modes for RS-232 (V.28), RS- ended signals with a minimum of +5V (with 449/V.36 (V. and V.0), EIA-530 (V. and 3kΩ & 2500pF loading), and can operate over V.0), EIA-530A (V. and V.0), V.35 (V.35 20kbps. Since the SP3508 uses a charge and V.28) and X.2(V.). The interface mode pump to generate the RS-232 output rails, the selection is done via three control pins, which driver outputs will never exceed +0V. The can be latched via microprocessor control. V.28 driver architecture is similar to Sipex's standard line of RS-232 transceivers. The SP3508 has eight drivers, eight receiv- The RS-423 (V.0) drivers are also single- ers, and a patented on-board charge pump ended signals which produce open circuit V OL (5,306,954) that is ideally suited for wide and V measurements of +4.0V to +6.0V. OH area network connectivity and other multi- When terminated with a 450Ω load to ground, protocol applications. Other features include the driver output will not deviate more than digital and line loopback modes, individual 0% of the open circuit value. This is in com- enable/disable control lines for each driver pliance of the ITU V.10 specification. The V.10 and receiver, fail-safe when inputs are either (RS-423) drivers are used in RS-449/V.36, open or shorted. EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit THEORY OF OPERATION over 20Kbps if necessary. The SP3508 device is made up of The third type of drivers are V. (RS-422) ) the drivers differential drivers. Due to the nature of dif- 2) the receivers ferential signaling, the drivers are more im- mune to noise as opposed to single-ended 3) charge pumps transmission methods. The advantage is 4) DTE/DCE switching algorithm evident over high speeds and long trans- 5) control logic. mission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels Drivers with a load of 100Ω. The strength allows the The SP3508 has eight enhanced indepen- SP3508 differential driver to drive over long dent drivers. Control for the mode selection cable lengths with minimal signal degrada- is done via a three-bit control word into D0, tion. The V. drivers are used in RS-449, D, and D2. The drivers are prearranged EIA-530, EIA-530A and V.36 modes as such that for each mode of operation, the Category I signals which are used for clock relative position and functionality of the driv- and data. Exar's new driver design over its ers are set up to accommodate the selected predecessors allow the SP3508 to operate interface mode. As the mode of the drivers over 20Mbps for differential transmission. is changed, the electrical characteristics will change to support the required signal The fourth type of drivers are V.35 differential levels. The mode of each driver in the dif- drivers. There are only three available on the ferent interface modes that can be selected SP3508 for data and clock (TxD, TxCE, and is shown in Table . TxC in DCE mode). Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 25

FEATURES These drivers are current sources that interface modes that can be selected. drive loop current through a differential pair There are two basic types of receiver cir- resulting in a 550mV differential voltage at cuits—ITU-T-V .28 (RS-232) and ITU-T-V., the receiver. These drivers also incorporate (RS-422). fixed termination networks for each driver in order to set the V and V depending on The RS-232 (V.28) receiver is single-ended OH OL load conditions. This termination network is and accepts RS-232 signals from the RS- basically a “Y” configuration consisting of 232 driver. The RS-232 receiver has an two 51Ω resistors connected in series and operating input voltage range of +5V and a 124Ω resistor connected between the two can receive signals downs to +3V. The input 50Ω resistors to GND. Filtering can be done sensitivity complies with RS-232 and V.28 on these pins to reduce common mode noise at +3V. The input impedance is 3kΩ to 7kΩ transmitted over the transmission line by in accordance to RS-232 and V.28. The re- connecting a capacitor to ground. ceiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “” and a The drivers also have separate enable pins +0.4V maximum for a logic “0”. The RS-232 which simplifies half-duplex configurations (V.28) protocol uses these receivers for all for some applications, especially program- data, clock and control signals. They are also mable DTE/DCE. The enable pins will either used in V.35 mode for control line signals: enable or disable the output of the drivers CTS, DSR, LL, and RL. The RS-232 receiv- according to the appropriate active logic ers can operate over 20kbps. illustrated on Figure 44. The enable pins have internal pull-up and pull-down devices, The second type of receiver is a differential depending on the active polarity of the re- type that can be configured internally to ceiver, that enable the driver upon power-on support ITU-T-V.0 and CCITT-V.35 if the enable lines are left floating. During depending on its input conditions. This disabled conditions, the driver outputs will receiver has a typical input impedance be at a high impedance 3-state. of 10kΩ and a differential threshold of less than +200mV, which complies with The driver inputs are both TTL or CMOS the ITU-T-V.11 (RS-422) specifications. compatible. All driver inputs have an internal V. receivers are used in RS-449/V.36, pull-up resistor so that the output will be at EIA-530, EIA-530A and X.2 as Category I a defined state at logic LOW (“0”). Unused signals for receiving clock, data, and some driver inputs can be left floating. The inter- control line signals not covered by Category nal pull-up resistor value is approximately II V.0 circuits. The differential V. trans- 500kΩ. ceiver has improved architecture that allows over 20Mbps transmission rates. Receivers The SP3508 has eight enhanced inde- Receivers dedicated for data and clock (RxD, pendent receivers. Control for the mode RxC, TxC) incorporate internal termination selection is done via a three-bit con- for V.. The termination resistor is typi- trol word that is the same as the driver cally 120Ω connected between the A and control word. Therefore, the modes for B inputs. The termination is essential for the drivers and receivers are identical in the minimizing crosstalk and signal reflection application. Like the drivers, the receivers over the transmission line . The minimum are prearranged for the specific requirements value is guaranteed to exceed 100Ω, thus of the synchronous serial interface. As the complying with the V. and RS-422 speci- operating mode of the receivers is changed, fications. This resistor is invoked when the the electrical characteristics will change receiver is operating as a V. receiver, in to support the required serial interface modes EIA-530, EIA-530A, RS-449/V.36, protocols of the receivers. Table  shows and X.2. the mode of each receiver in the different Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 26

FEATURES The same receivers also incorporate a ter- are open, terminated but open, or shorted mination network internally for V.35 applica- together. For single-ended V.28 and V.0 tions. For V.35, the receiver input termination receivers, there are internal 5kΩ pull-down is a “Y” termination consisting of two 51Ω resistors on the inputs which produces a resistors connected in series and a 124Ω logic high (“”) at the receiver outputs. The resistor connected between the two 50Ω differential receivers have a proprietary cir- resistors and GND. The receiver itself is cuit that detect open or shorted inputs and identical to the V. receiver. if so, will produce a logic HIGH (“”) at the receiver output. The differential receivers can be configured to be ITU-T-V.0 single-ended receivers by CHARGE PUMP internally connecting the non-inverting input SP3508 uses an internal capacitive charge to ground. This is internally done by default pump to generate Vdd and Vss. The design from the decoder. The non-inverting input is is a patented (5,306,954) four-phased volt- rerouted to V0GND and can be grounded separately. The ITU-T-V.0 receivers can age shifting charge pump converters that operate over 20Kbps and are used in RS- converts the input voltage of 3.3V to nomi- 449/V.36, EA-530, EA-530A and X.2 nal output voltages of +/-6V (Vdd & Vss). modes as Category II signals as indicated SP3508 also includes an inverter block by their corresponding specifications. All that inverts Vcc to -Vcc (Vss2). There is a receivers include an enable/disable line free-running oscillator that controls the four for disabling the receiver output allowing phases of the voltage shifting. A description convenient half-duplex configurations. The of each phase follows. enable pins will either enable or disable the output of the receivers according to the ap- propriate active logic illustrated on Figure 4-phased doubler pump 44. The receiver’s enable lines include an internal pull-up or pull-down device, depend- Phase 1 ing on the active polarity of the receiver, that enables the receiver upon power up if the -V charge storage -During this phase of SS enable lines are left floating. During disabled the clock cycle, the positive side of capacitors conditions, the receiver outputs will be at C and C2 are initially charged to V . C+ CC a high impedance state. If the receiver is is then switched to ground and the charge in disabled any associated termination is also C- is transferred to C2-. Since C2+ is con- disconnected from the inputs. nected to V , the voltage potential across CC capacitor C2 is now 2xV . All receivers include a fail-safe feature that CC outputs a logic high when the receiver inputs VCC = +3V +3V CVDD + + + – VDD Storage Capacitor C1– C2– – + VSS1 Storage Capacitor –3V –3V CVSS1 Figure 45. Charge Pump - Phase . Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 27

FEATURES Phase 2 -V transfer -Phase two of the clock connects the negative terminal of C2 to the V storage SS SS capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to C . This generated voltage is regulated to -5.5V. Simultaneously, the positive VSS side of the capacitor C is switched to V and the negative side is connected to ground. CC VCC = +3V CVDD + – VDD Storage Capacitor + + C1 C2 – – – + VSS Storage Capacitor –6V C VSS1 Figure 46. Charge Pump - Phase 2. Phase 3 -V charge storage -The third phase of the clock is identical to the first phase-the charge DD transferred in C produces -V in the negative terminal of C which is applied to the negative CC side of the capacitor C2. Since C2+ is at V , the voltage potential across C2 is 2xV . CC CC VCC = +3V C +3V VDD + – VDD Storage Capacitor + + C1 C2 – – – + VSS1 Storage Capacitor –3V –3V C VSS1 Figure 47.Charge Pump - Phase 3. Phase 4 -V transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, DD and transfers the generated 5.5V across C2 to C , the V storage capacitor. This voltage VDD DD is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simulta- neously with this, the positive side of capacitor C is switched to V and the negative side CC is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from V ; in a no-load condition V+ and V- will be symmetrical. CC Older charge pump approaches that generate V- from V+ will show a decrease in the mag- nitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as µF with a 6V breakdown voltage rating. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 28

FEATURES VCC = +3V +6V CVDD + – VDD Storage Capacitor + + C1 C2 – – – + VSS1 Storage Capacitor C VSS1 Figure 48. Charge Pump - Phase 4. 2-phased inverter pump Phase 1 Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage applied at Vcc. Phase 2 In the second phase of the clock cycle, switches S2 and S4 are closed and S and S3 are opened. This connects the flying capacitor, C3, in parallel with the output capacitor, C . VSS2 The Charge stored in C3 is now transferred to C . Simultaneously, the negative side of VSS2 C is connected to V and the positive side is connected to ground. With the voltage VSS2 SS2 across C smaller than the voltage across C3, the charge flows from C3 to C until the VSS2 VSS2 voltage at the V equals -V . SS2 CC VSS2 = -VCC VCC S1 S2 C3 + + CVSS2 V SS2 S3 S4 Figure 49. Circuit for an Ideal Voltage Inverter. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 29

enable pins for each driver and receiverQuality, Rate Detect, Standby) or may be disabled using individual Spare drivers and receivers may be used for optional signals (Signal 17TMEN46TMTM(A)Receiver_816ICEN#45RIICReceiver_715RRTEN#RRT(B)44DCD_DTERRT(A)Receiver_614DMEN#DM(B)43DSRDM(A)Receiver_513CSEN#CS(B)42CTSCS(A)Receiver_412TxCEN#TxC(B)41TxCTxC(A)Receiver_311RTEN#RT(B)40RxCRT(A)Receiver_210RDEN#RD(B)39RxDRD(A)Receiver_19LLEN#38LLLL(A)Driver_88RLEN37RLRL(A)Driver_77RRCENRRC(B)36DCD_DCERRC(A)Driver_66TRENTR(B)35DTRTR(A)Driver_55RSENRS(B)34RTSRS(A)Driver_44STENST(B)33STST(A)Driver_33TTENTT(B)32TxCETT(A)Driver_22SDENSD(B)31TxDSD(A)Driver_1NumberPin MnemonicCircuitPin MnemonicNPin Interface to System LogicConnectorInterface to PoSP3508 Multiprotocol Configured as DCE 64 63616258595657535551524950 65 67777987858381918995939997umberPin rt- proprietary / non-standard implementationsPin assignments and signal functions are sub V.28LL18V.10LL V.28RL21V.10RL V.11CD(B)V.28CD20V.11CD(A)V.11CA(B)V.28CA4V.11CA(A) V.11DA(B)V.28DA24V.11DA(A) V.11BA(B) V.28BA2V.11BA(A) V.28TM25V.10TM V.28CE22V.11CF(B)V.28CF8V.11CF(A)V.11CC(B)V.28CC6V.11CC(A)V.11CB(B)V.28CB5V.11CB(A)V.11DB(B)V.28DB15V.11DB(A)V.11DD(B)V.28DD17V.11DD(A)V.11BB(B)V.28BB3V.11BB(A)TypenicPin(F)TypenicSignal MnemoDB-25 Signal MnemoRS-232 or V.24EIA-530 Recommended Signals and Port Pin Assignm ject to national or regional variation 18V.10LL10 21V.10RL14 23V.11TR(B)3020V.11TR(A)1219V.11RS(B)254V.11RS(A)7 11V.11TT(B)3524V.11TT(A)1712V.11SD(B)222V.11SD(A)4 25V.10TM18 10V.11RR(B)318V.11RR(A)1322V.11DM(B)296V.11DM(A)1113V.11CS(B)275V.11CS(A)912V.11ST(B)2315V.11ST(A)59V.11RT(B)2617V.11RT(A)816V.11RD(B)243V.11RD(A)6Pin(F)TypenicPin(F)DB-25 Signal MnemoDB-37 RS-449 ents and V.28 V.28 V.28 V.28 V.35V.35V.35V.35 V.28 V.28 V.28 V.28 V.28V.35V.35V.35V.35V.35V.35TypeSignal M 141 140 108 105 113113103103 142 125 109 107 106114114115115104104nicnemV.35 o L N H C WUSP NN J F E DAAYXVTRPin(F)M34 DC X(), not both** X.21 use either B() or V.11C(B)10V.11C(A)3 V.11X(B)14**V.11X(A)7**V.11T(B)9V.11T(A)2 V.11I(B)12V.11I(A)5V.11S(B)13V.11S(A)6V.11B(B)14**V.11B(A)7**V.11R(B)11V.11R(A)4TypenicPin(F)Signal MnemoDB-15 X.21 E CONFIGURA T IO N Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 30

enable pins for each driver and receiverQuality, Rate Detect, Standby) or may be disabled using individual Spare drivers and receivers may be used for optional signals (Signal 17TMEN46TMTM(A)Receiver_816ICEN#45RIICReceiver_715RRTEN#RRT(B)44DCD_DTERRT(A)Receiver_614DMEN#DM(B)43DSRDM(A)Receiver_513CSEN#CS(B)42CTSCS(A)Receiver_412TxCEN#TxC(B)41TxCTxC(A)Receiver_311RTEN#RT(B)40RxCRT(A)Receiver_210RDEN#RD(B)39RxDRD(A)Receiver_19LLEN#38LLLL(A)Driver_88RLEN37RLRL(A)Driver_77RRCENRRC(B)36DCD_DCERRC(A)Driver_66TRENTR(B)35DTRTR(A)Driver_55RSENRS(B)34RTSRS(A)Driver_44STENST(B)33STST(A)Driver_33TTENTT(B)32TxCETT(A)Driver_22SDENSD(B)31TxDSD(A)Driver_1NumberPin MnemonicCircuitPin MnemonicNPin Interface to System LogicConnectorInterface to PoSP3508 Multiprotocol Configured as DTE 64 63616258595657535551524950 65 67777987858381918995939997umbePin rt- r proprietary / non-standard implementationsPin assignments and signal functions are sub V.28TM25V.10TM V.28CE22V.11CF(B)V.28CF8V.11CF(A)V.11CC(B)V.28CC6V.11CC(A)V.11CB(B)V.28CB5V.11CB(A)V.11DB(B)V.28DB15V.11DB(A)V.11DD(B)V.28DD17V.11DD(A)V.11BB(B)V.28BB3V.11BB(A) V.28LL18V.10LL V.28RL21V.10RL V.11CD(B)V.28CD20V.11CD(A)V.11CA(B)V.28CA4V.11CA(A) V.11DA(B)V.28DA24V.11DA(A)V.11BA(B)V.28BA2V.11BA(A)TypenicPin(M)TypenicSignal MnemoDB-25 Signal Mnemo RS-232 or V.24EIA-530 Recommended Signals and Port Pin Assignm ject to national or regional variation and 25V.10TM18V.28 V.2810V.11RR(B)318V.11RR(A)13V.2822V.11DM(B)296V.11DM(A)11V.2813V.11CS(B)275V.11CS(A)9V.2812V.11ST(B)23V.3515V.11ST(A)5V.359V.11RT(B)26V.3517V.11RT(A)8V.3516V.11RD(B)24V.353V.11RD(A)6V.35 18V.10LL10V.28 21V.10RL14V.28 23V.11TR(B)3020V.11TR(A)12V.2819V.11RS(B)254V.11RS(A)7V.28 11V.11TT(B)35V.3524V.11TT(A)17V.3512V.11SD(B)22V.352V.11SD(A)4V.35Pin(M)TypenicPin(M)TypeDB-25 Signal MnemoDB-37 Signal RS-449 ents M 142 125 109 107 106114114115115104104 141 140 108 105 113113103103nicnem V.35 DT o E NN J F E DAAYXVTR L N H C WUSPPin(MM34 CO ) N X(), not both** X.21 use either B() or V.11I(B)12V.11I(A)5V.11S(B)13V.11S(A)6V.11B(B)14**V.11B(A)7**V.11R(B)11V.11R(A)4 V.11C(B)10V.11C(A)3 V.11X(B)14**V.11X(A)7**V.11T(B)9V.11T(A)2TypenicPin(M)Signal MnemoDB-15 X.21 FIGURATION Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 3

FEATURES TERM_OFF FUNCTION There are internal pull-up devices on D0, D and D2, which allow the device to be in The SP3508 contains a TERM_OFF pin that SHUTDOWN mode ("111") upon power up. disables all three receiver input termination However, if the device is powered-up with networks regardless of mode. This allows the D_LATCH at a logic HIGH, the decoder the device to be used in monitor mode ap- state of the SP3508 will be undefined. plications typically found in networking test equipment. The TERM_OFF pin internally contains a CTR1/CTR2 EUROPEAN COMPLIANCY pull-down device with an impedance of over As with all of Exar's previous multi-protocol 500kΩ, which will default in a "ON" condition serial transceiver IC's the drivers and re- during power-up if V.35 receivers enable ceivers have been designed to meet all the line and the SHUTDOWN mode from the requirements to NET/NET2 and TBR2 in decoder will disable the termination regard- order to meet CTR/CTR2 compliancy. The less of TERM_OFF. SP3508 is also tested in-house at Exar and adheres to all the NET/2 physical layer testing and the ITU Series V specifications LOOPBACK FUNCTION before shipment. Please note that although The SP3508 contains a LOOPBACK pin that the SP3508, as with its predecessors, ad- invokes a loopback path. This loopback path here to CRT/CTR2 compliancy testing, is illustrated in Figure 50. LOOPBACK has any complex or usual configuration should an internal pull-up resistor that defaults to be double-checked to ensure CTR/CTR2 normal mode during power up or if the pin is compliance. Consult the factory for details. left floating. During loopback, the driver out- put and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP3508 contains a D_LATCH pin that latches the data into the D0, D and D2 decoder inputs. If tied to a logic LOW ("0"), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP3508 accordingly. If tied to a logic HIGH ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 32

97 SD(a) TxD 31 99 SD(b) 50 RD(a) 39 RxD 49 RD(b) 93 TT(a) 32 TxCE 95 TT(b) 52 RT(a) 40 RxC 51 RT(b) 89 ST(a) 33 ST 91 ST(b) 55 TxC(a) 41 TxC 53 TxC(b) 81 RS(a) RTS 34 83 RS(b) 57 CS(a) 42 CTS 56 CS(b) 85 TR(a) 35 DTR 87 TR(b) 59 DM(a) 43 DSR 58 DM(b) 79 RRC(a) 36 DCD_DCE 77 RRC(b) 62 RRT(a) 44 DCD_DTE 61 RRT(b) 37 67 RL RL(a) RI 45 63 IC 38 65 LL LL(a) TM 46 64 TM(a) Figure 50. Loopback Path Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 33

CVDD C1 C2 1mF 1mF 1mF +3.3V 10mF VCC VDD76C17+4C17-0C72+2C26-VC9CS3S31+-262684 1CmVFSSC13 +3.3V3219AVCC TxDCThraarngsec ePiuvmepr SSeeccttiiSooDnnV(SSa2)2977 CVSS2 mDB2- 2(6V .S1e1,r iVa.l3 5P, oVr.t2 8C)onnector PinsTXD_R X D _ A Signal (DTE_DCE) SD(b)99 14 (V.11, V.35) TXD_RXD_B 32 TxCE TT(a)93 24 (V.11, V.35, V.28) TXCE_TXC_A TT(b)95 11 (V.11, V.35) TXCE_TXC_B 33 ST SSTT((ab))8991 34 RTS RS(a)81 4 (V.11, V.28) RTS_CTS_A RS(b)83 19 (V.11) RTS_CTS_B 35 DTR TR(a)85 20 (V.11, V.28) DTR_DSR_A TR(b)87 23 (V.11) DTR_DSR_B RRC(a)79 36 DCD_DCE RRC(b)77 37 RL RL(a)67 21 (V.10, V.28) RL_RI 38 LL LL(a)65 18 (V.10, V.28) LL_TM 39 RxD RD(a)50 3 (V.11, V.35, V.28) RXD_TXD_A RD(b)49 16 (V.11, V.35) RXD_TXD_B 40 RxC RT(a)52 17 (V.11, V.35, V.28) RXC_TXCE_A RT(b)51 9 (V.11, V.35) RXC_TXCE_B 41 TxC TTxxCC((ab))5553 1152 ((VV..1111,, VV..3355,) V.28) **TTXXCC__RRXXCC__AB 42 CTS CCSS((ba))5576 153 ((V.V1.111,) V.28) CCTTSS__RRTTSS__BA 43 DSR DDMM((ab))5598 62 2( V(.V1.11,1 )V.28) DDSSRR__DDTTRR__AB 44 DCD_DTE RRRRTT((ab))6621 81 0( V(.V1.11,1 )V.28) DDCCDD__DDCCDD__AB 45 RI IC63 22 (V.10, V.28) RI_RL 46 TM TM(a)64 25 (V.10, V.28) LL_TM +3.3V 2SDEN Logic Section D0 18 DCE/DTE 3456TSRTTTSREEEENNNN SP3508CD_FLATCDDH12 122901 789RRLRLLCEEENNN TLEOROMP_BOAFCFK 2320 +3.3V 10RDEN 11RTEN 12TxCEN 13CSEN 11117456TDRIMMRCETEENENNN AGND 28 * -RDR ereDccireevieiivrvveee rrra paaapppplpppillleiiiseee sssf o frffooo rrrD CDDDECTT EEEo nooolnnnylll yyyo nooo nnnp ipppniiisnnn sss8 118a55 n adaan nnd1dd 0 1.11022... GND Input Line Output Line I/O Lines represented by double arrowhead signifies a bi-directional bus. Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE program- mability Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 34

PACKAGE: 100 PIN LQFP Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 35

ORDERING INFORMATION Part Number Temperature Range Package Types SP3508CF-L ...........................................0°C to +70°C ..................................................00–pin JEDEC LQFP SP3508EF-L ........................................-40°C to +85°C ..................................................00–pin JEDEC LQFP REVISION HISTORY Date Revision Description /2/04 A Implemented Tracking revision 2/27/04 B Included Diamond column in spec table inidcating which specs apply over full operating temperature range. Correct typo to Fig. 5 pin 6 and 62. 3/3/04 C Corrected max dimension for symbol c on LQFP package outline 6/03/04 D Added table to page 27 and 28 0/2/04 E Certified conformance to NET1/NET2 and TBR-1/TBR-2 TUV by TUV Rhein- land (Test report # TBR2/3045940.00/04) 0/29/04 F Corrected V.28 Driver Open circuit values, pages 27 and 28 -- both for DCE and DTE that BA(B) should connect to pin 4. 7/7/08 .0.0 Change Revision format from letter code to number code. Change Logo, footnote and notice statement from Sipex to Exar. Add T limits to Absolute J Maximum Ratings. Change propagation delay limit specification for V.11 and V.35 Driver/Receiver from 60ns Maximum to 85ns Maximum. Update ordering information to show only RoHS packaging (-L) is available. Notice EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliabil- ity. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2008 EXAR Corporation Datasheet July 2008 Send your Interface technical inquiry with technical details to: uarttechsupport@exar.com Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 36

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