(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 (cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:16)(cid:15)(cid:2)(cid:17)(cid:13)(cid:18)(cid:5) (cid:6)(cid:19)(cid:1) (cid:17)(cid:16)(cid:18)(cid:2)(cid:1)(cid:7)(cid:15)(cid:13)(cid:20)(cid:15)(cid:16) FEATURES The driver outputs and the receiver inputs connect (cid:1) internally to form a differential input/output (I/O) bus port One-Fourth Unit Load Allows up to 128 that is designed to offer minimum loading to the bus. Devices on a Bus This port operates over a wide range of common-mode (cid:1) ESD Protection for Bus Terminals: voltage, making the device suitable for party-line − ±15-kV Human Body Model applications. The device also includes additional − ±8-kV IEC61000-4-2, Contact Discharge features for party-line data buses in electrically noisy − ±15-kV IEC61000-4-2, Air-Gap Discharge environment applications such as industrial process (cid:1) Meets or Exceeds the Requirements of ANSI control or power inverters. Standard TIA/EIA-485-A and ISO 8482: 1987(E) The SN75LBC182 and SN65LBC182 bus pins also (cid:1) Controlled Driver Output-Voltage Slew Rates exhibit a high input resistance equivalent to one-fourth Allow Longer Cable Stub Lengths unit load allowing connection of up to 128 similar (cid:1) Designed for Signaling Rates† Up to 250-kbps devices on the bus. The high ESD tolerance protects (cid:1) Low Disabled Supply Current...250 µA Max the device for cabled connections. (For an even higher (cid:1) level of protection, see the SN65/75LBC184, literature Thermal Shutdown Protection number SLLS236.) (cid:1) Open-Circuit Fail-Safe Receiver Design (cid:1) The differential driver design incorporates Receiver Input Hysteresis...70 mV Typ slew-rate-controlled outputs sufficient to transmit data (cid:1) Glitch-Free Power-Up and Power-Down up to 250 kbps. Slew-rate control allows longer Protection unterminated cable runs and longer stub lengths from APPLICATIONS the main backbone than possible with uncontrolled voltage transitions. The receiver design provides a (cid:1) Utility Meters fail-safe output of a high level when the inputs are left (cid:1) Industrial Process Control floating (open circuit). Very low device supply current (cid:1) can be achieved by disabling the driver and the receiver. Building Automation The SN65LBC182 is characterized for operation from DESCRIPTION −40°C to 85°C, and the SN75LBC182 is characterized for operation from 0°C to 70°C. The SN65LBC182 and SN75LBC182 are differential data line transceivers with a high level of ESD protection functional block diagram in the trade-standard footprint of the SN75176. They are designed for balanced transmission lines and meet 3 ANSI standard TIA/EIA-485-A and ISO 8482. The DE 6 SN65LBC182 and SN75LBC182 combine a 3-state, 4 A D 7 differential line driver and differential input line receiver, B both of which operate from a single 5-V power supply. RE 2 The driver and receiver have active-high and active-low 1 R enables, respectively, which can be externally connected together to function as a direction control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). (cid:21)(cid:16)(cid:22)(cid:12)(cid:19)(cid:7)(cid:17)(cid:13)(cid:22)(cid:2) (cid:12)(cid:18)(cid:17)(cid:18) (cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) (cid:23)(cid:31) !"(cid:27)(cid:27)#(cid:24)(cid:30) (cid:29)(cid:31) (cid:26)(cid:25) $"%&(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) ’(cid:29)(cid:30)#( Copyright  2001, Texas Instruments Incorporated (cid:21)(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28) (cid:30)(cid:26) (cid:31)$#!(cid:23)(cid:25)(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24)(cid:31) $#(cid:27) (cid:30))# (cid:30)#(cid:27)(cid:28)(cid:31) (cid:26)(cid:25) (cid:17)#*(cid:29)(cid:31) (cid:13)(cid:24)(cid:31)(cid:30)(cid:27)"(cid:28)#(cid:24)(cid:30)(cid:31) (cid:31)(cid:30)(cid:29)(cid:24)’(cid:29)(cid:27)’ +(cid:29)(cid:27)(cid:27)(cid:29)(cid:24)(cid:30),( (cid:21)(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( www.ti.com 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 schematic of inputs and outputs SN65LBC182D (Marked as 6LB182) SN75LBC182D (Marked as 7LB182) SN65LBC182P (Marked as 65LBC182) VCC SN75LBC182P (Marked as 75LBC182) (TOP VIEW) R 1 8 VCC RE 2 7 B DE 3 6 A D 4 5 GND A Port Only 16 kΩ 12 µA Nominal 72 kΩ A or B I/O 16 kΩ B Port Only 12 µA Nominal Function Tables DRIVER IINNPPUUTT EENNAABBLLEE OUTPUTS DD DDEE A B H H H L L H L H X L Z Z Open H H L RECEIVER DIFFERENTIAL ENABLE OUTPUT INPUTS RE R VID ≥ 0.2 V L H -0.2V < VID < 0.2 V L ? VID ≤ -0.2 V L L X H Z Open L H AVAILABLE OPTIONS PACKAGE TA PLASTIC SMALL-OUTLINE† PLASTIC DUAL-IN-LINE PACKAGE (JEDEC MS-012) (JEDEC MS-001) 0°C to 70°C SN75LBC182D SN75LBC182P −40°C to 85°C SN65LBC182D SN65LBC182P †Add R suffix for taped and reel. †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 absolute maximum ratings† over operating free−air temperature range unless otherwise noted Supply voltage range, (see Note 1) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V Input voltage, V (D, DE, R or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V I Receiver output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA O Electrostatic discharge: Human body model (see Note 2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV Contact discharge (IEC61000-4-2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . . 8 kV Air discharge (IEC61000-4-2) A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR‡ TA = 70°C TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW P 1150 mW 9.2 mW/°C 736 mW 598 mW ‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. NOTE: The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V Voltage at any bus I/O terminal (separately or common mode) VI or VIC −7 12 V High-level input voltage, VIH 2 DD,, DDEE,, RREE VV Low-level input voltage, VIL 0.8 Differential input voltage, VID (see Note 3) −12 12 V Driver −60 60 OOuuttppuutt ccuurrrreenntt,, IIOO mmAA Receiver −8 4 SN65LBC182 −40 85 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA °°CC SN75LBC182 0 70 NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. www.ti.com 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 driver electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = −18 mA −1.5 V VO Output voltage IO = 0 0 VCC V RL = 54 Ω, See Figure 1 1.5 2.2 VCC V ||VVOODD|| DDiiffffeerreennttiiaall oouuttppuutt vvoollttaaggee Vtest = −7 V to 12 V, See Figure 2 1.5 2.2 VCC V ∆VOD Change in magnitude of differential output voltage −0.2 0.2 SSeeee FFiigguurree 11 VOC(SS) Steady-state common-mode output voltage 1 3 VV Change in steady-state common-mode output ∆VOC(SS) voltage −0.2 0.2 SSeeee FFiigguurreess 11 aanndd 44 Peak-to-peak change in common-mode output VOC(PP) voltage during state transitions 0.8 V IOZ High-impedance output current See receiver input currents IIH High-level input current (D, DE) VI = 2.4 V 50 µA IIL Low-level input current (D, DE) VI = 0.4 V −50 µA IOS Short-circuit output current VO = −7 V to 12 V −250 250 mA SN75LBC182 12 25 IICCCC SSuuppppllyy ccuurrrreenntt NNoo llooaadd,, DDEE aatt VVCCCC,, RREE aatt VVCCCC mmAA SN65LBC182 12 30 †All typical values are at VCC = 5 V and TA = 25°C. driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Differential output signal rise time 0.25 0.72 1.2 tf Differential output signal fall time 0.25 0.73 1.2 tPLH Propagation delay time, low-to-high-level output RRLL == 5544 ΩΩ,, CCLL == 5500 ppFF,, 1.3 µµss SSeeee FFiigguurree 33 tPHL Propagation delay time, high-to-low-level output 1.3 tsk(p) Pulse skew (tPHL − tPLH) 0.075 0.15 tPZH Output enable time to high level 3.5 RRLL == 111100 ΩΩ,, SSeeee FFiigguurree 55 µss tPHZ Output disable time from high level 3.5 tPZL Output enable time to low level 3.5 RRLL == 111100 ΩΩ,, SSeeee FFiigguurree 66 µss tPLZ Output disable time from low level 3.5 4 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage 0.2 VV VIT− Negative-going input threshold voltage −0.2 Vhys Hysteresis voltage (VIT+ − VIT-) 70 mV VIK Enable-input clamp voltage II = −18 mA −1.5 V VOH High-level output voltage VID = 200 mV, IO = −8 mA, See Figure 7 2.8 V VOL Low-level output voltage VID = 200 mV, IO = 4 mA, See Figure 7 0.4 V IOZ High-impedance-state output current VO = 0.4 to 2.4 V ±1 µA VIH = 12 V, VCC = 5 V 250 VIH = 12 V, VCC = 0 V 250 IIII BBuuss iinnppuutt ccuurrrreenntt OOtthheerr iinnppuutt aatt 00 VV µAA VIH = −7 V, VCC = 5 V −200 VIH = −7 V, VCC = 0 V −200 IIH High-level input current (RE) VIH = 2 V 50 µA IIL Low-level input current (RE) VIL = 0.8 V −50 µA DE at 0 V, RE at 0 V 3.5 mA IICCCC SSuuppppllyy ccuurrrreenntt NNoo llooaadd DE at 0 V, RE at VCC 175 250 µA †All typical values are at VCC = 5 V and TA = 25°C. receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Differential output signal rise time 20 tf Differential output signal fall time 20 CCLL == 5500 ppFF,, SSeeee FFiigguurree 77 nnss tPLH Propagation delay time, low-to-high-level output 150 tPHL Propagation delay time, high-to-low-level output 150 tPZH Output enable time to high level 100 nnss tPZL Output enable time to low level 100 SSeeee FFiigguurree 88 tPHZ Output disable time from high level 100 nnss tPLZ Output disable time from low level 100 tsk(p) Pulse skew tPHL − tPLH 50 ns www.ti.com 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION IO II 27 Ω 0 V or 3 V VOD 50 pF† IO VO 27 Ω VOC VO †Includes probe and jig capacitance Figure 1. Driver Test Circuit, V and V Without Common-Mode Loading OD OC 375 Ω Input VOD 60 Ω VTEST = −7 V to 12 V 375 Ω VTEST Figure 2. Driver Test Circuit, V With Common-Mode Loading OD 3 V Input 1.5 V 1.5 V RL = 54 Ω CL = 50 pF(cid:3) VOD 0 V Signal (cid:2) 50 Ω tPLH tPHL Generator VOD(H) 90% 90% Output 0 V 10% 10% VOD(L) tr tf †PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω ‡Includes probe and jig capacitance Figure 3. Driver Switching Test Circuit and Waveforms VOC VOC(PP) ∆VOC(SS) Figure 4. V Definitions OC 6 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION Output 3 V S1 Input 1.5 V 1.5 V 0 or 3 V 0 V tPZH 0.5 V CL = 50 pF RL = 110 Ω VOH (see Note B) Generator (see Note A) 50 Ω Output 2.3 V tPHZ Voff ≈ 0 V TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. Driver t and t Test Circuit and Voltage Waveforms PZH PHZ 5 V 3 V Input RL = 110 Ω 1.5 V 1.5 V S1 0 V Output 0 or 3 V tPZL tPLZ CL = 50 pF (see Note B) 5 V Generator (see Note A) 50 Ω Output 2.3 V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 6. Driver t and t Test Circuit and Voltage Waveforms PZL PLZ II A IO R VID Input VI B Output 50 pF VO 1.5 V RE (see Note A) 3 V Inputs 50% 50% 1.5 V 0 V tPLH tPHL VOH 90% 90% Output 50% 10% 10% VOL tr tf NOTE A: This value includes probe and jig capacitance (± 10%). Figure 7. Receiver t and t Test Circuit and Voltage Waveforms PLH PHL www.ti.com 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 5 V A 0 V or 3 V 620 Ω R B 1.5 V 50 pF 620 Ω VO RE (see Note A) Input 3 V A 0 V 3 V 3 V Inputs RE 1.5 V 0 V 0 V tPHZ tPZH tPLZ tPZL VOH ∼ 2.5 V 0.5 V 0.5 V Output VO 0.5 V 0.5 V ∼ 2.5 V VOL NOTE A: This value includes probe and jig capacitance (± 10%). Figure 8. Receiver t , t , t , and t Test Circuit and Voltage Waveforms PZL PLZ PZH PHZ 8 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS DRIVER DIFFERENTIAL OUTPUT VOLTAGE DRIVER PROPAGATION DELAY TIME vs vs TEMPERATURE TEMPERATURE 3.0 800 V e − RL = 54 Ω ag ns 780 utput Volt 2.5 VCC = 5V.2C5C V = 5 V ay Time − 760 tPHL al O Del 740 nti 2.0 on Differe VCC = 4.75 V pagati 720 tPLH − Driver 1.5 river Pro 678000 D D O − V d 660 p t 1.0 640 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 9 Figure 10 DRIVER TRANSITION TIME DIFFERENTIAL OUTPUT VOLTAGE vs vs TEMPERATURE OUTPUT CURRENT 900 4.5 4.0 800 V s − − n tf ge 3.5 me 700 olta 3.0 Ti V nsition 600 tr Output 2.5 VCC = 5.5 V t − Driver Trat 450000 − Differential D 112...050 VCC = 4.5 V VCC = 5 V O V 0.5 300 0.0 −40 −20 0 20 40 60 80 0 10 20 30 40 50 60 70 80 90 100 TA − Free-Air Temperature − °C IO − Output Current − mA Figure 11 Figure 12 www.ti.com 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) SLLS500A − MAY 2001 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS RECEIVER INPUT CURRENT vs INPUT VOLTAGE 0.25 0.20 A m 0.15 − ent 0.10 r r u ut C 0.05 p A, B (VCC = 0 V) n r I −0.00 e v ei −0.05 c e B (VCC = 5 V) R I − (I) −0.10 A (VCC = 5 V) −0.15 −0.20 −10 −5 0 5 10 15 VI − Input Voltage − V Figure 13 APPLICATION INFORMATION SN65LBC182 SN65LBC182 SN75LBC182 SN75LBC182 RT RT Up to 128 Transceivers NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 14. Typical Application Circuit 10 www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65LBC182D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 & no Sb/Br) SN65LBC182DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 & no Sb/Br) SN65LBC182DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 6LB182 & no Sb/Br) SN65LBC182P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 65LBC182 & no Sb/Br) SN75LBC182D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 & no Sb/Br) SN75LBC182DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 & no Sb/Br) SN75LBC182DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7LB182 & no Sb/Br) SN75LBC182P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 75LBC182 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65LBC182DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75LBC182DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65LBC182DR SOIC D 8 2500 340.5 338.1 20.6 SN75LBC182DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated