SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 (cid:0) Meet or Exceed the Requirements of SN65C1406...D PACKAGE TIA/EIA-232-F and ITU Recommendation SN75C1406...D, DW, N, OR NS PACKAGE (TOP VIEW) V.28 (cid:0) Very Low Power Consumption... VDD 1 16 VCC 5 mW Typ 1RA 2 15 1RY (cid:0) Wide Driver Supply Voltage Range... 1DY 3 14 1DA ±4.5 V to ±15V 2RA 4 13 2RY (cid:0) Driver Output Slew Rate Limited to 2DY 5 12 2DA 30 V/µs Max 3RA 6 11 3RY (cid:0) 3DY 7 10 3DA Receiver Input Hysteresis...1000 mV Typ (cid:0) VSS 8 9 GND Push-Pull Receiver Outputs (cid:0) On-Chip Receiver 1-µs Noise Filter (cid:0) Functionally Interchangeable With Motorola MC145406 and Texas Instruments TL145406 (cid:0) Package Options Include Plastic Small-Outline (D, DW, NS) Packages and DIPs (N) description The SN65C1406 and SN75C1406 are low-power BiMOS devices containing three independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1406 and SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the receivers have filters that reject input noise pulses shorter than 1 µs. Both these features eliminate the need for external components. The SN65C1406 and SN75C1406 are designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1406 and SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. The SN65C1406 is characterized for operation from –40°C to 85°C. The SN75C1406 is characterized for operation from 0°C to 70°C. AVAILABLE OPTIONS PACKAGED DEVICES SMALL SMALL PLASTIC PLASTIC TA OUTLINE OUTLINE DIP SMALL OUTLINE (D) (DW) (N) (NS) –40°C to 85°C SN65C1406D — — — 0°C to 70°C SN75C1406D SN75C1406DW SN75C1406N SN75C1406NS The D, DW, and PW packages are available taped and reeled. Add the suffix R to device type (e.g., SN75C1406DR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 logic diagram (positive logic) Typical of Each Receiver 2, 4, 6 15, 13, 11 RA RY Typical of Each Driver 3, 5, 7 14, 12, 10 DY DA 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 schematics of inputs and outputs EQUIVALENT DRIVER INPUT EQUIVALENT DRIVER OUTPUT VDD VDD Input Internal DA 1.4-V Reference 160 Ω Output 74 Ω DY VSS GND 72 Ω VSS EQUIVALENT RECEIVER INPUT EQUIVALENT RECEIVER OUTPUT VCC 3.4 kΩ Input RA Output 1.5 kΩ RY ESD ESD Protection Protection 530 Ω GND GND All resistor values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage: VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V SS V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage range, V: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V I SS DD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V Output voltage range, V : Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V – 6 V) to (V + 6 V) O SS DD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V + 0.3 V) CC Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150 °C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to the network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 4.5 12 15 V VSS Supply voltage –4.5 –12 –15 V VCC Supply voltage 4.5 5 6 V Driver VSS+2 VDD VVII IInnppuutt vvoollttaaggee VV Receiver ±25 VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current –1 mA IOL Low-level output curren 3.2 mA SN65C1406 –40 85 TTAA OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree °°CC SN75C1406 0 70 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 DRIVER SECTION electrical characteristics over operating free-air temperature range, V = 12 V, V = –12 V, DD SS V = 5 V ±10% (unless otherwise noted) CC PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VIIHH = 0.8 V,, RL = 3 kΩ, VDD = 5 V, VSS = –5 V 4 4.5 VV See Figure 1 VDD = 12 V, VSS = –12 V 10 10.8 VVOOLL Low-level output voltagge VIIHH = 2 V,, RL = 3 kΩ, VDD = 5 V, VSS = –5 V –4.4 –4 VV (see Note 3) See Figure 1 VDD = 12 V, VSS = –12 V –10.7 –10 IIH High-level input current VI = 5 V, See Figure 2 1 µA IIL Low-level input current VI = 0, See Figure 2 –1 µA High-level short-circuit IOS(H) output current‡ VI = 0.8 V, VO = 0 or VSS, See Figure 1 –7.5 –12 –19.5 mA Low-level short-circuit IOS(L) output current‡ VI = 2 V, VO = 0 or VDD, See Figure 1 7.5 12 19.5 mA No load,, VDD = 5 V, VSS = –5 V 115 250 IIDDDD SSuuppppllyy ccuurrrreenntt ffrroomm VVDDDD µµAA All inputs at 2 V or 0.8 V VDD = 12 V, VSS = –12 V 115 250 No load,, VDD = 5 V, VSS = –5 V –115 –250 IISSSS SSuuppppllyy ccuurrrreenntt ffrroomm VVSSSS µµAA All inputs at 2 V or 0.8 V VDD = 12 V, VSS = –12 V –115 –250 rO Output resistance VDD = VSS = VCC = 0, VO = –2 V to 2 V, 300 400 Ω See Note 4 †All typical values are at TA = 25°C. ‡Not more than one output should be shorted at a time. NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 4. Test conditions are those specified by TIA/EIA-232-F. switching characteristics at T = 25°C, V = 12 V, V = –12 V, V = 5 V ± 10% A DD SS CC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output§ RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 15 pF, 1.2 3 µs tPHL Propagation delay time, high- to low-level output§ RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 15 pF, 2.5 3.5 µs tTLH Transition time, low- to high-level output¶ RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 15 pF, 0.53 2 3.2 µs tTHL Transition time, high- to low-level output¶ RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 15 pF, 0.53 2 3.2 µs tTLH Transition time, low- to high-level output# RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 2500 pF, 1 2 µs tTHL Transition time, high- to low-level output# RSeLe = F 3ig kuΩre t o3 7 kΩ, CL = 2500 pF, 1 2 µs SR Output slew rate RL = 3 kΩ to 7 kΩ, CL = 15 pF, 4 10 30 V/µs See Figure 3 §tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points. ¶Measured between 10% and 90% points of output waveform #Measured between 3-V and –3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 RECEIVER SECTION electrical characteristics over operating free-air temperature range, V = 12 V, V = –12 V, DD SS V = 5 V ±10% (unless otherwise noted) CC PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Positive-going input VIT+ threshold voltage See Figure 5 1.7 2 2.55 V Negative-going input VIT– threshold voltage See Figure 5 0.65 1 1.25 V Input hysteresis voltage Vhys (VIT+–VIT–) 600 1000 mV VI = 0.75 V, IOH = –20 µA, See Figure 5 and Note 5 3.5 VCC = 4.5 V 2.8 4.4 VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VVI = 00.7755 VV, IIOH = –11 mAA, VCC = 5 V 3.8 4.9 VV SSeeee FFiigguurree 55 VCC = 5.5 V 4.3 5.4 VOL Low-level output voltage VI = 3 V, IOL = 3.2 mA, See Figure 5 0.17 0.4 V VI = 2.5 V 3.6 4.6 8.3 IIIIHH HHiigghh-lleevveell iinnppuutt ccuurrrreenntt mmAA VI = 3 V 0.43 0.55 1 VI = –2.5 V –3.6 –5 –8.3 IIIILL LLooww-lleevveell iinnppuutt ccuurrrreenntt mmAA VI = –3 V –0.43 –0.55 –1 Higgh-level short-circuit IIOOSS((HH)) VVII == 00.7755 VV, VVOO == 00, SSeeee FFiigguurree 44 –88 –1155 mmAA output current Low-level short-circuit IIOOSS((LL)) VVII == VVCCCC, VVOO == VVCCCC, SSeeee FFiigguurree 44 1133 2255 mmAA output current No load, VDD = 5 V, VSS = –5 V 320 450 IICCCC SSuuppppllyy ccuurrrreenntt ffrroomm VVCCCC All inputs at 0 or 5 V VDD = 12 V, VSS = –12 V 320 450 µµAA †All typical values are at TA = 25°C. NOTE 5: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs remain in the high state. switching characteristics at T = 25°C, V = 12 V, V = –12 V, V = 5 V ± 10% (unless otherwise A DD SS CC noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output CL = 50 pF, RL = 5 kΩ, 3 4 µs See Figure 6 tPHL Propagation delay time, high- to low-level output CL = 50 pF, RL = 5 kΩ, 3 4 µs See Figure 6 tTLH Transition time, low- to high-level output‡ CL = 50 pF, RL = 5 kΩ, 300 450 ns See Figure 6 tTHL Transition time, high- to low-level output‡ CL = 50 pF, RL = 5 kΩ, 100 300 ns See Figure 6 tw(N) Duration of longest pulse rejected as noise§ CL = 50 pF, RL = 5 kΩ 1 4 µs ‡Measured between 10% and 90% points of output waveform §The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION IOS(L) VDD VCC VDD or GND VDD –IOS(H) IIH VCC VI VSS or GND VI –IIL VO RL = 3 kΩ VI VSS VSS Figure 1. Driver Test Circuit VOH, VOL, IOS(L), IOS(H) Figure 2. Driver Test Circuit, IIL, IIH VDD 3 V Input VCC Input 1.5 1.5 0 V Pulse Generator tPHL tPLH (See Note B) VOH 90% 90% RL CL 50% 50% (see Note A) Output 10% 10% VOL VSS tTHL tTLH TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. Figure 3. Driver Test Circuit and Voltage Waveforms VDD VDD VCC –IOS(H) VCC VI VIT, VI IOS(L) VOH –IOH VCC VOL IOL VSS VSS Figure 4. Receiver Test Circuit, IOS(H), IOS(L) Figure 5. Receiver Test Circuit, VIT, VOL, VOH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 4 V VDD Input 50% 50% Input VCC 0 V Pulse Generator tPHL tPLH (See Note B) VOH RL CL 90% 50% 50% 90% (see Note A) Output 10% 10% VOL VSS tTHL tTLH TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: C. CL includes probe and jig capacitance. D. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. Figure 6. Receiver Test Circuit and Voltage Waveforms APPLICATION INFORMATION The TIA/EIA-232-F specification is for data interchange between a host computer and a peripheral at signaling rates up to 20 kbit/s. Many TIA/EIA-232-F devices will operate at higher data rates with lower capacitive loads (short cables). For reliable operation at greater than 20 kbit/s, the designer needs to have control of both ends of the cable. By mixing different types of TIA/EIA-232-F devices and cable lengths, errors can occur at higher frequencies (above 20 kbit/s). When operating within the TIA/EIA-232-F requirements of less than 20 kbit/s and with compliant line circuits, interoperability is assured. For applications operating above 20 kbit/s, the design engineer should consider devices and system designs that meet the TIA/EIA-232-F requirements. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65C1406D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C1406 & no Sb/Br) SN65C1406DE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C1406 & no Sb/Br) SN65C1406DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65C1406 & no Sb/Br) SN75C1406D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) SN75C1406DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) SN75C1406DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) SN75C1406DWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) SN75C1406DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) SN75C1406N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN75C1406N & no Sb/Br) SN75C1406NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65C1406DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN75C1406DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN75C1406DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN75C1406NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65C1406DR SOIC D 16 2500 333.2 345.9 28.6 SN75C1406DR SOIC D 16 2500 333.2 345.9 28.6 SN75C1406DWR SOIC DW 16 2000 350.0 350.0 43.0 SN75C1406NSR SO NS 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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