SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 (cid:0) Meet or Exceed the Requirements of SN65ALS180...D PACKAGE TIA/EIA-422-B, TIA/EIA-485-A† and SN75ALS180...D OR N PACKAGE (TOP VIEW) ITU Recommendation V.11 (cid:0) High-Speed Advanced Low-Power Schottky NC 1 14 VCC Circuitry R 2 13 VCC (cid:0) Designed for 25-Mbaud Operation in Both RE 3 12 A Serial and Parallel Applications DE 4 11 B (cid:0) Low Skew Between Devices...6 ns Max D 5 10 Z (cid:0) GND 6 9 Y Low Supply-Current Requirements GND 7 8 NC ...30 mA Max (cid:0) Individual Driver and Receiver I/O Pins With NC – No internal connection Dual V and Dual GND CC (cid:0) Wide Positive and Negative Input/Output Bus Voltage Ranges (cid:0) Driver Output Capacity...±60 mA (cid:0) Thermal Shutdown Protection (cid:0) Driver Positive- and Negative-Current Limiting (cid:0) Receiver Input Impedance...12 kΩ Min (cid:0) Receiver Input Sensitivity...±200 mV Max (cid:0) Receiver Input Hysteresis...60 mV Typ (cid:0) Operate From a Single 5-V Supply (cid:0) Glitch-Free Power-Up and Power-Down Protection description/ordering information The SN65ALS180 and SN75ALS180 differential driver and receiver pairs are integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed for balanced transmission lines and meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendation V.11. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP (N) Tube of 25 SN75ALS180N SN75ALS180N 0°C to 70°C Tube of 50 SN75ALS180D SSOOIICC ((DD)) 7755AALLSS118800 Reel of 2500 SN75ALS180DR Tube of 50 SN65ALS180D ––4400°°CC ttoo 8855°°CC SSOOIICC ((DD)) 6655AALLSS118800 Reel of 2500 SN65ALS180DR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †These devices meet or exceed the requirements of TIA/EIA-485-A, except for the Generator Contention Test (para. 3.4.2) and the Generator Current Limit (para. 3.4.3). The applied test voltage ranges are –6 V to 8 V for the SN75ALS180 and –4 V to 8 V for the SN65ALS180. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 description/ordering information (continued) The SN65ALS180 and SN75ALS180 combine a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected to separate terminals for greater flexibility and are designed to offer minimum loading to the bus when the driver is disabled or V = 0. CC These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Function Tables DRIVER INPUT ENABLE OUTPUTS D DE Y Z H H H L L H L H X L Z Z RECEIVER DIFFERENTIAL INPUTS ENABLE OUTPUT A–B RE R VID ≥ 0.2 V L H –0.2 V < VID < 0.2 V L ? VID ≤ –0.2 V L L X H Z Open L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic diagram (positive logic) 4 DE 9 5 Y D 10 Z 3 RE 12 2 A R 11 B 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 schematics of inputs and outputs EQUIVALENT OF EACH INPUT RECEIVER A INPUT RECEIVER B INPUT VCC VCC VCC 180 kΩ R(eq) NOM 3 kΩ NOM 3 kΩ 18 kΩ 18 kΩ NOM Input NOM NOM Input Input 180 kΩ NOM 1.1 kΩ 1.1 kΩ NOM NOM Driver and Driver Enable Inputs: R(eq) = 12 kΩ NOM Receiver Enable Input: R(eq) = 30 kΩ NOM R(eq) = Equivalent Resistor DRIVER OUTPUT TYPICAL OF RECEIVER OUTPUT VCC VCC 85 Ω NOM Output Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V Enable input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W JA N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C st †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. θ 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V 12 VVII oorr VVIICC VVoollttaaggee aatt aannyy bbuuss tteerrmmiinnaall ((sseeppaarraatteellyy oorr ccoommmmoonn mmooddee)) VV –7 VIH High-level input voltage D, DE, and RE 2 V VIL Low-level input voltage D, DE, and RE 0.8 V VID Differential input voltage (see Note 4) ±12 V Driver –60 mA IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt Receiver –400 µA Driver 60 IIOOLL LLooww-lleevveell oouuttppuutt ccuurrrreenntt mmAA Receiver 8 SN65ALS180 –40 85 TTAA OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree °°CC SN75ALS180 0 70 NOTE 4: Differential-input/output bus voltage is measured at the noninverting terminal, A/Y, with respect to the inverting terminal, B/Z. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 DRIVERS electrical characteristics over recommended ranges of supply voltage and operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT VIK Input clamp voltage II = –18 mA –1.5 V VO Output voltage IO = 0 0 6 V |VOD1| Differential output voltage IO = 0 1.5 6 V |VOODD22| Differential output voltagge RL = 100 Ω, See Figure 1 1/2 VoOr D21§ V RL = 54 Ω, See Figure 1 1.5 2.5 5 VOD3 Differential output voltage Vtest = –7 V to 12 V, See Figure 2 1.5 5 V Change in magnitude of ∆|VOD| differential output voltage¶ RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V 3 VOC Common-mode output voltage RL = 54 Ω or 100 Ω, See Figure 1 –1 V Change in magnitude of ∆|VOC| common-mode output voltage¶ RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V Output disabled VO = 12 V 1 IIOO OOuuttppuutt ccuurrrreenntt mmAA (see Note 5) VO = –7 V –0.8 IIH High-level input current VI = 2.4 V 20 µA IIL Low-level input current VI = 0.4 V –400 µA VO = –6 V SN75ALS180 –250 VO = –4 V SN65ALS180 –250 IOS Short-circuit output current### VO = 0 All –150 mA VO = VCC All 250 VO = 8 V All 250 Driver outputs enabled, 25 30 ICCCC Supplyy current No load Receiver disabled mA Outputs disabled 19 26 †The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs. ‡All typical values are at VCC = 5 V, TA = 25°C. §The minimum VOD2 with 100-Ω load is either 1/2 VOD2 or 2 V, whichever is greater. ¶∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. #Duration of the short circuit should not exceed one second for this test. NOTE 5: This applies for both power on and off; refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a combined driver and receiver terminal. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT td(OD) Differential output delay time RL = 54 Ω, CL = 50 pF, See Figure 3 3 8 13 ns Pulse skew (td(ODH) – td(ODL)) RL = 54 Ω, CL = 50 pF, See Figure 3 1 6 ns tt(OD) Differential output transition time RL = 54 Ω, CL = 50 pF, See Figure 3 3 8 13 ns tPZH Output enable time to high level RL = 110 Ω, See Figure 4 23 50 ns tPZL Output enable time to low level RL = 110 Ω, See Figure 5 19 24 ns tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 8 13 ns tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 8 13 ns ‡All typical values are at VCC = 5 V and TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 SYMBOL EQUIVALENTS DATA-SHEET TIA/EIA-422-B TIA/EIA-485-A PARAMETER VO Voa, Vob Voa, Vob |VOD1| Vo Vo |VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω) Vt |VOD3| (test termination measurement 2) Vtest Vtst ∆|VOD| ||Vt| – |Vt|| ||Vt| – |Vt|| VOC |Vos| |Vos| ∆|VOC| |Vos – Vos| |Vos – Vos| IOS |Isa|, |Isb| IO |Ixa|, |Ixb| Iia, Iib RECEIVERS electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Positive-going input threshold VIT+ voltage VO = 2.7 V, IO = –0.4 mA 0.2 V Negative-going input threshold VIT– voltage VO = 0.5 V, IO = 8 mA –0.2‡ V Vhys Hysteresis voltage (VIT+ – VIT–) 60 mV VIK Enable-input clamp voltage II = –18 mA –1.5 V VOH High-level output voltage VID = 200 mV, IOH = –400 µA, See Figure 6 2.7 V VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, See Figure 6 0.45 V IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA Other input = 0 V VI = 12 V 1 IIII LLiinnee iinnppuutt ccuurrrreenntt mmAA (see Note 6) VI = –7 V –0.8 IIH High-level enable-input current VIH = 2.7 V 20 µA IIL Low-level enable-input current VIL = 0.4 V –100 µA ri Input resistance 12 kΩ IOS Short-circuit output current VID = 200 mV, VO = 0 –15 –85 mA Receiver outputs enabled, 19 30 ICCCC Supplyy current No load Driver inputs disabled mA Outputs disabled 19 26 †All typical values are at VCC = 5 V, TA = 25°C. ‡The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOTE 6: This applies for both power on and power off. Refer to TIA/EIA-485-A for exact conditions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VID = –1.5 V to 1.5 V, CL = 15 pF, tPLH Propagation delay time, low- to high-level output See Figure 7 9 14 19 ns VID = –1.5 V to 1.5 V, CL = 15 pF, tPHL Propagation delay time, high- to low-level output See Figure 7 9 14 19 ns VID = –1.5 V to 1.5 V, CL = 15 pF, Skew (|tPHL – tPLH|) See Figure 7 2 6 ns tPZH Output enable time to high level CL = 15 pF, See Figure 8 7 14 ns tPZL Output enable time to low level CL = 15 pF, See Figure 8 7 14 ns tPHZ Output disable time from high level CL = 15 pF, See Figure 8 20 35 ns tPLZ Output disable time from low level CL = 15 pF, See Figure 8 8 17 ns †All typical values are at VCC = 5 V, TA = 25°C. PARAMETER MEASUREMENT INFORMATION R L 2 VOD2 RL VOC 2 Figure 1. Driver V and V OD OC 375 Ω 60 Ω VOD3 Vtest 375 Ω Figure 2. Driver V OD3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION 3 V Input 1.5 V 1.5 V CL = 50 pF 0 V (see Note A) Output td(ODH) td(ODL) Generator 50 Ω RL = 54 Ω 90% ≈2.5 V (see Note B) Output 50% 50% 10% 10% ≈–2.5 V 3 V tt(OD) tt(OD) TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO=50Ω. Figure 3. Driver Test Circuit and Voltage Waveforms Output 3 V S1 Input 1.5 V 1.5 V 0 V or 3 V 0 V CL = 50 pF RL = 110 Ω tPZH 0.5 V (see Note A) Generator VOH (see Note B) 50 Ω Output 2.3 V Voff ≈ 0 V tPHZ TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO=50Ω. Figure 4. Driver Test Circuit and Voltage Waveforms 5 V RL = 110 Ω 3 V S1 Output 0 V or 3 V Input 1.5 V 1.5 V CL = 50 pF 0 V (see Note A) tPZL tPLZ Generator (see Note B) 50 Ω 5 V Output 2.3 V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO=50Ω. Figure 5. Driver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VID VOH +IOL –IOH VOL Figure 6. Receiver V and V OH OL 3 V Input 1.5 V 1.5 V 0 V Output tPLH tPHL Generator (see Note B) 51 Ω VOH 1.5 V CL = 15 pF (see Note A) Output 1.3 V 1.3 V 0 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO=50Ω. Figure 7. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION 1.5 V S1 S2 2 kΩ –1.5 V 5 V CL = 15 pF (see Note A) 5 kΩ 1N916 or Equivalent Generator (see Note B) 50 Ω S3 TEST CIRCUIT 3 V 3 V S1 to 1.5 V S1 to –1.5 V Input 1.5 V S2 Open Input 1.5 V S2 Closed S3 Closed S3 Open 0 V 0 V tPZH tPZL ≈ VOH 4.5 V Output 1.5 V Output 1.5 V 0 V VOL 3 V 3 V S1 to 1.5 V S1 to –1.5 V Input 1.5 V S2 Closed Input 1.5 V S2 Closed S3 Closed S3 Closed 0 V 0 V tPHZ tPLZ VOH ≈1.3 V 0.5 V Output Output 0.5 V ≈ 1.3 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO=50Ω. Figure 8. Receiver Test Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS – DRIVERS HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 5 5 VCC = 5 V 4.5 4.5 TA = 25°C Output Voltage – V 23..4355 Output Voltage – V 23..4355 h-Level 2 w-Level 2 g 1.5 o 1.5 – Hi – LL H 1 O 1 O V V 0.5 VCC = 5 V 0.5 TA = 25°C 0 0 0 –20 –40 –60 –80 –100 –120 0 20 40 60 80 100 120 IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA Figure 9 Figure 10 DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 4 3.5 V – e g 3 a olt V ut 2.5 p ut O al 2 nti re 1.5 e Diff – 1 D O V 0.5 VCC = 5 V TA = 25°C 0 0 10 20 30 40 50 60 70 80 90 100 IO – Output Current – mA Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS – RECEIVERS HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE 5 5 VID = 0.2 V VCC = 5 V TA = 25°C VID = 200 mV – V V IOH = –440 µA e 4 – 4 Output Voltag 3 VCC = 5.25 V utput Voltage 3 h-Level 2 VCC = 5 V Level O 2 Hig gh- – Hi VOH 1 VCC = 4.75 V – OH 1 V 0 0 0 –10 –20 –30 –40 –50 –40 –20 0 20 40 60 80 100 120 IOH – High-Level Output Current – mA TA – Free-Air Temperature – °C Figure 12 Figure 13 LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE 0.6 0.6 VCC = 5 V VCC = 5 V TA = 25°C VID = –200 mA V 0.5 VID = –200 mV V 0.5 IOL = 8 mA ge – ge – Volta 0.4 Volta 0.4 ut ut p p Out 0.3 Out 0.3 w-Level 0.2 w-Level 0.2 o o L L – – OL 0.1 OL 0.1 V V 0 0 0 5 10 15 20 25 30 –40 –20 0 20 40 60 80 100 120 IOL – Low-Level Output Current – mA TA – Free-Air Temperature – °C Figure 14 Figure 15 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65ALS180, SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS SLLS052G – AUGUST 1987 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS – RECEIVERS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs ENABLE VOLTAGE ENABLE VOLTAGE 5 6 VID = 0.2 V VID = 0.2 V Load = 8 kΩ to GND Load = 1 kΩ to VCC VCC = 5.25 V TA = 25°C 5 TA = 25°C 4 VCC = 5.25 V V V VCC = 4.75 V – – e e 4 ag 3 VCC = 4.75 V ag VCC = 5 V olt VCC = 5 V olt V V ut ut 3 p p ut 2 ut O O – – 2 O O V V 1 1 0 0 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 VI – Enable Voltage – V VI – Enable Voltage – V Figure 16 Figure 17 APPLICATION INFORMATION SN65ALS180 SN65ALS180 SN75ALS180 SN75ALS180 RT RT Up to 32 Transceivers NOTE A: The line should terminate at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 18. Typical Application Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN65ALS180D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65ALS180 & no Sb/Br) SN65ALS180DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65ALS180 & no Sb/Br) SN65ALS180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 65ALS180 & no Sb/Br) SN75ALS180D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS180 & no Sb/Br) SN75ALS180DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS180 & no Sb/Br) SN75ALS180DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS180 & no Sb/Br) SN75ALS180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS180 & no Sb/Br) SN75ALS180N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN75ALS180N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN65ALS180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN75ALS180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN65ALS180DR SOIC D 14 2500 367.0 367.0 38.0 SN75ALS180DR SOIC D 14 2500 367.0 367.0 38.0 PackMaterials-Page2

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