SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 • Characterized for Use to 300 mA D OR P PACKAGE • (TOP VIEW) No Output Latch-Up at 55 V (After Conducting 300 mA) • S 1 8 VCC High-Voltage Outputs (100 V Typ) 1A 2 7 2A • Output Clamp Diodes for Transient 1Y 3 6 2Y Suppression (300 mA, 70 V) GND 4 5 CLAMP • TTL- or MOS-Compatible Diode-Clamped Inputs • Function Tables pnp Transistor Inputs Reduce Input Current • SN75476 Standard Supply Voltage (each AND driver) • Suitable for Hammer-Driver Applications INPUTS OUTPUT • Plastic DIP (P) With Copper-Lead Frame A S Y Provides Cooler Operation and Improved H H H Reliability L X L X L L description SN75477 The SN75476 through SN75478 are dual (each NAND driver) peripheral drivers designed for use in systems that INPUTS OUTPUT require high current, high voltage, and fast A S Y switching times. The SN75476, SN75477, and H H L SN75478 provide AND, NAND, and OR drivers L X H respectively. These devices have diode-clamped X L H inputs as well as high-current, high-voltage clamp diodes on the outputs for inductive transient SN75478 protection. (each OR driver) The SN75476, SN75477, and SN75478 drivers INPUTS OUTPUT are characterized for operation from 0°C to 70°C. A S Y H X H X H H schematics of inputs and outputs L L L H = high level, L = low level EQUIVALENT TYPICAL X = irrelevant OF EACH INPUT OF ALL OUTPUTS CLAMP VCC Output Input GND PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 logic symbols† logic diagrams (positive logic) SN75476 2 SN75476 3 1Y 2 3 1A 1A & 1Y 1 1 CLAMP S 6 S 6 2Y 2Y 7 5 7 2A CLAMP 2A 5 CLAMP 4 GND Positive Logic: Y = AS or A+S SN75477 SN75477 2 3 1Y 2 3 1A 1A & 1Y 1 1 CLAMP S 6 S 6 2Y 2Y 7 5 7 2A CLAMP 2A 5 CLAMP 4 GND Positive Logic: Y = AS or A+S SN75478 SN75478 2 3 1Y 2 3 1A 1A ≥1 1Y 1 1 CLAMP S 6 S 6 2Y 2Y 7 5 7 2A CLAMP 2A 5 CLAMP 4 GND Positive Logic: Y = A+S or A S †These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC publication 617-12. 2 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I Continuous output current (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Peak output current: t ≤ 10 ms, duty cycle ≤ 50% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA w t ≤ 30 ns, duty cycle ≤ 0.002% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A w Output clamp current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA OK Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. Voltage values are with respect to network GND. 2. Both halves of this dual circuit may conduct rated current simultaneously; however, power dissipation averaged over a short time interval must fall within the continuous power dissipation ratings. DISSIPATION RATING TABLE PPAACCKKAAGGEE TAA ≤ 25°C DERATING FACTOR TAA = 70°C POWER RATING ABOVE TA = 25°C POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 5 5.5 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Operating free-air temperature, TA 0 70 °C POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 3 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = –12 mA –0.95 –1.5 V VVCCCC == 44..55 VV,, IOL = 100 mA 0.16 0.3 VOL Low-level output voltage VIH = 2 V, IOL = 175 mA 0.22 0.5 V VIL = 0.8 V IOL = 300 mA 0.33 0.6 VO(BR) Output breakdown voltage VCC = 4.5 V, IOH = 100 m A 70 100 V VR(K) Output clamp reverse voltage VCC = 4.5 V, IR = 100 m A 70 100 V VF(K) Output clamp forward voltage VCC = 4.5 V, IF = 300 mA 0.8 1.15 1.6 V IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCCCC = 4.5 V,, VIIHH = 2 V,, 11 110000 mm AA VIL = 0.8 V, VOH = 70 V IIH High-level input current VCC = 5.5 V, VI = 5.5 V 0.01 10 m A A input –80 –110 IIIILL LLooww-lleevveell iinnppuutt ccuurrrreenntt VVCCCC == 55.55 VV, VVII == 00.88 VV mm AA S input –160 –220 SN75476 VI = 5 V 10 17 ICCH Supply current, outputs high SN75477 VCC = 5.5 V VI = 0 10 17 mA SN75478 VI = 5 V 10 17 SN75476 VI = 0 54 75 ICCL Supply current, outputs low SN75477 VCC = 5.5 V VI = 5 V 54 75 mA SN75478 VI = 0 54 75 †All typical values are at VCC = 5 V, TA = 25°C. switching characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 200 350 ns tPHL Propagation delay time, high-to-low-level output CLL = 15 pF,, RLL = 100 W ,, 200 350 ns tTLH Transition time, low-to-high-level output See Figure 1 50 125 ns tTHL Transition time, high-to-low-level output 90 125 ns VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee aafftteerr sswwiittcchhiinngg VSS = 55 V,, IOO ≈ 300 mA,, VVSS–1188 mmVV See Figure 2 4 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION Input 2.4 V VCC 30 V SN75476 RL = 100 W SN75477 A/S Output Circuit Pulse S/A Under Generator Test (see Note A) CL = 15 pF (see Note B) SN75478 0.4 V Open TEST CIRCUIT ≤ 5 ns ≤10 ns 3 V 2.7 V 2.7 V SN75446 Input 1.5 V 1.5 V SN75448 0.7 V 0.7 V 0 V 5 m s ≤ 5 ns ≤ 10 ns 3 V SN75447 Input 2.7 V 2.7 V 1.5 V 1.5 V 0.7 V 0.7 V 0 V tPHL tPLH VOH 90% 90% Output 50% 50% 10% 10% VOL tTHL tTLH VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR = 100 kHz, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Switching Characteristics POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 5 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

SN75476 THRU SN75478 DUAL PERIPHERAL DRIVERS SLRS025A – DECEMBER 1976 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION VS = 55 V Input 2.4 V 5 V 2 mH SN75476 SN75477 180 W Pulse A Generator (see Note A) Circuit Output S Under Test CL = 15 pF (see Note B) SN75478 GND 0.4 V TEST CIRCUIT ≤ 5 ns ≤10 ns 3 V 90% 90% SN75476 SN75478 Input 1.5 V 1.5 V 10% 10% 0 V 40 m s ≤ 5 ns ≤ 10 ns 3 V SN75477 Input 90% 90% 1.5 V 1.5 V 10% 10% 0 V VOH Output VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 2. Latch-Up Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN75477D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75477 & no Sb/Br) SN75477DE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75477 & no Sb/Br) SN75477DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75477 & no Sb/Br) SN75477DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75477 & no Sb/Br) SN75477DRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 75477 & no Sb/Br) SN75477P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN75477P & no Sb/Br) SN75477PE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN75477P & no Sb/Br) SN75478P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN75478P & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN75477DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN75477DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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