SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 (cid:1) Meets IEEE Standard 488-1978 (GPIB) (cid:1) 8-Channel Bidirectional Transceiver (cid:1) DW OR N PACKAGE Power-Up/Power-Down Protection (TOP VIEW) (Glitch Free) (cid:1) TE VCC High-Speed, Low-Power Schottky Circuitry 1 20 (cid:1) Low Power Dissipation...72 mW Max Per B1 2 19 D1 Channel B2 3 18 D2 (cid:1) B3 4 17 D3 (cid:1) FHaigsht -PImroppeadgaantcioen p Tnipm Iensp.u.ts.22 ns Max I/O GPoPrItBs BB45 56 1165 DD45 TI/eOr mPionratsl (cid:1) Receiver Hysteresis...650 mV Typ B6 7 14 D6 (cid:1) Open-Collector Driver Output Option B7 8 13 D7 (cid:1) B8 9 12 D8 No Loading of Bus When Device Is GND 10 11 PE Powered Down (V = 0) CC description The SN75160B 8-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed, low-power Schottky device designed for two-way data communications over single-ended transmission lines. It is designed to meet the requirements of IEEE Standard 488-1978. The transceiver features driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current. Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus and receiver outputs. The outputs do not load the bus when V = 0. When combined with the SN75161B or CC SN75162B management bus transceivers, the pair provides the complete 16-wire interface for the IEEE-488 bus. The SN75160B is characterized for operation from 0°C to 70°C. Function Tables EACH DRIVER EACH RECEIVER INPUTS OUTPUT INPUTS OUTPUT D TE PE B B TE PE D H H H H L L X L L H X L H L X H H X L Z† X H X Z X L X Z† H = high level, L = low level, X = irrelevant, Z = high impedance †This is the high-impedance state of a normal 3-state output modified by the internal resistors to VCC and GND. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 logic symbol† logic diagram (positive logic) 11 11 PE PE M1[3S] 1 M2[0C] TE 1 TE EN3[XMT] EN4[RCV] 19 D1 19 D1 2 2 3(1 /2 ) B1 B1 4 1 18 18 3 D2 D2 B2 17 4 D3 B3 16 5 3 D4 B4 B2 15 6 D5 B5 17 14 7 D3 D6 B6 13 8 D7 B7 12 9 4 D8 B8 B3 †This symbol is in accordance with ANSI/IEEE Std 91-1984 D4 16 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs Terminal 5 I/O Ports B4 15 D5 GPIB I/O Ports 6 B5 14 D6 7 B6 13 D7 8 B7 12 D8 9 B8 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS EQUIVALENT OF ALL INPUT/OUTPUT PORTS VCC 9 kW R(eq) 1.7 kW 10 kW NOM NOM NOM Input 4 kW NOM 4 kW NOM GND Input/Output Port Driver output R(eq) = 30 W NOM Receiver output R(eq) = 110 W NOM Circuit inside dashed lines is on the driver outputs only. R(eq) = equivalent resistor absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I Low-level driver output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA OL Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING DW 1125 mW 9.0 mW/°C 720 mW N 1150 mW 9.2 mW/°C 736 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Bus ports with pullups active –5.2 mA HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt, IIOOHH Terminal ports –800 m A Bus ports 48 LLooww-lleevveell oouuttppuutt ccuurrrreenntt, IIOOLL mmAA Terminal ports 16 Operating free-air temperature, TA 0 70 °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = –18 mA –0.8 –1.5 V Hysteresis voltage Vhys (VIT+ – VIT–) Bus See Figure 8 0.4 0.65 V Terminal IOH = –800 m A, TE at 0.8 V 2.7 3.5 VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VV Bus IOH = –5.2 mA, PE and TE at 2 V 2.5 3.3 Terminal IOL = 16 mA, TE at 0.8 V 0.3 0.5 VVOOLL LLooww-lleevveell oouuttppuutt vvoollttaaggee VV Bus IOL = 48 mA, TE at 2 V 0.35 0.5 Input current at maximum IIII TTeerrmmiinnaall VVII == 55.55 VV 00.22 110000 mm AA input voltage IIH High-level input current Terminal VI = 2.7 V 0.1 20 m A IIL Low-level input current Terminal VI = 0.5 V –10 –100 m A II(bus) = 0 2.5 3.0 3.7 VVII//OO((bbus)) VVoollttaaggee aatt bbuuss ppoorrtt DDrriivveerr ddiissaabblleedd VV II(bus) = –12 mA –1.5 VI(bus) = –1.5 V to 0.4 V –1.3 VI(bus) = 0.4 V to 2.5 V 0 –3.2 2.5 PPoowweerr oonn DDrriivveerr ddiissaabblleedd VVII((bbus)) == 22.55 VV ttoo 33.77 VV II/O((bus)) Current into bus port –3.2 mA VI(bus) = 3.7 V to 5 V 0 2.5 VI(bus) = 5 V to 5.5 V 0.7 2.5 Power off VCC = 0, VI(bus) = 0 to 2.5 V –40 Terminal –15 –35 –75 IIOOSS SShhoorrtt-cciirrccuuiitt oouuttppuutt ccuurrrreenntt mmAA Bus –25 –50 –125 Receivers low and enabled 70 90 IICCCC SSuuppppllyy ccuurrrreenntt NNoo llooaadd mmAA Drivers low and enabled 85 110 VCCCC = 0 to 5 V, VII//OO = 0 to 2 V, CCII//OO((bbus)) BBuuss-ppoorrtt ccaappaacciittaannccee f = 1 MHz 1166 ppFF †All typical values are at VCC = 5 V, TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 switching characteristics, V = 5 V, C = 15 pF, T = 25°C (unless otherwise noted) CC L A FROM TO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) Propation delay time, tPLH low- to high-level output TTeerrmmiinnaall BBuuss CLL = 30 pF, 14 20 nnss Propagation delay time, See Figure 1 tPHL high- to low-level output 14 20 Propagation delay time, tPLH low- to high-level output BBuuss TTeerrmmiinnaall CLL = 30 pF, 10 20 nnss Propagation delay time, See Figure 2 tPHL high- to low-level output 15 22 tPZH Output enable time to high level 25 35 tPHZ Output disable time from high level 13 22 TTEE BBUUSS SSeeee FFiigguurree 33 nnss tPZL Output enable time to low level 22 35 tPLZ Output disable time from low level 22 32 tPZH Output enable time to high level 20 30 tPHZ Output disable time from high level 12 20 TTEE TTeerrmmiinnaall SSeeee FFiigguurree 44 nnss tPZL Output enable time to low level 23 32 tPLZ Output disable time from low level 19 30 ten Output pullup enable time 15 22 PPEE BBuuss SSeeee FFiigguurree 55 nnss tdis Output pullup disable time 13 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 5 V PE 3 V Output 200 W 3 V D Input 1.5 V 1.5 V Generator D B 0 V (see Note A) tPLH tPHL 480 W 50 W CL = 30 pF B Output 2.2 V VOH (see Note B) 1.0 V VOH TE VOLTAGE WAVEFORMS 3 V TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms TE 4.3 V 3 V B Input 1.5 V 1.5 V Output 240 W 0 V Generator B D tPLH tPHL (see Note A) VOH 50 W CL = 30 pF 3 kW D Output 1.5 V 1.5 V (see Note B) VOH VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 5 V 3 V PE 200 W 3 V Output TE Input 1.5 V 1.5 V 0 V S1 D B S2 tPZH tPHZ B Output 90% VOH 480 W S1 to 3 V 2 V S2 Open 0.8 V (sCeLe = N 3o0te p BF) tPZL tPLZ 3.5 V Generator B Output TE S1 to GND 1.0 V (see Note A) S2 Closed 0.5 V 50 W VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms 4.3 V 3 V Generator TE 1.5 V 1.5 V Output S2 TE Input (see Note A) 0 V tPZH tPHZ 50 W 240 W D D Output 90% VOH S1 TO 3 V 1.5 V S2 Open 3 V S1 B CL = 15 3p FkW tPZL tPLZ 0 V (see Note B) D Output 4 V S1 TO GND 1.0 V S2 Closed 0.7 V TEST CIRCUIT VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION Generator PE (see Note A) Output 3 V PE Input D B 1.5 V 1.5 V 50 W 0 V RL = 480 W ten tdis VOH CL = 15 pF 90% B Output (see Note B) 2 V VOL = 0.8 V 3 V TE VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 W . B. CL includes probe and jig capacitance. Figure 5. PE-to-Bus Pullup Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 TYPICAL CHARACTERISTICS TERMINAL I/O PORTS TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 4 ÎÎÎÎ 0.6 ÎÎÎÎ ÎVÎCC Î= 5 ÎV ÎVÎCC Î= 5 VÎ 3.5 TA = 25°C TA = 25°C – V ÎÎÎÎ – V 0.5 ÎÎÎÎ e e g 3 g a a Volt Volt 0.4 ut 2.5 ut p p ut ut O 2 O 0.3 el el v v e e High-L 1.5 Low-L 0.2 – 1 – H H L L VVOO VOVO 0.1 0.5 0 0 0 –5 –10 –15 –20 –25 –30 –35 –40 0 10 20 30 40 50 60 IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA Figure 6 Figure 7 TERMINAL I/O PORTS OUTPUT VOLTAGE vs BUS INPUT VOLTAGE ÎÎÎÎ 4 ÎÎVCCÎ = 5Î V 3.5ÎÎNo LÎoadÎ TA = 25°C ÎÎÎÎ 3 V – e g 2.5 a olt V ut 2 utp VIT– VIT+ O 1.5 – O O VV 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VI – Bus Input Voltage – V Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 TYPICAL CHARACTERISTICS GPIB I/O PORTS GPIB I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 0 ÎÎÎÎ 0.6ÎÎÎÎ gh-Level Output Voltage – V 32 ÎÎVTACÎÎ C= =25 ÎÎ5° CVÎÎ w-Level Output Voltage – V 0000....5432ÎÎVTÎÎAC C= ÎÎ=25 5° CVÎÎ Hi Lo – 1 – H H L L VVOO VVOO 0.1 0 0 0 –10 –20 –40 –30 –50 –60 0 10 20 30 40 50 60 70 80 90 100 IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA Figure 9 Figure 10 GPIB I/O PORTS GPIB I/O PORTS OUTPUT VOLTAGE CURRENT vs vs THERMAL INPUT VOLTAGE VOLTAGE 4ÎÎÎÎÎ ÎÎÎÎ VCC = 5 V VCC = 5 V ÎÎNo ÎLoaÎd Î 2 ÎTÎA = 2Î5°CÎ ÎÎTA Î= 25ΰC Î 1 3 V – A 0 e m ag – –1 olt nt V e ut 2 urr –2 p C ut – –3 O – OO II/O –4 VV 1 ÁÎÁÎÁÎÁÎÁÎÁÎÁÎÁÎ –5 The Unshaded ÁÎÎÎÁÎÎÎÁÎÎÎÁÎÎÎÁÎÎÎÁÎÎÎÁÎÎÎÁÎ Area Conforms to –6 ÁÎÎÎÁÎÎÎParaÁÎÎÎgrapÁÎÎÎh 3ÁÎÎÎ.5.3 ÁÎÎÎof ÁÎÎÎÁÎÎ IEEE Standard 488-1978 0 –7 ÁÎÁÎÁÎÁÎÁÎÁÎÁÎÁÎ 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 –2 –1 0 1 2 3 4 5 6 VI – Thermal Input Voltage – V VI/O – Voltage – V Figure 11 Figure 12 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN75160BDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BDWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 SN75160B & no Sb/Br) SN75160BN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN75160BN (RoHS) SN75160BNE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN75160BN (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN75160BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN75160BDWR SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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