(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 (cid:1) Member of the Texas Instruments DGG, DGV, OR DL PACKAGE Widebus Family (TOP VIEW) (cid:1) Designed to Be Used in Voltage-Limiting GND 1 48 GATE Applications (cid:1) 6.5-Ω On-State Connection Between Ports A1 2 47 B1 A2 3 46 B2 A and B A3 4 45 B3 (cid:1) Flow-Through Pinout for Ease of Printed A4 5 44 B4 Circuit Board Trace Routing A5 6 43 B5 (cid:1) Direct Interface With GTL+ Levels A6 7 42 B6 (cid:1) ESD Protection Exceeds JESD 22 A7 8 41 B7 − 2000-V Human-Body Model (A114-A) A8 9 40 B8 − 200-V Machine Model (A115-A) A9 10 39 B9 − 1000-V Charged-Device Model (C101) A10 11 38 B10 A11 12 37 B11 description/ordering information A12 13 36 B12 A13 14 35 B13 The SN74TVC16222A provides 23 parallel A14 15 34 B14 NMOS pass transistors with a common gate. The A15 16 33 B15 low on-state resistance of the switch allows A16 17 32 B16 connections to be made with minimal propagation A17 18 31 B17 delay. A18 19 30 B18 The device can be used as a 22-bit switch, with the A19 20 29 B19 gates cascaded together to a reference transistor. A20 21 28 B20 The low-voltage side of each pass transistor is A21 22 27 B21 limited to a voltage set by the reference transistor. A22 23 26 B22 This is done to protect components with inputs A23 24 25 B23 that are sensitive to high-state voltage-level overshoots. (See Application Information in this data sheet.) All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor are equal, the maximum output high-state voltage (V ) is approximately the reference voltage (V ), with OH REF minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices. Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the low-voltage side, and the I/O signals are bidirectional through each FET. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74TVC16222DL SSSSOOPP −− DDLL TTVVCC1166222222AA Tape and reel SN74TVC16222DLR −−4400°°CC ttoo 8855°°CC TSSOP − DGG Tape and reel SN74TVC16222DGGR TVC16222A TVSOP − DGV Tape and reel SN74TVC16222DGVR TW222A †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and TI are trademarks of Texas Instruments. (cid:20)(cid:21)(cid:15)(cid:22)(cid:23)(cid:7)(cid:5)(cid:14)(cid:15)(cid:2) (cid:22)(cid:11)(cid:5)(cid:11) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2005, Texas Instruments Incorporated (cid:20)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:5)$+(cid:30)! (cid:14)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:20)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 simplified schematic GATE B1 B2 B3 B4 B23 48 47 46 45 44 25 1 2 3 4 5 24 GND A1 A2 A3 A4 A23 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Input/output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I/O Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN TYP MAX UNIT VI/O Input/output voltage 0 5.5 V VGATE GATE voltage 0 5.5 V IPASS Pass-transistor current 20 64 mA TA Operating free-air temperature −40 85 °C application operating conditions (see Figure 3) MIN TYP MAX UNIT VBIAS BIAS voltage VREF + 0.6 2.1 5 V VGATE GATE voltage VREF + 0.6 2.1 5 V VREF Reference voltage 0 1.5 4.4 V VDPU Drain pullup voltage 2.36 2.5 2.64 V IPASS Pass-transistor current 14 20 mA IREF Reference-transistor current 5 µA TA Operating free-air temperature −40 85 °C 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VBIAS = 0, II = −18 mA −1.2 V IREF = 5 (cid:1)A, VREF = 1.365 V, VS = 0.175 V, VOL VDPU = 2.625 V, RDPU = 150 Ω See Figure 2 350 mV Ci(GATE) VI = 3 V or 0 73 pF Cio(off) VO = 3 V or 0 4 12 pF Cio(on) VO = 3 V or 0 12 25 pF ron‡ IVRDEPFU = = 5 2 (cid:1).6A2,5 V, RVRDEPFU == 11.5306 5Ω V, SVeSe = F 0ig.1u7re5 2V, 12.5 Ω †All typical values are at TA = 25°C. ‡Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. electrical characteristics from −40°C to 75°C PARAMETER TEST CONDITIONS MIN MAX UNIT ron‡ IVRDEPFU = = 5 2 (cid:1).6A2,5 V, RVRDEPFU == 11.5505 2Ω V, SVeSe = F 0ig.1u7re5 2V, 10 Ω ‡Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, V = 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1) DPU FROM TO PARAMETER MIN MAX UNIT (INPUT) (OUTPUT) tPLH 0 4 AA oorr BB BB oorr AA nnss tPHL 0 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 3.3 V VDPU Motherboard Interface 200 kΩ RDPU = RDPU = RDPU = RDPU = 150 Ω 150 Ω 150 Ω 150 Ω † † † † ‡ GATE B1 (VBIAS) B2 B3 B4 B23 48 47 46 45 44 25 TVC16222A 1 2 3 4 5 24 A1 (VREF) § A2 (VS) § A3 (VS) § A4 (VS) § A23 (VS) Open-Drain Test Interface TESTER CALIBRATION SETUP (see Note C) 2.5 V Input GATE 1.25 V 1.25 V Tester 0 V tPLHREF tPHLREF DEFINITION SYMBOL 2.5 V Output tested † Output 1.25 V 1.25 V Output reference ‡ Reference Input tested § VOL tPLHDUT tPHLDUT 2.5 V Output Device 1.25 V 1.25 V Under Test VOL tPLH tPHL (see Note D) (see Note E) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. B. The outputs are measured one at a time, with one transition per measurement. C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point. tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test. D. tPLH = tPLHDUT − tPLHREF E. tPHL = tPHLDUT − tPHLREF Figure 1. Tester Calibration Setup and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC background information In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define, among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC architecture, but the existing bus standards must be preserved. To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster performance, most new high-performance digital integrated circuits are designed and produced with advanced submicron semiconductor process technologies. These devices have thin gate-oxide or short channel lengths and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os) without causing damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage levels on the preexisting buses with which they must communicate. Therefore, it became necessary to protect the I/Os of devices by limiting the I/O voltages. The Texas Instruments (TI) translation voltage-clamp (TVC) family is designed specifically for protecting sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing the TI TVC solution. TVC Family Low-Voltage Standard-Voltage Voltage-Clamp I/O Device I/O Bus Device Figure 2. Thin Gate-Oxide Protection Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the V input of the reference transistor. The BIAS V input is connected through a pullup resistor (typically 200 kΩ ) to the V supply. A filter capacitor on V BIAS DD BIAS is recommended. The opposite side of the reference transistor is used as the reference voltage (V ) REF connection. The VREF input must be less than VDDREF − 1 V to bias the reference transistor into conduction. The reference transistor regulates the gate voltage (V ) of all the pass transistors. V is determined by GATE GATE the characteristic gate-to-source voltage difference (VGS) because VGATE = VREF + VGS. The low-voltage side of the pass transistors has a high-level voltage limited to a maximum of VGATE − VGS, or VREF. VDDREF = 3.3 V VDPU Motherboard Interface 200 kΩ 150 Ω 150 Ω 150 Ω 150 Ω GATE† B1 (VBIAS)† B2 B3 B4 B23 48 47 46 45 44 25 TVC16222A 1 2 3 4 5 24 A1 (VREF)† A2 A3 A4 A23 Open-Drain CPU Interface †VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. Figure 3. Typical Application Circuit 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION electrical characteristics The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired reference voltage for the varying device environments. Figure 5 shows the V-I characteristics with low reference voltages and a reference-transistor drain-supply voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, V was held at 2.5 V and REF I was increased by raising V (see Figure 6). The result was a tighter grouping of the V-I curves. REF DDREF VDDREF VDDPASS RDREF RDPASS GATE VBIAS VDPASS VREF VSPASS Figure 4. TI SPICE-Simulation Schematic and Voltage-Node Names POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION −2 VREF = 1 V A m −4 VDDREF = 3.3 V − RDREF = 200 kΩ nt −6 RDPASS = 150 Ω rre −8 VDDPASS = 3.3 V u C −10 s s −12 a P − −14 SS −16 A Weak P −18 I Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V −2 VREF = 1.5 V A m −4 VDDREF = 3.3 V rrent − −−68 VRRDDDDRPAPEASFSS = S =2 =01 053 0.k3 ΩΩ V u C −10 s s −12 a P − −14 SS −16 A Weak P −18 I Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V A −2 VREF = 2 V m −4 VDDREF = 3.3 V ent − −6 RRDDRPAESFS = =2 0105 0k ΩΩ urr −8 VDDPASS = 3.3 V C −10 s s −12 a P − −14 SS −16 A Weak P −18 I Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V Figure 5. V-I Electrical Characteristics at Low VREF Voltages 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION A −2 VREF = 2.5 V m −4 VDDREF = 3.3 V ent − −6 RRDDRPAESFS = =2 0105 0k ΩΩ urr −8 VDDPASS = 3.3 V C −10 s as −12 P − −14 S S −16 A Weak P −18 I Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V −2 VREF = 2.5 V A m −4 VDDREF = 4 V ent − −6 RRDDRPAESFS = =2 0105 0k ΩΩ rr −8 VDDPASS = 3.3 V u C −10 s as −12 P − −14 S S −16 A Weak P −18 I Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V A −2 VREF = 2.5 V ent − m −−46 VRRDDDDRPARESEFS F= ==2 01505 V 0k ΩΩ urr −8 VDDPASS = 3.3 V C s −10 s a −12 P − −14 S S −16 PA Weak I −18 Nominal −20 Strong 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V Figure 6. V-I Electrical Characteristics at V = 2.5 V REF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:10)(cid:11) (cid:10)(cid:10)(cid:12)(cid:13)(cid:14)(cid:5) (cid:6)(cid:15)(cid:16)(cid:5)(cid:11)(cid:17)(cid:18) (cid:7)(cid:16)(cid:11)(cid:19)(cid:20) SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION features and benefits The TVC family has several features that benefit a system designer when implementing a sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits. Table 1. Features and Benefits FEATURES BENEFITS Any FET can be used as the reference transistor. Ease of layout All FETs on one die, tight process control Very low spread of VO relative to VREF No active control logic (passive device) No logic power supply (VCC) required Flow-through pinout Ease of trace routing Devices offered in different bit widths and packages Optimizes design and cost effectiveness Designer flexibility with VREF input Allows migration to lower-voltage I/Os without board redesign conclusion The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced designs to align with industry standards. frequently asked questions (FAQs) 1. Q: Can any of the transistors in the array be used as the reference transistor? A: Yes, any transistor can be used as long as its V pin is connected to the GATE pin. BIAS 2. Q: In the recommended operating conditions table of the data sheet, the typical V is 3.3 V. BIAS Should V be equal to or greater than V on the reference transistor? BIAS REF A: V is a variable that is determined by V . V is connected to V through a resistor to allow the BIAS REF BIAS DD bias voltage to be controlled by V . V can be as high as 5.5 V. V needs to be at least 1 V less REF DD REF than V on the reference transistor. DDREF 3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage side? A: Both ports are 5-V tolerant. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 74TVC16222ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74TVC16222ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74TVC16222ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74TVC16222ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADGGR ACTIVE TSSOP DGG 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADGVR ACTIVE TVSOP DGV 48 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADL ACTIVE SSOP DL 48 25 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADLG4 ACTIVE SSOP DL 48 25 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADLR ACTIVE SSOP DL 48 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74TVC16222ADLRG4 ACTIVE SSOP DL 48 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74TVC16222ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74TVC16222ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74TVC16222ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74TVC16222ADGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74TVC16222ADGVR TVSOP DGV 48 2000 346.0 346.0 33.0 SN74TVC16222ADLR SSOP DL 48 1000 346.0 346.0 49.0 PackMaterials-Page2

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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