SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 (cid:2) (cid:2) Support Mixed-Mode Signal Operation (5-V Bus Hold on Data Inputs Eliminates the Input and Output Voltages With 3.3-V V ) Need for External Pullup/Pulldown CC (cid:2) Support Unregulated Battery Operation Resistors (cid:2) Down to 2.7 V Latch-Up Performance Exceeds 500 mA Per (cid:2) Typical V (Output Ground Bounce) JESD 17 OLP <0.8 V at V = 3.3 V, T = 25°C (cid:2) ESD Protection Exceeds JESD 22 CC A (cid:2) − 2000-V Human-Body Model (A114-A) I and Power-Up 3-State Support Hot off − 200-V Machine Model (A115-A) Insertion SN54LVTH574...J OR W PACKAGE SN74LVTH574...RGY PACKAGE SN54LVTH574...FK PACKAGE SN74LVTH574...DB, DW, NS, (TOP VIEW) (TOP VIEW) OR PW PACKAGE C C (TOP VIEW) E C D D E CQ O V 2 1 OV 1 1 20 OE 1 20 VCC 1D 2 19 1Q 3D 4 3 2 1 20 1918 2Q 1D 2 19 1Q 2D 3 18 2Q 4D 5 17 3Q 2D 3 18 2Q 3D 4 17 3Q 5D 6 16 4Q 3D 4 17 3Q 4D 5 16 4Q 6D 7 15 5Q 4D 5 16 4Q 5D 6 15 5Q 7D 8 14 6Q 5D 6 15 5Q 9 10 11 12 13 6D 7 14 6Q 6D 7 14 6Q 7D 8 13 7Q D D KQ Q 7D 8 13 7Q 8D 9 12 8Q 8 GN CL8 7 8D 9 12 8Q 10 11 GND 10 11 CLK D K N L G C description/ordering information These octal flip-flops are designed specifically for low-voltage (3.3-V) V operation, but with the capability to CC provide a TTL interface to a 5-V system environment. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74LVTH574RGYR LXH574 Tube SN74LVTH574DW SSOOIICC − DDWW LLVVTTHH557744 Tape and reel SN74LVTH574DWR SOP − NS Tape and reel SN74LVTH574NSR LVTH574 −4400°CC ttoo 8855°CC SSOP − DB Tape and reel SN74LVTH574DBR LXH574 Tube SN74LVTH574PW TTSSSSOOPP − PPWW LLXXHH557744 Tape and reel SN74LVTH574PWR VFBGA − GQN SN74LVTH574GQNR TTaappee aanndd rreeeell LLXXHH557744 VFBGA − ZQN (Pb-free) SN74LVTH574ZQNR CDIP − J Tube SNJ54LVTH574J SNJ54LVTH574J −5555°CC ttoo 112255°CC CFP − W Tube SNJ54LVTH574W SNJ54LVTH574W LCCC − FK Tube SNJ54LVTH574FK SNJ54LVTH574FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 description/ordering information (continued) The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry off off disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. SN74LVTH574...GQN OR ZQN PACKAGE (TOP VIEW) terminal assignments 1 2 3 4 1 2 3 4 A A 1D OE VCC 1Q B B 3D 3Q 2D 2Q C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E GND 8D CLK 8Q E FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT OE CLK D Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 1 OE 11 CLK C1 19 1Q 2 1D 1D To Seven Other Channels Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high-impedance or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V O Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Current into any output in the low state, I : SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 5) SN54LVTH574 SN74LVTH574 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2.7 3.6 2.7 3.6 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 5.5 5.5 V IOH High-level output current −24 −32 mA IOL Low-level output current 48 64 mA Δt/Δv Input transition rise or fall rate Outputs enabled 10 10 ns/V Δt/ΔVCC Power-up ramp rate 200 200 μs/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVTH574 SN74LVTH574 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V VCC = 2.7 V to 3.6 V, IOH = −100 μA VCC−0.2 VCC−0.2 VCC = 2.7 V, IOH = −8 mA 2.4 2.4 VVOH IOH = −24 mA 2 VV VVCC = 33 VV IOH = −32 mA 2 IOL = 100 μA 0.2 0.2 VVCC = 22.77 VV IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 VVOL IOL = 32 mA 0.5 0.5 VV VVCC = 33 VV IOL = 48 mA 0.55 IOL = 64 mA 0.55 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 CCoonnttrrooll iinnppuuttss VCC = 3.6 V, VI = VCC or GND ±1 ±1 III VI = VCC 1 1 μAA DDaattaa iinnppuuttss VVCC = 33.66 VV VI = 0 −5 −5 Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 μA VI = 0.8 V 75 75 IIII((hhoolldd)) DDaattaa iinnppuuttss VVCC = 33 VV VI = 2 V −75 −75 μμAA VCC = 3.6 V‡, VI = 0 to 3.6 V ±500 IOZH VCC = 3.6 V, VO = 3 V 5 5 μA IOZL VCC = 3.6 V, VO = 0.5 V −5 −5 μA IOZPU VOCEC = = d 0o nto’t 1c.a5r eV, VO = 0.5 V to 3 V, ±100* ±100 μA IOZPD VOCEC = = d 1o.n5’ tV c atore 0, VO = 0.5 V to 3 V, ±100* ±100 μA Outputs high 0.19 0.19 VVCCCC == 33..66 VV,, IICCCC IIOO = 00,, Outputs low 5 5 mmAA VI = VCC or GND Outputs disabled 0.19 0.19 ΔICC§ VOCthCe =r i3n pVu ttso a3t. 6V CVC, O onr eG iNnpDut at VCC − 0.6 V, 0.2 0.2 mA Ci VI = 3 V or 0 3 3 pF Co VO = 3 V or 0 7 7 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. †All typical values are at VCC = 3.3 V, TA = 25°C. ‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. §This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH574 SN74LVTH574 VC±C 0=. 33 .V3 V VCC = 2.7 V VC±C 0=. 33 .V3 V VCC = 2.7 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency 150 150 150 150 MHz tw Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns tsu Setup time, data before CLK↑ 2 2.4 2 2.4 ns th Hold time, data after CLK↑ 0.9 0.9 0.3 0 ns switching characteristics over recommended free-air temperature, C = 50 pF (unless otherwise L noted) (see Figure 1) SN54LVTH574 SN74LVTH574 PARAMETER ((IIFNNRPPOUUMTT)) ((OOUUTTTOPPUUTT)) VC±C 0=. 33 .V3 V VCC = 2.7 V VC±C 0=. 33 .V3 V VCC = 2.7 V UNIT MIN MAX MIN MAX MIN TYP† MAX MIN MAX fmax 150 150 150 150 MHz tPLH 1.7 4.9 5.9 1.8 3 4.5 5.3 CCLLKK QQ nnss tPHL 1.7 4.9 5.5 1.8 3 4.5 5.3 tPZH 1.4 5.1 6.5 1.5 3.2 4.8 5.9 OOEE QQ nnss tPZL 1.4 5.1 6.1 1.5 3.5 4.8 5.9 tPHZ 1 5.9 6.4 2 3.5 4.8 5.1 OOEE QQ nnss tPLZ 0.8 4.8 5.3 2 3.2 4.4 4.4 †All typical values are at VCC = 3.3 V, TA = 25°C. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION 6 V TEST S1 500 Ω S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 6 V CL = 50 pF 500 Ω tPHZ/tPZH GND (see Note A) 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 2.7 V 2.7 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 2.7 V 2.7 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output 3 V Output 1.5 V 1.5 V VOL (WseaevS eN1f ooatrte m6 B V1) 1.5 V VOL + 0.3 V VOL tPHL tPLH tPZH tPHZ Output Output 1.5 V 1.5 V VOH WSa1v eafto GrmN D2 1.5 V VOH − 0.3 V VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9583201Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9583201Q2A SNJ54LVTH 574FK 5962-9583201QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9583201QS A SNJ54LVTH574W 5962-9583201VSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type -55 to 125 5962-9583201VS A SNV54LVTH574W SN74LVTH574DB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH574 & no Sb/Br) SN74LVTH574DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH574 & no Sb/Br) SN74LVTH574NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH574 & no Sb/Br) SN74LVTH574PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LXH574 & no Sb/Br) SN74LVTH574RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LXH574 & no Sb/Br) SNJ54LVTH574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9583201Q2A SNJ54LVTH 574FK Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ54LVTH574W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9583201QS A SNJ54LVTH574W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVTH574, SN54LVTH574-SP, SN74LVTH574 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: SN74LVTH574, SN54LVTH574 •Enhanced Product: SN74LVTH574-EP, SN74LVTH574-EP •Military: SN54LVTH574 •Space: SN54LVTH574-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVTH574DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVTH574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVTH574NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVTH574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVTH574RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVTH574DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVTH574DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVTH574NSR SO NS 20 2000 367.0 367.0 45.0 SN74LVTH574PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVTH574RGYR VQFN RGY 20 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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