SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 FEATURES SN54LVTH16373...WD PACKAGE • MembersoftheTexasInstrumentsWidebus™ SN74LVTH16373... DGG OR DL PACKAGE Family (TOP VIEW) • State-of-the-ArtAdvancedBiCMOS Technology(ABT)Designfor3.3-VOperation 1OE 1 48 1LE andLowStatic-PowerDissipation 1Q1 2 47 1D1 • SupportMixed-ModeSignalOperation(5-V 1Q2 3 46 1D2 GND 4 45 GND InputandOutputVoltagesWith3.3-VV ) CC 1Q3 5 44 1D3 • SupportUnregulatedBatteryOperationDown 1Q4 6 43 1D4 to2.7V VCC 7 42 VCC • TypicalV (OutputGroundBounce)<0.8V OLP 1Q5 8 41 1D5 atV =3.3V,T =25(cid:176) C CC A 1Q6 9 40 1D6 • I andPower-Up3-StateSupportHot GND 10 39 GND off Insertion 1Q7 11 38 1D7 • BusHoldonDataInputsEliminatestheNeed 1Q8 12 37 1D8 forExternalPullup/PulldownResistors 2Q1 13 36 2D1 • DistributedV andGNDPinsMinimize 2Q2 14 35 2D2 CC High-SpeedSwitchingNoise GND 15 34 GND • Flow-ThroughArchitectureOptimizesPCB 2Q3 16 33 2D3 2Q4 17 32 2D4 Layout • Latch-UpPerformanceExceeds500mAPer VCC 18 31 VCC 2Q5 19 30 2D5 JESD17 2Q6 20 29 2D6 • ESDProtectionExceedsJESD22 GND 21 28 GND – 2000-VHuman-BodyModel(A114-A) 2Q7 22 27 2D7 – 200-VMachineModel(A115-A) 2Q8 23 26 2D8 2OE 24 25 2LE DESCRIPTION/ORDERING INFORMATION The 'LVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for low-voltage (3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment. These CC devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and workingregisters. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A FBGA–GRD SN74LVTH16373GRDR Reelof1000 LL373 FBGA–ZRD(Pb-free) SN74LVTH16373ZRDR Tubeof25 SN74LVTH16373DL SN74LVTH16373DLG4 SSOP–DL LVTH16373 –40(cid:176) Cto85(cid:176) C Reelof1000 SN74LVTH16373DLR SN74LVTH16373DLRG4 TSSOP–DGG Reelof2000 SN74LVTH16373DGGR LVTH16373 VFBGA–GQL SN74LVTH16373GQLR Reelof1000 LL373 VFBGA–ZQL(Pb-free) SN74LVTH16373ZQLR (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. WidebusisatrademarkofTexasInstruments. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1992–2006,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are Instruments standard warranty. Production processing does not testedunlessotherwisenoted.Onallotherproducts,production necessarilyincludetestingofallparameters. processingdoesnotnecessarilyincludetestingofallparameters.

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 ORDERINGINFORMATION(continued) T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A Tube SNJ54LVTH16373WD –55(cid:176) Cto125(cid:176) C CFP–WD SNJ54LVTH16373WD 5962-9681001QXA DESCRIPTION/ORDERING INFORMATION (CONTINUED) Thesedevicescanbeusedastwo8-bitlatches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the Dinputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the buslines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines withoutinterfaceorpullupcomponents. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while theoutputsareinthehigh-impedancestate. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistorswiththebus-holdcircuitryisnotrecommended. When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. CC However, to ensure the high-impedance state above 1.5 V, OE should be tied to V through a pullup resistor; CC theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry off off disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, whichpreventsdriverconflict. GQL OR ZQL PACKAGE TERMINALASSIGNMENTS(1) (TOP VIEW) (56-BallGQL/ZQLPackage) 1 2 3 4 5 6 1 2 3 4 5 6 A A 1OE NC NC NC NC 1CLK B B 1Q2 1Q1 GND GND 1D1 1D2 C C 1Q4 1Q3 V V 1D3 1D4 D CC CC E D 1Q6 1Q5 GND GND 1D5 1D6 F E 1Q8 1Q7 1D7 1D8 G F 2Q1 2Q2 2D2 2D1 H J G 2Q3 2Q4 GND GND 2D4 2D3 K H 2Q5 2Q6 V V 2D6 2D5 CC CC J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2CLK (1) NC–Nointernalconnection 2 SubmitDocumentationFeedback

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 GRD OR ZRD PACKAGE TERMINALASSIGNMENTS(1) (TOP VIEW) (54-BallGRD/ZRDPackage) 1 2 3 4 5 6 1 2 3 4 5 6 A A 1Q1 NC 1OE 1LE NC 1D1 B 1Q3 1Q2 NC NC 1D2 1D3 B C 1Q5 1Q4 V V 1D4 1D5 CC CC C D 1Q7 1Q6 GND GND 1D6 1D7 D E 2Q1 1Q8 GND GND 1D8 2D1 E F 2Q3 2Q2 GND GND 2D2 2D3 G 2Q5 2Q4 V V 2D4 2D5 F CC CC H 2Q7 2Q6 NC NC 2D6 2D7 G J 2Q8 NC 2OE 2LE NC 2D8 H J (1) NC–Nointernalconnection FUNCTIONTABLE (8-BITSECTION) INPUTS OUTPUT OE CLK D Q L H H H L H L L L L X Q 0 H X X Z LOGICDIAGRAM(POSITIVELOGIC) 1 24 1OE 2OE 48 25 1LE 2LE C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages. SubmitDocumentationFeedback 3

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 4.6 V CC V Inputvoltagerange(2) –0.5 7 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V O V Voltagerangeappliedtoanyoutputinthehighstate(2) –0.5 V +0.5 V O CC SN54LVTH16373 96 I Currentintoanyoutputinthelowstate mA O SN74LVTH16373 128 SN54LVTH16373 48 I Currentintoanyoutputinthehighstate(3) mA O SN74LVTH16373 64 I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O DGGpackage 70 DLpackage 63 q Packagethermalimpedance(4) (cid:176) C JA GQL/ZQLpackage 42 GRD/ZRDpackage 36 T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputclamp-currentratingsareobserved. (3) ThiscurrentflowsonlywhentheoutputisinthehighstateandV >V . O CC (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. Recommended Operating Conditions(1) SN54LVTH16373 SN74LVTH16373 UNIT MIN MAX MIN MAX V Supplyvoltage 2.7 3.6 2.7 3.6 V CC V High-levelinputvoltage 2 2 V IH V Low-levelinputvoltage 0.8 0.8 V IL V Inputvoltage 5.5 5.5 V I I High-leveloutputcurrent –24 –32 mA OH I Low-leveloutputcurrent 48 64 mA OL D t/D v Inputtransitionriseorfallrate Outptsenabled 10 10 ns/V D t/D V Power-upramprate 200 200 m s/V CC T Operatingfree-airtemperature –55 125 –40 85 (cid:176) C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 4 SubmitDocumentationFeedback

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LVTH16373 SN74LVTH16373 PARAMETER TESTCONDITIONS UNIT MIN TYP(1) MAX MIN TYP(1) MAX V V =2.7V, I =–18mA –1.2 –1.2 V IK CC I V =2.7Vto3.6V, I =–100m A V –0.2 V –0.2 CC OH CC CC V =2.7V, I =–8mA 2.4 2.4 CC OH V V OH I =–24mA 2 OH V =3V CC I =–32mA 2 OH I =100m A 0.2 0.2 OL V =2.7V CC I =24mA 0.5 0.5 OL I =16mA 0.4 0.4 OL V V OL I =32mA 0.5 0.5 OL V =3V CC I =48mA 0.55 OL I =64mA 0.55 OL V =0or3.6V, V =5.5V 10 10 CC I Control V =3.6V, V =V orGND – 1 – 1 I inputs CC I CC m A I Data VI=VCC 1 1 V =3.6V inputs CC V =0 –5 –5 I I V =0, V orV =0to4.5V – 100 m A off CC I O V =0.8V 75 75 I I Data VCC=3V V =2V –75 –75 m A I(hold) inputs I V =3.6V,(2) V =0to3.6V – 500 CC I I V =3.6V, V =3V 5 5 m A OZH CC O I V =3.6V, V =0.5V –5 –5 m A OZL CC O I VCC=0to1.5V,VO=0.5Vto3V, – 100(3) – 100 m A OZPU OE=don'tcare I VCC=1.5Vto0,VO=0.5Vto3V, – 100(3) – 100 m A OZPD OE=don'tcare Outputshigh 0.19 0.19 V =3.6V, CC I I =0, Outputslow 5 5 mA CC O V =V orGND I CC Outputsdisabled 0.19 0.19 D I (4) VCC=3Vto3.6V,OneinputatVCC–0.6V, 0.2 0.2 mA CC OtherinputsatV orGND CC C V =3Vor0 3 3 pF i I C V =3Vor0 9 9 pF o O (1) AlltypicalvaluesareatV =3.3V,T =25(cid:176) C. CC A (2) Thisisthebus-holdmaximumdynamiccurrent.Itistheminimumoverdrivecurrentrequiredtoswitchtheinputfromonestateto another. (3) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (4) ThisistheincreaseinsupplycurrentforeachinputthatisatthespecifiedTTLvoltagelevel,ratherthanV orGND. CC SubmitDocumentationFeedback 5

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 Timing Requirements overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) SN54LVTH16373 SN74LVTH16373 V =3.3V V =3.3V C–C0.3V VCC=2.7V C–C0.3V VCC=2.7V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 3 3 3 3 ns w t Setuptime,databeforeLEfl 2 2 1 0.6 ns su t Holdtime,dataafterLEfl 3 3.3 1 1.1 ns h Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =50pF(unlessotherwisenoted)(seeFigure1) L SN54LVTH16373 SN74LVTH16373 FROM TO V =3.3V V =3.3V PARAMETER (INPUT) (OUTPUT) C–C0.3V VCC=2.7V C–C0.3V VCC=2.7V UNIT MIN MAX MIN MAX MIN TYP(1) MAX MIN MAX t 1.4 4.5 5.2 1.5 2.7 3.8 4.2 PLH D Q ns t 1.4 4.4 4.8 1.5 2.5 3.6 4 PHL t 1.8 5.5 5.8 2.1 3 4.3 4.8 PLH LE Q ns t 1.8 5.2 5.6 2.1 2.9 4 4 PHL t 1.4 5.7 6.7 1.5 2.8 4.3 5.1 PZH OE Q ns t 1.4 5.5 6 1.5 2.8 4.3 4.7 PZL t 2 6 6.2 2.4 3.5 5 5.4 PHZ OE Q ns t 1.4 5.2 5.6 2 3.2 4.7 4.8 PLZ t 0.5 sk(LH) ns t 0.5 sk(HL) (1) AlltypicalvaluesareatV =3.3V,T =25(cid:176) C. CC A 6 SubmitDocumentationFeedback

SN54LVTH16373,, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS144P–MAY1992–REVISEDNOVEMBER2006 PARAMETER MEASUREMENT INFORMATION 6 V TEST S1 500 W S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 6 V (seCeL N= o5t0e pAF) 500 W tPHZ/tPZH GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 2.7 V 2.7 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 2.7 V 2.7 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 3 V Output 1.5 V 1.5 V S1 at 6 V 1.5 V VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output VOH Waveform 2 VOH Output 1.5 V 1.5 V S1 at GND 1.5 V VOH − 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure1.LoadCircuitandVoltageWaveforms SubmitDocumentationFeedback 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9681001QXA ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9681001QX A SNJ54LVTH16373 WD 74LVTH16373DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373 & no Sb/Br) SN74LVTH16373DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373 & no Sb/Br) SN74LVTH16373DL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373 & no Sb/Br) SN74LVTH16373DLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373 & no Sb/Br) SN74LVTH16373ZQLR LIFEBUY BGA ZQL 56 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LL373 MICROSTAR & no Sb/Br) JUNIOR SN74LVTH16373ZRDR LIFEBUY BGA ZRD 54 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LL373 MICROSTAR & no Sb/Br) JUNIOR SNJ54LVTH16373WD ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9681001QX A SNJ54LVTH16373 WD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVTH16373, SN74LVTH16373 : •Catalog: SN74LVTH16373 •Enhanced Product: SN74LVTH16373-EP, SN74LVTH16373-EP •Military: SN54LVTH16373 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVTH16373DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74LVTH16373DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74LVTH16373ZQLR BGAMI ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CROSTA RJUNI OR SN74LVTH16373ZRDR BGAMI ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVTH16373DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVTH16373DLR SSOP DL 48 1000 367.0 367.0 55.0 SN74LVTH16373ZQLR BGAMICROSTAR ZQL 56 1000 350.0 350.0 43.0 JUNIOR SN74LVTH16373ZRDR BGAMICROSTAR ZRD 54 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OUTLINE ZQL0056A JRBGA - 1 mm max height SCALE 2.100 PLASTIC BALL GRID ARRAY 4.6 B A 4.4 BALL A1 CORNER 7.1 6.9 1 MAX C SEATING PLANE 0.35 0.15 TYP BALL TYP 0.1 C 3.25 TYP SYMM (0.625) TYP K J (0.575) TYP H G 5.85 F SYMM TYP E D C 0.45 56X NOTE 3 0.35 B 0.15 C B A 0.08 C A 0.65 TYP 1 2 3 4 5 6 BALL A1 CORNER 0.65 TYP 4219711/B 01/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. No metal in this area, indicates orientation. www.ti.com

EXAMPLE BOARD LAYOUT ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY (0.65) TYP 56X ( 0.33) 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK 0.05 MAX 0.05 MIN METAL UNDER OPENING SOLDER MASK EXPOSED METAL ( 0.33) ( 0.33) METAL EXPOSED METAL SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219711/B 01/2017 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com

EXAMPLE STENCIL DESIGN ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY 56X ( 0.33) (0.65) TYP 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4219711/B 01/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.009 (0,23) 0.075 (1,91) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.390 (9,91) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 1 48 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 24 25 NO. OF 48 56 LEADS** 0.640 0.740 A MAX (16,26) (18,80) 0.610 0.710 A MIN (15,49) (18,03) 4040176/D 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA GDFP1-F56 and JEDEC MO-146AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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