(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 (cid:1) (cid:1) Member of the Texas Instruments I Supports Partial-Power-Down Mode off Widebus+ Family Operation (cid:1) (cid:1) Operates From 1.65 V to 3.6 V Supports Mixed-Mode Signal Operation on (cid:1) Inputs Accept Voltages to 5.5 V All Ports (5-V Input/Output Voltage With (cid:1) Max t of 4.8 ns at 3.3 V 3.3-V VCC) pd (cid:1) (cid:1) Other Products to Consider: Input and Output Ports Have Equivalent SN74LVC32245, SN74LVCH32245A 26-Ω Series Resistors, So No External (cid:1) Resistors Are Required Latch-Up Performance Exceeds 100 mA Per (cid:1) JESD 78, Class II Typical V (Output Ground Bounce) OLP (cid:1) <0.8 V at V = 3.3 V, T = 25°C ESD Protection Exceeds JESD 22 CC A (cid:1) − 2000-V Human-Body Model (A114-A) Typical V (Output V Undershoot) OHV OH − 200-V Machine Model (A115-A) >2 V at V = 3.3 V, T = 25°C CC A − 1000-V Charged-Device Model (C101) description/ordering information This 32-bit (quad-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V operation. CC The SN74LVC32245A is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING LFBGA − GKE SN74LVCR32245AGKER −−4400°°CC ttoo 8855°°CC TTaappee aanndd rreeeell NNDD224455AA LFBGA − ZKE (Pb-free) SN74LVCR32245AZKER †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. (cid:22)(cid:8)(cid:21)(cid:23)(cid:17)(cid:7)(cid:16)(cid:15)(cid:21)(cid:2) (cid:23)(cid:12)(cid:16)(cid:12) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2003, Texas Instruments Incorporated (cid:22)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:16)$+(cid:30)! (cid:15)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:22)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 GKE OR ZKE PACKAGE (TOP VIEW) terminal assignments 1 2 3 4 5 6 1 2 3 4 5 6 A A 1B2 1B1 1DIR 1OE 1A1 1A2 B B 1B4 1B3 GND GND 1A3 1A4 C C 1B6 1B5 VCC VCC 1A5 1A6 D D 1B8 1B7 GND GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 E F 2B4 2B3 VCC VCC 2A3 2A4 F G 2B6 2B5 GND GND 2A5 2A6 G H 2B7 2B8 2DIR 2OE 2A8 2A7 H J 3B2 3B1 3DIR 3OE 3A1 3A2 J K 3B4 3B3 GND GND 3A3 3A4 K L 3B6 3B5 VCC VCC 3A5 3A6 L M 3B8 3B7 GND GND 3A7 3A8 M N 4B2 4B1 GND GND 4A1 4A2 N P 4B4 4B3 VCC VCC 4A3 4A4 P R 4B6 4B5 GND GND 4A5 4A6 R T 4B7 4B8 4DIR 4OE 4A8 4A7 T FUNCTION TABLE (each 8-bit section) INPUTS OOPPEERRAATTIIOONN OE DIR L L B data to A bus L H A data to B bus H X Isolation 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 logic diagram (positive logic) A3 H3 1DIR 2DIR A4 H4 1OE 2OE A5 E5 1A1 2A1 A2 E2 1B1 2B1 To Seven Other Channels To Seven Other Channels J3 T3 3DIR 4DIR J4 T4 3OE 4OE J5 N5 3A1 4A1 J2 N2 3B1 4B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V I Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, V O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O Continuous current through each V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θJA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 4) MIN MAX UNIT Operating 1.65 3.6 VVCCCC SSuuppppllyy vvoollttaaggee VV Data retention only 1.5 VCC = 1.65 V to 1.95 V 0.65 ×VCC VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 2.3 V to 2.7 V 1.7 VV VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 ×VCC VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 2.3 V to 2.7 V 0.7 VV VCC = 2.7 V to 3.6 V 0.8 VI Input voltage 0 5.5 V High or low state 0 VCC VVOO OOuuttppuutt vvoollttaaggee VV 3-state 0 5.5 VCC = 1.65 V −2 VCC = 2.3 V −4 IIOOHH HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt mmAA VCC = 2.7 V −8 VCC = 3 V −12 VCC = 1.65 V 2 VCC = 2.3 V 4 IIOOLL LLooww--lleevveell oouuttppuutt ccuurrrreenntt mmAA VCC = 2.7 V 8 VCC = 3 V 12 ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT IOH = −100 µA 1.65 V to 3.6 V VCC−0.2 IOH = −2 mA 1.65 V 1.2 IOH = −4 mA 2.3 V 1.7 VVOOHH VV 2.7 V 2 IIOOHH == −−88 mmAA 3 V 2.4 IOH = −12 mA 3 V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 2 mA 1.65 V 0.45 VVOOLL IOL = 4 mA 2.3 V 0.7 VV IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3 V 0.8 II Control inputs VI = 0 to 5.5 V 3.6 V ±5 µA Ioff VI or VO = 5.5 V 0 ±10 µA IOZ‡ VO = 0 to 5.5 V 3.6 V ±5 µA VI = VCC or GND 20 IICCCC 3.6 V ≤ VI ≤ 5.5 V§ IIOO == 00 33..66 VV 20 µAA ∆ICC One input at VCC − 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA Ci Control inputs VI = VCC or GND 3.3 V 3 pF Cio A or B ports VO = VCC or GND 3.3 V 12 pF †All typical values are at VCC = 3.3 V, TA = 25°C. ‡For I/O ports, the parameter IOZ includes the input leakage current. §This applies in the disabled state only. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR FROM TO ± 0.15 V ± 0.2 V VCC = 2.7 V ± 0.3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX MIN MAX MIN MAX tpd A or B B or A 1 7.8 1 5.8 1.5 5.7 1.5 4.8 ns ten OE A or B 1.5 10 1 8 1.5 7.9 1.5 6.3 ns tdis OE A or B 1.5 11.9 1 8.4 1.5 8.3 1.5 7.4 ns operating characteristics, TA = 25°C TTEESSTT VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR UUNNIITT CONDITIONS TYP TYP TYP Outputs enabled 35 38 43 CCppdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee ff == 1100 MMHHzz ppFF Outputs disabled 3 3 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:10)(cid:4)(cid:11)(cid:12) (cid:9)(cid:10)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:17)(cid:1) (cid:16)(cid:8)(cid:12)(cid:2)(cid:1)(cid:7)(cid:18)(cid:15)(cid:6)(cid:18)(cid:8) (cid:19)(cid:15)(cid:16)(cid:20) (cid:9)(cid:13)(cid:1)(cid:16)(cid:12)(cid:16)(cid:18) (cid:21)(cid:17)(cid:16)(cid:22)(cid:17)(cid:16)(cid:1) SCES428B − FEBRUARY 2003 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VM VLOAD CL RL V∆ VI tr/tf 1.8 V ±0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V 2.5 V ±0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V 3.3 V ±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V VI Timing Input VM 0 V tw tsu th VI VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM VM VM Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL S(1s eaet NVLoOteA BD) VM VOL + V∆ VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − V∆ VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 27-Dec-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVCR32245AGKER NRND LFBGA GKE 96 1000 TBD SNPB Level-2-235C-1 YEAR -40 to 85 ND245A SN74LVCR32245AZKER NRND LFBGA ZKE 96 1000 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 ND245A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVCR32245AGKER LFBGA GKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 SN74LVCR32245AZKER LFBGA ZKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVCR32245AGKER LFBGA GKE 96 1000 336.6 336.6 41.3 SN74LVCR32245AZKER LFBGA ZKE 96 1000 336.6 336.6 41.3 PackMaterials-Page2

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