Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs 1 Features Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown • ControlInputs(DIRand OE)V andV Levels 1 IH IL resistors with the bus-hold circuitry is not areReferencedtoV CCA recommended. • BusHoldonDataInputsEliminatestheNeedfor This device is fully specified for partial-power-down ExternalPullupandPulldownResistors applications using I . The I circuitry disables the off off • VCCIsolation outputs, preventing damaging current backflow • FullyConfigurableDual-RailDesign throughthedevice. • IoffSupportsPartial-Power-DownModeOperation The VCC isolation feature ensures that if either VCCA • Latch-UpPerformanceExceeds100mAPer or VCCB is at GND, then the outputs are in the high- JESD78,ClassII impedancestate. • ESDProtectionExceedsJESD22 To ensure the high-impedance state during power up or power down, OE should be tied to V through a CCA 2 Applications pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the • PersonalElectronics driver. • Industrial • Enterprise DeviceInformation(1) • Telecommunications PARTNUMBER PACKAGE BODYSIZE(NOM) SSOP(24) 8.65mm×3.90mm 3 Description TVSOP(24) 5.00mm×4.40mm SN74LVCH8T245 The SN74LVCH8T245 is an 8-bit noninverting bus TSSOP(24) 7.80mm×4.40mm transceiver that uses two separate configurable VQFN(24) 5.50mm×3.50mm power-supply rails. The A port is designed to track (1) For all available packages, see the orderable addendum at V , which accepts any supply voltage from 1.65 V CCA theendofthedatasheet. to 5.5 V. The B port is designed to track V , which CCB also accepts any supply voltage from 1.65 V to 5.5 V. LogicDiagram(PositiveLogic) This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, 2 and5.5-Vvoltagenodes. DIR The SN74LVCH8T245 is designed for asynchronous 22 OE communication between two data buses. The logic levels of the direction-control (DIR) input and the 3 output-enable (OE) input activate either the B-port A1 outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits 21 B1 data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input To Seven Other Channels circuitryonbothAandBportsarealwaysactive. The SN74LVCH8T245 is designed so that the control pins(DIRandOE)arereferencedtoV . CCA 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................13 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................13 3 Description............................................................. 1 8.3 FeatureDescription.................................................13 8.4 DeviceFunctionalModes........................................14 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 15 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation............................................15 6 Specifications......................................................... 4 9.2 TypicalApplication..................................................15 6.1 AbsoluteMaximumRatings......................................4 10 PowerSupplyRecommendations..................... 17 6.2 ESDRatings..............................................................4 11 Layout................................................................... 17 6.3 RecommendedOperatingConditions.......................4 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................17 6.5 ElectricalCharacteristics...........................................6 11.2 LayoutExample....................................................18 6.6 SwitchingCharacteristics:V =1.8V±0.15V....7 12 DeviceandDocumentationSupport................. 19 CCA 6.7 SwitchingCharacteristics:V =2.5V±0.2V......8 12.1 DocumentationSupport........................................19 CCA 6.8 SwitchingCharacteristics:V =3.3V±0.3V......9 12.2 CommunityResource............................................19 CCA 6.9 SwitchingCharacteristics:V =5V±0.5V.......10 12.3 Trademarks...........................................................19 CCA 6.10 OperatingCharacteristics......................................11 12.4 ElectrostaticDischargeCaution............................19 6.11 TypicalCharacteristics..........................................11 12.5 Glossary................................................................19 7 ParameterMeasurementInformation................12 13 Mechanical,Packaging,andOrderable Information........................................................... 19 8 DetailedDescription............................................ 13 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionA(February2007)toRevisionB Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 5 Pin Configuration and Functions DB,DGV,orPWPackages 24-PinSSOP,TVSOP,orTSSOP RHLPackage TopView 24-PinVQFN TopView VCCA 1 24 VCCB CA CB DIR 2 23 VCCB VC VC A1 3 22 OE 1 24 A2 4 21 B1 DIR 2 23 V CCB A3 5 20 B2 A1 3 22 OE A4 6 19 B3 A2 4 21 B1 A5 7 18 B4 A3 5 20 B2 A6 8 17 B5 A4 6 19 B3 A7 9 16 B6 A5 7 18 B4 A8 10 15 B7 A6 8 17 B5 GND 11 14 B8 A7 9 16 B6 GND 12 13 GND A8 10 15 B7 GND 11 14 B8 12 13 D D N N G G PinFunctions PIN SSOP, I/O DESCRIPTION NAME TVSOP, VQFN TSSOP A1 3 3 I/O Input/outputA1.ReferencedtoV . CCA A2 4 4 I/O Input/outputA2.ReferencedtoV . CCA A3 5 5 I/O Input/outputA3.ReferencedtoV . CCA A4 6 6 I/O Input/outputA4.ReferencedtoV . CCA A5 7 7 I/O Input/outputA5.ReferencedtoV . CCA A6 8 8 I/O Input/outputA6.ReferencedtoV . CCA A7 9 9 I/O Input/outputA7.ReferencedtoV . CCA A8 10 10 I/O Input/outputA8.ReferencedtoV . CCA B1 21 21 I/O Input/outputB1.ReferencedtoV . CCB B2 20 20 I/O Input/outputB2.ReferencedtoV . CCB B3 19 19 I/O Input/outputB3.ReferencedtoV . CCB B4 18 18 I/O Input/outputB4.ReferencedtoV . CCB B5 17 17 I/O Input/outputB5.ReferencedtoV . CCB B6 16 16 I/O Input/outputB6.ReferencedtoV . CCB B7 15 15 I/O Input/outputB7.ReferencedtoV . CCB B8 14 14 I/O Input/outputB8.ReferencedtoV . CCB DIR 2 2 I Direction-controlsignal.ReferencedtoV . CCA OE 22 22 I 3-stateoutput-modeenables.PullOEhightoplacealloutputsin3-statemode.ReferencedtoV . CCA V 1 1 — A-portsupplyvoltage.1.65V≤V ≤5.5V CCA CCA V 23,24 23,24 — B-portsupplyvoltage.1.65V≤V ≤5.5V CCB CCA 11,12, 11,12, GND — Ground 13 13 Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltage V andV –0.5 6.5 V CCA CCB I/Oports(Aport) –0.5 6.5 Inputvoltage(2) I/Oports(Bport) –0.5 6.5 V Controlinputs –0.5 6.5 Voltagerangeappliedtoanyoutput Aport –0.5 6.5 inthehigh-impedanceorpower-offstate(2) Bport –0.5 6.5 V Aport –0.5 V +0.5 Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) CCA V Bport –0.5 V +0.5 CCB Inputclampcurrent V <0 –50 mA I Outputclampcurrent V <0 –50 mA O Continuousoutputcurrent,I ±50 mA O Continuousthroughcurrent V ,V ,andGND ±100 mA CCA CCB Junctiontemperature,T –40 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Theoutputpositive-voltageratingmaybeexceededupto6.5Vmaximumiftheoutputcurrentratingisobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) Machinemodel(MM) ±200 (1) JEDECdocumentJEP155statesthat500VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2)(3) MIN MAX UNIT V 1.65 5.5 CCA Supplyvoltage V V 1.65 5.5 CCB V =1.65Vto4.5V V ×0.65 CCI CCI V =2.3Vto2.7V 1.7 V High-levelinputvoltage(1) Datainputs(4) CCI V IH V =3Vto3.6V 2 CCI V =4.5Vto5.5V V ×0.7 CCI CCI V =1.65Vto4.5V V ×0.35 CCI CCI V =2.3Vto2.7V 0.7 V Low-levelinputvoltage(1) Datainputs(4) CCI V IL V =3Vto3.6V 0.8 CCI V =4.5Vto5.5V V ×0.3 CCI CCI (1) V istheV associatedwiththedatainputport. CCI CC (2) V istheV associatedwiththeoutputport. CCO CC (3) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperationandminimizepower CCA consumption.SeeImplicationsofSloworFloatingCMOSInputs,SCBA004. (4) ForV valuesnotspecifiedinthedatasheet,V min=V ×0.7V,V (max)=V ×0.3V. CCI IH CCI IL CCI 4 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 Recommended Operating Conditions (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2)(3) MIN MAX UNIT V =1.65Vto4.5V V ×0.65 CCI CCA Controlinputs VCCI=2.3Vto2.7V 1.7 VIH High-levelinputvoltage (referencedtoVCCA)(5) VCCI=3Vto3.6V 2 V V =4.5Vto5.5V V ×0.7 CCI CCA V =1.65Vto4.5V V ×0.35 CCI CCA Controlinputs VCCI=2.3Vto2.7V 0.7 VIL Low-levelinputvoltage (referencedtoVCCA)(5) VCCI=3Vto3.6V 0.8 V V =4.5Vto5.5V V ×0.3 CCI CCA V Inputvoltage Controlinputs(3) 0 5.5 V I Activestate 0 V V Input/outputvoltage(2) CCO V I/O 3-State 0 5.5 V =1.65Vto4.5V –4 CCO V =2.3Vto2.7V –8 CCO I High-leveloutputcurrent mA OH V =3Vto3.6V –24 CCO V =4.5Vto5.5V –32 CCO V =1.65Vto4.5V 4 CCO V =2.3Vto2.7V 8 CCO I Low-leveloutputcurrent mA OL V =3Vto3.6V 24 CCO V =4.5Vto5.5V 32 CCO V =1.65Vto4.5V 20 CCI V =2.3Vto2.7V 20 CCI Δt/Δv Inputtransitionriseorfallrate Datainputs ns/V V =3Vto3.6V 10 CCI V =4.5Vto5.5V 5 CCI T Operatingfree-airtemperature –40 85 °C A (5) ForV valuesnotspecifiedinthedatasheet,V min=V ×0.7V,V (max)=V ×0.3V. CCA IH CCA IL CCA 6.4 Thermal Information SN74LVCH8T245 THERMALMETRIC(1) DB(SSOP) DGV(TVSOP) PW(TSSOP) RHL(VQFN) UNIT 24PINS 24PINS 24PINS 24PINS R Junction-to-ambientthermalresistance 88.5 91.1 90.6 37.4 °C/W θJA R Junction-to-case(top)thermalresistance 48.7 23.7 27.6 38.1 °C/W θJC(top) R Junction-to-boardthermalresistance 44.1 44.5 45.3 15.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 12.8 0.6 1.3 0.7 °C/W JT Junction-to-boardcharacterization ψ 43.6 44.1 44.8 15.2 °C/W JB parameter Junction-to-case(bottom)thermal R — — — 4.3 °C/W θJC(bot) resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 6.5 Electrical Characteristics AlltypicallimitsapplyoverT =25°C,andallmaximumandminimumlimitsapplyoverT =–40°Cto85°C(unlessotherwise A A noted).(1)(2) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I =–100μA,V =V V =V =1.65Vto4.5V V =0.1 OH I IH CCA CCB CCO I =–4mA,V =V V =V =1.65V 1.2 OH I IH CCA CCB High-leveloutput VOH voltage(1) IOH=–8mA,VI=VIH VCCA=VCCB=2.3V 1.9 V I =–24mA,V =V V =V =3V 2.4 OH I IH CCA CCB I =–32mA,V =V V =V =4.5V 3.8 OH I IH CCA CCB I =100μA,V =V V =V =1.65Vto4.5V 0.1 OL I IL CCA CCB I =4mA,V =V V =V =1.65V 0.45 OL I IL CCA CCB Low-leveloutput V I =8mA,V =V V =V =2.3V 0.3 V OL voltage OL I IL CCA CCB I =24mA,V =V V =V =3V 0.55 OL I IL CCA CCB I =32mA,V =V V =V =4.5V 0.55 OL I IL CCA CCB I Controlinputs V =V orGND V =V =1.65Vto4.5V ±0.5 ±2 μA I I CCA CCA CCB V =0.58V V =V =1.65V 15 I CCA CCB I (3) Bus-holdlow VI=0.7V VCCA=VCCB=2.3V 45 μA BHL sustainingcurrent V =0.8V V =V =3V 75 I CCA CCB V =1.35V V =V =4.5V 100 I CCA CCB V =1.07V V =V =1.65V –15 I CCA CCB I (4) Bus-holdhigh VI=1.7V VCCA=VCCB=2.3V –45 μA BHH sustainingcurrent V =2V V =V =3V –75 I CCA CCB V =3.15V V =V =4.5V –100 I CCA CCB V =V =1.95V 200 CCA CCB I (5) Bus-holdlow V =0toV VCCA=VCCB=2.7V 300 μA BHLO overdrivecurrent I CC V =V =3.6V 500 CCA CCB V =V =5.5V 900 CCA CCB V =V =1.95V –200 CCA CCB I (6) Bus-holdhigh V =0toV VCCA=VCCB=2.7V –300 μA BHHO overdrivecurrent I CC V =V =3.6V –500 CCA CCB V =V =5.5V –900 CCA CCB V =0V, Inputandoutput VCCA=0to5.5V APort ±0.5 ±2 CCB I power-offleakage V orV =0to5.5V μA off I O current VCCA=0to5.5V, BPort ±0.5 ±2 V =0V CCB V =V = APort, OE=V CCA CCB ±2 IH 1.65Vto4.5V BPort Off-stateoutput V =V orGND, V =0V, I O CCO CCA BPort ±2 μA OZ current V =V orGND V =5.5V I CCI CCB OE=X V =5.5V, CCA APort ±2 V =0V CCB V =V =1.65Vto4.5V 20 CCA CCB Supplycurrent I V =V orGND,I =0 V =5V,V =0V 20 μA CCA Aport I CCI O CCA CCB V =0V,V =5V –2 CCA CCB (1) V istheV associatedwiththeoutputport. CCO CC (2) V istheV associatedwiththeinputport. CCI CC (3) Thebus-holdcircuitcansinkatleasttheminimumlowsustainingcurrentattheV maximum.I shouldbemeasuredafterlowering IL BHL V toGNDandthenraisingittoV maximum. IN IL (4) Thebus-holdcircuitcansourceatleasttheminimumhighsustainingcurrentatV min.I shouldbemeasuredafterraisingV to IH BHH IN V andthenloweringittoV min. CC IH (5) AnexternaldrivermustsourceatleastI toswitchthisnodefromlowtohigh. BHLO (6) AnexternaldrivermustsinkatleastI toswitchthisnodefromhightolow. BHHO 6 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 Electrical Characteristics (continued) AlltypicallimitsapplyoverT =25°C,andallmaximumandminimumlimitsapplyoverT =–40°Cto85°C(unlessotherwise A A noted).(1)(2) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =V =1.65Vto4.5V 20 CCA CCB Supplycurrent I V =V orGND,I =0 V =5V,V =0V –2 μA CCB Bport I CCI O CCA CCB V =0V,V =5V 20 CCA CCB Combinedsupply V =V orGND,I =0 V =V =1.65Vto4.5V 30 μA current I CCI O CCA CCB DIRatV -0.6V, Supply-current CCA ΔI Bport=open, V =V =3to5.5V 50 μA CCA changeDIR CCA CCB AportatV orGND CCA Inputcapacitance C V =V orGND V =V =3.3V 4 5 pF i controlinputs I CCA CCA CCB Inputandoutput C capacitance V =V orGND V =V =3.3V 8.5 10 pF io O CCA/B CCA CCB AorBport 6.6 Switching Characteristics: V = 1.8 V ± 0.15 V CCA overrecommendedoperatingfree-airtemperaturerange,V =1.8V±0.15V(unlessotherwisenoted)(seeFigure3) CCA FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) V =1.8V±0.15V 1.7 21.9 CCB V =2.5V±0.2V 1.3 9.2 CCB t ,t A B ns PLH PHL V =3.3V±0.3V 1 7.4 CCB V =5V±0.5V 0.4 7.1 CCB V =1.8V±0.15V 0.9 23.8 CCB V =2.5V±0.2V 0.8 23.6 CCB t ,t B A ns PLH PHL V =3.3V±0.3V 0.7 23.4 CCB V =5V±0.5V 0.7 23.4 CCB V =1.8V±0.15V 1.5 29.6 CCB V =2.5V±0.2V 1.5 29.4 CCB t ,t OE A ns PHZ PLZ V =3.3V±0.3V 1.5 29.3 CCB V =5V±0.5V 1.4 29.2 CCB V =1.8V±0.15V 2.4 32.2 CCB V =2.5V±0.2V 1.9 13.1 CCB t ,t OE B ns PHZ PLZ V =3.3V±0.3V 1.7 12 CCB V =5V±0.5V 1.3 10.3 CCB V =1.8V±0.15V 0.4 24 CCB V =2.5V±0.2V 0.4 23.8 CCB t ,t OE A ns PZH PZL V =3.3V±0.3V 0.4 23.7 CCB V =5V±0.5V 0.4 23.7 CCB V =1.8V±0.15V 1.8 32 CCB V =2.5V±0.2V 1.5 16 CCB t ,t OE B ns PZH PZL V =3.3V±0.3V 1.2 12.6 CCB V =5V±0.5V 0.9 10.8 CCB Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 6.7 Switching Characteristics: V = 2.5 V ± 0.2 V CCA overrecommendedoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted)(seeFigure3) CCA FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) V =1.8V±0.15V 1.5 21.4 CCB V =2.5V±0.2V 1.2 9 CCB t ,t A B ns PLH PHL V =3.3V±0.3V 0.8 6.2 CCB V =5V±0.5V 0.6 4.8 CCB V =1.8V±0.15V 1.2 9.3 CCB V =2.5V±0.2V 1 9.1 CCB t ,t B A ns PLH PHL V =3.3V±0.3V 1 8.9 CCB V =5V±0.5V 0.9 8.8 CCB V =1.8V±0.15V 1.4 9 CCB V =2.5V±0.2V 1.4 9 CCB t ,t OE A ns PHZ PLZ V =3.3V±0.3V 1.4 9 CCB V =5V±0.5V 1.4 9 CCB V =1.8V±0.15V 2.3 29.6 CCB V =2.5V±0.2V 1.8 11 CCB t ,t OE B ns PHZ PLZ V =3.3V±0.3V 1.7 9.3 CCB V =5V±0.5V 0.9 6.9 CCB V =1.8V±0.15V 1 10.9 CCB V =2.5V±0.2V 1 10.9 CCB t ,t OE A ns PZH PZL V =3.3V±0.3V 1 10.9 CCB V =5V±0.5V 1 10.9 CCB V =1.8V±0.15V 1.7 28.2 CCB V =2.5V±0.2V 1.5 12.9 CCB t ,t OE B ns PZH PZL V =3.3V±0.3V 1.2 9.4 CCB V =5V±0.5V 1 6.9 CCB 8 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 6.8 Switching Characteristics: V = 3.3 V ± 0.3 V CCA overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure3) CCA FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) V =1.8V±0.15V 1.5 21.2 CCB V =2.5V±0.2V 1.1 8.8 CCB t ,t A B ns PLH PHL V =3.3V±0.3V 0.8 6.2 CCB V =5V±0.5V 0.5 4.4 CCB V =1.8V±0.15V 0.8 7.2 CCB V =2.5V±0.2V 0.8 6.2 CCB t ,t B A ns PLH PHL V =3.3V±0.3V 0.7 6.1 CCB V =5V±0.5V 0.6 6 CCB V =1.8V±0.15V 1.6 8.2 CCB V =2.5V±0.2V 1.6 8.2 CCB t ,t OE A ns PHZ PLZ V =3.3V±0.3V 1.6 8.2 CCB V =5V±0.5V 1.6 8.2 CCB V =1.8V±0.15V 2.1 29 CCB V =2.5V±0.2V 1.7 10.3 CCB t ,t OE B ns PHZ PLZ V =3.3V±0.3V 1.5 8.6 CCB V =5V±0.5V 0.8 6.3 CCB V =1.8V±0.15V 0.8 8.1 CCB V =2.5V±0.2V 0.8 8.1 CCB t ,t OE A ns PZH PZL V =3.3V±0.3V 0.8 8.1 CCB V =5V±0.5V 0.8 8.1 CCB V =1.8V±0.15V 1.8 27.7 CCB V =2.5V±0.2V 1.4 12.4 CCB t ,t OE B ns PZH PZL V =3.3V±0.3V 1.1 8.5 CCB V =5V±0.5V 0.9 6.4 CCB Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 6.9 Switching Characteristics: V = 5 V ± 0.5 V CCA overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure3) CCA FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) V =1.8V±0.15V 1.5 21.4 CCB V =2.5V±0.2V 1 8.8 CCB t ,t A B ns PLH PHL V =3.3V±0.3V 0.7 6 CCB V =5V±0.5V 0.4 4.2 CCB V =1.8V±0.15V 0.7 7 CCB V =2.5V±0.2V 0.4 4.8 CCB t ,t B A ns PLH PHL V =3.3V±0.3V 0.3 4.5 CCB V =5V±0.5V 0.3 4.3 CCB V =1.8V±0.15V 0.3 5.4 CCB V =2.5V±0.2V 0.3 5.4 CCB t ,t OE A ns PHZ PLZ V =3.3V±0.3V 0.3 5.4 CCB V =5V±0.5V 0.3 5.4 CCB V =1.8V±0.15V 2 28.7 CCB V =2.5V±0.2V 1.6 9.7 CCB t ,t OE B ns PHZ PLZ V =3.3V±0.3V 1.4 8 CCB V =5V±0.5V 0.7 5.7 CCB V =1.8V±0.15V 0.7 6.4 CCB V =2.5V±0.2V 0.7 6.4 CCB t ,t OE A ns PZH PZL V =3.3V±0.3V 0.7 6.4 CCB V =5V±0.5V 0.7 6.4 CCB V =1.8V±0.15V 1.5 27.6 CCB V =2.5V±0.2V 1.3 11.4 CCB t ,t OE B ns PZH PZL V =3.3V±0.3V 1 8.1 CCB V =5V±0.5V 0.9 6 CCB 10 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 6.10 Operating Characteristics T =25°C A PARAMETER(1) TESTCONDITIONS TYP UNIT V =V =1.8V 2 CCA CCB V =V =2.5V 2 CCA CCB A-portinput,B-portoutput C =0,f=10MHz,t =t =1ns L r f V =V =3.3V 2 CCA CCB V =V =5V 3 C (2) CCA CCB pF pdA V =V =1.8V 12 CCA CCB V =V =2.5V 13 CCA CCB B-portinput,A-portoutput C =0,f=10MHz,t =t =1ns L r f V =V =3.3V 13 CCA CCB V =V =5V 16 CCA CCB V =V =1.8V 13 CCA CCB V =V =2.5V 13 CCA CCB A-portinput,B-portoutput C =0,f=10MHz,t =t =1ns L r f V =V =3.3V 14 CCA CCB V =V =5V 16 C (2) CCA CCB pF pdB V =V =1.8V 2 CCA CCB V =V =2.5V 2 CCA CCB B-portinput,A-portoutput C =0,f=10MHz,t =t =1ns L r f V =V =3.3V 2 CCA CCB V =V =5V 3 CCA CCB (1) SeeCMOSPowerConsumptionandCpdCalculation,SCAA035. (2) Powerdissipationcapacitancepertransceiver. 6.11 Typical Characteristics 1.4 5.6 1.2 5.4 1.0 5.2 V) V) ( ( Voltage 00..86 Voltage 54..08 L H O O V V 0.4 4.6 -40oC -40oC 0.2 25oC 4.4 25oC 85oC 85oC 0 4.2 0 20 40 60 80 100 0 -20 -40 -60 -80 -100 I Current(mA) I Current(mA) OL OH Figure1.VoltagevsCurrent Figure2.VoltagevsCurrent Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 7 Parameter Measurement Information 2×VCCO TEST S1 S1 From Output RL Open tpd Open UnderTest GND tPLZ/tPZL 2×VCCO tPHZ/tPZH GND CL RL (see NoteA) LOAD CIRCUIT tw VCCI Input VCCI/2 VCCI/2 VCCO CL RL VTP 0 V 1.8 V±0.15 V 15 pF 2 kW 0.15 V VOLTAGE WAVEFORMS 2.5 V±0.2 V 15 pF 2 kW 0.15 V PULSE DURATION 3.3 V±0.3 V 15 pF 2 kW 0.3 V 5 V±0.5 V 15 pF 2 kW 0.3 V Output VCCA Control VCCA/2 VCCA/2 (low-level enabling) 0 V tPZL tPLZ VCCI Output VCCO Input VCCI/2 VCCI/2 Waveform 1 VCCO/2 VOL+ VTP 0 V S1 at 2×VCCO VOL (see Note B) tPLH tPHL tPZH tPHZ Output Output VCCO/2 VCCO/2VOH WSa1v eafto rGmN 2D VCCO/2 VOH−VTP VOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLETIMES NOTES: A. CLincludes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50W, dv/dt≥1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZand tPHZare the same as tdis. F. tPZLand tPZHare the same as ten. G. tPLHand tPHLare the same as tpd. H. VCCIis the VCCassociated with the input port. I. VCCOis the VCCassociated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 12 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 8 Detailed Description 8.1 Overview The SN74LVCH8T245 is an 8-bit, dual supply noninverting voltage level translator. Pins A1 through A4, and the control pins (DIR and OE) are referenced to V , while pins B1 through B4 are referenced to V . Both the A CCA CCB port and B port can accept I/O voltages ranging from 1.65 V to 5.5 V. The high on DIR allows data transmission from Port A to Port B, and a low on DIR allows data transmission from Port B to Port A. See AVC Logic Family TechnologyandApplications(SCEA006). 8.2 Functional Block Diagram 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels 8.3 Feature Description 8.3.1 FullyConfigurableDual-RailDesign Both V and V can be supplied at any voltage from 1.65 V to 5.5 V, making the device suitable for CCA CCB translatingbetweenanyofthevoltagenodes:1.8V,2.5V,3.3Vand5V. 8.3.2 Partial-Power-DownModeOperation I circuitry disables the outputs, preventing damaging current backflow through the device when it is powered off down. This can occur in applications where subsections of a system are powered down (partial power down) to reducepowerconsumption. 8.3.3 ActiveBusHoldCircuitry Active bus-hold circuitry holds unused or undriven inputs at a valid logic state, which helps with board space savings and reduced component costs. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. 8.3.4 SupportsHigh-SpeedTranslation The device can support high data rate applications, which can be calculated from the maximum propagation delay. This is also dependant on the output load. For example, for a 3.3-V to 5-V conversion, the maximum frequencyis200MHz. 8.3.5 V Isolation CC The V isolation feature ensures that if either V or V are at GND (or < 0.4 V), both ports will be in a high- CC CCA CCB impedancestate(I showninElectricalCharacteristics).Thispreventsfalselogiclevelsfrombeingpresentedto OZ eitherbus. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSN74LVCH8T245. Table1.FunctionTable(Each8-BitSection) CONTROLINPUTS(1) OUTPUTCIRCUITS OPERATION OE DIR APORT BPORT L L Enabled Hi-Z BdatatoAbus L H Hi-Z Enabled AdatatoBbus H X Hi-Z Hi-Z Isolation (1) InputcircuitsofthedataI/Osarealwaysactive. 14 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LVCH8T245 device can be used in level-translation applications for interfacing devices or systems operatingatdifferentinterfacevoltageswithoneanother.Themaximumoutputcurrentcanbeupto32mAwhen deviceispoweredby5V. 9.2 Typical Application 1.8V 5V 0.1μF 0.1μF 1 µF VCCA VCCB DIR OE 1.8V 5V SN74LVCH8T245 Controller System A1 B1 A2 B2 A3 B3 A4 B4 Data Data A5 B5 A6 B6 A7 B7 A8 B8 GND GND GND Figure4. TypicalApplicationCircuit Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com Typical Application (continued) 9.2.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable2. Table2.DesignParameters PARAMETERS VALUES Inputvoltage 1.65Vto5.5V Outputvoltage 1.65Vto5.5V 9.2.2 DetailedDesignProcedure Tobeginthedesignprocess,determinethefollowing: • Inputvoltagerange – Use the supply voltage of the device that is driving the SN74LVCH8T245 to determine the input voltage range. For a valid logic high, the value must exceed the V of the input port. For a valid logic low, the IH valuemustbelessthantheV oftheinputport. IL • Outputvoltagerange – Use the supply voltage of the device that the SN74LVCH8T245 is driving to determine the output voltage range. 9.2.2.1 EnableTimes CalculatetheenabletimesfortheSN74LVCH8T245usingEquation1,Equation2,Equation3,andEquation4: t (DIRtoA)=t (DIRtoB)+t (BtoA) (1) PZH PLZ PLH t (DIRtoA)=t (DIRtoB)+t (BtoA) (2) PZL PHZ PHL t (DIRtoB)=t (DIRtoA)+t (AtoB) (3) PZH PLZ PLH t (DIRtoB)=t (DIRtoA)+t (AtoB) (4) PZL PHZ PHL In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the device initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 9.2.3 ApplicationCurve Output (5 V) V) e ( g a olt V Input (1.8 V) Time (200 ns/div) Figure5.TranslationUp(1.8Vto5V)at2.5MHz 16 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 10 Power Supply Recommendations The output-enable (OE) input circuit is designed so that it is supplied by V and when the OE input is high, all CCA outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to V through a pullup resistor and must not be enabled until CCA V and V are fully ramped and stable. The minimum value of the pullup resistor to V is determined by CCA CCB CCA thecurrent-sinkingcapabilityofthedriver. V or V can be powered up first. If the SN74LVCH8T245 is powered up in a permanently enabled state CCA CCB (for example OE is always kept low), pullup resistors are recommended at the input. This ensures proper, glitch- free,power-up.SeeDesigningwithSN4LVCXT245andSN74LVCHXT245FamilyofDirectionControlledVoltage Translators/Level-Shifters (SLVA746). In addition, the OE pin may be shorted to GND if the application does not requireuseofthehigh-impedancestateatanytime. 11 Layout 11.1 Layout Guidelines Toensurereliabilityofthedevice,TIrecommendsthefollowingcommonprinted-circuitboardlayoutguidelines. • Bypasscapacitorsshouldbeusedonpowersupplies. • Shorttracelengthsshouldbeusedtoavoidexcessiveloading. • Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of signalsdependingonthesystemrequirements. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 SCES637B–AUGUST2005–REVISEDFEBRUARY2016 www.ti.com 11.2 Layout Example LEGEND VIAto Power Plane Polygonal Copper Pour VIAto GND Plane (Inner Layer) VCCA VCCB Bypass Capacitor Bypass Capacitor V CCA 1 V V 16 CCA CCB Keep OE high until V and 2 DIR VCCB 15 VCCBare powered CuCAp From 3 A1 OE 14 Controller CoFnrtoromller 4 A2 B1 13 SyTsotem CoFnrtoromller 5 A3 B2 12 SyTsotem CoFnrtoromller 6 A4 B3 11 SyTsotem CoFnrtoromller 7 A5 B4 10 SyTsotem CoFnrtoromller 8 A6 B5 12 SyTsotem CoFnrtoromller 9 A7 B6 11 SyTsotem CoFnrtoromller 10 A8 B7 10 SyTsotem To 11 GND B8 10 System 12 GND GND 13 SN74LVCH8T245 Figure6. SN74LVCH8T245Layout 18 SubmitDocumentationFeedback Copyright©2005–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH8T245

SN74LVCH8T245 www.ti.com SCES637B–AUGUST2005–REVISEDFEBRUARY2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • Designing with SN74LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage Translators/Level-Shifters,SLVA746 • Bus-HoldCircuit,SCLA015 • AVCLogicFamilyTechnologyandApplications,SCEA006 • CMOSPowerConsumptionandCpdCalculation,SCAA035 12.2 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2005–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN74LVCH8T245

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVCH8T245DBR ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 & no Sb/Br) SN74LVCH8T245DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 & no Sb/Br) SN74LVCH8T245PW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 & no Sb/Br) SN74LVCH8T245PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 & no Sb/Br) SN74LVCH8T245PWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 & no Sb/Br) SN74LVCH8T245RHLR ACTIVE VQFN RHL 24 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 NJ245 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVCH8T245DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74LVCH8T245DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVCH8T245PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 SN74LVCH8T245RHLR VQFN RHL 24 1000 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVCH8T245DBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVCH8T245DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LVCH8T245PWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVCH8T245RHLR VQFN RHL 24 1000 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OUTLINE RHL0024A VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD 3.6 A B 3.4 PIN 1 INDEX AREA 5.6 5.4 C 1 MAX SEATING PLANE 0.05 0.00 2.05±0.1 0.08 C 2X 1.5 SYMM 0.5 24X 0.3 (0.1) TYP 12 13 18X 0.5 11 14 21 2X SYMM 4.05±0.1 4.5 2 23 0.30 24X 0.18 PIN 1 ID 1 24 0.1 C A B (OPTIONAL) 4X (0.2) 2X (0.55) 0.05 C 4225250/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHL0024A VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD (3.3) (2.05) 2X (1.5) SYMM 1 24 24X (0.6) 24X (0.24) 2X (0.4) 23 2 18X (0.5) 2X (1.105) 25 6X (0.67) SYMM (4.05) 4.6 (5.3) 4.4 SOLDER MASK OPENING METAL UNDER SOLDER MASK (Ø 0.2) VIA TYP (R0.05) TYP 11 14 12 13 4X (0.775) 4X (0.2) 2X (0.55) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X 0.07 MIN SOLDER MASK 0.07 MAX ALL AROUND OPENING ALL AROUND EXPOSED METAL EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225250/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHL0024A VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD (3.3) (2.05) 2X (1.5) SYMM SOLDER MASK EDGE 1 24 TYP 24X (0.6) 24X (0.24) 23 2 18X (0.5) 25 SYMM 4.6 (5.3) 4.4 4X (1.34) METAL TYP (R0.05) TYP 11 14 12 13 2X (0.84) 6X (0.56) 4X (0.2) 2X (0.55) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 18X 4225250/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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