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  • 制造商: Texas Instruments
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ICGOO电子元器件商城为您提供SN74LVCH244ADBQR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74LVCH244ADBQR价格参考¥1.14-¥3.27。Texas InstrumentsSN74LVCH244ADBQR封装/规格:逻辑 - 缓冲器,驱动器,接收器,收发器, Buffer, Non-Inverting 2 Element 4 Bit per Element 3-State Output 20-SSOP/QSOP。您可以下载SN74LVCH244ADBQR参考资料、Datasheet数据手册功能说明书,资料中有SN74LVCH244ADBQR 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC BUFF/DVR TRI-ST DUAL 20QSOP缓冲器和线路驱动器 Octal Buffer/Driver W/3-State Output

产品分类

逻辑 - 缓冲器,驱动器,接收器,收发器

品牌

Texas Instruments

产品手册

点击此处下载产品Datasheet

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

逻辑集成电路,缓冲器和线路驱动器,Texas Instruments SN74LVCH244ADBQR74LVCH

数据手册

点击此处下载产品Datasheet

产品型号

SN74LVCH244ADBQR

产品目录页面

点击此处下载产品Datasheet

产品种类

缓冲器和线路驱动器

传播延迟时间

6.9 ns at 2.7 V, 5.9 ns at 3.3 V

低电平输出电流

24 mA

供应商器件封装

20-SSOP/QSOP

元件数

2

其它名称

296-23284-1

包装

剪切带 (CT)

单位重量

125.800 mg

商标

Texas Instruments

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

20-SSOP(0.154",3.90mm 宽)

封装/箱体

SSOP-20

工作温度

-40°C ~ 85°C

工厂包装数量

2500

最大工作温度

+ 85 C

最小工作温度

- 40 C

极性

Non-Inverting

标准包装

1

每元件位数

4

每芯片的通道数量

8

电压-电源

1.65 V ~ 3.6 V

电流-输出高,低

24mA,24mA

电源电压-最大

3.6 V

电源电压-最小

1.65 V

电源电流

0.01 mA

系列

SN74LVCH244A

输入线路数量

8

输出类型

3-State

输出线路数量

3

逻辑类型

缓冲器/线路驱动器,非反相

逻辑系列

LVC

高电平输出电流

- 24 mA

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SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 FEATURES • OperateFrom1.65Vto3.6V • I SupportsPartial-Power-DownMode off • InputsAcceptVoltagesto5.5V Operation • Maxt of5.9nsat3.3V • BusHoldonDataInputsEliminatestheNeed pd • TypicalV (OutputGroundBounce) forExternalPullup/PulldownResistors <0.8VatOVLP =3.3V,T =25(cid:176) C • Latch-UpPerformanceExceeds250mAPer CC A • TypicalV (OutputV Undershoot) JESD17 >2VatVOHV=3.3V,T O=H25(cid:176) C • ESDProtectionExceedsJESD22 CC A • SupportMixed-ModeSignalOperationonAll – 2000-VHuman-BodyModel(A114-A) Ports – 200-VMachineModel(A115-A) (5-VInput/OutputVoltageWith3.3-VVCC) – 1000-VCharged-DeviceModel(C101) SN54LVCH244A...J OR W PACKAGE SN74LVCH244A...RGY PACKAGE SN54LVCH244A...FK PACKAGE SN74LVCH244A...DB, DBQ, DGV, DW, (TOP VIEW) (TOP VIEW) NS, OR PW PACKAGE E C 4 1E CE (TOP VIEW) O C Y AO CO 1 V 2 11V 2 1OE 1 20 VCC 1 20 3 2 1 20 19 1A1 2 19 2OE 1A1 2 19 2OE 1A2 4 18 1Y1 2Y4 3 18 1Y1 2Y4 3 18 1Y1 2Y3 5 17 2A4 1A2 4 17 2A4 1A2 4 17 2A4 1A3 6 16 1Y2 2Y3 5 16 1Y2 2Y3 5 16 1Y2 2Y2 7 15 2A3 1A3 6 15 2A3 1A3 6 15 2A3 1A4 8 14 1Y3 9 10 11 12 13 2Y2 7 14 1Y3 2Y2 7 14 1Y3 1A4 8 13 2A2 1A4 8 13 2A2 1 D 14 2 Y N AY A 2Y1 9 12 1Y4 2Y1 9 12 1Y4 2 G 21 2 GND 10 11 2A1 10 11 D 1 N A G 2 DESCRIPTION/ORDERING INFORMATION The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V V operation, and the CC SN74LVCH244Aoctalbuffer/linedriverisdesignedfor1.65-Vto3.6-VV operation. CC These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedancestate. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistorswiththebus-holdcircuitryisnotrecommended. Inputscanbedrivenfromeither3.3-Vor5-Vdevices.Thisfeature allows the use of these devices as translators inamixed3.3-V/5-Vsystemenvironment. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs,preventingdamagingcurrentbackflowthroughthedeviceswhentheyarepowereddown. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1995–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A QFN–RGY Reelof1000 SN74LVCH244ARGYR LCH244A Tubeof25 SN74LVCH244ADW SOIC–DW LVCH244A Reelof2000 SN74LVCH244ADWR SOP–NS Reelof2000 SN74LVCH244ANSR LVCH244A SSOP–DB Reelof2000 SN74LVCH244ADBR LCH244A –40(cid:176) Cto85(cid:176) C SSOP(QSOP)–DBQ Reelof2500 SN74LVCH244ADBQR LVCH244A Tubeof70 SN74LVCH244APW TSSOP–PW Reelof2000 SN74LVCH244APWR LCH244A Reelof250 SN74LVCH244APWT TVSOP–DGV Reelof2000 SN74LVCH244ADGVR LCH244A CDIP–J Tubeof20 SNJ54LVCH244AJ SNJ54LVCH244AJ –55(cid:176) Cto125(cid:176) C CFP–W Tubeof85 SNJ54LVCH244AW SNJ54LVCH244AW LCCC–FK Tubeof55 SNJ54LVCH244AFK SNJ54LVCH244AFK (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. FUNCTIONTABLE (EACHBUFFER) INPUTS OUTPUT OE A Y L H H L L L H X Z LOGICDIAGRAM(POSITIVELOGIC) 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 2 SubmitDocumentationFeedback

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent – 50 mA O ContinuouscurrentthroughV orGND – 100 mA CC DBpackage(4) 70 DBQpackage(4) 68 DGVpackage(4) 92 q Packagethermalimpedance DWpackage(4) 58 (cid:176) C/W JA NSpackage(4) 60 PWpackage(4) 83 RGYpackage(5) 37 T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintherecommendedoperatingconditionstable. CC (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (5) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. SubmitDocumentationFeedback 3

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 Recommended Operating Conditions(1) SN54LVCH244A SN74LVCH244A UNIT MIN MAX MIN MAX Operating 2 3.6 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 1.5 V =1.65Vto1.95V 0.65· V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 2 CC V =1.65Vto1.95V 0.35· V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 0.8 CC V Inputvoltage 0 5.5 0 5.5 V I Highorlowstate 0 V 0 V CC CC V Outputvoltage V O 3-state 0 5.5 0 5.5 V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 –12 CC V =3V –24 –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 12 CC V =3V 24 24 CC D t/D v Inputtransitionriseorfallrate 10 10 ns/V T Operatingfree-airtemperature –55 125 –40 85 (cid:176) C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 4 SubmitDocumentationFeedback

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LVCH244A SN74LVCH244A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP(1) MAX MIN TYP(1) MAX 1.65Vto3.6V V –0.2 I =–100m A CC OH 2.7Vto3.6V V –0.2 CC I =–4mA 1.65V 1.2 OH V I =–8mA 2.3V 1.7 V OH OH 2.7V 2.2 2.2 I =–12mA OH 3V 2.4 2.4 I =–24mA 3V 2.2 2.2 OH 1.65Vto3.6V 0.2 I =100m A OL 2.7Vto3.6V 0.2 I =4mA 1.65V 0.45 OL V V OL I =8mA 2.3V 0.7 OL I =12mA 2.7V 0.4 0.4 OL I =24mA 3V 0.55 0.55 OL I V =0to5.5V 3.6V – 5 – 5 m A I I I V orV =5.5V 0 – 10 m A off I O V =0.58V (2) I 1.65V V =1.07V (2) I V =0.7V 45 I 2.3V I V =1.7V –45 m A I(hold) I V =0.8V 75 75 I 3V V =2V –75 –75 I V =0to3.6V(3) 3..6V – 500 – 500 I I V =0to5.5V 3.6V – 15 – 10 m A OZ O V =V orGND 10 10 I I CC I =0 3.6V m A CC 3.6V£ V £ 5.5V(4) O 10 10 I D I OneinputatVCC–0.6V, 2.7Vto3.6V 500 500 m A CC OtherinputsatV orGND CC C V =V orGND 3.3V 4 12 4 pF i I CC C V =V orGND 3.3V 5.5 12 5.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25(cid:176) C. CC A (2) Thisinformationwasnotavailableatthetimeofpublication. (3) Thisisthebus-holdmaximumdynamiccurrentrequiredtoswitchtheinputfromonestatetoanother. (4) Thisappliesinthedisabledstateonly. SubmitDocumentationFeedback 5

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) SN54LVCH244A FROM TO V =3.3V PARAMETER (INPUT) (OUTPUT) VCC=2.7V C–C0.3V UNIT MIN MAX MIN MAX t A Y 7.5 1 6.5 ns pd t OE Y 9 1 8 ns en t OE Y 8 1 7 ns dis Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) SN74LVCH244A FROM TO V =1.8V V =2.5V V =3.3V PARAMETER (INPUT) (OUTPUT) C– C0.15V C–C0.2V VCC=2.7V C–C0.3V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t A Y (1) (1) (1) (1) 6.9 1.5 5.9 ns pd t OE Y (1) (1) (1) (1) 8.6 1 7.6 ns en t OE Y (1) (1) (1) (1) 6.8 1.5 5.8 ns dis (1) Thisinformationwasnotavailableatthetimeofpublication. Operating Characteristics T =25(cid:176) C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipationcapacitance Outputsenabled (1) (1) 47 C f=10MHz pF pd perbuffer/driver Outputsdisabled (1) (1) 2 (1) Thisinformationwasnotavailableatthetimeofpublication. 6 SubmitDocumentationFeedback

SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O–JULY1995–REVISEDFEBRUARY2007 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms SubmitDocumentationFeedback 7

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9754201Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9754201Q2A SNJ54LVCH 244AFK 5962-9754201QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9754201QR A SNJ54LVCH244AJ 5962-9754201QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9754201QS A SNJ54LVCH244AW 5962-9754201V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9754201V2A SNV54LVCH 244AFK 5962-9754201VSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9754201VS A SNV54LVCH244AW SN74LVCH244ADBQR ACTIVE SSOP DBQ 20 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVCH244A & no Sb/Br) SN74LVCH244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244ADW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH244A & no Sb/Br) SN74LVCH244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH244A & no Sb/Br) SN74LVCH244ANSR ACTIVE SO NS 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH244A & no Sb/Br) SN74LVCH244APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVCH244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244APWT ACTIVE TSSOP PW 20 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LCH244A & no Sb/Br) SN74LVCH244ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LCH244A & no Sb/Br) SNJ54LVCH244AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9754201Q2A SNJ54LVCH 244AFK SNJ54LVCH244AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9754201QR A SNJ54LVCH244AJ SNJ54LVCH244AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9754201QS A SNJ54LVCH244AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVCH244A, SN54LVCH244A-SP, SN74LVCH244A : •Catalog: SN74LVCH244A, SN54LVCH244A •Military: SN54LVCH244A •Space: SN54LVCH244A-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVCH244ADBQR SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVCH244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVCH244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVCH244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVCH244ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVCH244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVCH244ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVCH244ADBQR SSOP DBQ 20 2500 367.0 367.0 38.0 SN74LVCH244ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVCH244ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVCH244ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVCH244ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVCH244APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LVCH244ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A TSSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/A 12/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/A 12/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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