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  • 制造商: Texas Instruments
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SN74LVCH16244ADGGR产品简介:

ICGOO电子元器件商城为您提供SN74LVCH16244ADGGR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74LVCH16244ADGGR价格参考¥5.57-¥11.12。Texas InstrumentsSN74LVCH16244ADGGR封装/规格:逻辑 - 缓冲器,驱动器,接收器,收发器, Buffer, Non-Inverting 4 Element 4 Bit per Element 3-State Output 48-TSSOP。您可以下载SN74LVCH16244ADGGR参考资料、Datasheet数据手册功能说明书,资料中有SN74LVCH16244ADGGR 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC BUFF/DVR TRI-ST 16BIT 48TSSOP缓冲器和线路驱动器 Tri-State 16-Bit

产品分类

逻辑 - 缓冲器,驱动器,接收器,收发器

品牌

Texas Instruments

产品手册

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产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

逻辑集成电路,缓冲器和线路驱动器,Texas Instruments SN74LVCH16244ADGGR74LVCH

数据手册

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产品型号

SN74LVCH16244ADGGR

产品目录页面

点击此处下载产品Datasheet

产品种类

缓冲器和线路驱动器

传播延迟时间

4.7 ns at 2.7 V, 4.1 ns at 3.3 V

低电平输出电流

24 mA

供应商器件封装

48-TSSOP

元件数

4

其它名称

296-8573-1

包装

剪切带 (CT)

单位重量

223.200 mg

商标

Texas Instruments

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

48-TFSOP(0.240",6.10mm 宽)

封装/箱体

TSSOP-48

工作温度

-40°C ~ 85°C

工厂包装数量

2000

最大工作温度

+ 85 C

最小工作温度

- 40 C

极性

Non-Inverting

标准包装

1

每元件位数

4

每芯片的通道数量

16

电压-电源

1.65 V ~ 3.6 V

电流-输出高,低

24mA,24mA

电源电压-最大

3.6 V

电源电压-最小

1.65 V

电源电流

0.02 mA

系列

SN74LVCH16244A

输入线路数量

16

输出类型

3-State

输出线路数量

3

逻辑类型

缓冲器/线路驱动器,非反相

逻辑系列

LVC

高电平输出电流

- 24 mA

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PDF Datasheet 数据手册内容提取

Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 SN74LVCH16244A 16-Bit Buffer/Driver With 3-State Outputs 1 Features 2 Applications • MemberoftheTexasInstruments • Servers 1 Widebus™Family • PCsandNotebooks • OperatesFrom1.65Vto3.6V • NetworkSwitches • InputsAcceptVoltagesto5.5V • WirelessandTelecomInfrastructures • Maxtpdof4.1nsat3.3V • TVSet-topBoxes • TypicalVOLP (OutputGroundBounce) • ElectronicPointsofSale <0.8VatV =3.3V,T =25°C CC A • TypicalV (OutputV Undershoot) 3 Description OHV OH >2VatV =3.3V,T =25°C This 16-bit buffer/driver is designed for 1.65-V to CC A • IoffSupportsLiveInsertion,Partial-Power-Down 3.6-V VCC operation. The device can be used as four 4-bitbuffers,two8-bitbuffers,orone16-bitbuffer. Mode,andBack-DriveProtection • SupportsMixed-ModeSignalOperationonAll The SN74LVCH16244A device is designed Ports(5-VInputorOutputVoltageWith specificallytoimprovetheperformanceanddensityof 3.3-VV ) 3-state memory address drivers, clock drivers, and CC bus-orientedreceiversandtransmitters. • BusHoldonDataInputsEliminatestheNeedfor ExternalPulluporPulldownResistors DeviceInformation(1) • Latch-UpPerformanceExceeds250mAPer PARTNUMBER PACKAGE BODYSIZE(NOM) JESD17 TSSOP(48) 12.50mm×6.10mm • ESDProtectionExceedsJESD22 SN74LVCH16244A TVSOP(48) 9.70mm×4.40mm – 2000-VHuman-BodyModel(A114-A) SSOP(48) 15.88mm×7.49mm – 200-VMachineModel(A115-A) (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic 1 25 1OE 3OE 47 2 36 13 1A1 1Y1 3A1 3Y1 46 3 35 14 1A2 1Y2 3A2 3Y2 44 5 33 16 1A3 1Y3 3A3 3Y3 43 6 32 17 1A4 1Y4 3A4 3Y4 48 24 2OE 4OE 41 8 30 19 2A1 2Y1 4A1 4Y1 40 9 29 20 2A2 2Y2 4A2 4Y2 38 11 27 22 2A3 2Y3 4A3 4Y3 37 12 26 23 2A4 2Y4 4A4 4Y4 PinnumbersshownarefortheDGG,DGV,andDLpackages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9.1 Overview.................................................................11 2 Applications........................................................... 1 9.2 FunctionalBlockDiagram.......................................11 3 Description............................................................. 1 9.3 FeatureDescription.................................................12 9.4 DeviceFunctionalModes........................................12 4 SimplifiedSchematic............................................. 1 10 ApplicationandImplementation........................ 13 5 RevisionHistory..................................................... 2 10.1 ApplicationInformation..........................................13 6 PinConfigurationandFunctions......................... 3 10.2 TypicalApplication ...............................................13 7 Specifications......................................................... 6 11 PowerSupplyRecommendations..................... 14 7.1 AbsoluteMaximumRatings .....................................6 12 Layout................................................................... 14 7.2 HandlingRatings.......................................................6 12.1 LayoutGuidelines.................................................14 7.3 RecommendedOperatingConditions......................7 12.2 LayoutExample....................................................14 7.4 ThermalInformation..................................................7 13 DeviceandDocumentationSupport................. 15 7.5 ElectricalCharacteristics...........................................8 7.6 SwitchingCharacteristics..........................................8 13.1 Trademarks...........................................................15 7.7 OperatingCharacteristics..........................................8 13.2 ElectrostaticDischargeCaution............................15 7.8 TypicalCharacteristics..............................................9 13.3 Glossary................................................................15 8 ParameterMeasurementInformation................10 14 Mechanical,Packaging,andOrderable Information........................................................... 15 9 DetailedDescription............................................ 11 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionA(November2005)toRevisionB Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 • UpdatedI Featurebullet...................................................................................................................................................... 1 off • AddedApplications................................................................................................................................................................. 1 • AddedDeviceInformationtable............................................................................................................................................. 1 • AddedHandlingRatingstable. .............................................................................................................................................. 6 • ChangedMAXambienttemperatureto125°C. ..................................................................................................................... 7 • AddedThermalInformationtable........................................................................................................................................... 7 • Updatedt valuesinSwitchingCharacteristicstable......................................................................................................... 8 sk(o) • AddedTypicalCharacteristics. .............................................................................................................................................. 9 2 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 6 Pin Configuration and Functions DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 48 2OE 1Y1 2 47 1A1 1Y2 3 46 1A2 GND 4 45 GND 1Y3 5 44 1A3 1Y4 6 43 1A4 V 7 42 V CC CC 2Y1 8 41 2A1 2Y2 9 40 2A2 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 3Y1 13 36 3A1 3Y2 14 35 3A2 GND 15 34 GND 3Y3 16 33 3A3 3Y4 17 32 3A4 V 18 31 V CC CC 4Y1 19 30 4A1 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE PinFunctions PIN I/O DESCRIPTION NO. NAME 1 1OE I Outputenable1 2 1Y1 O 1Y1Output 3 1Y2 O 1Y2Output 4 GND — Groundpin 5 1Y3 O 1Y3Output 6 1Y4 O 1Y4Output 7 VCC — Powerpin 8 2Y1 O 2Y1Output 9 2Y2 O 2Y2Output 10 GND — Groundpin 11 2Y3 O 2Y3Output 12 2Y4 O 2Y4Output 13 3Y1 O 3Y1Output 14 3Y2 O 3Y2Output 15 GND — Groundpin 16 3Y3 O 3Y3Output 17 3Y4 O 3Y4Output 18 VCC — Powerpin Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com PinFunctions(continued) PIN I/O DESCRIPTION NO. NAME 19 4Y1 O 4Y1Output 20 4Y2 O 4Y2Output 21 GND — Groundpin 22 4Y3 O 4Y3Output 23 4Y4 O 4Y4Output 24 4OE I Outputenable4 25 3OE I Outputenable3 26 4A4 I 4A4Input 27 4A3 I 4A3Input 28 GND — Groundpin 29 4A2 I 4A2Input 30 4A1 I 4A1Input 31 VCC — Powerpin 32 3A4 I 3A4Input 33 3A3 I 3A3Input 34 GND — Groundpin 35 3A2 I 3A2Input 36 3A1 I 3A1Input 37 2A4 I 2A4Input 38 2A3 I 2A3Input 39 GND — Groundpin 40 2A2 I 2A2Input 41 2A1 I 2A1Input 42 VCC — Powerpin 43 1A4 I 1A4Input 44 1A3 I 1A3Input 45 GND — Groundpin 46 1A2 I 1A2Input 47 1A1 I 1A1Input 48 2OE I Outputenable2 4 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 GQLORZQLPACKAGE (TOPVIEW) 1 2 3 4 5 6 A B C D E F G H J K PinAssignments(1) (56-BallGQLorZQLPackage) 1 2 3 4 5 6 A 1OE NC NC NC NC 2OE B 1Y2 1Y1 GND GND 1A1 1A2 C 1Y4 1Y3 V V 1A3 1A4 CC CC D 2Y2 2Y1 GND GND 2A1 2A2 E 2Y4 2Y3 2A3 2A4 F 3Y1 3Y2 3A2 3A1 G 3Y3 3Y4 GND GND 3A4 3A3 H 4Y1 4Y2 V V 4A2 4A1 CC CC J 4Y3 4Y4 GND GND 4A4 4A3 K 4OE NC NC NC NC 3OE (1) NC–Nointernalconnection GRDORZRDPACKAGE (TOPVIEW) 1 2 3 4 5 6 A B C D E F G H J PinAssignments(1) (54-BallGRDorZRDPackage) 1 2 3 4 5 6 A 1Y1 NC 1OE 2OE NC 1A1 B 1Y3 1Y2 NC NC 1A2 1A3 C 2Y1 1Y4 V V 1A4 2A1 CC CC D 2Y3 2Y2 GND GND 2A2 2A3 E 3Y1 2Y4 GND GND 2A4 3A1 F 3Y3 3Y2 GND GND 3A2 3A3 G 4Y1 3Y4 V V 3A4 4A1 CC CC H 4Y3 4Y2 NC NC 4A2 4A3 J 4Y4 NC 4OE 3OE NC 4A4 (1) NC–Nointernalconnection Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthrougheachV orGND ±100 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 CC V =1.65Vto1.95V 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 CC V Inputvoltage 0 5.5 V I Highorlowstate 0 V CC V Outputvoltage V O 3-state 0 5.5 V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 CC V =3V –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 CC V =3V 24 CC Δt/Δv Inputtransitionriseorfallrate 10 ns/V T Operatingfree-airtemperature –40 125 °C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 7.4 Thermal Information DGG DGV DL THERMALMETRIC(1) UNIT 48PINS 48PINS 48PINS R Junction-to-ambientthermalresistance 64.3 78.4 68.4 θJA R Junction-to-case(top)thermalresistance 17.6 30.7 34.7 θJC(top) R Junction-to-boardthermalresistance 31.5 41.8 41.0 θJB °C/W ψ Junction-to-topcharacterizationparameter 1.1 3.8 12.3 JT ψ Junction-to-boardcharacterizationparameter 31.2 41.3 40.4 JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =–100µA 1.65Vto3.6V V –0.2 OH CC I =–4mA 1.65V 1.2 OH I =–8mA 2.3V 1.7 OH V V OH 2.7V 2.2 I =–12mA OH 3V 2.4 I =–24mA 3V 2.2 OH I =100µA 1.65Vto3.6V 0.2 OL I =4mA 1.65V 0.45 OL V I =8mA 2.3V 0.7 V OL OL I =12mA 2.7V 0.4 OL I =24mA 3V 0.55 OL I V =0to5.5V 3.6V ±5 µA I I V =0.58V 15 I 1.65V V =1.07V –15 I V =0.7V 45 I 2.3V I V =1.7V –45 µA I(hold) I V =0.8V 75 I 3V V =2V –75 I V =0to3.6V(2) 3.6V ±500 I I V orV =5.5V 0 ±10 µA off I O I V =0to5.5V 3.6V ±10 µA OZ O V =V orGND 20 I CC I I =0 3.6V µA CC 3.6V≤V ≤5.5V(3) O 20 I ΔI OneinputatV –0.6V, OtherinputsatV orGND 2.7Vto3.6V 500 µA CC CC CC C V =V orGND 3.3V 5.5 pF i I CC C V =V orGND 3.3V 6 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A (2) Thisisthebus-holdmaximumdynamiccurrentrequiredtoswitchtheinputfromonestatetoanother. (3) Thisappliesinthedisabledstateonly. 7.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C±C0.15V C±C0.2V VCC=2.7V C±C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t A Y 1.5 6.6 1 3.9 1 4.7 1.1 4.1 ns pd t OE Y 1.5 7.5 1 4.7 1 5.8 1 4.6 ns en t OE Y 1.5 10.3 1 5.3 1 6.2 1.8 5.8 ns dis t 1 1 1 1 ns sk(o) 7.7 Operating Characteristics T =25°C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipationcapacitance Outputsenabled 33 32 35 C f=10MHz pF pd perbuffer/driver Outputsdisabled 2 2 3 8 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 7.8 Typical Characteristics 4 4 TPD in ns TPD in ns 3.5 3.5 3 3 2.5 2.5 s s n n D - 2 D - 2 P P T T 1.5 1.5 1 1 0.5 0.5 0 0 0 1 2 3 4 -100 -50 0 50 100 150 VCC - V D004 Temperature (qC) D004 Figure1.TDPAcrossV at25°C Figure2.TPDAcrossTemperatureat3.3V CC Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see NoteCAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL V∆ 1.8 V±0.15 V VCC ≤2ns VCC/2 2×VCC 30 pF 1 kΩ 0.15 V 2.5 V±0.2 V VCC ≤2ns VCC/2 2×VCC 30 pF 500Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V 3.3 V±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1ee a tN VoLteO ABD) VM VOL+V∆ VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOftou GrtmpNu D2t VM VOH−V∆ VOH VOL (see Note B) ≈0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludes probe and jig capacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol. Waveform2is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZand tPHZare the same as tdis. F. tPZLand tPZHare the same as ten. G. tPLHand tPHLare the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 9 Detailed Description 9.1 Overview The SN74LVCH16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It providestrueoutputsandsymmetricalactive-lowoutput-enable(OE)inputs. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in amixed3.3-V/5-Vsystemenvironment. The SN74LVCH16244A device is fully specified for partial-power-down applications using I . The I circuitry off off disablestheoutputs,preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate.Useofpulluporpulldownresistors withthebus-holdcircuitryisnotrecommended. 9.2 Functional Block Diagram 1 25 1OE 3OE 47 2 36 13 1A1 1Y1 3A1 3Y1 46 3 35 14 1A2 1Y2 3A2 3Y2 44 5 33 16 1A3 1Y3 3A3 3Y3 43 6 32 17 1A4 1Y4 3A4 3Y4 48 24 2OE 4OE 41 8 30 19 2A1 2Y1 4A1 4Y1 40 9 29 20 2A2 2Y2 4A2 4Y2 38 11 27 22 2A3 2Y3 4A3 4Y3 37 12 26 23 2A4 2Y4 4A4 4Y4 PinnumbersshownarefortheDGG,DGV,andDLpackages. Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto3.6V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • I feature off – AllowsvoltagesontheinputsandoutputswhenV is0V CC 9.4 Device Functional Modes Table1.FunctionTable (Each4-bitBuffer) INPUTS OUTPUT OE A Y L H H L L L H X Z 12 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 10 Application and Implementation 10.1 Application Information The SN74LVCH16244A device is a 16-bit buffer driver. This device can be used as four 4-bit, two 8-bit, or one 16-bit buffer. It allows data transmission from the A bus to the Y bus with 4 separate enable pins that control 4 bits each. The output-enable (OE) input can be used to disable sections of the device so that the buses are effectively isolated. The device has 5.5 V tolerant inputs at any valid V . This allows the device to be used in CC multi-power systems, and it can be used for down translation. Active bus-hold circuitry holds unused or undriven inputsatavalidlogicstate.Useofpulluporpulldownresistorswiththebus-holdcircuitryisnotrecommended. 10.2 Typical Application Regulated 3.6 V OE Vcc DIR 1A1 1Y1 uC System Logic uC or LEDs 1A4 1Y4 System Logic GND Figure4. TypicalApplicationDiagram 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads;therefore,routingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendOutputConditions – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A SCES494B–OCTOBER2003–REVISEDJUNE2014 www.ti.com Typical Application (continued) 10.2.3 ApplicationCurves 300 ICC 1.8 V ICC 2.5 V 250 ICC 3.3 V 200 A m - C 150 C I 100 50 0 0 10 20 30 40 50 60 Frequency - MHz D004 Figure5.I vsFrequency CC 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μf is recommended; if there are multiple V pins, then 0.01 μf or 0.022 μf is recommended for each CC power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiple-bitlogicdevices,inputsshouldneverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float outputs, CC unlessthepartisatransceiver.Ifthetransceiverhasanoutputenablepin,itwilldisabletheoutputsectionofthe partwhenasserted.ThiswillnotdisabletheinputsectionoftheI/Os,sotheycannotfloatwhendisabled. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram 14 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVCH16244A

SN74LVCH16244A www.ti.com SCES494B–OCTOBER2003–REVISEDJUNE2014 13 Device and Documentation Support 13.1 Trademarks WidebusisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN74LVCH16244A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVCH16244ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVCH16244A & no Sb/Br) SN74LVCH16244ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LDH244A & no Sb/Br) SN74LVCH16244ADL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVCH16244A & no Sb/Br) SN74LVCH16244ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVCH16244A & no Sb/Br) SN74LVCH16244ADLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVCH16244A & no Sb/Br) SN74LVCH16244AZRDR LIFEBUY BGA ZRD 54 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LDH244A MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVCH16244ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74LVCH16244ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74LVCH16244ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74LVCH16244AZRDR BGAMI ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVCH16244ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVCH16244ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74LVCH16244ADLR SSOP DL 48 1000 367.0 367.0 55.0 SN74LVCH16244AZRDR BGAMICROSTAR ZRD 54 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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