Product Order Technical Tools & Support & Folder Now Documents Software Community SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features 3 Description • OperateFrom1.65Vto3.6V The SNx4LVC74A devices integrate two positive- 1 edge triggered D-type flip-flops in one convenient • InputsAcceptVoltagesto5.5V device. • Maximumt of5.2nsat3.3V pd The SN54LVC74A is designed for 2.7-V to 3.6-V V • TypicalV (OutputGroundBounce) CC OLP operation, and the SN74LVC74A is designed for <0.8VatV =3.3V,T =25°C CC A 1.65-Vto3.6-VV operation. CC • TypicalV (OutputV Undershoot) OHV OH A low level at the preset (PRE) or clear (CLR) inputs >2VatV =3.3V,T =25°C CC A sets or resets the outputs, regardless of the levels of • Latch-UpPerformanceExceeds250mAPer the other inputs. When PRE and CLR are inactive JESD17 (high), data at the data (D) input meeting the setup • ESDProtectionExceedsJESD22 time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock – 2000-VHuman-BodyModel(A114-A) triggering occurs at a voltage level and is not directly – 1000-VCharged-DeviceModel(C101) related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be 2 Applications changedwithoutaffectingthelevelsattheoutputs. • Servers The data I/Os and control inputs are overvoltage • Medical,Healthcare,andFitness tolerant. This feature allows the use of these devices fordown-translationinamixed-voltageenvironment. • TelecomInfrastructures • TVs,Set-TopBoxes,andAudio DeviceInformation(1) • TestandMeasurement PARTNUMBER PACKAGE BODYSIZE(NOM) • IndustrialTransport SNJ54LVC74AFK LCCC(20) 8.89mm×8.89mm • WirelessInfrastructure SNJ54LVC74AJ CDIP(14) 19.56mm×6.67mm • EnterpriseSwitching SNJ54LVC74AW CFP(14) 9.21mm×5.97mm • MotorDrives SN74LVC74AD SOIC(14) 8.65mm×3.91mm • FactoryAutomationandControl SN74LVC74ADB SSOP(14) 6.20mm×5.30mm SN74LVC74ANS SO(14) 10.30mm×5.30mm SN74LVC74APW TSSOP(14) 5.00mm×4.40mm SN74LVC74ARGY VQFN(14) 3.50mm×3.50mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. LogicDiagram,EachFlip-Flop(PositiveLogic) Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. On products compliant to MIL-PRF-38535, all parameters are testedunlessotherwisenoted.Onallotherproducts,production processingdoesnotnecessarilyincludetestingofallparameters.

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8 DetailedDescription............................................ 10 2 Applications........................................................... 1 8.1 Overview.................................................................10 3 Description............................................................. 1 8.2 FunctionalBlockDiagram.......................................10 4 RevisionHistory..................................................... 2 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................10 5 PinConfigurationandFunctions......................... 3 9 ApplicationandImplementation........................ 11 6 Specifications......................................................... 4 9.1 ApplicationInformation............................................11 6.1 AbsoluteMaximumRatings......................................4 9.2 TypicalApplication .................................................11 6.2 ESDRatings..............................................................4 10 PowerSupplyRecommendations..................... 13 6.3 RecommendedOperatingConditions.......................4 6.4 ThermalInformation:SN74LVC74A.........................5 11 Layout................................................................... 13 6.5 ElectricalCharacteristics...........................................5 11.1 LayoutGuidelines.................................................13 6.6 TimingRequirements:SN54LVC74A.......................6 11.2 LayoutExample....................................................13 6.7 TimingRequirements:SN74LVC74A.......................6 12 DeviceandDocumentationSupport................. 14 6.8 TimingRequirements:SN74LVC74A,–40°Cto 12.1 DocumentationSupport........................................14 125°Cand–40°Cto85°C..........................................7 12.2 RelatedLinks........................................................14 6.9 SwitchingCharacteristics:SN54LVC74A.................7 12.3 ReceivingNotificationofDocumentationUpdates14 6.10 SwitchingCharacteristics:SN74LVC74A...............7 12.4 CommunityResource............................................14 6.11 SwitchingCharacteristics:SN74LVC74A,–40°Cto 12.5 Trademarks...........................................................14 125°Cand–40°Cto85°C..........................................8 12.6 ElectrostaticDischargeCaution............................14 6.12 OperatingCharacteristics........................................8 12.7 Glossary................................................................14 6.13 TypicalCharacteristics............................................8 13 Mechanical,Packaging,andOrderable 7 ParameterMeasurementInformation..................9 Information........................................................... 14 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionT(July2013)toRevisionU Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • ChangedPackagethermalimpedance,R ,valuesinThermalInformation:SN74LVC74AFrom:86To:93.7(D), θJA From:96To:107.3(DB),From:76To:90.3(NS),From:113To:121.7(PW),andFrom:47To:54.9(RGY).................... 5 ChangesfromRevisionS(May2005)toRevisionT Page • Extendedmaximumtemperatureoperatingrangefrom85°Cto125°C................................................................................. 4 2 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 5 Pin Configuration and Functions D,DB,J,PW,NS,orWPackage RGYPackage 14-PinSOIC,SSOP,CDIP,TSSOP,SO,orCFP 14-PinVQFNWithExposedThermalPad TopView TopView R L C 1CLR 1 14 VCC 1C VC 1D 2 13 2CLR 1 14 1CLK 3 12 2D 1D 2 13 2CLR 1PRE 4 11 2CLK 1CLK 3 12 2D 1Q 5 10 2PRE 1PRE 4 11 2CLK 1Q 6 9 2Q 1Q 5 10 2PRE GND 7 8 2Q 1Q 6 9 2Q 7 8 Not to scale D Q N 2 G FKPackage 20-PinLCCC TopView D CLR C CC CLR 1 1 N V 2 3 2 1 0 9 2 1 1CLK 4 18 2D NC 5 17 NC 1PRE 6 16 2CLK NC 7 15 NC 1Q 8 14 2PRE 9 10 11 12 13 Q D C Q Q Not to scale 1 N N 2 2 G PinFunctions PIN CDIP,CFP,PDIP,SO,SOIC, I/O DESCRIPTION NAME LCCC SSOP,TSSOP,VQFN 1CLK 3 4 I Channel1clockinput 1CLR 1 2 I Channel1clearinput.PulllowtosetQoutputlow. 1D 2 3 I Channel1datainput 1PRE 4 6 I Channel1presetinput.PulllowtosetQoutputhigh. 1Q 5 8 O Channel1output 1Q 6 9 O Channel1invertedoutput 2CLK 11 16 I Channel2clockinput 2CLR 13 19 I Channel2clearinput.PulllowtosetQoutputlow. 2D 12 18 I Channel2datainput 2PRE 10 14 I Channel2presetinput.PulllowtosetQoutputhigh. 2Q 9 13 O Channel2output 2Q 8 12 O Channel2Invertedoutput GND 7 10 — Ground NC — 1,5,7,11,15,17 — Noconnect V 14 20 — Supply CC Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltage,V –0.5 6.5 V CC Inputvoltage,V(2) –0.5 6.5 V I Outputvoltage,V (2)(3) –0.5 V +0.5 V O CC Inputclampcurrent,I V <0 –50 mA IK I Outputclampcurrent,I V <0 –50 mA OK O Continuousoutputcurrent,I ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedinRecommendedOperatingConditions. CC 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions see(1) MIN MAX UNIT SN54LVC74A 2 3.6 Operating V Supplyvoltage SN74LVC74A 1.65 3.6 V CC Dataretentiononly 1.5 V =1.65Vto1.95V SN74LVC74A 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V SN74LVC74A 1.7 V IH CC V =2.7Vto3.6V 2 CC V =1.65Vto1.95V SN74LVC74A 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V SN74LVC74A 0.7 V IL CC V =2.7Vto3.6V 0.8 CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V SN74LVC74A –4 CC V =2.3V SN74LVC74A –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 CC V =3V –24 CC V =1.65V SN74LVC74A 4 CC V =2.3V SN74LVC74A 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 CC V =3V 24 CC Δt/Δv Inputtransitionriseorfallrate 10 ns/V (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeetheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). 4 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 Recommended Operating Conditions (continued) see(1) MIN MAX UNIT SN54LVC74A –55 125 T Operatingfree-airtemperature °C A SN74LVC74A –40 125 6.4 Thermal Information: SN74LVC74A SN74LVC74A THERMALMETRIC(1) D DB NS PW RGY UNIT (SOIC) (SSOP) (SO) (TSSOP) (VQFN) 14PINS 14PINS 14PINS 14PINS 14PINS R Junction-to-ambientthermalresistance 93.7 107.3 90.3 121.7 54.9 °C/W θJA R Junction-to-case(top)thermalresistance 54.8 59.2 48.1 50.3 52.2 °C/W θJC(top) R Junction-to-boardthermalresistance 48 54.6 49.1 63.4 30.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 20.3 24.1 17.9 6.2 2.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 47.7 54.1 48.8 62.8 30.9 °C/W JB R Junction-to-case(bottom)thermalresistance — — — — 12.5 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =1.65Vto3.6VandT =–55°Cto CC A V –0.2 125°C(SN54LVC74Aonly) CC I =–100µA OH V =2.7Vto3.6VandT =–40°Cto CC A V –0.2 125°C(SN74LVC74Aonly) CC I =–4mA,V =1.65V,andT =–40°Cto125°C OH CC A 1.2 (SN74LVC74Aonly) V High-leveloutputvoltage V OH I =–8mA,V =2.3V,andT =–40°Cto125°C OH CC A 1.7 (SN74LVC74Aonly) V =2.7V 2.2 CC I =–12mA OH V =3V 2.4 CC I =–24mA,V =3V 2.2 OH CC V =1.65Vto3.6V,andT =–40°C CC A 0.2 to125°C(SN74LVC74Aonly) I =100µA OL V =2.7Vto3.6VandT =–55°Cto CC A 0.2 125°C(SN54LVC74Aonly) I =4mA,V =1.65V,andT =–40°Cto125°C VOL Low-leveloutputvoltage (OSLN74LVC74ACConly) A 0.45 V I =8mA,V =2.3V,andT =–40°Cto125°C OL CC A 0.7 (SN74LVC74Aonly) I =12mA,V =2.7V 0.4 OL CC I =24mA,V =3V 0.55 OL CC I Inputcurrent V =5.5VorGND,V =3.6V ±5 µA I I CC I Supplycurrent V =V orGND,I =0,V =3.6V 10 µA CC I CC O CC OneinputatV –0.6V,otherinputsatV orGND,and ΔI Changeinsupplycurrent CC CC 500 µA CC V =2.7Vto3.6V CC C Inputcapacitance V =V orGND,V =3.3V,T =25°C 5 pF i I CC CC A Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com 6.6 Timing Requirements: SN54LVC74A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) MIN MAX UNIT V =2.7V 83 CC f Clockfrequency MHz clock V =3.3V±0.3V 100 CC PREorCLRlow 3.3 t Pulseduration ns w CLKhighorlow 3.3 V =2.7V 3.4 CC Data V =3.3V±0.3V 3 CC t SetuptimebeforeCLK↑ ns su V =2.7V 2.2 CC PREorCLRinactive V =3.3V±0.3V 2 CC t Holdtime,dataafterCLK↑ 1 ns h 6.7 Timing Requirements: SN74LVC74A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) MIN MAX UNIT f Clockfrequency V =1.8Vor2.5V 83 MHz clock CC V =1.8V±0.15V 4.1 CC PREorCLRlow V =2.5V±0.2V 3.3 CC t Pulseduration ns w V =1.8V±0.15V 4.1 CC CLKhighorlow V =2.5V±0.2V 3.3 CC V =1.8V±0.15V 3.6 CC Data V =2.5V±0.2V 2.3 CC t SetuptimebeforeCLK↑ ns su V =1.8V±0.15V 2.7 CC PREorCLRinactive V =2.5V±0.2V 1.9 CC t Holdtime,dataafterCLK↑ V =1.8Vor2.5V 1 ns h CC 6 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 6.8 Timing Requirements: SN74LVC74A, –40°C to 125°C and –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) MIN MAX UNIT TA=–40°Cto VCC=2.7V 83 f Clockfrequency 125°C V =3.3V±0.3V 100 MHz clock CC T =–40°Cto85°CandV =3.3V±0.3V 150 A CC PREorCLRlow V =2.7Vor3.3V 3.3 CC t Pulseduration ns w CLKhighorlow V =2.7Vor3.3V 3.3 CC V =2.7V 3.4 CC T =–40°Cto125°C A Data V =3.3V±0.3V 3 CC T =–40°Cto85°CandV =3.3V±0.3V 3 A CC t SetuptimebeforeCLK↑ ns su V =2.7V 2.2 CC PREorCLR TA=–40°Cto125°C V =3.3V±0.3V 2 inactive CC T =–40°Cto85°CandV =3.3V±0.3V 2 A CC Holdtime,dataafter t V =2.7Vor3.3V 1 ns h CLK↑ CC 6.9 Switching Characteristics: SN54LVC74A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) Maximumclock VCC=2.7V 83 f — — MHz max frequency V =3.3V±0.3V 100 CC V =2.7V 6 CC CLK Propagation(delay) VCC=2.7V 1 5.2 t QorQ ns pd time V =3.3V±0.3V 6.4 CC PREorCLR V =3.3V±0.3V 1 5.4 CC 6.10 Switching Characteristics: SN74LVC74A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) Maximumclock f — — 83 MHz max frequency V =1.8V±0.15V 1 7.1 CC CLKPRE Propagation(delay) VCC=2.5V±0.2V 1 4.4 t QorQ ns pd time V =1.8V±0.15V 1 6.9 CC orCLR V =2.5V±0.2V 1 4.6 CC Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com 6.11 Switching Characteristics: SN74LVC74A, –40°C to 125°C and –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted;seeFigure3) FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) V =2.7V 83 CC Maximumclock TA=–40°Cto125°C f — — V =3.3V±0.3V 100 MHz max frequency CC T =–40°Cto85°CandV =3.3V±0.3V 150 A CC V =2.7V 1 6 CC T =–40°Cto125°C A CLK V =3.3V±0.3V 5.2 CC Propagation(delay) TA=–40°Cto85°CandVCC=3.3V±0.3V 1 5.2 t QorQ ns pd time V =2.7V 1 6.4 CC T =–40°Cto125°C A PREorCLR V =3.3V±0.3V 5.4 CC T =–40°Cto85°CandV =3.3V±0.3V 1 5.4 A CC t Skew(time),output — — T =–40°Cto85°CandV =3.3V±0.3V 1 ns sk(o) A CC 6.12 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT V =1.8V 24 CC C Powerdissipationcapacitanceperflip-flop f=10MHz V =2.5V 24 pF pd CC V =3.3V 26 CC 6.13 Typical Characteristics 14 10 VCC=3V, VCC=3V, TA=25°C TA=25°C 12 s –ns OFonuerOOuuttppuuttSswSiwtcithcihnigng e–n 8 OFonuerOOuuttppuuttSswSiwtcithcihnigng Time 10 EightOutputsSwitching yTim EightOutputsSwitching y a ela Del D 8 n 6 n o atio gati g a a 6 p p o o r Pr –P 4 – d d 4 p p t t 2 2 0 50 100 150 200 250 300 0 50 100 150 200 250 300 CL–LoadCapacitance–pF CL–LoadCapacitance–pF Figure1.PropagationDelay(Low-to-HighTransition) Figure2.Figure2.PropagationDelay(High-to-Low vsLoadCapacitance Transition)vsLoadCapacitance 8 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 7 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see NoteCAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VΔ 1.8 V±0.15 V VCC ≤2 ns VCC/2 2×VCC 30 pF 1 kΩ 0.15 V 2.5 V±0.2 V VCC ≤2 ns VCC/2 2×VCC 30 pF 500Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V 3.3 V±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1ee a tN VoLteO ABD) VM VOL+ VΔ VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOftou GrtmpNu D2t VM VOH–VΔ VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING A. C includesprobeandjigcapacitance. L B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutput control. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutput control. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,Z =50Ω. O D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andt arethesameast . PZL PZH en G. t andt arethesameast . PLH PHL pd H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com 8 Detailed Description 8.1 Overview The SNx4LVC74A devices feature two independent positive-edge triggered D flip-flops. Integrated preset (PRE) andclear(CLR)functionsallowforeasysetupandcontrolduringoperation. The SN54LVC74A device is specified from –55°C to 125°C, and the SN74LVC74A device is specified from –40°Cto125°C. 8.2 Functional Block Diagram Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, dataattheDinputcanbechangedwithoutaffectingthelevelsattheoutputs. 8.4 Device Functional Modes Table1describestheSNx4LVC74Afunctionalityandinteractionsbetweenthe PRE,CLR,CLK,andDinputs. Table1.FunctionTable INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q Q 0 0 (1) Thisconfigurationisnonstable;thatis,itdoesnotpersistwhenPRE orCLRreturnstoitsinactive(high)level. 10 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information AcommonapplicationfortheSN74LVC74Aisafrequencydivider.Byconnectingthe QoutputtotheDinput,the Q output toggles states on each positive edge of the incoming clock signal. Because it takes two positive edges, or two clock pulses, to complete one complete pulse on the output (one pulse to toggle from low to high, another totogglefromhightolow),theincomingclockfrequencyiseffectivelydividedbytwo. 9.2 Typical Application 3 V VCC Q 1D Q Output ClockInput 1CLK GND SN74LVC74A Copyright © 2016,Texas Instruments Incorporated Figure4. FrequencyDivider 9.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive currents in excess of maximum limits. The high drive also creates fast edges into light loads, so consider routing andloadconditionstopreventringing. 9.2.2 DetailedDesignProcedure 1. Recommendedinputconditions: – Forrisetimeandfalltimespecification,see(Δt/ΔV)inRecommendedOperatingConditions. – Forspecifiedhighandlowlevels,see(V andV )inRecommendedOperatingConditions. IH IL – Inputs are overvoltage tolerant allowing them to go as high as (V max) in Recommended Operating I ConditionsatanyvalidV . CC 2. Recommendedmaximumoutputconditions: – Loadcurrentsmustnotexceed(I max)peroutputandmustnotexceed(ContinuouscurrentthroughV O CC orGND)totalcurrentforthepart.TheselimitsarelocatedinAbsoluteMaximumRatings. – OutputsmustnotbepulledaboveV . CC Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurves 100 60 TA=25°C,VCC=3V, TA=25°C,VCC=3V, VIH=3V,VIL=0V, 40 VIH=3V,VIL=0V, 80 AllOutputsSwitching AllOutputsSwitching 20 60 0 A A m m – 40 – –20 OL OH I I –40 20 –60 0 –80 –20 –100 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOL–V VOH–V Figure5.OutputDriveCurrent(IOL) Figure6.OutputDriveCurrent(IOH) vsLOW-levelOutputVoltage(VOL) vsHIGH-levelOutputVoltage(VOH) 12 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A www.ti.com SCAS287U–JANUARY1993–REVISEDJANUARY2017 10 Power Supply Recommendations The power supply may be any voltage between the minimum and maximum supply voltage rating located in RecommendedOperatingConditions. Each V terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is CC recommended for devices with a single supply. If there are multiple V terminals, then 0.01-µF or 0.022-µF CC capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies ofnoise.Thebypasscapacitormustbeinstalledasclosetothepowerterminalaspossibleforthebestresults. 11 Layout 11.1 Layout Guidelines Inputs must not float when using multiple bit logic devices. In many cases, functions or parts of functions of digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected becausetheundefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or V ,whichevermakesmoresenseorismoreconvenient. CC 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure7. LayoutDiagram Copyright©1993–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54LVC74A SN74LVC74A

SN54LVC74A,SN74LVC74A SCAS287U–JANUARY1993–REVISEDJANUARY2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: ImplicationsofSloworFloatingCMOSInputs (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstoordernow. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER ORDERNOW DOCUMENTS SOFTWARE COMMUNITY SN54LVC74A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LVC74A Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 14 SubmitDocumentationFeedback Copyright©1993–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC74A SN74LVC74A

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9761601Q2A SNJ54LVC 74AFK 5962-9761601QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC A SNJ54LVC74AJ 5962-9761601QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD A SNJ54LVC74AW 5962-9761601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601VD A SNV54LVC74AW SN74LVC74AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A & no Sb/Br) SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A & no Sb/Br) SN74LVC74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC74A & no Sb/Br) SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9761601Q2A SNJ54LVC 74AFK SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC A SNJ54LVC74AJ SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD A SNJ54LVC74AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A : •Catalog: SN74LVC74A, SN54LVC74A •Automotive: SN74LVC74A-Q1, SN74LVC74A-Q1 •Enhanced Product: SN74LVC74A-EP, SN74LVC74A-EP •Military: SN54LVC74A •Space: SN54LVC74A-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC74ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC74ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC74ADT SOIC D 14 250 210.0 185.0 35.0 SN74LVC74ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC74APWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC74APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC74APWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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IMPORTANTNOTICEANDDISCLAIMER TIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCE DESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES“ASIS” ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANY IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRD PARTYINTELLECTUALPROPERTYRIGHTS. TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.Youaresolelyresponsiblefor(1)selectingtheappropriate TIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicable standards,andanyothersafety,security,orotherrequirements.Theseresourcesaresubjecttochangewithoutnotice.TIgrantsyou permissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.Other reproductionanddisplayoftheseresourcesisprohibited.NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythird partyintellectualpropertyright.TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims, damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources. TI’sproductsareprovidedsubjecttoTI’sTermsofSale(www.ti.com/legal/termsofsale.html)orotherapplicabletermsavailableeitheron ti.comorprovidedinconjunctionwithsuchTIproducts.TI’sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI’sapplicable warrantiesorwarrantydisclaimersforTIproducts. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2018,TexasInstrumentsIncorporated