SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 (cid:2) (cid:2) Operate From 1.65 V to 3.6 V Support Mixed-Mode Signal Operation on (cid:2) Inputs Accept Voltages to 5.5 V All Ports (5-V Input/Output Voltage With (cid:2) Specified From −40°C to 85°C, 3.3-V VCC) (cid:2) −40°C to 125°C, and −55°C to 125°C Ioff Supports Partial-Power-Down Mode (cid:2) Operation Max t of 7 ns at 3.3 V pd (cid:2) (cid:2) Latch-Up Performance Exceeds 250 mA Per Typical V (Output Ground Bounce) OLP JESD 17 <0.8 V at V = 3.3 V, T = 25°C CC A (cid:2) (cid:2) ESD Protection Exceeds JESD 22 Typical V (Output V Undershoot) OHV OH − 2000-V Human-Body Model (A114-A) >2 V at V = 3.3 V, T = 25°C CC A − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LVC574A...FK PACKAGE SN54LVC574A...J OR W PACKAGE SN74LVC574A...RGY PACKAGE (TOP VIEW) SN74LVC574A...DB, DGV, DW, N, NS, (TOP VIEW) OR PW PACKAGE C (TOP VIEW) OE VCC 2D 1D OEVC1Q O1DE 12 2109 V1QCC 1D 2 1 20 19 1Q 3D 4 3 2 1 20 1918 2Q 2D 3 18 2Q 2D 3 18 2Q 4D 5 17 3Q 5D 6 16 4Q 3D 4 17 3Q 3D 4 17 3Q 6D 7 15 5Q 4D 5 16 4Q 4D 5 16 4Q 7D 8 14 6Q 5D 6 15 5Q 5D 6 15 5Q 9 10 11 12 13 6D 7 14 6Q 6D 7 14 6Q 7D 8 13 7Q 7D 8 13 7Q 8D ND LK8Q 7Q 8D 9 12 8Q 8D 9 12 8Q G C GND 10 11 CLK 10 11 D K N L G C description/ordering information The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V operation, and the CC SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V operation. CC These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Reel of 1000 SN74LVC574ARGYR LC574A −4400°CC ttoo 8855°CC VFBGA − GQN SN74LVC574AGQNR RReeeell ooff 11000000 LLCC557744AA VFBGA − ZQN (Pb-free) SN74LVC574AZQNR PDIP − N Tube of 20 SN74LVC574AN SN74LVC574AN Tube of 25 SN74LVC574ADW SSOOIICC − DDWW LLVVCC557744AA Reel of 2000 SN74LVC574ADWR SOP − NS Reel of 2000 SN74LVC574ANSR LVC574A −4400°CC ttoo 112255°CC SSOP − DB Reel of 2000 SN74LVC574ADBR LC574A Tube of 70 SN74LVC574APW TTSSSSOOPP − PPWW Reel of 2000 SN74LVC574APWR LLCC557744AA Reel of 250 SN74LVC574APWT TVSOP − DGV Reel of 2000 SN74LVC574ADGVR LC574A CDIP − J Tube of 20 SNJ54LVC574AJ SNJ54LVC574AJ −55°C to 125°C CFP − W Tube of 85 SNJ54LVC574AW SNJ54LVC574AW LCCC − FK Tube of 55 SNJ54LVC574AFK SNJ54LVC574AFK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQN OR ZQN PACKAGE (TOP VIEW) terminal assignments 1 2 3 4 1 2 3 4 A A 1D OE VCC 1Q B B 3D 3Q 2D 2Q C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E GND 8D CLK 8Q E FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT OE CLK D Q L ↑ H H L ↑ L L L L X Q0 H X X Z 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 logic diagram (positive logic) 1 OE 11 CLK C1 19 1Q 2 1D 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V I Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, V O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Power dissipation, Ptot (TA = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 5. For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K. 6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 recommended operating conditions (see Note 7) SN54LVC574A −55 TO 125°C UUNNIITT MIN MAX Operating 2 3.6 VVCC SSuuppppllyy vvoollttaaggee Data retention only 1.5 VV VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V VI Input voltage 0 5.5 V High or low state 0 VCC VVO OOuuttppuutt vvoollttaaggee 3−state 0 5.5 VV VCC = 2.7 V −12 IIOH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V −24 mmAA VCC = 2.7 V 12 IIOOL LLooww-lleevveell oouuttppuutt ccuurrrreenntt mmAA VCC = 3 V 24 Δt/Δv Input transition rise or fall rate 6 ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions (see Note 7) SN74LVC574A TA = 25°C −40 TO 85°C −40 TO 125°C UUNNIITT MIN MAX MIN MAX MIN MAX Operating 1.65 3.6 1.65 3.6 1.65 3.6 VVCC SSuuppppllyy vvoollttaaggee Data retention only 1.5 1.5 1.5 VV VCC = 1.65 V to 1.95 V 0.65 ×VCC 0.65 ×VCC 0.65 ×VCC HHiighh-llevell iinputt VVIIHH vvoollttaaggee VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VV VCC = 2.7 V to 3.6 V 2 2 2 VCC = 1.65 V to 1.95 V 0.35 ×VCC 0.35 ×VCC 0.35 ×VCC LLow-llevell iinputt VVIILL vvoollttaaggee VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VV VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 VI Input voltage 0 5.5 0 5.5 0 5.5 V High or low state 0 VCC 0 VCC 0 VCC VVO OOuuttppuutt vvoollttaaggee 3−state 0 5.5 0 5.5 0 5.5 VV VCC = 1.65 V −4 −4 −4 HHiigghh-lleevveell VCC = 2.3 V −8 −8 −8 IIOH output current VCC = 2.7 V −12 −12 −12 mmAA VCC = 3 V −24 −24 −24 VCC = 1.65 V 4 4 4 LLooww-lleevveell VCC = 2.3 V 8 8 8 IIOL output current VCC = 2.7 V 12 12 12 mmAA VCC = 3 V 24 24 24 Δt/Δv Input transition rise or fall rate 6 6 6 ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC574A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC −55 TO 125°C UUNNIITT MIN TYP† MAX IOH = −100 μA 2.7 V to 3.6 V VCC − 0.2 2.7 V 2.2 VVOH IIOH = −1122 mmAA 3 V 2.4 VV IOH = −24 mA 3 V 2.2 IOL = 100 μA 2.7 V to 3.6 V 0.2 VVOOLL IOL = 12 mA 2.7 V 0.4 VV IOL = 24 mA 3 V 0.55 II VI = 5.5 V or GND 3.6 V ±5 μA IOZ VO = 0 to 5.5 V 3.6 V ±15 μA VI = VCC or GND 10 IICC 3.6 V ≤ VI ≤ 5.5 V‡ IIO = 00 33.66 VV 10 μAA ΔICC One input atVCC − 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 μA Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5.5 pF †TA = 25°C ‡This applies in the disabled state only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LVC574A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC TA = 25°C −40 TO 85°C −40 TO 125°C UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −100 μA 1.65 V to 3.6 V VCC − 0.2 VCC − 0.2 VCC − 0.2 IOH = −4 mA 1.65 V 1.29 1.2 1.2 IOH = −8 mA 2.3 V 1.9 1.7 1.7 VVOH 2.7 V 2.2 2.2 2.2 VV IIOH = −1122 mmAA 3 V 2.4 2.4 2.4 IOH = −24 mA 3 V 2.3 2.2 2.2 IOL = 100 μA 1.65 V to 3.6 V 0.1 0.2 0.2 IOL = 4 mA 1.65 V 0.24 0.45 0.45 VVOOLL IOL = 8 mA 2.3 V 0.3 0.7 0.7 VV IOL = 12 mA 2.7 V 0.4 0.4 0.4 IOL = 24 mA 3 V 0.55 0.55 0.55 II VI = 5.5 V or GND 3.6 V ±1 ±5 ±5 μA Ioff VI or VO = 5.5 V 0 ±4 ±10 ±10 μA IOZ VI = 0 to 5.5 V 3.6 V ±1 ±10 ±10 μA VI = VCC or GND 1.5 10 10 IICC 3.6 V ≤ VI ≤ 5.5 V† IIO = 00 33.66 VV 1.5 10 10 μAA One input at VCC − 0.6 V, ΔICC Other inputs at VCC or 2.7 V to 3.6 V 500 500 500 μA GND Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5.5 pF †This applies in the disabled state only. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A VVCCCC −55 TO 125°C UUNNIITT MIN MAX 2.7 V 150 ffclock CClloocckk ffrreeqquueennccyy 3.3 V ± 0.3 V 150 MMHHzz 2.7 V 3.3 ttw PPuullssee dduurraattiioonn, CCLLKK hhiigghh oorr llooww 3.3 V ± 0.3 V 3.3 nnss 2.7 V 2 ttsu SSeettuupp ttiimmee, ddaattaa bbeeffoorree CCLLKK↑↑ 3.3 V ± 0.3 V 2 nnss 2.7 V 2 tth HHoolldd ttiimmee, ddaattaa aafftteerr CCLLKK↑↑ 3.3 V ± 0.3 V 2 nnss 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A FFRROOMM TTOO PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) VVCCCC −55 TO 125°C UUNNIITT MIN MAX 2.7 V 150 ffmax 3.3 V ± 0.3 V 150 MMHHzz 2.7 V 8 ttpd CCLLKK QQ 3.3 V ± 0.3 V 1 7 nnss 2.7 V 9 tten OOEE QQ 3.3 V ± 0.3 V 1 7.5 nnss 2.7 V 7 ttdis OOEE QQ 3.3 V ± 0.3 V 0.5 6.4 nnss timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A VVCCCC TA = 25°C −40 TO 85°C −40 TO 125°C UUNNIITT MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 55 55 40 2.5 V ± 0.2 V 95 95 80 ffclock CClloocckk ffrreeqquueennccyy 2.7 V 150 150 150 MMHHzz 3.3 V ± 0.3 V 150 150 150 1.8 V ± 0.15 V 9 9 9 2.5 V ± 0.2 V 4 4 4 ttw PPuullssee dduurraattiioonn, CCLLKK hhiigghh oorr llooww 2.7 V 3.3 3.3 3.3 nnss 3.3 V ± 0.3 V 3.3 3.3 3.3 1.8 V ± 0.15 V 6 6 6 2.5 V ± 0.2 V 4 4 4 ttsu SSeettuupp ttiimmee, ddaattaa bbeeffoorree CCLLKK↑↑ 2.7 V 2 2 2 nnss 3.3 V ± 0.3 V 2 2 2 1.8 V ± 0.15 V 4 4 4 2.5 V ± 0.2 V 2 2 2 tth HHoolldd ttiimmee, ddaattaa aafftteerr CCLLKK↑↑ nnss 2.7 V 1.5 1.5 1.5 3.3 V ± 0.3 V 1.5 1.5 1.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A FFRROOMM TTOO PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) VVCCCC TA = 25°C −40 TO 85°C −40 TO 125°C UUNNIITT MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 55 55 40 2.5 V ± 02 V 95 95 80 ffmax MMHHzz 2.7 V 150 150 150 3.3 V ± 0.3 V 150 150 150 1.8 V ± 0.15 V 1.0 7.1 21.5 1 21.6 1.0 21.6 2.5 V ± 0.2 V 1.0 4.9 10.0 1 10.5 1.0 10.5 ttpd CCLLKK QQ nnss 2.7 V 1.0 5.0 7.8 1 8 1.0 8.0 3.3 V ± 0.3 V 2.2 4.6 6.8 2.2 7 2.2 7.0 1.8 V ± 0.15 V 1.0 6.6 19.0 1 19.5 1.0 19.5 2.5 V ± 0.2 V 1.0 4.8 10.0 1 10.5 1.0 10.5 tten OOEE QQ nnss 2.7 V 1.0 5.5 8.3 1 8.5 1.0 8.5 3.3 V ± 0.3 V 1.5 4.4 7.3 1.5 7.5 1.5 7.5 1.8 V ± 0.15 V 1.0 5.4 18.3 1 18.8 1.0 18.8 2.5 V ± 0.2 V 1.0 3.0 7.3 1 7.8 1.0 7.8 ttdis OOEE QQ nnss 2.7 V 1.0 4.0 6.8 1 7 1.0 7.3 3.3 V ± 0.3 V 1.7 3.9 6.2 1.7 6.4 1.7 6.6 tsk(o) 3.3 V ± 0.3 V 1 1 ns operating characteristics, TA = 25°C TEST PARAMETER CONDITIONS VCC TYP UNIT 1.8 V 25 Outpputs enabled 2.5 V 29 3.3 V 30 CCpdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee ppeerr fflliipp−fflloopp ff == 1100 MMHHzz ppFF 1.8 V 9 Outpputs disabled 2.5 V 9 3.3 V 11 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VΔ 1.8 V ±0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V 2.5 V ±0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V 3.3 V ±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VΔ VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VΔ VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9757601QRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9757601QR A SNJ54LVC574AJ 5962-9757601QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757601QS A SNJ54LVC574AW SN74LVC574ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC574A & no Sb/Br) SN74LVC574ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC574A & no Sb/Br) SN74LVC574ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC574A & no Sb/Br) SN74LVC574ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC574A & no Sb/Br) SN74LVC574AN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74LVC574AN (RoHS) SN74LVC574ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC574A & no Sb/Br) SN74LVC574APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 LC574A & no Sb/Br) SN74LVC574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) SN74LVC574APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC574A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74LVC574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LC574A & no Sb/Br) SN74LVC574AZQNR LIFEBUY BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LC574A MICROSTAR & no Sb/Br) JUNIOR SNJ54LVC574AJ ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9757601QR A SNJ54LVC574AJ SNJ54LVC574AW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757601QS A SNJ54LVC574AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC574A, SN74LVC574A : •Catalog: SN74LVC574A •Automotive: SN74LVC574A-Q1, SN74LVC574A-Q1 •Enhanced Product: SN74LVC574A-EP, SN74LVC574A-EP •Military: SN54LVC574A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC574ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVC574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVC574ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVC574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVC574APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC574APWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVC574ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN74LVC574AZQNR BGAMI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC574ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC574ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC574ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC574APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC574APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVC574APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVC574APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LVC574ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 SN74LVC574AZQNR BGAMICROSTAR ZQN 20 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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