Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 SNx4LVC573A Octal Transparent D-Type Latches With 3-State Outputs 1 Features 2 Applications • OperateFrom1.65Vto3.6V • Servers 1 • InputsAcceptVoltagesto5.5V • PC,Notebook • Maxt of6.9nsat3.3V • NetworkSwitch pd • TypicalV (OutputGroundBounce) • Health &Fitness/Wearables OLP <0.8VatVCC=3.3V,TA=25°C • TelecomInfrastructure • TypicalVOHV(OutputVOH Undershoot) • ElectronicPointofSales >2VatV =3.3V,T =25°C CC A • SupportMixed-ModeSignalOperationonAll 3 Description Ports(5-VInput/OutputVoltageWith3.3-VV ) The SN54LVC573A octal transparent D-type latch is CC • IoffSupportsLiveInsertion,PartialPowerDown designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC573A octal transparent D-type latch is Mode,andBackDriveProtection designed for 1.65-V to 3.6-V V operation. These • Latch-UpPerformanceExceeds250mA CC devices feature 3-state outputs designed specifically PerJESD17 for driving highly capacitive or relatively low- • ESDProtectionExceedsJESD22 impedance loads. They are particularly suitable for – 2000-VHuman-BodyModel(A114-A) implementing buffer registers, input/output (I/O) ports, bidirectionalbusdrivers,andworkingregisters. – 200-VMachineModel(A115-A) – 1000-VCharged-DeviceModel(C101) DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) PDIP(20) 25.40x6.35mm VQGN(20) 4.50x3.50mm SN74LVC573A SOIC(20) 12.80x7.50mm SSOP(20) 7.20x5.30mm TVSOP(20) 5.00x4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic 1 OE 11 LE C1 19 2 1Q 1D 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. On products compliant to MIL-PRF-38535, all parameters are testedunlessotherwisenoted.Onallotherproducts,production processingdoesnotnecessarilyincludetestingofallparameters.

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription.............................................. 9 2 Applications........................................................... 1 9.1 Overview...................................................................9 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.........................................9 4 SimplifiedSchematic............................................. 1 9.3 FeatureDescription...................................................9 9.4 DeviceFunctionalModes..........................................9 5 RevisionHistory..................................................... 2 10 ApplicationsandImplementation...................... 10 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................10 7 Specifications......................................................... 4 10.2 TypicalApplication................................................10 7.1 AbsoluteMaximumRatings .....................................4 11 PowerSupplyRecommendations..................... 11 7.2 HandlingRatings.......................................................4 12 Layout................................................................... 11 7.3 RecommendedOperatingConditions......................5 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................11 7.5 ElectricalCharacteristics..........................................6 12.2 LayoutExample....................................................11 7.6 TimingRequirements,SN54LVC573A.....................6 13 DeviceandDocumentationSupport................. 12 7.7 TimingRequirements,SN74LVC573A.....................6 13.1 RelatedLinks........................................................12 7.8 SwitchingCharacteristics,SN54LVC573A ..............7 13.2 Trademarks...........................................................12 7.9 SwitchingCharacteristics,SN74LVC573A...............7 13.3 ElectrostaticDischargeCaution............................12 7.10 OperatingCharacteristics........................................7 13.4 Glossary................................................................12 7.11 TypicalCharacteristics............................................7 14 Mechanical,Packaging,andOrderable Information........................................................... 12 8 ParameterMeasurementInformation..................8 5 Revision History ChangesfromRevisionR(September2005)toRevisionS Page • RemovedOrderingInformationtable. ................................................................................................................................... 1 • Updateddevicetemperatureratings. .................................................................................................................................... 4 • AddedHandlingRatings. ....................................................................................................................................................... 4 • AddedTypicalCharacteristics. .............................................................................................................................................. 7 • AddedDetailedDescriptionsection....................................................................................................................................... 9 • AddedApplicationsandImplemetationsection. .................................................................................................................. 10 • AddedPowerSupplyRecommendationssection................................................................................................................. 11 • AddedLayoutsection. ......................................................................................................................................................... 11 2 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A www.ti.com SCAS300S–JANUARY1993–REVISEDMAY2014 6 Pin Configuration and Functions SN54LVC573A...J OR W PACKAGE SN74LVC573A...RGY PACKAGE SN54LVC573A...FK PACKAGE SN74LVC573A...DB, DGV, DW, N, (TOP VIEW) (TOP VIEW) NS, OR PW PACKAGE C C (TOP VIEW) E C D DE CQ O V 2 1OV 1 OE 1 20 VCC 1 20 3 2 1 20 19 1D 2 19 1Q 1D 2 19 1Q 3D 4 18 2Q 2D 3 18 2Q 2D 3 18 2Q 4D 5 17 3Q 3D 4 17 3Q 3D 4 17 3Q 5D 6 16 4Q 4D 5 16 4Q 4D 5 16 4Q 6D 7 15 5Q 5D 6 15 5Q 5D 6 15 5Q 7D 8 14 6Q 9 10 11 12 13 6D 7 14 6Q 6D 7 14 6Q 7D 8 13 7Q 7D 8 13 7Q D D EQ Q 8 N L8 7 8D 9 12 8Q 8D 9 12 8Q G GND 10 11 LE 10 11 D E N L G GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 4 A B C D E PinFunctions PIN SN54LVC573A SN74LVC573A DESCRIPTION NAME DB,DGV,DW,N, GQNANDZQN J,W,ANDFK NS,PW,ANDRGY OE 1 1 A2 EnablePin 1D 2 2 A1 Input1 2D 3 3 B3 Input2 3D 4 4 B1 Input3 4D 5 5 C2 Input4 5D 6 6 C1 Input5 6D 7 7 D3 Input6 7D 8 8 D1 Input7 8D 9 9 E2 Input8 GND 10 10 E1 GroundPin LE 11 11 E3 LatchEnable 8Q 12 12 E4 Output8 7Q 13 13 D2 Output7 6Q 14 14 D4 Output6 5Q 15 15 C3 Output5 4Q 16 16 C4 Output4 3Q 17 17 B2 Output3 2Q 18 18 B4 Output2 1Q 19 19 A4 Output1 VCC 20 20 A3 PowerPin Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC DBpackage(4) 70 DGVpackage(4) 92 DWpackage(4) 58 GQNorZQNpackage(4) 78 θ Packagethermalimpedance °C/W JA Npackage(4) 69 NSpackage(4) 60 PWpackage(4) 83 RGYpackage(5) 37 (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintherecommendedoperatingconditionstable. CC (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (5) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas500V mayactuallyhavehigherperformance. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas250V mayactuallyhavehigherperformance. 4 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A www.ti.com SCAS300S–JANUARY1993–REVISEDMAY2014 7.3 Recommended Operating Conditions(1) SN54LVC573A SN74LVC573A UNIT MIN MAX MIN MAX Operating 2 3.6 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 1.5 V =1.65Vto1.95V 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 2 CC V =1.65Vto1.95V 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 0.8 CC V Inputvoltage 0 5.5 0 5.5 V I Highorlowstate 0 V 0 V CC CC V Outputvoltage V O 3-state 0 5.5 0 5.5 V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 –12 CC V =3V –24 –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 12 CC V =3V 24 24 CC Δt/Δv Inputtransitionriseorfallrate 6 6 ns/V T Operatingfree-airtemperature –55 125 –40 85 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 7.4 Thermal Information SN74LVC573A THERMALMETRIC(1) PW UNIT 20PINS R Junction-to-ambientthermalresistance 102.5 θJA R Junction-to-case(top)thermalresistance 35.9 θJCtop R Junction-to-boardthermalresistance 53.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 2.2 JT ψ Junction-to-boardcharacterizationparameter 52.9 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LVC573A SN74LVC573A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP(1) MAX MIN TYP(1) MAX 1.65Vto3.6V V –0.2 CC I =–100µA OH 2.7Vto3.6V V –0.2 CC I =–4mA 1.65V 1.2 OH V I =–8mA 2.3V 1.7 V OH OH 2.7V 2.2 2.2 I =–12mA OH 3V 2.4 2.4 I =–24mA 3V 2.2 2.2 OH 1.65Vto3.6V 0.2 I =100µA OL 2.7Vto3.6V 0.2 I =4mA 1.65V 0.45 OL V V OL I =8mA 2.3V 0.7 OL I =12mA 2.7V 0.4 0.4 OL I =24mA 3V 0.55 0.55 OL I V =0to5.5V 3.6V ±5 ±5 µA I I I V orV =5.5V 0 ±10 µA off I O I V =0to5.5V 3.6V ±15 ±10 µA OZ O V =V orGND 10 10 I CC I I =0 3.6V µA CC 3.6V≤V ≤5.5V(2) O 10 10 I OneinputatV –0.6V, ΔI CC 2.7Vto3.6V 500 500 µA CC OtherinputsatV orGND CC C V =V orGND 3.3V 4 4 pF i I CC C V =V orGND 3.3V 5.5 5.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A (2) Thisappliesinthedisabledstateonly. 7.6 Timing Requirements, SN54LVC573A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54LVC573A V =3.3V V =2.7V CC UNIT CC ±0.3V MIN MAX MIN MAX t Pulseduration,LEhigh 3.3 3.3 ns w t Setuptime,databeforeLE↓ 2 2 ns su t Holdtime,dataafterLE↓ 2.5 2.5 ns h 7.7 Timing Requirements, SN74LVC573A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN74LVC573A V =1.8V V =2.5V V =3.3V CC CC V =2.7V CC UNIT ±0.15V ±0.2V CC ±0.3V MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 9 4 3.3 3.3 ns w t Setuptime,databeforeLE↓ 6 4 2 2 ns su t Holdtime,dataafterLE↓ 4 2 1.5 1.5 ns h 6 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A www.ti.com SCAS300S–JANUARY1993–REVISEDMAY2014 7.8 Switching Characteristics, SN54LVC573A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54LVC573A FROM TO V =3.3V PARAMETER V =2.7V CC UNIT (INPUT) (OUTPUT) CC ±0.3V MIN MAX MIN MAX D 7.7 1 6.9 t Q ns pd LE 8.4 1 7.7 t OE Q 8.5 1 7.5 ns en t OE Q 7 0.5 6.7 ns dis 7.9 Switching Characteristics, SN74LVC573A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN74LVC573A FROM TO V =1.8V V =2.5V V =3.3V PARAMETER CC CC V =2.7V CC UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V CC ±0.3V MIN MAX MIN MAX MIN MAX MIN MAX D 1 19.1 1 9.6 1 7.7 1.5 6.9 t Q ns pd LE 1 22.8 1 10.5 1 8.4 2 7.7 t OE Q 1 20 1 10.5 1 8.5 1.5 7.5 ns en t OE Q 1 19.3 1 7.8 1 7 1.6 6.5 ns dis t 1 ns sk(o) 7.10 Operating Characteristics T =25°C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Outputs Powerdissipation enabled 61 56 37 C capacitance f=10MHz pF pd perlatch Outputs 3 3 4 disabled 7.11 Typical Characteristics 8 6 TDP TPD in ns 7 5 6 4 5 P D D 4 P 3 T T 3 2 2 1 1 0 0 0 0.5 1 1.5 2 2.5 3 3.5 -100 -50 0 50 100 150 Vcc - Volts Temp - °C D001 D001 Figure1.SN74LVC573ALEtoQTDPVccvsTPDat25°C Figure2.SN74LVC573ALEtoQAcrossTemp3.3VVcc Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH – VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A www.ti.com SCAS300S–JANUARY1993–REVISEDMAY2014 9 Detailed Description 9.1 Overview The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V operation, and the CC SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V V operation. These devices CC feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high- impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power- down applications using I . The I circuitry disables the outputs, preventing damaging current backflow through off off thedevicewhenitispowereddown. 9.2 Functional Block Diagram 1 OE 11 LE C1 19 2 1Q 1D 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto3.6V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • I Feature off – AllowsvoltagesontheinputsandoutputswhenV is0V CC 9.4 Device Functional Modes FunctionTable (EachLatch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com 10 Applications and Implementation 10.1 Application Information The SN74LVC573A is a high drive CMOS device that can be used for a multitude of bus interface type applications where the data needs to be retained or latched . It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5VtolerantallowingittotranslatedowntoV . CC 10.2 Typical Application Regulated3.6 V OE Vcc LE 1D 1Q uC System Logic LEDs uC or 8D 8Q System Logic GND 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloadssoroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputconditions – Risetimeandfalltimespecifications.See(Δt/ΔV)inRecommendedOperatingConditionstable. – Specifiedhighandlowlevels.See(V andV )inRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. Recommendoutputconditions – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC 10 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A www.ti.com SCAS300S–JANUARY1993–REVISEDMAY2014 Typical Application (continued) 10.2.3 ApplicationCurves 3 ICC 1.8V ICC 2.5V 2.5 ICC 3.3V 2 A m - C 1.5 C I 1 0.5 0 0 20 40 60 Frequency - MHz D001 Figure4.SN74LVC573AI vsFrequency CC 11 Power Supply Recommendations The power supply can be any voltage between the Min and Max supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, a 0.1-μF capacitor is recommended. If there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed asclosetothepowerpinaspossibleforbestresults. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more CC convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of theIOssotheyalsocannotfloatwhendisabled. 12.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LVC573A SN74LVC573A

SN54LVC573A,SN74LVC573A SCAS300S–JANUARY1993–REVISEDMAY2014 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54LVC573A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LVC573A Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronymsanddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 12 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC573A SN74LVC573A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9757501Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9757501Q2A SNJ54LVC 573AFK 5962-9757501QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757501QR A SNJ54LVC573AJ 5962-9757501QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757501QS A SNJ54LVC573AW SN74LVC573ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC573A & no Sb/Br) SN74LVC573ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC573A & no Sb/Br) SN74LVC573ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC573A & no Sb/Br) SN74LVC573AN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74LVC573AN (RoHS) SN74LVC573ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC573A & no Sb/Br) SN74LVC573ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC573A & no Sb/Br) SN74LVC573APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC573APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC573A & no Sb/Br) SN74LVC573ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LC573A & no Sb/Br) SN74LVC573AZQNR LIFEBUY BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LC573A MICROSTAR & no Sb/Br) JUNIOR SNJ54LVC573AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9757501Q2A SNJ54LVC 573AFK SNJ54LVC573AJ ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757501QR A SNJ54LVC573AJ SNJ54LVC573AW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9757501QS A SNJ54LVC573AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC573A, SN74LVC573A : •Catalog: SN74LVC573A •Automotive: SN74LVC573A-Q1, SN74LVC573A-Q1 •Enhanced Product: SN74LVC573A-EP, SN74LVC573A-EP •Military: SN54LVC573A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC573ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVC573ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC573ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVC573ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVC573APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC573APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVC573APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC573ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN74LVC573AZQNR BGAMI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC573ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC573ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC573ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC573ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC573APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC573APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVC573APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LVC573ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 SN74LVC573AZQNR BGAMICROSTAR ZQN 20 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

None

GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated