Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs 1 Features 2 Applications • OperateFrom1.65Vto3.6V • NetworkSwitches 1 • InputsAcceptVoltagesto5.5V • TVSet-topBoxes • Maxt of6.8nsat3.3V • MotorDrives pd • TypicalV (OutputGroundBounce) • PCsandNotebooks OLP <0.8VatV =3.3V,T =25°C CC A 3 Description • TypicalV (OutputV Undershoot) OHV OH >2VatV =3.3V,T =25°C The SN54LVC373A octal transparent D-type latch is CC A designed for 2.7-V to 3.6-V V operation, and the • SupportsMixed-ModeSignalOperation CC SN74LVC373A octal transparent D-type latch is onAllPorts designedfor1.65-Vto3.6-VV operation. (5-VInput/OutputVoltageWith3.3-VV ) CC CC • IoffSupportsLive-Insertion,Partial-Power-Down DeviceInformation(1) Mode,andBack-DriveProtection PARTNUMBER PACKAGE BODYSIZE(NOM) • Latch-UpPerformanceExceeds250mAPer SSOP(20) 7.20mm×5.30mm JESD17 SOIC(20) 12.80mm×7.50mm • ESDProtectionExceedsJESD22 SNx4LVC373A PDIP(20) 24.33mm6.35mm – 2000-VHuman-BodyModel(A114-A) TSSOP(20) 6.50mm×4.40mm – 200-VMachineModel(A115-A) VQFN(20) 4.50mm×3.50mm – 1000-VCharged-DeviceModel(C101) (1) For all available packages, see the orderable addendum at theendofthedatasheet. • OnProductsComplianttoMIL-PRF-38535, AllParametersAreTestedUnlessOtherwise Noted.OnAllOtherProducts,Production ProcessingDoesNotNecessarilyIncludeTesting ofAllParameters. 4 Simplified Schematic 1 OE 11 LE C1 2 3 1Q 1D 1D To Seven Other Channels PinnumbersshownarefortheDB,DGV,DW,FK,J,N,NS,PW,RGY,andWpackages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription.............................................. 9 2 Applications........................................................... 1 9.1 Overview...................................................................9 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.........................................9 4 SimplifiedSchematic............................................. 1 9.3 FeatureDescription.................................................10 9.4 DeviceFunctionalModes........................................10 5 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 11 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................11 7 Specifications......................................................... 4 10.2 TypicalApplication ...............................................11 7.1 AbsoluteMaximumRatings .....................................4 11 PowerSupplyRecommendations..................... 12 7.2 HandlingRatings.......................................................4 12 Layout................................................................... 12 7.3 RecommendedOperatingConditions......................5 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................12 7.5 ElectricalCharacteristics...........................................6 12.2 LayoutExample....................................................12 7.6 TimingRequirements,SN54LVC373A.....................6 13 DeviceandDocumentationSupport................. 13 7.7 TimingRequirements,SN74LVC373A.....................6 13.1 RelatedLinks........................................................13 7.8 SwitchingCharacteristics,SN54LVC373A...............7 13.2 Trademarks...........................................................13 7.9 SwitchingCharacteristics,SN74LVC373A...............7 13.3 ElectrostaticDischargeCaution............................13 7.10 OperatingCharacteristics........................................7 13.4 Glossary................................................................13 7.11 TypicalCharacteristics............................................7 14 Mechanical,Packaging,andOrderable Information........................................................... 13 8 ParameterMeasurementInformation..................8 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionS(May2005)toRevisionT Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 • ChangedI Feature............................................................................................................................................................... 1 off • AddedMilitaryDisclaimertoFeatures.................................................................................................................................... 1 • AddedApplications................................................................................................................................................................. 1 • AddedHandlingRatingstable................................................................................................................................................ 4 • ChangedMAXambienttemperaturefrom85°Cto125°C..................................................................................................... 5 • AddedThermalInformationtable........................................................................................................................................... 5 • AddedTypicalCharacteristics. .............................................................................................................................................. 7 • AddedDetailedDescriptionsection........................................................................................................................................ 9 2 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 6 Pin Configuration and Functions SN54LVC373A...J OR W PACKAGE SN74LVC373A...RGYPACKAGE SN74LVC373A...DB, DGV, DW, N, (TOPVIEW) SN54LVC373A...FK PACKAGE NS, OR PW PACKAGE C (TOPVIEW) (TOPVIEW) E C O V C O1QE 12 2109 V8QCC 1Q 2 1 20 19 8Q 1D 1Q OEVC8Q 1D 3 18 8D 1D 3 18 8D 3 2 1 20 19 2D 4 17 7D 2D 4 17 7D 2D 4 18 8D 2Q 5 16 7Q 2Q 5 16 7Q 2Q 5 17 7D 3Q 6 15 6Q 3Q 6 15 6Q 3D 7 14 6D 3D 7 14 6D 3Q 6 16 7Q 4D 8 13 5D 4D 8 13 5D 3D 7 15 6Q 4Q 9 12 5Q 4Q 9 12 5Q 4D 8 14 6D GND 10 11 LE 10 11 9 10 11 12 13 D E N L G Q D EQ D 4 N L5 5 G PinFunctions PIN I/O DESCRIPTION NO. NAME 1 OE I EnablePin 2 1Q O Output1 3 1D I Input1 4 2D I Input2 5 2Q O Output2 6 3Q O Output3 7 3D I Input3 8 4D I Input4 9 4Q O Output4 10 GND – GroundPin 11 LE I LatchEnable 12 5Q O Output5 13 5D I Input5 14 6D I Input6 15 6Q O Output6 16 7Q O Output7 17 7D I Input7 18 8D I Input8 19 8Q O Output8 20 VCC – PowerPin GQN OR ZQN PACKAGE Table1.PinAssignments (TOP VIEW) 1 2 3 4 1 2 3 4 A 1Q OE V 8Q CC A B 2D 7D 1D 8D B C 3Q 2Q 6Q 7Q C D 4D 5D 3D 6D D E GND 4Q LE 5Q E Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54LVC373A SN74LVC373A UNIT MIN MAX MIN MAX Operating 2 3.6 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 1.5 V =1.65Vto1.95V 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 2 CC V =1.65Vto1.95V 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 0.8 CC V Inputvoltage 0 5.5 0 5.5 V I Highorlowstate 0 V 0 V CC CC V Outputvoltage V O 3-state 0 5.5 0 5.5 V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 –12 CC V =3V –24 –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 12 CC V =3V 24 24 CC Δt/Δv Inputtransitionriseorfallrate 10 10 ns/V T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,(SCBA004). 7.4 Thermal Information SN74LVC373A THERMALMETRIC(1) PW UNIT 20PINS R Junction-to-ambientthermalresistance 102.5 θJA R Junction-to-case(top)thermalresistance 35.9 θJC(top) R Junction-to-boardthermalresistance 53.5 θJB °C/W ψ Junction-to-topcharacterizationparameter 2.2 JT ψ Junction-to-boardcharacterizationparameter 52.9 JB R Junction-to-case(bottom)thermalresistance n/a θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LVC373A SN74LVC373A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP(1) MAX MIN TYP(1) MAX 1.65Vto3.6V V –0.2 CC I =–100µA OH 2.7Vto3.6V V –0.2 CC I =–4mA 1.65V 1.2 OH V I =–8mA 2.3V 1.7 V OH OH 2.7V 2.2 2.2 I =–12mA OH 3V 2.4 2.4 I =–24mA 3V 2.2 2.2 OH 1.65Vto3.6V 0.2 I =100µA OL 2.7Vto3.6V 0.2 I =4mA 1.65V 0.45 OL V V OL I =8mA 2.3V 0.7 OL I =12mA 2.7V 0.4 0.4 OL I =24mA 3V 0.55 0.55 OL I V =0to5.5V 3.6V ±5 ±5 µA I I I V orV =5.5V 0 ±10 µA off I O I V =0to5.5V 3.6V ±15 ±10 µA OZ O V =V orGND 10 10 I CC I I =0 3.6V µA CC 3.6V≤V ≤5.5V(2) O 10 10 I OneinputatV –0.6V, ΔI CC 2.7Vto3.6V 500 500 µA CC OtherinputsatV orGND CC C V =V orGND 3.3V 4 12 4 pF i I CC C V =V orGND 3.3V 5.5 12 5.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A (2) Thisappliesinthedisabledstateonly. 7.6 Timing Requirements, SN54LVC373A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54LVC373A V =3.3V PARAMETER V =2.7V CC UNIT CC ±0.3V MIN MAX MIN MAX t Pulseduration,LEhigh 3.3 3.3 ns w t Setuptime,databeforeLE↓ 2 2 ns su t Holdtime,dataafterLE↓ 2 2 ns h 7.7 Timing Requirements, SN74LVC373A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN74LVC373A V =1.8V V =2.5V V =3.3V PARAMETER CC CC V =2.7V CC UNIT ±0.15V ±0.2V CC ±0.3V MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 9 4 3.3 3.3 ns w t Setuptime,databeforeLE↓ 6 4 2 2 ns su t Holdtime,dataafterLE↓ 4 2 1.5 1.5 ns h 6 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 7.8 Switching Characteristics, SN54LVC373A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN54LVC373A FROM TO V =3.3V PARAMETER V =2.7V CC UNIT (INPUT) (OUTPUT) CC ±0.3V MIN MAX MIN MAX D 8.5 1 7.5 t Q ns pd LE 9.5 1 8.5 t OE Q 8.7 1 7.7 ns en t OE Q 8 0.5 7 ns dis 7.9 Switching Characteristics, SN74LVC373A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) SN74LVC373A FROM TO V =1.8V V =2.5V V =3.3V PARAMETER CC CC V =2.7V CC UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V CC ±0.3V MIN MAX MIN MAX MIN MAX MIN MAX D 1 19.1 1 9.6 7.8 1.5 6.8 t Q ns pd LE 1 22.8 1 10.5 8.2 2 7.6 t OE Q 1 20 1 10.5 8.7 1.5 7.7 ns en t OE Q 1 19.3 1 7.8 7.6 1.5 7 ns dis t 1 1 1 1 ns sk(o) 7.10 Operating Characteristics T =25°C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipationcapacitance Outputsenabled 61 56 46 C f=10MHz pF pd perlatch Outputsdisabled 3 3 3 7.11 Typical Characteristics 8 6 TPD in ns 7 5 6 4 5 s s n n D - 4 D - 3 P P T T 3 2 2 1 1 TPD in ns 0 0 0 0.5 1 1.5 2 2.5 3 3.5 -100 -50 0 50 100 150 VCC - V D003 Temperature (qC) D001 Figure1.SN74LVC373ALEtoQTDP Figure2.SN74LVC373ALEtoQ V vsTPDat25°C AcrossTemperatureat3.3-VV CC CC Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH - VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 9 Detailed Description 9.1 Overview While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputsarelatchedatthelogiclevelssetupattheDinputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines withoutinterfaceorpullupcomponents. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered whiletheoutputsareinthehigh-impedancestate. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs,preventingdamagingcurrentbackflowthroughthedeviceswhentheyarepowereddown. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators inamixed3.3-V/5-Vsystemenvironment. 9.2 Functional Block Diagram 1 OE 11 LE C1 2 1Q 3 1D 1D To Seven Other Channels PinnumbersshownarefortheDB,DGV,DW,FK,J,N,NS,PW,RGY,andWpackages. Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto3.6V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • I feature off – AllowsvoltagesontheinputsandoutputswhenV is0V CC 9.4 Device Functional Modes Table2.FunctionTable(EachLatch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z 10 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 10 Application and Implementation 10.1 Application Information The SN74LVC373A is a high-drive CMOS device that can be used for a multitude of bus-interface type applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. The inputsare5.5VtolerantallowingittotranslatedowntoV . CC 10.2 Typical Application Regulated 3.3 V OE VCC CLK 1D 1Q µC System Logic µC or 8D 8Q LEDs System Logic GND Figure4. TypicalApplicationDiagram 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads;therefore,routingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendOutputConditions – Loadcurrentsshouldnotexceed50mAperoutputand100mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A SCAS295T–JANUARY1993–REVISEDJULY2014 www.ti.com Typical Application (continued) 10.2.3 ApplicationCurves 3 ICC 1.8 V ICC 2.5 V 2.5 ICC 3.3 V Hz 2 M cy - 1.5 n e u q Fre 1 0.5 0 0 10 20 30 40 50 60 ICC - V D003 Figure5.I vsFrequency CC 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μf is recommended; if there are multiple V pins, then 0.01 μf or 0.022 μf is recommended for each CC power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldneverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float outputs, CC unlessthepartisatransceiver. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram 12 SubmitDocumentationFeedback Copyright©1993–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN54LVC373A SN74LVC373A

SN54LVC373A,SN74LVC373A www.ti.com SCAS295T–JANUARY1993–REVISEDJULY2014 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54LVC373A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LVC373A Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1993–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54LVC373A SN74LVC373A

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9757301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9757301Q2A SNJ54LVC 373AFK 5962-9757301QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QR A SNJ54LVC373AJ 5962-9757301QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QS A SNJ54LVC373AW SN74LVC373ADBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373ADW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC373A & no Sb/Br) SN74LVC373ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC373A & no Sb/Br) SN74LVC373ADWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC373A & no Sb/Br) SN74LVC373AN ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74LVC373AN (RoHS) SN74LVC373ANSR ACTIVE SO NS 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC373A & no Sb/Br) SN74LVC373APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC373APWT ACTIVE TSSOP PW 20 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A & no Sb/Br) SN74LVC373ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC373A & no Sb/Br) SN74LVC373AZQNR ACTIVE BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LC373A MICROSTAR & no Sb/Br) JUNIOR SNJ54LVC373AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9757301Q2A SNJ54LVC 373AFK SNJ54LVC373AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QR A SNJ54LVC373AJ SNJ54LVC373AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QS A SNJ54LVC373AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC373A, SN74LVC373A : •Catalog: SN74LVC373A •Automotive: SN74LVC373A-Q1, SN74LVC373A-Q1 •Enhanced Product: SN74LVC373A-EP, SN74LVC373A-EP •Military: SN54LVC373A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC373ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVC373ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC373ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVC373ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVC373APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC373APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC373ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN74LVC373AZQNR BGAMI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC373ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC373ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC373ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC373ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC373APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC373APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LVC373ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 SN74LVC373AZQNR BGAMICROSTAR ZQN 20 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DB0020A TSSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/A 12/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/A 12/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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