Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 SN74LVC2G32 Dual 2-Input Positive-OR Gate 1 Features 3 Description • AvailableintheTexasInstruments This dual 2-input positive-OR gate is designed for 1 1.65-Vto5.5-VV operation. NanoFree™Package CC • Supports5-VV Operation The SN74LVC2G32 device performs the Boolean CC • InputsAcceptVoltagesto5.5V functionY(cid:2)A(cid:1)BorY(cid:2)A•Binpositivelogic. • Maximumt of3.8nsat3.3V NanoFree package technology is a major pd • LowPowerConsumption,10-µAMaximumI breakthrough in IC packaging concepts, using the die CC asthepackage. • ±24-mAOutputDriveat3.3V This device is fully specified for partial-power-down • TypicalV (OutputGroundBounce) OLP applications using I . The I circuitry disables the <0.8VatV =3.3V,T =25°C off off CC A outputs, preventing damaging current backflow • TypicalV (OutputV Undershoot) OHV OH throughthedevicewhenitispowereddown. >2VatV =3.3V,T =25°C CC A • I SupportsLiveInsertion,Partial-Power-Down DeviceInformation(1) off Mode,andBack-DriveProtection PARTNUMBER PACKAGE BODYSIZE • CanBeUsedasaDownTranslatortoTranslate SN74LVC2G32DCT SSOP(8) 2.95mm×2.80mm InputsFromaMaximumof5.5VDowntotheVCC SN74LVC2G32DCU VSSOP(8) 2.30mm×2.00mm Level SN74LVC2G32YZP DSBGA(8) 1.91mm×0.91mm • Latch-UpPerformanceExceeds100mAPer (1) For all available packages, see the orderable addendum at JESD78,ClassII theendofthedatasheet. • ESDProtectionExceedsJESD22 – 2000-VHumanBodyModel(A114-A) – 1000-VCharged-DeviceModel(C101) 2 Applications • DownTranslation • LogicalOR LogicDiagram(PositiveLogic) 1 1A 7 2 1Y 1B 5 2A 3 6 2Y 2B 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.........................................9 2 Applications........................................................... 1 8.3 FeatureDescription...................................................9 3 Description............................................................. 1 8.4 DeviceFunctionalModes..........................................9 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 10 9.1 ApplicationInformation............................................10 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplication .................................................10 6 Specifications......................................................... 4 10 PowerSupplyRecommendations..................... 11 6.1 AbsoluteMaximumRatings .....................................4 11 Layout................................................................... 11 6.2 ESDRatings..............................................................4 6.3 RecommendedOperatingConditions......................5 11.1 LayoutGuidelines.................................................11 6.4 ThermalInformation..................................................5 11.2 LayoutExample....................................................11 6.5 ElectricalCharacteristics...........................................6 12 DeviceandDocumentationSupport................. 12 6.6 SwitchingCharacteristics..........................................6 12.1 RelatedDocumentation.........................................12 6.7 OperatingCharacteristics..........................................6 12.2 CommunityResources..........................................12 6.8 TypicalCharacteristics..............................................7 12.3 Trademarks...........................................................12 7 ParameterMeasurementInformation..................8 12.4 ElectrostaticDischargeCaution............................12 12.5 Glossary................................................................12 8 DetailedDescription.............................................. 9 13 Mechanical,Packaging,andOrderable 8.1 Overview...................................................................9 Information........................................................... 12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionM(November2013)toRevisionN Page • AddedApplicationssection,DeviceInformationtable,PinConfigurationandFunctionssection,ESDRatingstable, ThermalInformationtable,TypicalCharacteristicssection,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection ..................................... 1 ChangesfromRevisionL(February2007)toRevisionM Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 • UpdatedFeatures................................................................................................................................................................... 1 • Updatedoperatingtemperaturerange................................................................................................................................... 5 2 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 www.ti.com SCES201N–APRIL1999–REVISEDSEPTEMBER2015 5 Pin Configuration and Functions DCTPackage 8-PinSSOP DCUPackage TopView 8-PinVSSOP TopView 1A 1 8 VCC 1A 1 8 VCC 1B 2 7 1Y 1B 2 7 1Y 2Y 3 6 2B 2Y 3 6 2B GND 4 5 2A GND 4 5 2A YZPPackage 8-PinDSBGA BottomView GND 45 2A 2Y 36 2B 1B 27 1Y 1A 18 VCC Seemechanicaldrawingfordimensions PinFunctions PIN I/O DESCRIPTION NAME NO. 1A 1 I InputforfirstORgate 1B 2 I InputforfirstORgate 1Y 7 O OutputforfirstORgate 2A 5 I InputforsecondORgate 2B 6 I InputforsecondORgate 2Y 3 O OutputforsecondORgate GND 4 — Ground V 8 — Power CC Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Junctiontemperature 150 °C J T Storagetemperaturerange –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputclamp-currentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 6.2 ESD Ratings PARAMETER DEFINITION VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101,all V pins(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 www.ti.com SCES201N–APRIL1999–REVISEDSEPTEMBER2015 6.3 Recommended Operating Conditions(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent –16 mA OH V =3V CC –24 V =4.5V –32 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseorfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 5 CC DCTandDCUpackages –40 125 T Operatingfree-airtemperature °C A YZPpackage –40 85 (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. 6.4 Thermal Information SN74LVC2G32 THERMALMETRIC(1) DCT(SSOP) DCU(VSSOP) YZP(DSBGA) UNIT 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 220 227 102 °C/W θJA (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto85°C –40°Cto125°C PARAMETER TESTCONDITIONS VCC MIN TYP(1) MAX MIN TYP(1) MAX UNIT IOH=–100µA 1.65Vto5.5V VCC–0.1 VCC–0.1 IOH=–4mA 1.65V 1.2 1.2 IOH=–8mA 2.3V 1.9 1.9 VOH V IOH=–16mA 2.4 2.4 3V IOH=–24mA 2.3 2.3 IOH=–32mA 4.5V 3.8 3.8 IOL=100µA 1.65Vto5.5V 0.1 0.1 IOL=4mA 1.65V 0.45 0.45 IOL=8mA 2.3V 0.3 0.3 VOL V IOL=16mA 0.4 0.4 3V IOL=24mA 0.55 0.6 IOL=32mA 4.5V 0.55 0.6 II AorBinputs VI=5.5VorGND 0to5.5V ±5 ±5 µA Ioff VIorVO=5.5V 0 ±10 ±10 µA ICC VI=5.5VorGND, IO=0 1.65Vto5.5V 10 10 µA ΔICC OOntheerinipnuptuatstaVtCVCC–C0o.r6GVN,D 3Vto5.5V 500 500 µA Ci VI=VCCorGND 3.3V 5 5 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A 6.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2) VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V PARAMETER FROM TO TEMPERATURE ±0.15V ±0.2V ±0.3V ±0.5V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX –40°Cto85°C 2.4 8 1 4.4 1 3.8 1 3.2 tpd AorB Y ns –40°Cto125°C 2.4 10 1 5.6 1 4.8 1 3.9 6.7 Operating Characteristics T =25°C A V =1.8V V =2.5V V =3.3V V =5V CC CC CC CC PARAMETER TESTCONDITIONS UNIT TYP TYP TYP TYP C Powerdissipationcapacitance f=10MHz 17 17 17 19 pF pd 6 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 www.ti.com SCES201N–APRIL1999–REVISEDSEPTEMBER2015 6.8 Typical Characteristics T =25°C A 6 tpHL 5 S) n y (4 tpLH a el D n 3 o ati ag2 p o Pr 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC (V) C001 Figure1.PropagationDelayvs.V CC Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com 7 Parameter Measurement Information V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 30 pF 1 kW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 30 pF 500W 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 50 pF 500W 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 50 pF 500W 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 www.ti.com SCES201N–APRIL1999–REVISEDSEPTEMBER2015 8 Detailed Description 8.1 Overview The SN74LVC2G32 provides two logical OR gates per device and each gate has two inputs. Both input paths useidenticalcircuitryformatchingpropagationdelays.Supplyvoltagefrom1.65Vto5.5Vissupported. 8.2 Functional Block Diagram 1 1A 7 2 1Y 1B 5 2A 3 6 2Y 2B Figure3. LogicDiagram(PositiveLogic) 8.3 Feature Description TheSN74LVC2G32inputspergatecanacceptupto5.5VregardlessofV . CC 8.4 Device Functional Modes Table1liststhefunctionalmodesfortheSN74LVC2G32. Table1.FunctionTable(Each Gate)(1) INPUTS OUTPUT A B Y H X H X H H L L L (1) Y=A+Binpositivelogic. Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LVC2G32 device is dual 2-input OR gate. High-output current capability is ideal for driving multiple outputs. 9.2 Typical Application 3-inputORconfiguration,Y=A+B+C A B Y C Figure4. 3-inputORgate 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to preventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions: – Forrisetimeandfalltimespecifications,see(Δt/ΔV)inRecommendedOperatingConditions table. – Forspecifiedhighandlowlevels,see(V andV )inRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendOutputConditions: – Loadcurrentsshouldnotexceed50mAperoutputand100mAtotalforthepart. – Series resistors on the output may be used if the user desires to slow the output edge signal or limit the outputcurrent. 10 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 www.ti.com SCES201N–APRIL1999–REVISEDSEPTEMBER2015 Typical Application (continued) 9.2.3 ApplicationCurve 5 VCC=5V VCC=3.3V 4 VCC=2.5V A) 3 VCC=1.8V m C ( C2 I 1 0 0 5 10 15 20 25 30 35 40 Frequency (MHz) C001 Figure5.I vsFrequency CC NoLoad 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in RecommendedOperatingConditionstable. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, a 0.1-μF capacitor is recommended. If there are multiple V terminals then 0.01-μF or 0.022-μF CC capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise.Thebypasscapacitorshouldbeinstalledasclosetothepowerterminalaspossibleforthebestresults. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND orV ,whichevermakesmoresenseorismoreconvenient. CC 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC2G32

SN74LVC2G32 SCES201N–APRIL1999–REVISEDSEPTEMBER2015 www.ti.com 12 Device and Documentation Support 12.1 Related Documentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs,SCBA004 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks NanoFree,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 12 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G32

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC2G32DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C32 & no Sb/Br) (R, Z) SN74LVC2G32DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C32 & no Sb/Br) (R, Z) SN74LVC2G32DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C32 & no Sb/Br) (R, Z) SN74LVC2G32DCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C32Q, C32R) & no Sb/Br) CR SN74LVC2G32DCURE4 ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C32R & no Sb/Br) SN74LVC2G32DCURG4 ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C32R & no Sb/Br) SN74LVC2G32DCUT ACTIVE VSSOP DCU 8 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C32Q, C32R) & no Sb/Br) CR SN74LVC2G32YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 CGN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC2G32 : •Automotive: SN74LVC2G32-Q1 •Enhanced Product: SN74LVC2G32-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC2G32DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3 SN74LVC2G32DCUR VSSOP DCU 8 3000 178.0 9.5 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G32DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G32DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G32DCUT VSSOP DCU 8 250 178.0 9.5 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G32YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC2G32DCTR SM8 DCT 8 3000 182.0 182.0 20.0 SN74LVC2G32DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 SN74LVC2G32DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 SN74LVC2G32DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0 SN74LVC2G32DCUT VSSOP DCU 8 250 202.0 201.0 28.0 SN74LVC2G32YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 PackMaterials-Page2

MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,13 M 0,15 8 5 0,15 NOM 2,90 4,25 ÇÇÇÇÇ 2,70 3,75 ÇÇÇÇÇ ÇÇÇÇÇ Gage Plane ÇÇÇÇÇ PIN 1 INDEX AREA 0,25 1 4 0°– 8° 3,15 0,60 2,75 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 4188781/C 09/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

PACKAGE OUTLINE YZP0008 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP D C SYMM 1.5 D: Max = 1.919 mm, Min =1 .858 mm TYP B E: Max = 0.918 mm, Min =0 .857 mm 0.5 TYP A 0.25 8X 1 2 0.21 0.015 C A B SYMM 4223082/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.23) 1 2 A (0.5) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223082/A 07/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL TYP D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4223082/A 07/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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