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SN74LVC2G07DBVR产品简介:
ICGOO电子元器件商城为您提供SN74LVC2G07DBVR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74LVC2G07DBVR价格参考¥1.05-¥1.05。Texas InstrumentsSN74LVC2G07DBVR封装/规格:逻辑 - 缓冲器,驱动器,接收器,收发器, Buffer, Non-Inverting 2 Element 1 Bit per Element Open Drain Output SOT-23-6。您可以下载SN74LVC2G07DBVR参考资料、Datasheet数据手册功能说明书,资料中有SN74LVC2G07DBVR 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC BUFF/DVR DL NON-INV SOT23-6缓冲器和线路驱动器 Dual w/ Open-Drain |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | http://www.ti.com/lit/gpn/sn74lvc2g07 |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,缓冲器和线路驱动器,Texas Instruments SN74LVC2G07DBVR74LVC |
数据手册 | |
产品型号 | SN74LVC2G07DBVR |
PCN组件/产地 | |
产品目录页面 | |
产品种类 | 缓冲器和线路驱动器 |
传播延迟时间 | 3.7 ns at 3.3 V, 2.9 ns at 5 V |
低电平输出电流 | 32 mA |
供应商器件封装 | SOT-23-6 |
元件数 | 2 |
其它名称 | 296-13494-6 |
包装 | Digi-Reel® |
单位重量 | 15.800 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | SOT-23-6 |
封装/箱体 | SOT-23-6 |
工作温度 | -40°C ~ 125°C |
工厂包装数量 | 3000 |
最大工作温度 | + 85 C |
最小工作温度 | - 45 C |
极性 | Non-Inverting |
标准包装 | 1 |
每元件位数 | 1 |
每芯片的通道数量 | 2 |
电压-电源 | 1.65 V ~ 5.5 V |
电流-输出高,低 | -,32mA |
电源电压-最大 | 5.5 V |
电源电压-最小 | 1.65 V |
系列 | SN74LVC2G07 |
输入线路数量 | 2 |
输出类型 | Open Drain |
输出线路数量 | 2 |
逻辑类型 | 缓冲器/线路驱动器,非反相并带开漏极 |
逻辑系列 | LVC |
Product Order Technical Tools & Support & Folder Now Documents Software Community SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 SN74LVC2G07 Dual Buffer and Driver With Open-Drain Outputs 1 Features 3 Description • DualOpen-DrainBufferConfiguration This dual buffer and driver is designed for 1.65-V to 1 5.5-V V operation. The output of the • -24-mAOutputDriveat3.3V CC SN74LVC2G07 device is open drain and can be • SupportTranslation-UpandDown connected to other open-drain outputs to implement • AvailableintheTexasInstruments active-low wired-OR or active-high wired-AND NanoFree™Package functions.Themaximumsinkcurrentis32mA. • Supports5-VV Operation NanoFreepackagetechnologyisamajor CC • InputsandOpen-DrainOutputsAcceptVoltages breakthrough in IC packaging concepts, using the die Upto5.5V asthepackage. • Maxt of3.7nsat3.3V This device is fully specified for partial-power-down pd applications using I . The I circuitry disables the • LowPowerConsumption,10-μAMaxI off off CC outputs, preventing damaging current backflow • TypicalV (OutputGroundBounce) OLP throughthedevicewhenitispowereddown. <0.8VatV =3.3V,T =25°C CC A • TypicalV (OutputV Undershoot) DeviceInformation(1) OHV OH >2VatVCC=3.3V,TA=25°C PARTNUMBER PACKAGE BODYSIZE(NOM) • IoffSupportsLiveInsertion,Partial-Power-Down SOT-23(6) 2.90mm×1.60mm Mode,andBack-DriveProtection SC70(6) 2.00mm×1.25mm • Latch-UpPerformanceExceeds100mA SN74LVC2G07 DRYSON(6) 1.45mm×1.00mm PerJESD78,ClassII DSFSON(6) 1.00mm×1.00mm • ESDProtectionExceedsJESD22 DSBGA(6) 1.41mm×0.91mm – 2000-VHuman-BodyModel(A114-A) (1) For all available packages, see the orderable addendum at – 200-VMachineModel(A115-A) theendofthedatasheet. – 1000-VCharged-DeviceModel(C101) FunctionalBlockDiagram 2 Applications 1 6 1A 1Y • Blu-rayPlayersandHomeTheaters • DVDRecordersandPlayers 3 4 2A 2Y • DesktopsorNotebookPCs • DigitalVideoCameras(DVC) • EmbeddedPCs • GPS:PersonalNavigationDevices • MobilePhones • NetworkProjectorFrontEnds • PortableMediaPlayers • SolidStateDrive(SSD):Enterprise • High-Definition(HDTV) • Tablet:Enterprise • AudioDock:Portable • DLPFrontProjectionSystem 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview...................................................................8 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.........................................8 3 Description............................................................. 1 8.3 FeatureDescription...................................................8 8.4 DeviceFunctionalModes..........................................8 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation.......................... 9 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation..............................................9 6 Specifications......................................................... 4 9.2 TypicalApplication ...................................................9 6.1 AbsoluteMaximumRatings .....................................4 10 PowerSupplyRecommendations..................... 10 6.2 ESDRatings..............................................................4 11 Layout................................................................... 10 6.3 RecommendedOperatingConditions......................4 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................10 6.5 ElectricalCharacteristics...........................................5 11.2 LayoutExamples...................................................10 6.6 SwitchingCharacteristicsfrom–40°Cto85°C.........5 12 DeviceandDocumentationSupport................. 11 6.7 SwitchingCharacteristicsfrom–40°Cto125°C.......5 12.1 DocumentationSupport........................................11 6.8 OperatingCharacteristics..........................................5 12.2 CommunityResources..........................................11 6.9 TypicalCharacteristics..............................................6 12.3 Trademarks...........................................................11 7 ParameterMeasurementInformation..................7 12.4 ElectrostaticDischargeCaution............................11 7.1 (Open-Drain).............................................................7 12.5 Glossary................................................................11 8 DetailedDescription.............................................. 8 13 Mechanical,Packaging,andOrderable Information........................................................... 11 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionK(November2013)toRevisionL Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 ChangesfromRevisionJ(August2012)toRevisionK Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • Updatedoperatingtemperaturerange................................................................................................................................... 4 2 SubmitDocumentationFeedback Copyright©2001–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 www.ti.com SCES308L–AUGUST2001–REVISEDMAY2015 5 Pin Configuration and Functions DBVPackage 6-PinSOT-23 YZPPackage TopView 6-PinDSBGA BottomView 1A 1 6 1Y 2A 3 4 2Y GND 2 5 V CC GND 2 5 V CC 1A 1 6 1Y 2A 3 4 2Y DRYPackage 6-PinSON TopView DCKPackage 6-PinSC70 1A 1 6 1Y TopView GND 2 5 V CC 1A 1 6 1Y 2A 3 4 2Y GND 2 5 V CC DSFPackage 2A 3 4 2Y 6-PinSON TopView 1A 1 6 1Y GND 2 5 V CC 2A 3 4 2Y PinFunctions PIN I/O DESCRIPTION NAME NO 1A 1 I Input1 GND 2 — Ground 2A 3 I Input2 2Y 4 O Open-drainoutput2 VCC 5 — Powerpin 1Y 6 O Open-drainoutput1 Copyright©2001–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltage(2) –0.5 6.5 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltageappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 6.5 V O I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T StorageTemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) +2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) +1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 5.5 V O V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseorfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 5 CC (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 4 SubmitDocumentationFeedback Copyright©2001–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 www.ti.com SCES308L–AUGUST2001–REVISEDMAY2015 Recommended Operating Conditions(1) (continued) MIN MAX UNIT T Operatingfree-airtemperature –40 125 °C A 6.4 Thermal Information SN74LVC2G07 THERMALMETRIC(1) SOT-23 SC70 DRY(SON) DSBGA DSF(SON) UNIT 6PINS 6PINS 6PINS 6PINS 6PINS RθJA Junction-to-ambientthermalresistance 165 259 234 123 300 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto85°C –40°Cto125°C PARAMETER TESTCONDITIONS VCC MIN TYP(1) MAX MIN TYP(1) MAX UNIT IOL=100μA 1.65Vto5.5V 0.1 0.1 IOL=4mA 1.65V 0.45 0.45 IOL=8mA 2.3V 0.3 0.3 VOL V IOL=16mA 0.4 0.4 3V IOL=24mA 0.55 0.55 IOL=32mA 4.5V 0.55 0.55 II Ainputs VI=5.5VorGND 0to5.5V ±5 ±5 μA Ioff VIorVO=5.5V 0 ±10 ±10 μA ICC VI=5.5VorGND, IO=0 1.65Vto5.5V 10 10 μA ΔICC OOntheerinipnuptuatstaVtCVCC–C0o.r6GVN,D 3Vto5.5V 500 500 μA CI VI=VCCorGND 3.3V 3.5 3.5 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A 6.6 Switching Characteristics from –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2) –40°Cto85°C PARAMETER FROM TO VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 1.5 8.6 1 4.4 1 3.7 1 2.9 ns 6.7 Switching Characteristics from –40°C to 125°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2) –40°Cto125°C PARAMETER FROM TO VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 1.5 8.6 1 4.9 1 4.2 1 3.4 ns 6.8 Operating Characteristics T =25°C A V =1.8V V =2.5V V =3.3V V =5V CC CC CC CC PARAMETER TESTCONDITIONS UNIT TYP TYP TYP TYP C Powerdissipationcapacitance f=10MHz 3 3 4 4 pF pd Copyright©2001–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 www.ti.com 6.9 Typical Characteristics 2.5 TPD 2 s 1.5 n D - P T 1 0.5 0 -100 -50 0 50 100 150 Temperature - °C D001 Figure1.TPDAcrossTemperatureat3.3VVcc 6 SubmitDocumentationFeedback Copyright©2001–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 www.ti.com SCES308L–AUGUST2001–REVISEDMAY2015 7 Parameter Measurement Information 7.1 (Open-Drain) V LOAD R S1 Open From Output L TEST S1 UnderTest GND t (see Notes E and F) V C PZL LOAD (see Note A)L RL tPLZ(see Notes E and G) VLOAD t /t V PHZ PZH LOAD LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L ∆ I r f 1.8V±0.15V V ≤2 ns V /2 2 ×V 30 pF 1 kΩ 0.15V CC CC CC 2.5V±0.2V V ≤2 ns V /2 2 ×V 30 pF 500Ω 0.15V CC CC CC 3.3V±0.3V 3V ≤2.5 ns 1.5V 6V 50 pF 500Ω 0.3V 5V±0.5V V ≤2.5 ns V /2 2 ×V 50 pF 500Ω 0.3V CC CC CC V I Timing Input V M 0V t W VI tsu th V Input V V I M M Data Input V V M M 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSE DURATION SETUP AND HOLDTIMES Input VM VM VI COounttpruotl VM VM VI 0V 0V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WaSv1e afotrVm 1 VM V +V LOAD VOL (see NoteL OBAD) OL ∆ VOL t t PHL PLH t t PZH PHZ Output VM VM VVOOHL (WseSae1v eNaOftoo uGtretmpN Bu D2t) VM VOH–V∆ ≈V0OHV VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATION DELAYTIMES ENABLE AND DISABLETIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics:PRR≤10 MHz, Z = 50Ω. O D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, t and t are the same as t . PLZ PZL PD F. t is measured atV . PZL M G.t is measured atV +V. PLZ OL ∆ H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms Copyright©2001–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC2G07 device contains two open drain buffer with a maximum sink current of 32 mA. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, preventing off off damagingcurrentbackflowthroughthedevicewhenitispowereddown. 8.2 Functional Block Diagram 1 6 1A 1Y 3 4 2A 2Y 8.3 Feature Description The open-drain configuration means that the device cannot provide its own output drive current; instead, it relies on pullup resistors to provide the "high" bus state. It can only drive the bus low. In the "Hi-Z" state, the SN74LVC2G07 acts as an open circuit and allows the external pullup to pull the bus high. Therefore, the pullup voltagedeterminestheoutputlevelandthereforetheSN74LVC2g07canbeusedforupordown-translation.The devicecansink24mAat3Vwhileretaininganoutputvoltage(V )of0.55Vorlower. OL 8.4 Device Functional Modes Table1showsthedevicefunctionalmodesoftheSN74LVC2G07device. Table1.FunctionTable INPUT OUTPUT A Y L L H H 8 SubmitDocumentationFeedback Copyright©2001–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 www.ti.com SCES308L–AUGUST2001–REVISEDMAY2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LVC2G07 is a high-drive CMOS device that can be used to implement a high output drive buffer, such as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high-drive and wired-OR/AND functions.Theinputsare5.5VtolerantallowingittotranslateupanddowntoV . CC 9.2 Typical Application VCC 0.1 (cid:29)F 1A 1Y From MCU 2A 2Y GND Figure3. TypicalApplication 9.2.1 DesignRequirements 1. RecommendedInputConditions – Risetimeandfalltimespecs.See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels.See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputs are overvoltage tolerant allowing them to go as high as (V max) in the Recommended Operating I ConditionstableatanyvalidV . CC 2. RecommendOutputConditions – Load currents should not exceed (I max) per output and should not exceed (Continuous current through O V orGND)totalcurrentforthepart.TheselimitsarelocatedintheAbsoluteMaximumRatings table. CC – Outputsshouldnotbepulledabove5.5V. 9.2.2 DetailedDesignProcedure ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads soroutingandloadconditionsshouldbeconsideredtopreventringing. Copyright©2001–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 SCES308L–AUGUST2001–REVISEDMAY2015 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve 6 TPD 5 4 s n D - 3 P T 2 1 0 0 1 2 3 4 5 6 Vcc - V D002 Figure4.TPDAcrossV at25°C CC 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply a 0.1-μF capacitor is recommended and if there are multiple V pins then a 0.01-μF or 0.022-μF CC capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installedasclosetothepowerpinaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more CC convenient. 11.2 Layout Examples VCC Input Unused Input Output Unused Input Output Input Figure5. LayoutExamplesforSN74LVC2G07 10 SubmitDocumentationFeedback Copyright©2001–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2G07
SN74LVC2G07 www.ti.com SCES308L–AUGUST2001–REVISEDMAY2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs,SCBA004. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks NanoFree,E2EaretrademarksofTexasInstruments. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2001–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC2G07
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC2G07DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C075, C07F, C07K, & no Sb/Br) C07R) SN74LVC2G07DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C07F, C07R) & no Sb/Br) SN74LVC2G07DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV & no Sb/Br) K, CVR) SN74LVC2G07DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 & no Sb/Br) SN74LVC2G07DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 & no Sb/Br) SN74LVC2G07DCKT ACTIVE SC70 DCK 6 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV & no Sb/Br) K, CVR) SN74LVC2G07DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 & no Sb/Br) SN74LVC2G07DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CV & no Sb/Br) SN74LVC2G07DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CV & no Sb/Br) SN74LVC2G07YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 125 (CV7, CVN) & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC2G07 : •Enhanced Product: SN74LVC2G07-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC2G07DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC2G07DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC2G07DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC2G07DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC2G07DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC2G07DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC2G07DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74LVC2G07DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC2G07DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74LVC2G07DCKTG4 SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC2G07DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC2G07DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC2G07YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC2G07DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC2G07DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC2G07DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC2G07DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC2G07DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC2G07DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC2G07DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74LVC2G07DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC2G07DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74LVC2G07DCKTG4 SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC2G07DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74LVC2G07DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74LVC2G07YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 PackMaterials-Page2
GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G
PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com
EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com
EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com
PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com
EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com
EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com
EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com
PACKAGE OUTLINE YZP0006 DSBGA - 0.5 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.5 MAX C SEATING PLANE 0.19 BALL TYP 0.05 C 0.15 0.5 TYP C SYMM 1 D: Max = 1.418 mm, Min =1 .357 mm B TYP 0.5 E: Max = 0.918 mm, Min =0 .857 mm TYP A 0.25 1 2 6X 0.21 SYMM 0.015 C A B 4219524/A 06/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFreeTM package configuration. www.ti.com
EXAMPLE BOARD LAYOUT YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.225) 1 2 A (0.5) TYP B SYMM C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.225) 0.05 MAX 0.05 MIN METAL METAL UNDER MASK SOLDER MASK ( 0.225) OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219524/A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com
EXAMPLE STENCIL DESIGN YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219524/A 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com
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