Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 SN74LVC245A Octal Bus Transceiver With 3-State Outputs 1 Features 2 Applications • OperatesFrom1.65Vto3.6V • CableModemTerminationSystems 1 • InputsAcceptVoltagesto5.5V • Servers • Maxt of6.3nsat3.3V • LEDDisplays pd • TypicalV (OutputGroundBounce) • NetworkSwitches OLP <0.8VatVCC=3.3V,TA=25°C • TelecomInfrastructure • TypicalVOHV(OutputVOH Undershoot) • MotorDrivers >2VatV =3.3V,T =25°C CC A • I/OExpanders • I SupportsLiveInsertion,Partial-Power-Down off ModeandBackDriveprotection 3 Description • SupportsMixed-ModeSignalOperationonAll These octal bus transceivers are designed for 1.65-V Ports(5-VInput/OutputVoltageWith3.3-VV ) to 3.6-V V operation. The ’LVC245A devices are CC CC designed for asynchronous communication between • Latch-UpPerformanceExceeds250mA databuses. PerJESD17 • ESDProtectionExceedsJESD22 DeviceInformation(1) – 2000-VHuman-BodyModel PARTNUMBER PACKAGE(PIN) BODYSIZE – 1000-VCharged-DeviceModel VQFN(20) 4.50mm×3.50mm SSOP(20) 7.50mm×5.30mm SN74LVC245A TSSOP(20) 6.50mm×4.40mm TVSOP(20) 5.00mm×4.40mm SOIC(20) 12.80mm×7.50mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic 1 DIR 19 OE 2 A1 18 B1 To Seven Other Channels PinnumbersshownarefortheDB,DGV,DW,N,NS,PW,andRGYpackages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9.1 Overview...................................................................9 2 Applications........................................................... 1 9.2 FunctionalBlockDiagram.........................................9 3 Description............................................................. 1 9.3 FeatureDescription...................................................9 9.4 DeviceFunctionalModes..........................................9 4 SimplifiedSchematic............................................. 1 10 ApplicationandImplementation........................ 10 5 RevisionHistory..................................................... 2 10.1 ApplicationInformation..........................................10 6 PinConfigurationandFunctions......................... 3 10.2 TypicalApplication ...............................................10 7 Specifications......................................................... 4 11 PowerSupplyRecommendations..................... 11 7.1 AbsoluteMaximumRatings......................................4 12 Layout................................................................... 11 7.2 ESDRatings..............................................................4 12.1 LayoutGuidelines.................................................11 7.3 RecommendedOperatingConditions.......................5 12.2 LayoutExample....................................................11 7.4 ThermalInformation..................................................5 13 DeviceandDocumentationSupport................. 12 7.5 ElectricalCharacteristics...........................................6 7.6 SwitchingCharacteristics..........................................6 13.1 Trademarks...........................................................12 7.7 OperatingCharacteristics..........................................7 13.2 ElectrostaticDischargeCaution............................12 7.8 TypicalCharacteristics..............................................7 13.3 Glossary................................................................12 8 ParameterMeasurementInformation..................8 14 Mechanical,Packaging,andOrderable Information........................................................... 12 9 DetailedDescription.............................................. 9 5 Revision History ChangesfromRevisionW(May2013)toRevisionX Page • AddedApplications,DeviceInformationtable,PinFunctionstable,ESDRatingstable,ThermalInformationtable, TypicalCharacteristics,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 ChangesfromRevisionV(September2010)toRevisionW Page • Added–40°Cto125°CtemperaturespecificationtoRecommendedOperatingConditionstable. ...................................... 5 2 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

SN74LVC245A www.ti.com SCAS218X–JANUARY1993–REVISEDJANUARY2015 6 Pin Configuration and Functions GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 4 A B C D E DB, DGV, DW, N, NS, OR PW PACKAGE RGYPACKAGE (TOPVIEW) (TOPVIEW) DIR 1 20 VCC DIR VCC A1 2 19 OE 1 20 A2 3 18 B1 A1 2 19 OE A3 4 17 B2 A2 3 18 B1 A4 5 16 B3 A3 4 17 B2 A5 6 15 B4 A4 5 16 B3 A6 7 14 B5 A5 6 15 B4 A7 8 13 B6 A6 7 14 B5 A8 9 12 B7 A7 8 13 B6 GND 10 11 B8 A8 9 12 B7 10 11 D 8 N B G PinFunctions PIN DB,DGV, TYPE DESCRIPTION NAME DW,NS,PW, GQNorZQN andRGY A1 2 A1 I/O TransceiverI/Opin A2 3 B3 I/O TransceiverI/Opin A3 4 B1 I/O TransceiverI/Opin A4 5 C2 I/O TransceiverI/Opin A5 6 C1 I/O TransceiverI/Opin A6 7 D3 I/O TransceiverI/Opin A7 8 D1 I/O TransceiverI/Opin A8 9 E2 I/O TransceiverI/Opin B1 18 B4 I/O TransceiverI/Opin B2 17 B2 I/O TransceiverI/Opin B3 16 C4 I/O TransceiverI/Opin B4 15 C3 I/O TransceiverI/Opin B5 14 D4 I/O TransceiverI/Opin B6 13 D2 I/O TransceiverI/Opin B7 12 E4 I/O TransceiverI/Opin B8 11 E3 I/O TransceiverI/Opin Directioncontrol.Whenhigh,thesignalpropagatesfromAtoB.Whenlow,thesignal DIR 1 A2 I propagatesfromBtoA. OE 19 A4 I Outputenable GND 10 E1 — Ground VCC 20 A3 — Powerpin Copyright©1993–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC245A

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Storagetemperaturerange –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 7.2 ESD Ratings PARAMETER DEFINITION VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) 2000 Electrostatic V(ESD) discharge Cpihnasr(g2)eddevicemodel(CDM),perJEDECspecificationJESD22-C101,all 1000 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

SN74LVC245A www.ti.com SCAS218X–JANUARY1993–REVISEDJANUARY2015 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) T =25°C –40°CTO85°C –40°CTO125°C A UNIT MIN MAX MIN MAX MIN MAX Operating 1.65 3.6 1.65 3.6 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 1.5 1.5 V =1.65Vto1.95V 0.65×V 0.65×V 0.65×V CC CC CC CC High-levelinput V V =2.3Vto2.7V 1.7 1.7 1.7 V IH voltage CC V =2.7Vto3.6V 2 2 2 CC 0.35× 0.35× V =1.65Vto1.95V 0.35×V CC CC V V Low-levelinput CC CC V V IL voltage V =2.3Vto2.7V 0.7 0.7 0.7 CC V =2.7Vto3.6V 0.8 0.8 0.8 CC V Inputvoltage 0 5.5 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V 0 V V O CC CC CC V =1.65V –4 –4 –4 CC High-leveloutput VCC=2.3V –8 –8 –8 I mA OH current V =2.7V –12 –12 –12 CC V =3V –24 –24 –24 CC V =1.65V 4 4 4 CC Low-leveloutput VCC=2.3V 8 8 8 I mA OL current V =2.7V 12 12 12 CC V =3V 24 24 24 CC Δt/Δv Inputtransitionriseorfallrate 10 10 10 ns/V (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 7.4 Thermal Information SN74LVC245A THERMALMETRIC(1) DB(2) DGV(2) DW(2) GZQQNN(o2)r N(2) NS(2) PW(2) RGY(3) UTNI 20PINS Junction-to-ambientthermal RθJA resistance 106.5 124.1 92.9 78 59.2 83.6 108.1 44.0 RθJC(t Junction-to-case(top)thermal 68.1 39.5 60.6 44.9 49.4 43.0 53.0 op) resistance Junction-to-boardthermal RθJB resistance 61.7 65.5 60.4 40.1 51.2 59.1 22.1 °C/ Junction-to-topcharacterization W ψJT parameter 28.5 2.1 28.2 29.9 21.9 4.7 3.0 Junction-to-board ψJB characterizationparameter 61.2 64.9 60.0 39.9 50.8 58.6 22.2 RθJC(b Junction-to-case(bottom) — — — — — — 16.6 ot) thermalresistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. Copyright©1993–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC245A

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) T =25°C –40°CTO85°C –40°CTO125°C A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MAX MIN MAX MIN MAX 1.65V I =–100μA to V –0.2 V –0.2 V –0.2 OH CC CC CC 3.6V I =–4mA 1.65V 1.29 1.2 1.1 OH VOH IOH=–8mA 2.3V 1.9 1.7 1.6 V 2.7V 2.2 2.2 2.1 I =–12mA OH 3V 2.4 2.4 2.3 I =–24mA 3V 2.3 2.2 2.1 OH 1.65V I =100μA to 0.1 0.2 0.2 OL 3.6V I =4mA 1.65V 0.24 0.45 0.60 V OL V OL I =8mA 2.3V 0.3 0.7 0.75 OL I =12mA 2.7V 0.4 0.4 0.6 OL I =24mA 3V 0.55 0.55 0.75 OL Control I V =0to5.5V 3.6V ±1 ±5 ±10 μA I inputs I I V orV =5.5V 0 ±1 ±10 ±20 μA off I O I (1) V =0to5.5V 3.6V ±1 ±10 ±20 μA OZ O V =V orGND 1 10 30 I CC I I =0 3.6V μA CC 3.6V≤V ≤5.5V(2) O 1 10 30 I OneinputatV –0.6V, 2.7Vto ΔI CC 500 500 5000 μA CC OtherinputsatV orGND 3.6V CC Control C V =V orGND 3.3V 4 pF i inputs I CC AorB Cio ports(3) VI=VCCorGND 3.3V 5.5 pF (1) AlltypicalvaluesareatV =3.3V,T =25C. CC A (2) Thisappliesinthedisabledstateonly. (3) ForI/Oports,theparameterI includestheinputleakagecurrent. oz 7.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) –40°CTO –40°CTO PARAMETER FROM TO V TA=25°C 85°C 125°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX MIN MAX 1.8V±0.15V 1 6 12.2 1 12.7 1 13.7 2.5V±0.2V 1 3.9 7.8 1 8.3 1 9.1 t AorB BorA ns pd 2.7V 1 4.2 7.1 1 7.3 1 8.3 3.3V±0.3V 1.5 3.8 6.1 1.5 6.3 1.5 7.3 1.8V±0.15V 1 7 14.8 1 15.3 1 16.8 2.5V±0.2V 1 4.5 10 1 10.5 1 12 t OE AorB ns en 2.7V 1 5.4 9.3 1 9.5 1 11 3.3V±0.3V 1.5 4.4 8.3 1.5 8.5 1.5 10 1.8V±0.15V 1 7.8 16.5 1 17 1 18 2.5V±0.2V 1 4 9 1 9.5 1 10.5 t OE AorB ns dis 2.7V 1 4.4 8.3 1 8.5 1 9.5 3.3V±0.3V 1.7 4.1 7.3 1.7 7.5 1.7 8.5 t 3.3V±0.3V 1 1.5 ns sk(o) 6 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

SN74LVC245A www.ti.com SCAS218X–JANUARY1993–REVISEDJANUARY2015 7.7 Operating Characteristics T =25°C A TEST PARAMETER V TYP UNIT CONDITIONS CC 1.8V 42 Outputsenabled 2.5V 43 3.3V 45 C Powerdissipationcapacitancepertransceiver f=10MHz pF pd 1.8V 1 Outputsdisabled 2.5V 1 3.3V 2 7.8 Typical Characteristics 14 10 VCC=3V, VCC=3V, TA=25°C TA=25°C 12 s –ns OFonuerOOuuttppuuttSswSiwtcithcihnigng e–n 8 OFonuerOOuuttppuuttSswSiwtcithcihnigng Time 10 EightOutputsSwitching yTim EightOutputsSwitching y a ela Del D 8 n 6 n o atio gati g a a 6 p p o o r Pr –P 4 – d d 4 p p t t 2 2 0 50 100 150 200 250 300 0 50 100 150 200 250 300 CL–LoadCapacitance–pF CL–LoadCapacitance–pF Figure1.PropagationDelay(LowtoHighTransition) Figure2.PropagationDelay(HightoLowTransition) vsLoadCapacitance vsLoadCapacitance Copyright©1993–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC245A

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see NoteCAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL V∆ 1.8 V±0.15 V VCC ≤2ns VCC/2 2×VCC 30 pF 1 kΩ 0.15 V 2.5 V±0.2 V VCC ≤2ns VCC/2 2×VCC 30 pF 500Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V 3.3 V±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500Ω 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1ee a tN VoLteO ABD) VM VOL+ V∆ VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOftou GrtmpNu D2t VM VOH- V∆ VOH VOL (see Note B) ≈0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-ANDHIGH-LEVELENABLING NOTES: A. CLincludes probe and jig capacitance. B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol. Waveform2is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZand tPHZare the same as tdis. F. tPZLand tPZHare the same as ten. G. tPLHand tPHLare the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

SN74LVC245A www.ti.com SCAS218X–JANUARY1993–REVISEDJANUARY2015 9 Detailed Description 9.1 Overview Thisoctalbustransceiverisdesignedfor1.65-Vto3.6-VV operation. CC The SN74LVC245A device is designed for asynchronous communication between data buses. This device transmitsdatafromtheAbustotheBbusorfromtheBbustotheAbus,dependingonthelogiclevelatthe direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectivelyareisolated. To ensure the high-impedance state during power up or power down, OE should be tied to V through a CC pull-upresistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translatorinamixed3.3-V/5-Vsystemenvironment. This device is fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs,preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. 9.2 Functional Block Diagram 1 DIR 19 OE 2 A1 18 B1 To Seven Other Channels PinnumbersshownarefortheDB,DGV,DW,N,NS,PW,andRGYpackages. 9.3 Feature Description • Allowsdownvoltagetranslation – 5Vto3.3V – 5Vor3.3Vto1.8V • Inputsacceptvoltagelevelsupto5.5V 9.4 Device Functional Modes Table1.FunctionTable INPUTS OPERATION OE DIR L L BdatatoAbus L H AdatatoBbus H X Isolation Copyright©1993–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC245A

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information SN74LVC245A is a high drive CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid V CC makingitidealfordowntranslation. 10.2 Typical Application Regulated1.8V Regulated1.65Vto3.6V Regulated5V SN74LVC245A SN74LVC245A V V 1OE CC 1OE CC DIR DIR A1 B1 A1 B1 uC uC uC SystemLogic uC SystemLogic or LEDs/Relays SystemLogic LEDs/Relays A8 B8 LEDs/Relays A8 B8 OtherSystem Boards GND GND Figure4. TypicalApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloadssoroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Forrisetimeandfalltimespecifcations,see(Δt/ΔV)intheRecommendedOperatingConditions table. – Forspecifiedhighandlowlevels,see(V andV )intheRecommendedOperatingConditions table. IH IL – Inputs are overvoltage tolerant allowing them to go as high as (V max) in the Recommended Operating I ConditionstableatanyvalidV . CC 2. RecommendOutputConditions – Load currents should not exceed (I max) per output and should not exceed (Continuous current through O V orGND)totalcurrentforthepart.TheselimitsarelocatedintheAbsoluteMaximumRatings table. CC – OutputsshouldnotbepulledaboveV . CC 10 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

SN74LVC245A www.ti.com SCAS218X–JANUARY1993–REVISEDJANUARY2015 Typical Application (continued) 10.2.3 ApplicationCurves 100 60 TA=25°C,VCC=3V, TA=25°C,VCC=3V, VIH=3V,VIL=0V, 40 VIH=3V,VIL=0V, 80 AllOutputsSwitching AllOutputsSwitching 20 60 0 A A m m – 40 – –20 OL OH I I –40 20 –60 0 –80 –20 –100 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOL–V VOH–V Figure5.OutputDriveCurrent(I ) Figure6.OutputDriveCurrent(I ) OL OH vsLOW-levelOutputVoltage(V ) vsHIGH-levelOutputVoltage(V ) OL OH 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, a 0.1 μF capacitor is recommended. If there are multiple V terminals then 0.01 μF or 0.022 μF CC capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise.Thebypasscapacitorshouldbeinstalledasclosetothepowerterminalaspossibleforthebestresults. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND orV ,whichevermakesmoresenseorismoreconvenient. CC 12.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure7. LayoutDiagram Copyright©1993–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC245A

SN74LVC245A SCAS218X–JANUARY1993–REVISEDJANUARY2015 www.ti.com 13 Device and Documentation Support 13.1 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronymsanddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 12 SubmitDocumentationFeedback Copyright©1993–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC245A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC245ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A & no Sb/Br) SN74LVC245ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A & no Sb/Br) SN74LVC245ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A & no Sb/Br) SN74LVC245AN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74LVC245AN (RoHS) SN74LVC245ANE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 SN74LVC245AN (RoHS) SN74LVC245ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A & no Sb/Br) SN74LVC245APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWRG3 ACTIVE TSSOP PW 20 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC245APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A & no Sb/Br) SN74LVC245ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LC245A & no Sb/Br) SN74LVC245AZQNR LIFEBUY BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 125 LC245A MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF SN74LVC245A : •Enhanced Product: SN74LVC245A-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC245ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVC245ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC245ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVC245ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVC245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC245APWRG3 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC245APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVC245APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVC245ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN74LVC245AZQNR BGAMI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC245ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC245ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC245ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC245ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC245APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC245APWRG3 TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC245APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVC245APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LVC245ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 SN74LVC245AZQNR BGAMICROSTAR ZQN 20 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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