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ICGOO电子元器件商城为您提供SN74LVC2244ADBQR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 提供SN74LVC2244ADBQR价格参考¥1.43-¥4.10以及Texas InstrumentsSN74LVC2244ADBQR封装/规格参数等产品信息。 你可以下载SN74LVC2244ADBQR参考资料、Datasheet数据手册功能说明书, 资料中有SN74LVC2244ADBQR详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC BUFF/DVR TRI-ST DUAL 20QSOP缓冲器和线路驱动器 Octal Buffer/Driver With 3-State Outputs |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,缓冲器和线路驱动器,Texas Instruments SN74LVC2244ADBQR74LVC |
数据手册 | |
产品型号 | SN74LVC2244ADBQR |
产品目录页面 | |
产品种类 | 缓冲器和线路驱动器 |
传播延迟时间 | 6.4 ns at 2.7 V, 5.5 ns at 3.3 V |
低电平输出电流 | 12 mA |
供应商器件封装 | 20-SSOP/QSOP |
元件数 | 2 |
其它名称 | 296-23275-1 |
包装 | 剪切带 (CT) |
单位重量 | 125.800 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | 20-SSOP(0.154",3.90mm 宽) |
封装/箱体 | SSOP-20 |
工作温度 | -40°C ~ 85°C |
工厂包装数量 | 2500 |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
极性 | Non-Inverting |
标准包装 | 1 |
每元件位数 | 4 |
每芯片的通道数量 | 8 |
电压-电源 | 1.65 V ~ 3.6 V |
电流-输出高,低 | 12mA,12mA |
电源电压-最大 | 3.6 V |
电源电压-最小 | 1.65 V |
电源电流 | 0.01 mA |
系列 | SN74LVC2244A |
输入线路数量 | 8 |
输出类型 | 3-State |
输出线路数量 | 3 |
逻辑类型 | 缓冲器/线路驱动器,非反相 |
逻辑系列 | LVC |
高电平输出电流 | - 12 mA |
Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 SN74LVC2244A Octal Buffer/Driver With 3-State Outputs 1 Features 2 Applications • OperatesFrom1.65Vto3.6V • WearableHealthandFitnessDevices 1 • InputsAcceptVoltagesto5.5V • NetworkSwitches • Maxt of5.5nsat3.3V • Servers pd • OutputPortsHaveEquivalent26-Ω Series • TestsandMeasurements Resistors,SoNoExternalResistorsAreRequired 3 Description • TypicalV (OutputGroundBounce) OLP <0.8VatV =3.3V,T =25°C The SN74LVC2244A octal buffer/line driver is CC A designedfor1.65-Vto3.6-VV operation. • TypicalV (OutputV Undershoot) CC OHV OH >2VatV =3.3V,T =25°C CC A DeviceInformation(1) • SupportsMixed-ModeSignalOperationonAll PARTNUMBER PACKAGE BODYSIZE(NOM) Ports(5-VInput/OutputVoltage SSOP(20) 7.20mm×5.30mm With3.3-VV ) CC SSOP(20) 8.65mm×3.90mm • I SupportsLiveInsertion,Partial-Power-Down off SN74LVC2244A TVSOP(20) 5.00mm×4.40mm Mode,andBack-DriveProtection SOIC(20) 12.80mm×7.50mm • Latch-UpPerformanceExceeds250mAPer TSSOP(20) 6.50mm×4.40mm JESD17 • ESDProtectionExceedsJESD22 (1) For all available packages, see the orderable addendum at theendofthedatasheet. – 2000-VHuman-BodyModel(A114-A) – 200-VMachineModel(A115-A) – 1000-VCharged-DeviceModel(C101) 4 Simplified Schematic 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription.............................................. 9 2 Applications........................................................... 1 9.1 Overview...................................................................9 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.........................................9 4 SimplifiedSchematic............................................. 1 9.3 FeatureDescription...................................................9 9.4 DeviceFunctionalModes..........................................9 5 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 10 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................10 7 Specifications......................................................... 4 10.2 TypicalApplication ...............................................10 7.1 AbsoluteMaximumRatings .....................................4 11 PowerSupplyRecommendations..................... 11 7.2 HandlingRatings.......................................................4 12 Layout................................................................... 11 7.3 RecommendedOperatingConditions......................5 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................11 7.5 ElectricalCharacteristics...........................................6 12.2 LayoutExample....................................................11 7.6 SwitchingCharacteristics,–40°Cto85°C.................6 13 DeviceandDocumentationSupport................. 12 7.7 SwitchingCharacteristics,–40°Cto125°C...............6 13.1 Trademarks...........................................................12 7.8 OperatingCharacteristics..........................................7 13.2 ElectrostaticDischargeCaution............................12 7.9 TypicalCharacteristics..............................................7 13.3 Glossary................................................................12 8 ParameterMeasurementInformation..................8 14 Mechanical,Packaging,andOrderable Information........................................................... 12 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionK(March2005)toRevisionL Page • UpdateddocumenttonewTIdatasheetstandards.............................................................................................................. 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • ChangedI bulletinFeatureslist.......................................................................................................................................... 1 off • AddedApplications................................................................................................................................................................. 1 • AddedPinFunctionstable...................................................................................................................................................... 3 • AddedHandlingRatingstable................................................................................................................................................ 4 • ChangedMAXambienttemperatureto125°CinRecommendedOperatingConditions. .................................................... 5 • AddedThermalInformationtable........................................................................................................................................... 5 • Added–40°Cto125°CtemperaturerangeinElectricalCharacteristicstable....................................................................... 6 • AddeddatatoSwitchingCharacteristics,–40°Cto85°C....................................................................................................... 6 • AddedSwitchingCharacteristicstable,–40°Cto125°C. ...................................................................................................... 6 • ChangedOperatingCharacteristicstable............................................................................................................................... 7 • AddedTypicalCharacteristics................................................................................................................................................ 7 • AddedDetailedDescriptionsection........................................................................................................................................ 9 • AddedApplicationandImplementationsection.................................................................................................................... 10 2 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
SN74LVC2244A www.ti.com SCAS572L–APRIL1996–REVISEDJULY2014 6 Pin Configuration and Functions DB, DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 1OE 1 20 VCC 1A1 2 19 2OE 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1 PinFunctions PIN I/O DESCRIPTION NO. NAME 1 1OE I OutputEnable1 2 1A1 I 1A1Input 3 2Y4 O 2Y4Output 4 1A2 I 1A2Input 5 2Y3 O 2Y3Output 6 1A3 I 1A3Input 7 2Y2 O 2Y2Output 8 1A4 I 1A4Input 9 2Y1 O 2Y1Output 10 GND — GroundPin 11 2A1 I 2A1Input 12 1Y4 O 1Y4Output 13 2A2 I 2A2Input 14 1Y3 O 1Y3Output 15 2A3 I 2A3Input 16 1Y2 O 1Y2Output 17 2A4 I 2A4Input 18 1Y1 O 1Y1Output 19 2OE I OutputEnable2 20 VCC — PowerPin Copyright©1996–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC2244A
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2) (3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
SN74LVC2244A www.ti.com SCAS572L–APRIL1996–REVISEDJULY2014 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 CC V =1.65Vto1.95V 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 CC V Inputvoltage 0 5.5 V I Highorlowstate 0 V CC V Outputvoltage V O 3-state 0 5.5 V =1.65V –2 CC V =2.3V –4 CC I High-leveloutputcurrent mA OH V =2.7V –8 CC V =3V –12 CC V =1.65V 2 CC V =2.3V 4 CC I Low-leveloutputcurrent mA OL V =2.7V 8 CC V =3V 12 CC Δt/Δv Inputtransitionriseorfallrate 10 ns/V T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). 7.4 Thermal Information SN74LVC2244A THERMALMETRIC(1) DB DBQ DGV DW NS PW UNIT 20PINS R Junction-to-ambientthermalresistance 94.5 94.7 114.7 88.3 74.7 102.5 θJA R Junction-to-case(top)thermalresistance 56.2 47.9 29.8 51.1 40.5 35.9 θJC(top) R Junction-to-boardthermalresistance 49.7 45.0 56.2 50.9 42.3 53.5 θJB ψJT Junction-to-topcharacterizationparameter 18.1 11.0 0.8 20.0 14.3 2.2 °C/W Junction-to-boardcharacterization ψ 49.5 44.6 55.5 50.5 41.9 52.9 JB parameter Junction-to-case(bottom)thermal R n/a n/a n/a n/a n/a n/a θJC(bot) resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport(SPRA953). Copyright©1996–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC2244A
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto85°C –40°Cto125°C PARAMETER TESTCONDITIONS V UNIT CC MIN TYP(1) MAX MIN TYP(1) MAX 1.65Vto I =–100μA V –0.2 V –0.2 OH 3.6V CC CC I =–2mA 1.65V 1.2 1.2 OH 2.3V 1.7 1.7 VOH IOH=–4mA 2.7V 2.2 2.2 V I =–6mA 3V 2.4 2.4 OH I =–8mA 2.7V 2 2 OH I =–12mA 3V 2 2 OH 1.65Vto I =100μA 0.2 0.2 OL 3.6V I =2mA 1.65V 0.45 0.45 OL 2.3V 0.7 0.7 VOL IOL=4mA 2.7V 0.4 0.4 V I =6mA 3V 0.55 0.55 OL I =8mA 2.7V 0.6 0.6 OL I =12mA 3V 0.8 0.8 OL I V =0to5.5V 3.6V ±5 ±5 μA I I I V orV =5.5V 0 ±10 ±10 μA off I O I V =0to5.5V 3.6V ±10 ±10 μA OZ O V =V orGND 10 10 I CC I I =0 3.6V μA CC 3.6V≤V ≤5.5V(2) O 10 10 I OneinputatV –0.6V,Other 2.7Vto ΔI CC 500 500 μA CC inputsatV orGND 3.6V CC C V =V orGND 3.3V 4 4 pF i I CC C V =V orGND 3.3V 5.5 5.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A (2) Thisappliesinthedisabledstateonly. 7.6 Switching Characteristics, –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C±C0.15V C±C0.2V VCC=2.7V C±C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t A Y 10.9 7.9 6.4 1.5 5.5 ns pd t OE Y 12.6 9.6 8.1 1 7.1 ns en t OE Y 12.1 7.8 7.3 1.5 6.8 ns dis 7.7 Switching Characteristics, –40°C to 125°C overoperatingfree-airtemperaturerange(unlessotherwisenoted) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C±C0.15V C±C0.2V VCC=2.7V C±C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t A Y 12.4 10 7.1 1.5 6.5 ns pd t OE Y 14.1 11.7 8.5 1 7.8 ns en t OE Y 13.6 9.9 7.8 1.5 7.6 ns dis 6 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
SN74LVC2244A www.ti.com SCAS572L–APRIL1996–REVISEDJULY2014 7.8 Operating Characteristics T =25°C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipationcapacitance Outputsenabled 43 43 46 C f=10MHz pF pd perbuffer/driver Outputsdisabled 1 1 2 7.9 Typical Characteristics 4 6 TDP in ns 3.5 5 3 4 2.5 s) s) n n D ( 2 P ( 3 P D T T 1.5 2 1 1 0.5 TPD in ns 0 0 -100 -50 0 50 100 150 0 0.5 1 1.5 2 2.5 3 3.5 Temperature (qC) D001 VCC (V) D002 Figure1.SN74LVC2244ATPDAcrossTemperatureat3.3V Figure2.SN74LVC2244ATDPAcrossV at25°C CC Copyright©1996–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC2244A
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
SN74LVC2244A www.ti.com SCAS572L–APRIL1996–REVISEDJULY2014 9 Detailed Description 9.1 Overview This octal buffer and line driver is designed for 1.65-V to 3.6-V V operation. The SN74LVC2244A device is CC organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 26-ohm resistors to reduce overshoot and undershoot. 9.2 Functional Block Diagram 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto3.6V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • I Feature off – AllowsvoltagesontheinputsandoutputswhenV is0V CC 9.4 Device Functional Modes Table1.FunctionTable (EachBuffer) INPUTS OUTPUT OE A Y L H H L L L H X Z Copyright©1996–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC2244A
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com 10 Application and Implementation 10.1 Application Information Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, preventing damaging current backflow through the device when it is off off powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 10.2 Typical Application Regulated 3.3 V OE VCC A1 Y1 µC System Logic µC or A4 Y4 LEDs System Logic GND Figure4. TypicalApplicationDiagram 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads,soroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendOutputConditions – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC 10 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
SN74LVC2244A www.ti.com SCAS572L–APRIL1996–REVISEDJULY2014 Typical Application (continued) 10.2.3 ApplicationCurves 300 250 200 A) m (C 150 C I 100 50 ICC 1.8 V ICC 2.5 V ICC 3.3 V 0 0 10 20 30 40 50 60 Frequency (MHz) D003 Figure5.I vsFrequency CC 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μf is recommended; if there are multiple V pins, then 0.01 μf or 0.022 μf is recommended for each CC power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiple-bitlogicdevices,inputsshouldneverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float outputs, CC unlessthepartisatransceiver.Ifthetransceiverhasanoutputenablepin,itwilldisabletheoutputsectionofthe partwhenasserted.ThiswillnotdisabletheinputsectionoftheIOs,sotheycannotfloatwhendisabled. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram Copyright©1996–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC2244A
SN74LVC2244A SCAS572L–APRIL1996–REVISEDJULY2014 www.ti.com 13 Device and Documentation Support 13.1 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 12 SubmitDocumentationFeedback Copyright©1996–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC2244A
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC2244ADBQR ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ADBQRE4 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A & no Sb/Br) SN74LVC2244APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) SN74LVC2244APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A & no Sb/Br) Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC2244ADBQR SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC2244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVC2244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC2244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LVC2244ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LVC2244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LVC2244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC2244ADBQR SSOP DBQ 20 2500 367.0 367.0 38.0 SN74LVC2244ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC2244ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC2244ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC2244ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC2244APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVC2244APWT TSSOP PW 20 250 367.0 367.0 38.0 PackMaterials-Page2
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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com
EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com
EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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