Product Order Technical Tools & Support & Folder Now Documents Software Community SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 SN74LVC1GU04 Single Inverter Gate 1 Features 3 Description • AvailableintheTexasInstruments This single inverter gate is designed for 1.65-V to 1 5.5-VV operation. NanoFree™Package CC • Supports5-VV Operation The SN74LVC1GU04 device contains one inverter CC with an unbuffered output and performs the Boolean • InputsAcceptVoltagesto5.5V functionY= A. • UnbufferedOutput NanoFree package technology is a major • Maximumt of3.7nsat3.3V pd breakthroughindevicepackagingconcepts,usingthe • LowPowerConsumption,10-μAMaximumICC dieasthepackage. • ±24-mAOutputDriveat3.3V DeviceInformation(1) • I SupportsLiveInsertion,Partial-Power-Down off Mode,andBack-DriveProtection PARTNUMBER PACKAGE BODYSIZE(NOM) • Latch-UpPerformanceExceeds100mAPer SN74LVC1GU04DBV SOT-23(5) 2.90mm×1.60mm JESD78,ClassII SN74LVC1GU04DCK SC70(5) 2.00mm×1.25mm • ESDProtectionExceedsJESD22 SN74LVC1GU04DRL SOT-5X3(5) 1.60mm×1.20mm – 2000-VHuman-BodyModel(A114-A) SN74LVC1GU04DRY SON(6) 1.45mm×1.00mm SN74LVC1GU04DSF SON(6) 1.00mm×1.00mm – 200-VMachineModel(A115-A) SN74LVC1GU04YZP DSBGA(5) 1.44mm×0.94mm – 1000-VCharged-DeviceModel(C101) SN74LVC1GU04YZV DSBGA(4) 0.91mm×0.91mm 2 Applications SN74LVC1GU04DPW X2SON(5) 0.80mm×0.80mm (1) For all available packages, see the orderable addendum at • AVReceivers theendofthedatasheet. • Blu-rayPlayersandHomeTheaters • DVDRecordersandPlayers LogicDiagram(PositiveLogic) • DesktoporNotebookPCs 2 4 A Y • DigitalRadioorInternetRadioPlayers • DigitalVideoCameras(DVC) • EmbeddedPCs • GPS:PersonalNavigationDevices • MobileInternetDevices • NetworkProjectorFront-Ends • PortableMediaPlayers • ProAudioMixers • SmokeDetectors • Solid-StateDrive(SSD):Enterprise • High-Definition(HDTV) • Tablets:Enterprise • AudioDocks:Portable • DLPFrontProjectionSystems • DVRandDVS • DigitalPictureFrame(DPF) • DigitalStillCameras 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.........................................9 2 Applications........................................................... 1 8.3 FeatureDescription...................................................9 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................10 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 11 9.1 ApplicationInformation............................................11 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplication .................................................11 6 Specifications......................................................... 5 10 PowerSupplyRecommendations..................... 12 6.1 AbsoluteMaximumRatings .....................................5 11 Layout................................................................... 13 6.2 ESDRatings..............................................................5 6.3 RecommendedOperatingConditions......................5 11.1 LayoutGuidelines.................................................13 6.4 ThermalInformation..................................................6 11.2 LayoutExample....................................................13 6.5 ElectricalCharacteristics...........................................6 12 DeviceandDocumentationSupport................. 14 6.6 SwitchingCharacteristics:T =–40°Cto+85°C......7 12.1 DocumentationSupport........................................14 A 6.7 SwitchingCharacteristics:T =–40°Cto+125°C....7 12.2 CommunityResources..........................................14 A 6.8 OperatingCharacteristics..........................................7 12.3 Trademarks...........................................................14 6.9 TypicalCharacteristic................................................7 12.4 ElectrostaticDischargeCaution............................14 7 ParameterMeasurementInformation..................8 12.5 Glossary................................................................14 8 DetailedDescription.............................................. 9 13 Mechanical,Packaging,andOrderable Information........................................................... 14 8.1 Overview...................................................................9 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionX(November2017)toRevisionY Page • Updatedinputvoltageminimumfrom0.5Vto–0.5VinAbsoluteMaximumRatingstable.................................................. 5 ChangesfromRevisionW(January2016)toRevisionX Page • ChangedvaluesintheThermalInformationtabletoalignwithJEDECstandards................................................................ 6 • UpdatedFeatureDescriptiontoincludemoredetailedinformationaboutspecificdevicefeatures...................................... 9 • ChangedTypicalApplicationtooscillatorcircuit.................................................................................................................. 11 • AddedDPWlayoutexample................................................................................................................................................. 13 ChangesfromRevisionV(November2013)toRevisionW Page • AddedApplicationssection,DeviceInformationtable,ESDRatingstable,ThermalInformationtable,Typical Characteristics,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementationsection, PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 ChangesfromRevisionU(June2011)toRevisionV Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • Updatedoperatingfree-airtemperaturerangeinRecommendedOperatingConditionstable.............................................. 5 2 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 5 Pin Configuration and Functions DBVPackage 5-PinSOT-23 DCKPackage TopView 5-PinSC70 TopView N.C. 1 5 VCC N.C. 1 5 VCC A 2 A 2 GND 3 4 Y GND 3 4 Y YZVPackage 4-PinDSBGA DRLPackage TopView 5-PinSOT TopView A V A1 A2 CC N.C. 1 5 VCC GND B1 B2 Y A 2 GGNNDD 3 4 Y DPWPackage 5-PinSON TopView NC V GND CC A Y PinFunctions(1)(2) PIN DBV,DRL, I/O DESCRIPTION NAME YZV DCK,DPW A 2 A1 I Input GND 3 B1 — Ground NC 1 – — Notconnected V 5 A2 — PositiveSupply CC Y 4 B2 O Output (1) NC–Nointernalconnection (2) SeeMechanical,Packaging,andOrderableInformationfordimensions Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com DSFPackage 6-PinSON DRYPackage TopView 6-PinSON N.C. 1 6 VCC TopView GNDA 32 45 YN.C. N.C. 1 6 VCC A 2 5 N.C. GND 3 4 Y YZPPackage 6-PinDSBGA TopView DNU V A1 A2 CC A B1 B2 GND Y C1 C2 DNU–Donotuse PinFunctions(1)(2) PIN I/O DESCRIPTION NAME DSF,DRY YZP A 2 B1 I Input GND 3 C1 — Ground NC 1,5 A1,B2 — Notconnected V 6 A2 — PositiveSupply CC Y 4 C2 O Output (1) NC–Nointernalconnection (2) SeeMechanical,Packaging,andOrderableInformationfordimensions 4 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltage(2) –0.5 6.5 V I V Voltageappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Maximumjunctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedinRecommendedOperatingConditions. CC 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001 ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101 ±1000 6.3 Recommended Operating Conditions See (1). MIN MAX UNIT V Supplyvoltage 1.65 5.5 V CC V High-levelinputvoltage I =–100μA 0.75×V V IH O CC V Low-levelinputvoltage I =100μA 0.25×V V IL O CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent –16 mA OH V =3V CC –24 V =4.5V –32 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.Formoreinformation,seethe CC ImplicationsofSloworFloatingCMOSInputsapplicationreport. Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com 6.4 Thermal Information SN74LVC1GU04 THERMALMETRIC(1) DBV DCK DRL DRY DSF DPW YZV YZP UNIT (SOT-23) (SC70) (SOT-5X3) (SON) (SON) (X2SON) (DSBGA) (DSBGA) 5PINS 5PINS 5PINS 5PINS 5PINS 5PINS 4PINS 5PINS Junction-to-ambient R 231.5 276.1 296.2 369.6 410.3 511 168.2 144.4 °C/W θJA thermalresistance Junction-to-case R (top)thermal 139.4 178.9 137.3 257.6 208.4 241.9 2.1 1.3 °C/W θJC(top) resistance Junction-to-board R 71.1 70.9 145.3 230.8 262.6 374.2 55.9 39.9 °C/W θJB thermalresistance Junction-to-top ψ characterization 45.2 47 14.7 77.2 36 45 1.1 0.5 °C/W JT parameter Junction-to-board ψ characterization 70.7 69.3 145.9 231 262.3 373.3 56.3 39.7 °C/W JB parameter Junction-to-case R (bottom)thermal N/A N/A N/A N/A N/A 168.0 N/A N/A °C/W θJC(bot) resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+125°C(unlessotherwisenoted) A PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT VIL=0V,IOH=–100µA,VCC=1.65Vto5.5V VCC –0.1 VIL=0V,IOH=–4mA,VCC=1.65V 1.2 High-leveloutput VIL=0V,IOH=–8mA,VCC=2.3V 1.9 VOH voltage VIL=0V,IOH=–16mA,VCC=3V 2.4 V VIL=0V,IOH=–24mA,VCC=3V 2.3 VIL=0V,IOH=–32mA,VCC=4.5V 3.8 VIH=VCC,IOL=100µA,VCC=1.65Vto5.5V 0.1 VIH=VCC,IOL=4mA,VCC=1.65V 0.45 Low-leveloutput VIH=VCC,IOL=8mA,VCC=2.3V 0.3 VOL voltage VIH=VCC,IOL=16mA,VCC=3V 0.4 V VIH=VCC,IOL=24mA,VCC=3V 0.55 VIH=VCC,IOL=32mA,VCC=4.5V 0.55 AInput: ±5 II Inputleakagecurrent VI=5.5VorGND,VCC=0Vto5.5V μA ICC Supplycurrent VI=5.5VorGND,IO=0,VCC=1.65Vto5.5V 10 μA CI Inputcapacitance VI=VCCorGND,VCC=3.3V,TA=–40°Cto85°C 7 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A 6 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 6.6 Switching Characteristics: T = –40°C to +85°C A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(SeeFigure2) PARAMETER TESTCONDITIONS MIN MAX UNIT V =1.8V±0.15V 1.3 5 CC V =2.5V±0.2V 1 4 CC t Propagationdelay A-to-Y ns pd V =3.3V±0.3V 1.1 3.7 CC V =5V±0.5V 1 3 CC 6.7 Switching Characteristics: T = –40°C to +125°C A overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(SeeFigure2) PARAMETER TESTCONDITIONS MIN MAX UNIT V =1.8V±0.15V 1.3 5.5 CC V =2.5V±0.2V 1 4.5 CC t Propagationdelay A-to-Y ns pd V =3.3V±0.3V 1.1 4.2 CC V =5V±0.5V 1 3.5 CC 6.8 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT V =1.8V 9 CC V =2.5V 11 CC C Powerdissipationcapacitance f=10MHz pF pd V =3.3V 13 CC V =5V 27 CC 6.9 Typical Characteristic 5 4 tpd(MAX) 3 tpd(ns) 2 tpd(MIN) 1 0 1 2 3 4 5 6 VCC (V) Figure1.t vsV pd CC Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com 7 Parameter Measurement Information V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 30 pF 1 kW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 30 pF 500W 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 50 pF 500W 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 50 pF 500W 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 8 Detailed Description 8.1 Overview TheSN74LVC1GU04devicecontainsoneinverterwithanunbufferedoutputwithamaximumsinkcurrentof 32mA. 8.2 Functional Block Diagram 2 4 A Y Figure3. LogicDiagram(PositiveLogic) 8.3 Feature Description 8.3.1 BalancedHigh-DriveCMOSPush-PullOutputs A balanced output allows the device to sink and source similar currents. The high-drive capability of this device creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followedatalltimes. 8.3.2 StandardCMOSInputs Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst-case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the ElectricalCharacteristics,usingohm'slaw(R=V ÷ I). Signals that are applied to the inputs need to have fast edge rates, as shown by Δt/Δv in the Recommended Operating Conditions, to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOSinput. 8.3.3 NegativeClampingDiodes TheinputsandoutputstothisdevicehavenegativeclampingdiodesasshowninFigure4. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings maybeexceedediftheinputandoutputclamp-currentratingsareobserved. Device VCC Input Logic Output -IIK -IOK GND Figure4. ElectricalPlacementofClampingDiodesforEachInputandOutput Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com Feature Description (continued) 8.3.4 PartialPowerDown(I ) off The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by I in the Electrical off Characteristics. 8.3.5 Over-voltageTolerantInputs Input signals to this device can be driven above the supply voltage so long as they remain below the maximum inputvoltagevaluespecifiedintheRecommendedOperatingConditions. 8.3.6 UnbufferedLogic A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function, and the output inverter. Some devices have multiple stages at the input or output for various reasons. An unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the requiredlogicfunctionwhichisdirectlydrivenfromtheinputsanddirectlydrivestheoutputs. The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use anunbufferedinverterinanoscillatorcircuit,seeUseoftheCMOSUnbufferedInverterinOscillatorCircuits. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSN74LVC1GU04. Table1.FunctionTable INPUT OUTPUT A Y H L L H 10 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes in the oscillator circuit due to having lower total gain than a buffered equivalent. An example application circuit is shown in Figure 5. To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use oftheCMOSUnbufferedInverterinOscillatorCircuits applicationreport. 9.2 Typical Application U Copyright © 2017, Texas Instruments Incorporated Figure5. TypicalApplicationDiagram 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so routingandloadconditionsshouldbeconsideredtopreventringing. 9.2.2 DetailedDesignProcedure To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use of the CMOS UnbufferedInverterinOscillatorCircuits applicationreport. 1. RecommendedInputConditions – Specifiedhighandlowlevels.See(V andV )inRecommendedOperatingConditions. IH IL – Inputs are overvoltage tolerant allowing them to go as high as (V max) in Recommended Operating I ConditionsatanyvalidV . CC 2. AbsoluteMaximumOutputConditions – Loadcurrentsmustnotexceed(I max)peroutputandmustnotexceed(ContinuouscurrentthroughV O CC orGND)totalcurrentforthepart.TheselimitsarelocatedinAbsoluteMaximumRatings. – OutputsmustnotbepulledabovethevoltageratedintheAbsoluteMaximumRatings. Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve 1600 Icc 1.8V 1400 Icc 2.5V Icc 3.3V 1200 Icc 5V 1000 A µ c - 800 c I 600 400 200 0 0 20 40 60 80 Frequency - MHz D001 Figure6. I vsFrequency CC 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the RecommendedOperatingConditionstable. The V pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is CC recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1- µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin aspossibleforbestresults. 12 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 www.ti.com SCES215Y–APRIL1999–REVISEDDECEMBER2017 11 Layout 11.1 Layout Guidelines Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore sometracesmustturncorners.Figure7 showsprogressivelybettertechniquesofroundingcorners.Onlythelast example(BEST)maintainsconstanttracewidthandminimizesreflections. An example layout is given in Figure 8 for the DPW (X2SON-5) package. This example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be usedtotraceoutthecenterpinconnectionthroughanotherboardlayer,oritcanbeleftoutofthelayout 11.2 Layout Example WORST BETTER BEST Figure7. TraceExample 0402 0.1 (cid:133)F Bypass Capacitor mil 4 8 mil 8 mil 8 mil SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP Figure8. ExampleLayoutWithDPW(X2SON-5)Package Copyright©1999–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC1GU04

SN74LVC1GU04 SCES215Y–APRIL1999–REVISEDDECEMBER2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: TexasInstruments,ImplicationsofSloworFloatingCMOSInputs applicationreport 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks NanoFree,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 14 SubmitDocumentationFeedback Copyright©1999–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1GU04

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 74LVC1GU04DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F & no Sb/Br) 74LVC1GU04DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F & no Sb/Br) 74LVC1GU04DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F & no Sb/Br) 74LVC1GU04DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CD5 & no Sb/Br) CDS 74LVC1GU04DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CD5 & no Sb/Br) CDS 74LVC1GU04DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CD5 & no Sb/Br) CDS 74LVC1GU04DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CD5 & no Sb/Br) CDS 74LVC1GU04DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CDR & no Sb/Br) SN74LVC1GU04DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CU45, CU4F, CU4J, & no Sb/Br) CU4R, CU4T) (CU4H, CU4P, CU4S) SN74LVC1GU04DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CU45, CU4F, CU4J, & no Sb/Br) CU4R) (CU4H, CU4P, CU4S) SN74LVC1GU04DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CD5, CDF, CDJ, CD & no Sb/Br) K, CDR, CDT) (CDH, CDP, CDS) SN74LVC1GU04DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CD5, CDF, CDJ, CD & no Sb/Br) K, CDR, CDT) (CDH, CDP, CDS) SN74LVC1GU04DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CM & no Sb/Br) SN74LVC1GU04DRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CDR & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74LVC1GU04DRY2 ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD & no Sb/Br) SN74LVC1GU04DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD & no Sb/Br) SN74LVC1GU04DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD & no Sb/Br) SN74LVC1GU04YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 CDN & no Sb/Br) SN74LVC1GU04YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 CD & no Sb/Br) (7, N) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74LVC1GU04DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 74LVC1GU04DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 74LVC1GU04DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 74LVC1GU04DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1GU04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74LVC1GU04DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1GU04DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1GU04DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC1GU04DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74LVC1GU04DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3 SN74LVC1GU04DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3 SN74LVC1GU04DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1GU04DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1GU04YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 SN74LVC1GU04YZVR DSBGA YZV 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74LVC1GU04DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 74LVC1GU04DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0 74LVC1GU04DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0 74LVC1GU04DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1GU04DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1GU04DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1GU04DPWR X2SON DPW 5 3000 205.0 200.0 33.0 SN74LVC1GU04DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0 SN74LVC1GU04DRY2 SON DRY 6 5000 202.0 201.0 28.0 SN74LVC1GU04DRY2 SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1GU04DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1GU04DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74LVC1GU04YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 SN74LVC1GU04YZVR DSBGA YZV 4 3000 220.0 220.0 35.0 PackMaterials-Page3

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DPW0005A X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD B 0.85 A 0.75 PIN 1 INDEX AREA 0.85 0.75 0.4 MAX C SEATING PLANE NOTE 3 (0.1) 0.05 (0.25) 4X (0.05) 0.00 0.25 0.1 2 4 NOTE 3 2X 3 2X (0.26) 0.48 5 1 0.27 0.27 4X 0.17 0.17 0.1 C A B (0.06) 0.05 C 0.32 3X 0.23 4223102/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. www.ti.com

EXAMPLE BOARD LAYOUT DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM ( 0.1) 4X (0.42) VIA 0.05 MIN ALL AROUND 1 TYP 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP SOLDER MASK 4X (0.06) OPENING, TYP ( 0.25) (0.21) TYP METAL UNDER EXPOSED METAL SOLDER MASK CLEARANCE TYP LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X 4223102/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.06) 5 4X (0.22) 1 ( 0.24) 4X (0.26) SYMM (0.21) (0.48) TYP SOLDER MASK 3 EDGE 2 4 (R0.05) TYP SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0005 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP C SYMM 1 B D: Max = 1.44 mm, Min = 1.38 mm TYP 0.5 TYP E: Max = 0.94 mm, Min = 0.88 mm A 0.25 5X 1 2 0.21 0.015 C A B SYMM 4219492/A 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.23) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219492/A 05/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL SYMM TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219492/A 05/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

D: Max = 0.918 mm, Min =0 .858 mm E: Max = 0.918 mm, Min =0 .858 mm

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PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com

EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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